1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/err.h>
   8#include <linux/platform_device.h>
   9#include <linux/module.h>
  10#include <linux/of.h>
  11#include <linux/of_device.h>
  12#include <linux/clk-provider.h>
  13#include <linux/regmap.h>
  14
  15#include <linux/reset-controller.h>
  16#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  17#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  18
  19#include "common.h"
  20#include "clk-regmap.h"
  21#include "clk-pll.h"
  22#include "clk-rcg.h"
  23#include "clk-branch.h"
  24#include "clk-alpha-pll.h"
  25#include "clk-regmap-divider.h"
  26#include "clk-regmap-mux.h"
  27#include "reset.h"
  28
  29#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  30
  31enum {
  32	P_XO,
  33	P_BIAS_PLL,
  34	P_UNIPHY0_RX,
  35	P_UNIPHY0_TX,
  36	P_UNIPHY1_RX,
  37	P_BIAS_PLL_NSS_NOC,
  38	P_UNIPHY1_TX,
  39	P_PCIE20_PHY0_PIPE,
  40	P_USB3PHY_0_PIPE,
  41	P_GPLL0,
  42	P_GPLL0_DIV2,
  43	P_GPLL2,
  44	P_GPLL4,
  45	P_GPLL6,
  46	P_SLEEP_CLK,
  47	P_UBI32_PLL,
  48	P_NSS_CRYPTO_PLL,
  49	P_PI_SLEEP,
  50};
  51
  52static struct clk_alpha_pll gpll0_main = {
  53	.offset = 0x21000,
  54	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  55	.clkr = {
  56		.enable_reg = 0x0b000,
  57		.enable_mask = BIT(0),
  58		.hw.init = &(struct clk_init_data){
  59			.name = "gpll0_main",
  60			.parent_data = &(const struct clk_parent_data){
  61				.fw_name = "xo",
  62			},
  63			.num_parents = 1,
  64			.ops = &clk_alpha_pll_ops,
  65		},
  66	},
  67};
  68
  69static struct clk_fixed_factor gpll0_out_main_div2 = {
  70	.mult = 1,
  71	.div = 2,
  72	.hw.init = &(struct clk_init_data){
  73		.name = "gpll0_out_main_div2",
  74		.parent_hws = (const struct clk_hw *[]){
  75				&gpll0_main.clkr.hw },
  76		.num_parents = 1,
  77		.ops = &clk_fixed_factor_ops,
  78		.flags = CLK_SET_RATE_PARENT,
  79	},
  80};
  81
  82static struct clk_alpha_pll_postdiv gpll0 = {
  83	.offset = 0x21000,
  84	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  85	.width = 4,
  86	.clkr.hw.init = &(struct clk_init_data){
  87		.name = "gpll0",
  88		.parent_hws = (const struct clk_hw *[]){
  89				&gpll0_main.clkr.hw },
  90		.num_parents = 1,
  91		.ops = &clk_alpha_pll_postdiv_ro_ops,
  92		.flags = CLK_SET_RATE_PARENT,
  93	},
  94};
  95
  96static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
  97	{ .fw_name = "xo" },
  98	{ .hw = &gpll0.clkr.hw},
  99	{ .hw = &gpll0_out_main_div2.hw},
 100};
 101
 102static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 103	{ P_XO, 0 },
 104	{ P_GPLL0, 1 },
 105	{ P_GPLL0_DIV2, 4 },
 106};
 107
 108static struct clk_alpha_pll ubi32_pll_main = {
 109	.offset = 0x25000,
 110	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 111	.flags = SUPPORTS_DYNAMIC_UPDATE,
 112	.clkr = {
 113		.enable_reg = 0x0b000,
 114		.enable_mask = BIT(6),
 115		.hw.init = &(struct clk_init_data){
 116			.name = "ubi32_pll_main",
 117			.parent_data = &(const struct clk_parent_data){
 118				.fw_name = "xo",
 119			},
 120			.num_parents = 1,
 121			.ops = &clk_alpha_pll_huayra_ops,
 122		},
 123	},
 124};
 125
 126static struct clk_alpha_pll_postdiv ubi32_pll = {
 127	.offset = 0x25000,
 128	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 129	.width = 2,
 130	.clkr.hw.init = &(struct clk_init_data){
 131		.name = "ubi32_pll",
 132		.parent_hws = (const struct clk_hw *[]){
 133				&ubi32_pll_main.clkr.hw },
 134		.num_parents = 1,
 135		.ops = &clk_alpha_pll_postdiv_ro_ops,
 136		.flags = CLK_SET_RATE_PARENT,
 137	},
 138};
 139
 140static struct clk_alpha_pll gpll6_main = {
 141	.offset = 0x37000,
 142	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 143	.clkr = {
 144		.enable_reg = 0x0b000,
 145		.enable_mask = BIT(7),
 146		.hw.init = &(struct clk_init_data){
 147			.name = "gpll6_main",
 148			.parent_data = &(const struct clk_parent_data){
 149				.fw_name = "xo",
 150			},
 151			.num_parents = 1,
 152			.ops = &clk_alpha_pll_ops,
 153		},
 154	},
 155};
 156
 157static struct clk_alpha_pll_postdiv gpll6 = {
 158	.offset = 0x37000,
 159	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 160	.width = 2,
 161	.clkr.hw.init = &(struct clk_init_data){
 162		.name = "gpll6",
 163		.parent_hws = (const struct clk_hw *[]){
 164				&gpll6_main.clkr.hw },
 165		.num_parents = 1,
 166		.ops = &clk_alpha_pll_postdiv_ro_ops,
 167		.flags = CLK_SET_RATE_PARENT,
 168	},
 169};
 170
 171static struct clk_alpha_pll gpll4_main = {
 172	.offset = 0x24000,
 173	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 174	.clkr = {
 175		.enable_reg = 0x0b000,
 176		.enable_mask = BIT(5),
 177		.hw.init = &(struct clk_init_data){
 178			.name = "gpll4_main",
 179			.parent_data = &(const struct clk_parent_data){
 180				.fw_name = "xo",
 181			},
 182			.num_parents = 1,
 183			.ops = &clk_alpha_pll_ops,
 184		},
 185	},
 186};
 187
 188static struct clk_alpha_pll_postdiv gpll4 = {
 189	.offset = 0x24000,
 190	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 191	.width = 4,
 192	.clkr.hw.init = &(struct clk_init_data){
 193		.name = "gpll4",
 194		.parent_hws = (const struct clk_hw *[]){
 195				&gpll4_main.clkr.hw },
 196		.num_parents = 1,
 197		.ops = &clk_alpha_pll_postdiv_ro_ops,
 198		.flags = CLK_SET_RATE_PARENT,
 199	},
 200};
 201
 202static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 203	F(24000000, P_XO, 1, 0, 0),
 204	F(50000000, P_GPLL0, 16, 0, 0),
 205	F(100000000, P_GPLL0, 8, 0, 0),
 206	{ }
 207};
 208
 209static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 210	.cmd_rcgr = 0x27000,
 211	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 212	.hid_width = 5,
 213	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 214	.clkr.hw.init = &(struct clk_init_data){
 215		.name = "pcnoc_bfdcd_clk_src",
 216		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 217		.num_parents = 3,
 218		.ops = &clk_rcg2_ops,
 219	},
 220};
 221
 222static struct clk_alpha_pll gpll2_main = {
 223	.offset = 0x4a000,
 224	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 225	.clkr = {
 226		.enable_reg = 0x0b000,
 227		.enable_mask = BIT(2),
 228		.hw.init = &(struct clk_init_data){
 229			.name = "gpll2_main",
 230			.parent_data = &(const struct clk_parent_data){
 231				.fw_name = "xo",
 232			},
 233			.num_parents = 1,
 234			.ops = &clk_alpha_pll_ops,
 235		},
 236	},
 237};
 238
 239static struct clk_alpha_pll_postdiv gpll2 = {
 240	.offset = 0x4a000,
 241	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 242	.width = 4,
 243	.clkr.hw.init = &(struct clk_init_data){
 244		.name = "gpll2",
 245		.parent_hws = (const struct clk_hw *[]){
 246				&gpll2_main.clkr.hw },
 247		.num_parents = 1,
 248		.ops = &clk_alpha_pll_postdiv_ro_ops,
 249		.flags = CLK_SET_RATE_PARENT,
 250	},
 251};
 252
 253static struct clk_alpha_pll nss_crypto_pll_main = {
 254	.offset = 0x22000,
 255	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 256	.clkr = {
 257		.enable_reg = 0x0b000,
 258		.enable_mask = BIT(4),
 259		.hw.init = &(struct clk_init_data){
 260			.name = "nss_crypto_pll_main",
 261			.parent_data = &(const struct clk_parent_data){
 262				.fw_name = "xo",
 263			},
 264			.num_parents = 1,
 265			.ops = &clk_alpha_pll_ops,
 266		},
 267	},
 268};
 269
 270static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 271	.offset = 0x22000,
 272	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 273	.width = 4,
 274	.clkr.hw.init = &(struct clk_init_data){
 275		.name = "nss_crypto_pll",
 276		.parent_hws = (const struct clk_hw *[]){
 277				&nss_crypto_pll_main.clkr.hw },
 278		.num_parents = 1,
 279		.ops = &clk_alpha_pll_postdiv_ro_ops,
 280		.flags = CLK_SET_RATE_PARENT,
 281	},
 282};
 283
 284static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
 285	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
 286	F(320000000, P_GPLL0, 2.5, 0, 0),
 287	F(600000000, P_GPLL4, 2, 0, 0),
 288	{ }
 289};
 290
 291static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
 292	{ .fw_name = "xo" },
 293	{ .hw = &gpll4.clkr.hw },
 294	{ .hw = &gpll0.clkr.hw },
 295	{ .hw = &gpll6.clkr.hw },
 296	{ .hw = &gpll0_out_main_div2.hw },
 297};
 298
 299static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
 300	{ P_XO, 0 },
 301	{ P_GPLL4, 1 },
 302	{ P_GPLL0, 2 },
 303	{ P_GPLL6, 3 },
 304	{ P_GPLL0_DIV2, 4 },
 305};
 306
 307static struct clk_rcg2 qdss_tsctr_clk_src = {
 308	.cmd_rcgr = 0x29064,
 309	.freq_tbl = ftbl_qdss_tsctr_clk_src,
 310	.hid_width = 5,
 311	.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 312	.clkr.hw.init = &(struct clk_init_data){
 313		.name = "qdss_tsctr_clk_src",
 314		.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 315		.num_parents = 5,
 316		.ops = &clk_rcg2_ops,
 317	},
 318};
 319
 320static struct clk_fixed_factor qdss_dap_sync_clk_src = {
 321	.mult = 1,
 322	.div = 4,
 323	.hw.init = &(struct clk_init_data){
 324		.name = "qdss_dap_sync_clk_src",
 325		.parent_hws = (const struct clk_hw *[]){
 326				&qdss_tsctr_clk_src.clkr.hw },
 327		.num_parents = 1,
 328		.ops = &clk_fixed_factor_ops,
 329	},
 330};
 331
 332static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
 333	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
 334	F(240000000, P_GPLL4, 5, 0, 0),
 335	{ }
 336};
 337
 338static struct clk_rcg2 qdss_at_clk_src = {
 339	.cmd_rcgr = 0x2900c,
 340	.freq_tbl = ftbl_qdss_at_clk_src,
 341	.hid_width = 5,
 342	.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 343	.clkr.hw.init = &(struct clk_init_data){
 344		.name = "qdss_at_clk_src",
 345		.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 346		.num_parents = 5,
 347		.ops = &clk_rcg2_ops,
 348	},
 349};
 350
 351static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
 352	.mult = 1,
 353	.div = 2,
 354	.hw.init = &(struct clk_init_data){
 355		.name = "qdss_tsctr_div2_clk_src",
 356		.parent_hws = (const struct clk_hw *[]){
 357				&qdss_tsctr_clk_src.clkr.hw },
 358		.num_parents = 1,
 359		.flags = CLK_SET_RATE_PARENT,
 360		.ops = &clk_fixed_factor_ops,
 361	},
 362};
 363
 364static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
 365	F(24000000, P_XO, 1, 0, 0),
 366	F(300000000, P_BIAS_PLL, 1, 0, 0),
 367	{ }
 368};
 369
 370static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 371	{ .fw_name = "xo" },
 372	{ .fw_name = "bias_pll_cc_clk" },
 373	{ .hw = &gpll0.clkr.hw },
 374	{ .hw = &gpll4.clkr.hw },
 375	{ .hw = &nss_crypto_pll.clkr.hw },
 376	{ .hw = &ubi32_pll.clkr.hw },
 377};
 378
 379static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 380	{ P_XO, 0 },
 381	{ P_BIAS_PLL, 1 },
 382	{ P_GPLL0, 2 },
 383	{ P_GPLL4, 3 },
 384	{ P_NSS_CRYPTO_PLL, 4 },
 385	{ P_UBI32_PLL, 5 },
 386};
 387
 388static struct clk_rcg2 nss_ppe_clk_src = {
 389	.cmd_rcgr = 0x68080,
 390	.freq_tbl = ftbl_nss_ppe_clk_src,
 391	.hid_width = 5,
 392	.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
 393	.clkr.hw.init = &(struct clk_init_data){
 394		.name = "nss_ppe_clk_src",
 395		.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
 396		.num_parents = 6,
 397		.ops = &clk_rcg2_ops,
 398	},
 399};
 400
 401static struct clk_branch gcc_xo_clk_src = {
 402	.halt_reg = 0x30018,
 403	.clkr = {
 404		.enable_reg = 0x30018,
 405		.enable_mask = BIT(1),
 406		.hw.init = &(struct clk_init_data){
 407			.name = "gcc_xo_clk_src",
 408			.parent_data = &(const struct clk_parent_data){
 409				.fw_name = "xo",
 410			},
 411			.num_parents = 1,
 412			.flags = CLK_SET_RATE_PARENT,
 413			.ops = &clk_branch2_ops,
 414		},
 415	},
 416};
 417
 418static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
 419	F(24000000, P_XO, 1, 0, 0),
 420	F(200000000, P_GPLL0, 4, 0, 0),
 421	{ }
 422};
 423
 424static const struct clk_parent_data gcc_xo_gpll0[] = {
 425	{ .fw_name = "xo" },
 426	{ .hw = &gpll0.clkr.hw },
 427};
 428
 429static const struct parent_map gcc_xo_gpll0_map[] = {
 430	{ P_XO, 0 },
 431	{ P_GPLL0, 1 },
 432};
 433
 434static struct clk_rcg2 nss_ce_clk_src = {
 435	.cmd_rcgr = 0x68098,
 436	.freq_tbl = ftbl_nss_ce_clk_src,
 437	.hid_width = 5,
 438	.parent_map = gcc_xo_gpll0_map,
 439	.clkr.hw.init = &(struct clk_init_data){
 440		.name = "nss_ce_clk_src",
 441		.parent_data = gcc_xo_gpll0,
 442		.num_parents = 2,
 443		.ops = &clk_rcg2_ops,
 444	},
 445};
 446
 447static struct clk_branch gcc_sleep_clk_src = {
 448	.halt_reg = 0x30000,
 449	.clkr = {
 450		.enable_reg = 0x30000,
 451		.enable_mask = BIT(1),
 452		.hw.init = &(struct clk_init_data){
 453			.name = "gcc_sleep_clk_src",
 454			.parent_data = &(const struct clk_parent_data){
 455				.fw_name = "sleep_clk",
 456			},
 457			.num_parents = 1,
 458			.ops = &clk_branch2_ops,
 459		},
 460	},
 461};
 462
 463static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
 464	F(24000000, P_XO, 1, 0, 0),
 465	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
 466	F(100000000, P_GPLL0, 8, 0, 0),
 467	F(133333333, P_GPLL0, 6, 0, 0),
 468	F(160000000, P_GPLL0, 5, 0, 0),
 469	F(200000000, P_GPLL0, 4, 0, 0),
 470	F(266666667, P_GPLL0, 3, 0, 0),
 471	{ }
 472};
 473
 474static const struct clk_parent_data
 475			gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 476	{ .fw_name = "xo" },
 477	{ .hw = &gpll0.clkr.hw },
 478	{ .hw = &gpll6.clkr.hw },
 479	{ .hw = &gpll0_out_main_div2.hw },
 480};
 481
 482static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 483	{ P_XO, 0 },
 484	{ P_GPLL0, 1 },
 485	{ P_GPLL6, 2 },
 486	{ P_GPLL0_DIV2, 3 },
 487};
 488
 489static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
 490	.cmd_rcgr = 0x76054,
 491	.freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
 492	.hid_width = 5,
 493	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
 494	.clkr.hw.init = &(struct clk_init_data){
 495		.name = "snoc_nssnoc_bfdcd_clk_src",
 496		.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
 497		.num_parents = 4,
 498		.ops = &clk_rcg2_ops,
 499	},
 500};
 501
 502static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 503	F(24000000, P_XO, 1, 0, 0),
 504	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 505	F(50000000, P_GPLL0, 16, 0, 0),
 506	F(100000000, P_GPLL0, 8, 0, 0),
 507	{ }
 508};
 509
 510static struct clk_rcg2 apss_ahb_clk_src = {
 511	.cmd_rcgr = 0x46000,
 512	.freq_tbl = ftbl_apss_ahb_clk_src,
 513	.hid_width = 5,
 514	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 515	.clkr.hw.init = &(struct clk_init_data){
 516		.name = "apss_ahb_clk_src",
 517		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 518		.num_parents = 3,
 519		.ops = &clk_rcg2_ops,
 520	},
 521};
 522
 523static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
 524	F(24000000, P_XO, 1, 0, 0),
 525	F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
 526	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 527	F(78125000, P_UNIPHY1_RX, 4, 0, 0),
 528	F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
 529	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 530	F(156250000, P_UNIPHY1_RX, 2, 0, 0),
 531	F(312500000, P_UNIPHY1_RX, 1, 0, 0),
 532	{ }
 533};
 534
 535static const struct clk_parent_data
 536gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 537	{ .fw_name = "xo" },
 538	{ .fw_name = "uniphy0_gcc_rx_clk" },
 539	{ .fw_name = "uniphy0_gcc_tx_clk" },
 540	{ .fw_name = "uniphy1_gcc_rx_clk" },
 541	{ .fw_name = "uniphy1_gcc_tx_clk" },
 542	{ .hw = &ubi32_pll.clkr.hw },
 543	{ .fw_name = "bias_pll_cc_clk" },
 544};
 545
 546static const struct parent_map
 547gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 548	{ P_XO, 0 },
 549	{ P_UNIPHY0_RX, 1 },
 550	{ P_UNIPHY0_TX, 2 },
 551	{ P_UNIPHY1_RX, 3 },
 552	{ P_UNIPHY1_TX, 4 },
 553	{ P_UBI32_PLL, 5 },
 554	{ P_BIAS_PLL, 6 },
 555};
 556
 557static struct clk_rcg2 nss_port5_rx_clk_src = {
 558	.cmd_rcgr = 0x68060,
 559	.freq_tbl = ftbl_nss_port5_rx_clk_src,
 560	.hid_width = 5,
 561	.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
 562	.clkr.hw.init = &(struct clk_init_data){
 563		.name = "nss_port5_rx_clk_src",
 564		.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
 565		.num_parents = 7,
 566		.ops = &clk_rcg2_ops,
 567	},
 568};
 569
 570static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
 571	F(24000000, P_XO, 1, 0, 0),
 572	F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
 573	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 574	F(78125000, P_UNIPHY1_TX, 4, 0, 0),
 575	F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
 576	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 577	F(156250000, P_UNIPHY1_TX, 2, 0, 0),
 578	F(312500000, P_UNIPHY1_TX, 1, 0, 0),
 579	{ }
 580};
 581
 582static const struct clk_parent_data
 583gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 584	{ .fw_name = "xo" },
 585	{ .fw_name = "uniphy0_gcc_tx_clk" },
 586	{ .fw_name = "uniphy0_gcc_rx_clk" },
 587	{ .fw_name = "uniphy1_gcc_tx_clk" },
 588	{ .fw_name = "uniphy1_gcc_rx_clk" },
 589	{ .hw = &ubi32_pll.clkr.hw },
 590	{ .fw_name = "bias_pll_cc_clk" },
 591};
 592
 593static const struct parent_map
 594gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 595	{ P_XO, 0 },
 596	{ P_UNIPHY0_TX, 1 },
 597	{ P_UNIPHY0_RX, 2 },
 598	{ P_UNIPHY1_TX, 3 },
 599	{ P_UNIPHY1_RX, 4 },
 600	{ P_UBI32_PLL, 5 },
 601	{ P_BIAS_PLL, 6 },
 602};
 603
 604static struct clk_rcg2 nss_port5_tx_clk_src = {
 605	.cmd_rcgr = 0x68068,
 606	.freq_tbl = ftbl_nss_port5_tx_clk_src,
 607	.hid_width = 5,
 608	.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
 609	.clkr.hw.init = &(struct clk_init_data){
 610		.name = "nss_port5_tx_clk_src",
 611		.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
 612		.num_parents = 7,
 613		.ops = &clk_rcg2_ops,
 614	},
 615};
 616
 617static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 618	F(24000000, P_XO, 1, 0, 0),
 619	F(200000000, P_GPLL0, 4, 0, 0),
 620	F(240000000, P_GPLL4, 5, 0, 0),
 621	{ }
 622};
 623
 624static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
 625	F(24000000, P_XO, 1, 0, 0),
 626	F(100000000, P_GPLL0, 8, 0, 0),
 627	{ }
 628};
 629
 630static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 631	{ .fw_name = "xo" },
 632	{ .hw = &gpll0.clkr.hw },
 633	{ .hw = &gpll4.clkr.hw },
 634};
 635
 636static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 637	{ P_XO, 0 },
 638	{ P_GPLL0, 1 },
 639	{ P_GPLL4, 2 },
 640};
 641
 642static struct clk_rcg2 pcie0_axi_clk_src = {
 643	.cmd_rcgr = 0x75054,
 644	.freq_tbl = ftbl_pcie_axi_clk_src,
 645	.hid_width = 5,
 646	.parent_map = gcc_xo_gpll0_gpll4_map,
 647	.clkr.hw.init = &(struct clk_init_data){
 648		.name = "pcie0_axi_clk_src",
 649		.parent_data = gcc_xo_gpll0_gpll4,
 650		.num_parents = 3,
 651		.ops = &clk_rcg2_ops,
 652	},
 653};
 654
 655static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
 656	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 657	F(100000000, P_GPLL0, 8, 0, 0),
 658	F(133330000, P_GPLL0, 6, 0, 0),
 659	F(200000000, P_GPLL0, 4, 0, 0),
 660	{ }
 661};
 662
 663static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 664	{ .fw_name = "xo" },
 665	{ .hw = &gpll0_out_main_div2.hw },
 666	{ .hw = &gpll0.clkr.hw },
 667};
 668
 669static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 670	{ P_XO, 0 },
 671	{ P_GPLL0_DIV2, 2 },
 672	{ P_GPLL0, 1 },
 673};
 674
 675static struct clk_rcg2 usb0_master_clk_src = {
 676	.cmd_rcgr = 0x3e00c,
 677	.freq_tbl = ftbl_usb0_master_clk_src,
 678	.mnd_width = 8,
 679	.hid_width = 5,
 680	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 681	.clkr.hw.init = &(struct clk_init_data){
 682		.name = "usb0_master_clk_src",
 683		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 684		.num_parents = 3,
 685		.ops = &clk_rcg2_ops,
 686	},
 687};
 688
 689static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
 690	.reg = 0x46018,
 691	.shift = 4,
 692	.width = 4,
 693	.clkr = {
 694		.hw.init = &(struct clk_init_data){
 695			.name = "apss_ahb_postdiv_clk_src",
 696			.parent_hws = (const struct clk_hw *[]){
 697					&apss_ahb_clk_src.clkr.hw },
 698			.num_parents = 1,
 699			.ops = &clk_regmap_div_ops,
 700		},
 701	},
 702};
 703
 704static struct clk_fixed_factor gcc_xo_div4_clk_src = {
 705	.mult = 1,
 706	.div = 4,
 707	.hw.init = &(struct clk_init_data){
 708		.name = "gcc_xo_div4_clk_src",
 709		.parent_hws = (const struct clk_hw *[]){
 710				&gcc_xo_clk_src.clkr.hw },
 711		.num_parents = 1,
 712		.ops = &clk_fixed_factor_ops,
 713		.flags = CLK_SET_RATE_PARENT,
 714	},
 715};
 716
 717static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
 718	F(24000000, P_XO, 1, 0, 0),
 719	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 720	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 721	{ }
 722};
 723
 724static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 725	{ .fw_name = "xo" },
 726	{ .fw_name = "uniphy0_gcc_rx_clk" },
 727	{ .fw_name = "uniphy0_gcc_tx_clk" },
 728	{ .hw = &ubi32_pll.clkr.hw },
 729	{ .fw_name = "bias_pll_cc_clk" },
 730};
 731
 732static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 733	{ P_XO, 0 },
 734	{ P_UNIPHY0_RX, 1 },
 735	{ P_UNIPHY0_TX, 2 },
 736	{ P_UBI32_PLL, 5 },
 737	{ P_BIAS_PLL, 6 },
 738};
 739
 740static struct clk_rcg2 nss_port1_rx_clk_src = {
 741	.cmd_rcgr = 0x68020,
 742	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 743	.hid_width = 5,
 744	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 745	.clkr.hw.init = &(struct clk_init_data){
 746		.name = "nss_port1_rx_clk_src",
 747		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 748		.num_parents = 5,
 749		.ops = &clk_rcg2_ops,
 750	},
 751};
 752
 753static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
 754	F(24000000, P_XO, 1, 0, 0),
 755	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 756	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 757	{ }
 758};
 759
 760static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 761	{ .fw_name = "xo" },
 762	{ .fw_name = "uniphy0_gcc_tx_clk" },
 763	{ .fw_name = "uniphy0_gcc_rx_clk" },
 764	{ .hw = &ubi32_pll.clkr.hw },
 765	{ .fw_name = "bias_pll_cc_clk" },
 766};
 767
 768static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 769	{ P_XO, 0 },
 770	{ P_UNIPHY0_TX, 1 },
 771	{ P_UNIPHY0_RX, 2 },
 772	{ P_UBI32_PLL, 5 },
 773	{ P_BIAS_PLL, 6 },
 774};
 775
 776static struct clk_rcg2 nss_port1_tx_clk_src = {
 777	.cmd_rcgr = 0x68028,
 778	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 779	.hid_width = 5,
 780	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 781	.clkr.hw.init = &(struct clk_init_data){
 782		.name = "nss_port1_tx_clk_src",
 783		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 784		.num_parents = 5,
 785		.ops = &clk_rcg2_ops,
 786	},
 787};
 788
 789static struct clk_rcg2 nss_port2_rx_clk_src = {
 790	.cmd_rcgr = 0x68030,
 791	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 792	.hid_width = 5,
 793	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 794	.clkr.hw.init = &(struct clk_init_data){
 795		.name = "nss_port2_rx_clk_src",
 796		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 797		.num_parents = 5,
 798		.ops = &clk_rcg2_ops,
 799	},
 800};
 801
 802static struct clk_rcg2 nss_port2_tx_clk_src = {
 803	.cmd_rcgr = 0x68038,
 804	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 805	.hid_width = 5,
 806	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 807	.clkr.hw.init = &(struct clk_init_data){
 808		.name = "nss_port2_tx_clk_src",
 809		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 810		.num_parents = 5,
 811		.ops = &clk_rcg2_ops,
 812	},
 813};
 814
 815static struct clk_rcg2 nss_port3_rx_clk_src = {
 816	.cmd_rcgr = 0x68040,
 817	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 818	.hid_width = 5,
 819	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 820	.clkr.hw.init = &(struct clk_init_data){
 821		.name = "nss_port3_rx_clk_src",
 822		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 823		.num_parents = 5,
 824		.ops = &clk_rcg2_ops,
 825	},
 826};
 827
 828static struct clk_rcg2 nss_port3_tx_clk_src = {
 829	.cmd_rcgr = 0x68048,
 830	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 831	.hid_width = 5,
 832	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 833	.clkr.hw.init = &(struct clk_init_data){
 834		.name = "nss_port3_tx_clk_src",
 835		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 836		.num_parents = 5,
 837		.ops = &clk_rcg2_ops,
 838	},
 839};
 840
 841static struct clk_rcg2 nss_port4_rx_clk_src = {
 842	.cmd_rcgr = 0x68050,
 843	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 844	.hid_width = 5,
 845	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 846	.clkr.hw.init = &(struct clk_init_data){
 847		.name = "nss_port4_rx_clk_src",
 848		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 849		.num_parents = 5,
 850		.ops = &clk_rcg2_ops,
 851	},
 852};
 853
 854static struct clk_rcg2 nss_port4_tx_clk_src = {
 855	.cmd_rcgr = 0x68058,
 856	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 857	.hid_width = 5,
 858	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 859	.clkr.hw.init = &(struct clk_init_data){
 860		.name = "nss_port4_tx_clk_src",
 861		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 862		.num_parents = 5,
 863		.ops = &clk_rcg2_ops,
 864	},
 865};
 866
 867static struct clk_regmap_div nss_port5_rx_div_clk_src = {
 868	.reg = 0x68440,
 869	.shift = 0,
 870	.width = 4,
 871	.clkr = {
 872		.hw.init = &(struct clk_init_data){
 873			.name = "nss_port5_rx_div_clk_src",
 874			.parent_hws = (const struct clk_hw *[]){
 875					&nss_port5_rx_clk_src.clkr.hw },
 876			.num_parents = 1,
 877			.ops = &clk_regmap_div_ops,
 878			.flags = CLK_SET_RATE_PARENT,
 879		},
 880	},
 881};
 882
 883static struct clk_regmap_div nss_port5_tx_div_clk_src = {
 884	.reg = 0x68444,
 885	.shift = 0,
 886	.width = 4,
 887	.clkr = {
 888		.hw.init = &(struct clk_init_data){
 889			.name = "nss_port5_tx_div_clk_src",
 890			.parent_hws = (const struct clk_hw *[]){
 891					&nss_port5_tx_clk_src.clkr.hw },
 892			.num_parents = 1,
 893			.ops = &clk_regmap_div_ops,
 894			.flags = CLK_SET_RATE_PARENT,
 895		},
 896	},
 897};
 898
 899static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
 900	F(24000000, P_XO, 1, 0, 0),
 901	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 902	F(200000000, P_GPLL0, 4, 0, 0),
 903	F(308570000, P_GPLL6, 3.5, 0, 0),
 904	F(400000000, P_GPLL0, 2, 0, 0),
 905	F(533000000, P_GPLL0, 1.5, 0, 0),
 906	{ }
 907};
 908
 909static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
 910	{ .fw_name = "xo" },
 911	{ .hw = &gpll0.clkr.hw },
 912	{ .hw = &gpll6.clkr.hw },
 913	{ .hw = &ubi32_pll.clkr.hw },
 914	{ .hw = &gpll0_out_main_div2.hw },
 915};
 916
 917static const struct parent_map
 918gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
 919	{ P_XO, 0 },
 920	{ P_GPLL0, 1 },
 921	{ P_GPLL6, 2 },
 922	{ P_UBI32_PLL, 3 },
 923	{ P_GPLL0_DIV2, 6 },
 924};
 925
 926static struct clk_rcg2 apss_axi_clk_src = {
 927	.cmd_rcgr = 0x38048,
 928	.freq_tbl = ftbl_apss_axi_clk_src,
 929	.hid_width = 5,
 930	.parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
 931	.clkr.hw.init = &(struct clk_init_data){
 932		.name = "apss_axi_clk_src",
 933		.parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
 934		.num_parents = 5,
 935		.ops = &clk_rcg2_ops,
 936	},
 937};
 938
 939static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
 940	F(24000000, P_XO, 1, 0, 0),
 941	F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
 942	{ }
 943};
 944
 945static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
 946	{ .fw_name = "xo" },
 947	{ .hw = &nss_crypto_pll.clkr.hw },
 948	{ .hw = &gpll0.clkr.hw },
 949};
 950
 951static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 952	{ P_XO, 0 },
 953	{ P_NSS_CRYPTO_PLL, 1 },
 954	{ P_GPLL0, 2 },
 955};
 956
 957static struct clk_rcg2 nss_crypto_clk_src = {
 958	.cmd_rcgr = 0x68144,
 959	.freq_tbl = ftbl_nss_crypto_clk_src,
 960	.mnd_width = 16,
 961	.hid_width = 5,
 962	.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
 963	.clkr.hw.init = &(struct clk_init_data){
 964		.name = "nss_crypto_clk_src",
 965		.parent_data = gcc_xo_nss_crypto_pll_gpll0,
 966		.num_parents = 3,
 967		.ops = &clk_rcg2_ops,
 968	},
 969};
 970
 971static struct clk_regmap_div nss_port1_rx_div_clk_src = {
 972	.reg = 0x68400,
 973	.shift = 0,
 974	.width = 4,
 975	.clkr = {
 976		.hw.init = &(struct clk_init_data){
 977			.name = "nss_port1_rx_div_clk_src",
 978			.parent_hws = (const struct clk_hw *[]){
 979				&nss_port1_rx_clk_src.clkr.hw },
 980			.num_parents = 1,
 981			.ops = &clk_regmap_div_ops,
 982			.flags = CLK_SET_RATE_PARENT,
 983		},
 984	},
 985};
 986
 987static struct clk_regmap_div nss_port1_tx_div_clk_src = {
 988	.reg = 0x68404,
 989	.shift = 0,
 990	.width = 4,
 991	.clkr = {
 992		.hw.init = &(struct clk_init_data){
 993			.name = "nss_port1_tx_div_clk_src",
 994			.parent_hws = (const struct clk_hw *[]){
 995					&nss_port1_tx_clk_src.clkr.hw },
 996			.num_parents = 1,
 997			.ops = &clk_regmap_div_ops,
 998			.flags = CLK_SET_RATE_PARENT,
 999		},
1000	},
1001};
1002
1003static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1004	.reg = 0x68410,
1005	.shift = 0,
1006	.width = 4,
1007	.clkr = {
1008		.hw.init = &(struct clk_init_data){
1009			.name = "nss_port2_rx_div_clk_src",
1010			.parent_hws = (const struct clk_hw *[]){
1011					&nss_port2_rx_clk_src.clkr.hw },
1012			.num_parents = 1,
1013			.ops = &clk_regmap_div_ops,
1014			.flags = CLK_SET_RATE_PARENT,
1015		},
1016	},
1017};
1018
1019static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1020	.reg = 0x68414,
1021	.shift = 0,
1022	.width = 4,
1023	.clkr = {
1024		.hw.init = &(struct clk_init_data){
1025			.name = "nss_port2_tx_div_clk_src",
1026			.parent_hws = (const struct clk_hw *[]){
1027					&nss_port2_tx_clk_src.clkr.hw },
1028			.num_parents = 1,
1029			.ops = &clk_regmap_div_ops,
1030			.flags = CLK_SET_RATE_PARENT,
1031		},
1032	},
1033};
1034
1035static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1036	.reg = 0x68420,
1037	.shift = 0,
1038	.width = 4,
1039	.clkr = {
1040		.hw.init = &(struct clk_init_data){
1041			.name = "nss_port3_rx_div_clk_src",
1042			.parent_hws = (const struct clk_hw *[]){
1043					&nss_port3_rx_clk_src.clkr.hw },
1044			.num_parents = 1,
1045			.ops = &clk_regmap_div_ops,
1046			.flags = CLK_SET_RATE_PARENT,
1047		},
1048	},
1049};
1050
1051static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1052	.reg = 0x68424,
1053	.shift = 0,
1054	.width = 4,
1055	.clkr = {
1056		.hw.init = &(struct clk_init_data){
1057			.name = "nss_port3_tx_div_clk_src",
1058			.parent_hws = (const struct clk_hw *[]){
1059					&nss_port3_tx_clk_src.clkr.hw },
1060			.num_parents = 1,
1061			.ops = &clk_regmap_div_ops,
1062			.flags = CLK_SET_RATE_PARENT,
1063		},
1064	},
1065};
1066
1067static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1068	.reg = 0x68430,
1069	.shift = 0,
1070	.width = 4,
1071	.clkr = {
1072		.hw.init = &(struct clk_init_data){
1073			.name = "nss_port4_rx_div_clk_src",
1074			.parent_hws = (const struct clk_hw *[]){
1075					&nss_port4_rx_clk_src.clkr.hw },
1076			.num_parents = 1,
1077			.ops = &clk_regmap_div_ops,
1078			.flags = CLK_SET_RATE_PARENT,
1079		},
1080	},
1081};
1082
1083static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1084	.reg = 0x68434,
1085	.shift = 0,
1086	.width = 4,
1087	.clkr = {
1088		.hw.init = &(struct clk_init_data){
1089			.name = "nss_port4_tx_div_clk_src",
1090			.parent_hws = (const struct clk_hw *[]){
1091					&nss_port4_tx_clk_src.clkr.hw },
1092			.num_parents = 1,
1093			.ops = &clk_regmap_div_ops,
1094			.flags = CLK_SET_RATE_PARENT,
1095		},
1096	},
1097};
1098
1099static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1100	F(24000000, P_XO, 1, 0, 0),
1101	F(149760000, P_UBI32_PLL, 10, 0, 0),
1102	F(187200000, P_UBI32_PLL, 8, 0, 0),
1103	F(249600000, P_UBI32_PLL, 6, 0, 0),
1104	F(374400000, P_UBI32_PLL, 4, 0, 0),
1105	F(748800000, P_UBI32_PLL, 2, 0, 0),
1106	F(1497600000, P_UBI32_PLL, 1, 0, 0),
1107	{ }
1108};
1109
1110static const struct clk_parent_data
1111			gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1112	{ .fw_name = "xo" },
1113	{ .hw = &ubi32_pll.clkr.hw },
1114	{ .hw = &gpll0.clkr.hw },
1115	{ .hw = &gpll2.clkr.hw },
1116	{ .hw = &gpll4.clkr.hw },
1117	{ .hw = &gpll6.clkr.hw },
1118};
1119
1120static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1121	{ P_XO, 0 },
1122	{ P_UBI32_PLL, 1 },
1123	{ P_GPLL0, 2 },
1124	{ P_GPLL2, 3 },
1125	{ P_GPLL4, 4 },
1126	{ P_GPLL6, 5 },
1127};
1128
1129static struct clk_rcg2 nss_ubi0_clk_src = {
1130	.cmd_rcgr = 0x68104,
1131	.freq_tbl = ftbl_nss_ubi_clk_src,
1132	.hid_width = 5,
1133	.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1134	.clkr.hw.init = &(struct clk_init_data){
1135		.name = "nss_ubi0_clk_src",
1136		.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1137		.num_parents = 6,
1138		.ops = &clk_rcg2_ops,
1139		.flags = CLK_SET_RATE_PARENT,
1140	},
1141};
1142
1143static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
1144	F(24000000, P_XO, 1, 0, 0),
1145	F(100000000, P_GPLL0, 8, 0, 0),
1146	{ }
1147};
1148
1149static struct clk_rcg2 adss_pwm_clk_src = {
1150	.cmd_rcgr = 0x1c008,
1151	.freq_tbl = ftbl_adss_pwm_clk_src,
1152	.hid_width = 5,
1153	.parent_map = gcc_xo_gpll0_map,
1154	.clkr.hw.init = &(struct clk_init_data){
1155		.name = "adss_pwm_clk_src",
1156		.parent_data = gcc_xo_gpll0,
1157		.num_parents = 2,
1158		.ops = &clk_rcg2_ops,
1159	},
1160};
1161
1162static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
1163	F(24000000, P_XO, 1, 0, 0),
1164	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1165	F(50000000, P_GPLL0, 16, 0, 0),
1166	{ }
1167};
1168
1169static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
1170	.cmd_rcgr = 0x0200c,
1171	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1172	.hid_width = 5,
1173	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1174	.clkr.hw.init = &(struct clk_init_data){
1175		.name = "blsp1_qup1_i2c_apps_clk_src",
1176		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1177		.num_parents = 3,
1178		.ops = &clk_rcg2_ops,
1179	},
1180};
1181
1182static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
1183	F(960000, P_XO, 10, 2, 5),
1184	F(4800000, P_XO, 5, 0, 0),
1185	F(9600000, P_XO, 2, 4, 5),
1186	F(12500000, P_GPLL0_DIV2, 16, 1, 2),
1187	F(16000000, P_GPLL0, 10, 1, 5),
1188	F(24000000, P_XO, 1, 0, 0),
1189	F(25000000, P_GPLL0, 16, 1, 2),
1190	F(50000000, P_GPLL0, 16, 0, 0),
1191	{ }
1192};
1193
1194static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
1195	.cmd_rcgr = 0x02024,
1196	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1197	.mnd_width = 8,
1198	.hid_width = 5,
1199	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1200	.clkr.hw.init = &(struct clk_init_data){
1201		.name = "blsp1_qup1_spi_apps_clk_src",
1202		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1203		.num_parents = 3,
1204		.ops = &clk_rcg2_ops,
1205	},
1206};
1207
1208static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
1209	.cmd_rcgr = 0x03000,
1210	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1211	.hid_width = 5,
1212	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1213	.clkr.hw.init = &(struct clk_init_data){
1214		.name = "blsp1_qup2_i2c_apps_clk_src",
1215		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1216		.num_parents = 3,
1217		.ops = &clk_rcg2_ops,
1218	},
1219};
1220
1221static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
1222	.cmd_rcgr = 0x03014,
1223	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1224	.mnd_width = 8,
1225	.hid_width = 5,
1226	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1227	.clkr.hw.init = &(struct clk_init_data){
1228		.name = "blsp1_qup2_spi_apps_clk_src",
1229		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1230		.num_parents = 3,
1231		.ops = &clk_rcg2_ops,
1232	},
1233};
1234
1235static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
1236	.cmd_rcgr = 0x04000,
1237	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1238	.hid_width = 5,
1239	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1240	.clkr.hw.init = &(struct clk_init_data){
1241		.name = "blsp1_qup3_i2c_apps_clk_src",
1242		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1243		.num_parents = 3,
1244		.ops = &clk_rcg2_ops,
1245	},
1246};
1247
1248static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
1249	.cmd_rcgr = 0x04014,
1250	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1251	.mnd_width = 8,
1252	.hid_width = 5,
1253	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1254	.clkr.hw.init = &(struct clk_init_data){
1255		.name = "blsp1_qup3_spi_apps_clk_src",
1256		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1257		.num_parents = 3,
1258		.ops = &clk_rcg2_ops,
1259	},
1260};
1261
1262static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
1263	.cmd_rcgr = 0x05000,
1264	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1265	.hid_width = 5,
1266	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1267	.clkr.hw.init = &(struct clk_init_data){
1268		.name = "blsp1_qup4_i2c_apps_clk_src",
1269		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1270		.num_parents = 3,
1271		.ops = &clk_rcg2_ops,
1272	},
1273};
1274
1275static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
1276	.cmd_rcgr = 0x05014,
1277	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1278	.mnd_width = 8,
1279	.hid_width = 5,
1280	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1281	.clkr.hw.init = &(struct clk_init_data){
1282		.name = "blsp1_qup4_spi_apps_clk_src",
1283		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1284		.num_parents = 3,
1285		.ops = &clk_rcg2_ops,
1286	},
1287};
1288
1289static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
1290	.cmd_rcgr = 0x06000,
1291	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1292	.hid_width = 5,
1293	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1294	.clkr.hw.init = &(struct clk_init_data){
1295		.name = "blsp1_qup5_i2c_apps_clk_src",
1296		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1297		.num_parents = 3,
1298		.ops = &clk_rcg2_ops,
1299	},
1300};
1301
1302static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
1303	.cmd_rcgr = 0x06014,
1304	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1305	.mnd_width = 8,
1306	.hid_width = 5,
1307	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1308	.clkr.hw.init = &(struct clk_init_data){
1309		.name = "blsp1_qup5_spi_apps_clk_src",
1310		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1311		.num_parents = 3,
1312		.ops = &clk_rcg2_ops,
1313	},
1314};
1315
1316static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
1317	.cmd_rcgr = 0x07000,
1318	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1319	.hid_width = 5,
1320	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1321	.clkr.hw.init = &(struct clk_init_data){
1322		.name = "blsp1_qup6_i2c_apps_clk_src",
1323		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1324		.num_parents = 3,
1325		.ops = &clk_rcg2_ops,
1326	},
1327};
1328
1329static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
1330	.cmd_rcgr = 0x07014,
1331	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1332	.mnd_width = 8,
1333	.hid_width = 5,
1334	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1335	.clkr.hw.init = &(struct clk_init_data){
1336		.name = "blsp1_qup6_spi_apps_clk_src",
1337		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1338		.num_parents = 3,
1339		.ops = &clk_rcg2_ops,
1340	},
1341};
1342
1343static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
1344	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
1345	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
1346	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
1347	F(16000000, P_GPLL0_DIV2, 5, 1, 5),
1348	F(24000000, P_XO, 1, 0, 0),
1349	F(24000000, P_GPLL0, 1, 3, 100),
1350	F(25000000, P_GPLL0, 16, 1, 2),
1351	F(32000000, P_GPLL0, 1, 1, 25),
1352	F(40000000, P_GPLL0, 1, 1, 20),
1353	F(46400000, P_GPLL0, 1, 29, 500),
1354	F(48000000, P_GPLL0, 1, 3, 50),
1355	F(51200000, P_GPLL0, 1, 8, 125),
1356	F(56000000, P_GPLL0, 1, 7, 100),
1357	F(58982400, P_GPLL0, 1, 1152, 15625),
1358	F(60000000, P_GPLL0, 1, 3, 40),
1359	F(64000000, P_GPLL0, 12.5, 1, 1),
1360	{ }
1361};
1362
1363static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
1364	.cmd_rcgr = 0x02044,
1365	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1366	.mnd_width = 16,
1367	.hid_width = 5,
1368	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1369	.clkr.hw.init = &(struct clk_init_data){
1370		.name = "blsp1_uart1_apps_clk_src",
1371		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1372		.num_parents = 3,
1373		.ops = &clk_rcg2_ops,
1374	},
1375};
1376
1377static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1378	.cmd_rcgr = 0x03034,
1379	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1380	.mnd_width = 16,
1381	.hid_width = 5,
1382	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1383	.clkr.hw.init = &(struct clk_init_data){
1384		.name = "blsp1_uart2_apps_clk_src",
1385		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1386		.num_parents = 3,
1387		.ops = &clk_rcg2_ops,
1388	},
1389};
1390
1391static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
1392	.cmd_rcgr = 0x04034,
1393	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1394	.mnd_width = 16,
1395	.hid_width = 5,
1396	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1397	.clkr.hw.init = &(struct clk_init_data){
1398		.name = "blsp1_uart3_apps_clk_src",
1399		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1400		.num_parents = 3,
1401		.ops = &clk_rcg2_ops,
1402	},
1403};
1404
1405static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
1406	.cmd_rcgr = 0x05034,
1407	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1408	.mnd_width = 16,
1409	.hid_width = 5,
1410	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1411	.clkr.hw.init = &(struct clk_init_data){
1412		.name = "blsp1_uart4_apps_clk_src",
1413		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1414		.num_parents = 3,
1415		.ops = &clk_rcg2_ops,
1416	},
1417};
1418
1419static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
1420	.cmd_rcgr = 0x06034,
1421	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1422	.mnd_width = 16,
1423	.hid_width = 5,
1424	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1425	.clkr.hw.init = &(struct clk_init_data){
1426		.name = "blsp1_uart5_apps_clk_src",
1427		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1428		.num_parents = 3,
1429		.ops = &clk_rcg2_ops,
1430	},
1431};
1432
1433static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
1434	.cmd_rcgr = 0x07034,
1435	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1436	.mnd_width = 16,
1437	.hid_width = 5,
1438	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1439	.clkr.hw.init = &(struct clk_init_data){
1440		.name = "blsp1_uart6_apps_clk_src",
1441		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1442		.num_parents = 3,
1443		.ops = &clk_rcg2_ops,
1444	},
1445};
1446
1447static const struct freq_tbl ftbl_crypto_clk_src[] = {
1448	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1449	F(80000000, P_GPLL0, 10, 0, 0),
1450	F(100000000, P_GPLL0, 8, 0, 0),
1451	F(160000000, P_GPLL0, 5, 0, 0),
1452	{ }
1453};
1454
1455static struct clk_rcg2 crypto_clk_src = {
1456	.cmd_rcgr = 0x16004,
1457	.freq_tbl = ftbl_crypto_clk_src,
1458	.hid_width = 5,
1459	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1460	.clkr.hw.init = &(struct clk_init_data){
1461		.name = "crypto_clk_src",
1462		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1463		.num_parents = 3,
1464		.ops = &clk_rcg2_ops,
1465	},
1466};
1467
1468static const struct freq_tbl ftbl_gp_clk_src[] = {
1469	F(24000000, P_XO, 1, 0, 0),
1470	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1471	F(100000000, P_GPLL0, 8, 0, 0),
1472	F(200000000, P_GPLL0, 4, 0, 0),
1473	F(266666666, P_GPLL0, 3, 0, 0),
1474	{ }
1475};
1476
1477static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1478	{ .fw_name = "xo" },
1479	{ .hw = &gpll0.clkr.hw },
1480	{ .hw = &gpll6.clkr.hw },
1481	{ .hw = &gpll0_out_main_div2.hw },
1482	{ .fw_name = "sleep_clk" },
1483};
1484
1485static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1486	{ P_XO, 0 },
1487	{ P_GPLL0, 1 },
1488	{ P_GPLL6, 2 },
1489	{ P_GPLL0_DIV2, 4 },
1490	{ P_SLEEP_CLK, 6 },
1491};
1492
1493static struct clk_rcg2 gp1_clk_src = {
1494	.cmd_rcgr = 0x08004,
1495	.freq_tbl = ftbl_gp_clk_src,
1496	.mnd_width = 8,
1497	.hid_width = 5,
1498	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1499	.clkr.hw.init = &(struct clk_init_data){
1500		.name = "gp1_clk_src",
1501		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1502		.num_parents = 5,
1503		.ops = &clk_rcg2_ops,
1504	},
1505};
1506
1507static struct clk_rcg2 gp2_clk_src = {
1508	.cmd_rcgr = 0x09004,
1509	.freq_tbl = ftbl_gp_clk_src,
1510	.mnd_width = 8,
1511	.hid_width = 5,
1512	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1513	.clkr.hw.init = &(struct clk_init_data){
1514		.name = "gp2_clk_src",
1515		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1516		.num_parents = 5,
1517		.ops = &clk_rcg2_ops,
1518	},
1519};
1520
1521static struct clk_rcg2 gp3_clk_src = {
1522	.cmd_rcgr = 0x0a004,
1523	.freq_tbl = ftbl_gp_clk_src,
1524	.mnd_width = 8,
1525	.hid_width = 5,
1526	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1527	.clkr.hw.init = &(struct clk_init_data){
1528		.name = "gp3_clk_src",
1529		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1530		.num_parents = 5,
1531		.ops = &clk_rcg2_ops,
1532	},
1533};
1534
1535static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1536	.mult = 1,
1537	.div = 4,
1538	.hw.init = &(struct clk_init_data){
1539		.name = "nss_ppe_cdiv_clk_src",
1540		.parent_hws = (const struct clk_hw *[]){
1541				&nss_ppe_clk_src.clkr.hw },
1542		.num_parents = 1,
1543		.ops = &clk_fixed_factor_ops,
1544		.flags = CLK_SET_RATE_PARENT,
1545	},
1546};
1547
1548static struct clk_regmap_div nss_ubi0_div_clk_src = {
1549	.reg = 0x68118,
1550	.shift = 0,
1551	.width = 4,
1552	.clkr = {
1553		.hw.init = &(struct clk_init_data){
1554			.name = "nss_ubi0_div_clk_src",
1555			.parent_hws = (const struct clk_hw *[]){
1556				&nss_ubi0_clk_src.clkr.hw },
1557			.num_parents = 1,
1558			.ops = &clk_regmap_div_ro_ops,
1559			.flags = CLK_SET_RATE_PARENT,
1560		},
1561	},
1562};
1563
1564static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1565	F(24000000, P_XO, 1, 0, 0),
1566};
1567
1568static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
1569	{ .fw_name = "xo" },
1570	{ .hw = &gpll0.clkr.hw },
1571	{ .fw_name = "sleep_clk" },
1572};
1573
1574static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
1575	{ P_XO, 0 },
1576	{ P_GPLL0, 2 },
1577	{ P_PI_SLEEP, 6 },
1578};
1579
1580static struct clk_rcg2 pcie0_aux_clk_src = {
1581	.cmd_rcgr = 0x75024,
1582	.freq_tbl = ftbl_pcie_aux_clk_src,
1583	.mnd_width = 16,
1584	.hid_width = 5,
1585	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1586	.clkr.hw.init = &(struct clk_init_data){
1587		.name = "pcie0_aux_clk_src",
1588		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1589		.num_parents = 3,
1590		.ops = &clk_rcg2_ops,
1591	},
1592};
1593
1594static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
1595	{ .fw_name = "pcie20_phy0_pipe_clk" },
1596	{ .fw_name = "xo" },
1597};
1598
1599static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
1600	{ P_PCIE20_PHY0_PIPE, 0 },
1601	{ P_XO, 2 },
1602};
1603
1604static struct clk_regmap_mux pcie0_pipe_clk_src = {
1605	.reg = 0x7501c,
1606	.shift = 8,
1607	.width = 2,
1608	.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1609	.clkr = {
1610		.hw.init = &(struct clk_init_data){
1611			.name = "pcie0_pipe_clk_src",
1612			.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
1613			.num_parents = 2,
1614			.ops = &clk_regmap_mux_closest_ops,
1615			.flags = CLK_SET_RATE_PARENT,
1616		},
1617	},
1618};
1619
1620static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1621	F(144000, P_XO, 16, 12, 125),
1622	F(400000, P_XO, 12, 1, 5),
1623	F(24000000, P_GPLL2, 12, 1, 4),
1624	F(48000000, P_GPLL2, 12, 1, 2),
1625	F(96000000, P_GPLL2, 12, 0, 0),
1626	F(177777778, P_GPLL0, 4.5, 0, 0),
1627	F(192000000, P_GPLL2, 6, 0, 0),
1628	F(384000000, P_GPLL2, 3, 0, 0),
1629	{ }
1630};
1631
1632static const struct clk_parent_data
1633			gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
1634	{ .fw_name = "xo" },
1635	{ .hw = &gpll0.clkr.hw },
1636	{ .hw = &gpll2.clkr.hw },
1637	{ .hw = &gpll0_out_main_div2.hw },
1638};
1639
1640static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
1641	{ P_XO, 0 },
1642	{ P_GPLL0, 1 },
1643	{ P_GPLL2, 2 },
1644	{ P_GPLL0_DIV2, 4 },
1645};
1646
1647static struct clk_rcg2 sdcc1_apps_clk_src = {
1648	.cmd_rcgr = 0x42004,
1649	.freq_tbl = ftbl_sdcc_apps_clk_src,
1650	.mnd_width = 8,
1651	.hid_width = 5,
1652	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1653	.clkr.hw.init = &(struct clk_init_data){
1654		.name = "sdcc1_apps_clk_src",
1655		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1656		.num_parents = 4,
1657		.ops = &clk_rcg2_ops,
1658	},
1659};
1660
1661static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1662	F(24000000, P_XO, 1, 0, 0),
1663	{ }
1664};
1665
1666static struct clk_rcg2 usb0_aux_clk_src = {
1667	.cmd_rcgr = 0x3e05c,
1668	.freq_tbl = ftbl_usb_aux_clk_src,
1669	.mnd_width = 16,
1670	.hid_width = 5,
1671	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1672	.clkr.hw.init = &(struct clk_init_data){
1673		.name = "usb0_aux_clk_src",
1674		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1675		.num_parents = 3,
1676		.ops = &clk_rcg2_ops,
1677	},
1678};
1679
1680static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1681	F(24000000, P_XO, 1, 0, 0),
1682	F(60000000, P_GPLL6, 6, 1, 3),
1683	{ }
1684};
1685
1686static const struct clk_parent_data
1687			gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1688	{ .fw_name = "xo" },
1689	{ .hw = &gpll6.clkr.hw },
1690	{ .hw = &gpll0.clkr.hw },
1691	{ .hw = &gpll0_out_main_div2.hw },
1692};
1693
1694static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1695	{ P_XO, 0 },
1696	{ P_GPLL6, 1 },
1697	{ P_GPLL0, 3 },
1698	{ P_GPLL0_DIV2, 4 },
1699};
1700
1701static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1702	.cmd_rcgr = 0x3e020,
1703	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
1704	.mnd_width = 8,
1705	.hid_width = 5,
1706	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1707	.clkr.hw.init = &(struct clk_init_data){
1708		.name = "usb0_mock_utmi_clk_src",
1709		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1710		.num_parents = 4,
1711		.ops = &clk_rcg2_ops,
1712	},
1713};
1714
1715static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1716	{ .fw_name = "usb3phy_0_cc_pipe_clk" },
1717	{ .fw_name = "xo" },
1718};
1719
1720static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1721	{ P_USB3PHY_0_PIPE, 0 },
1722	{ P_XO, 2 },
1723};
1724
1725static struct clk_regmap_mux usb0_pipe_clk_src = {
1726	.reg = 0x3e048,
1727	.shift = 8,
1728	.width = 2,
1729	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1730	.clkr = {
1731		.hw.init = &(struct clk_init_data){
1732			.name = "usb0_pipe_clk_src",
1733			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1734			.num_parents = 2,
1735			.ops = &clk_regmap_mux_closest_ops,
1736			.flags = CLK_SET_RATE_PARENT,
1737		},
1738	},
1739};
1740
1741static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1742	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1743	F(160000000, P_GPLL0, 5, 0, 0),
1744	F(216000000, P_GPLL6, 5, 0, 0),
1745	F(308570000, P_GPLL6, 3.5, 0, 0),
1746};
1747
1748static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
1749	{ .fw_name = "xo"},
1750	{ .hw = &gpll0.clkr.hw },
1751	{ .hw = &gpll6.clkr.hw },
1752	{ .hw = &gpll0_out_main_div2.hw },
1753};
1754
1755static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
1756	{ P_XO, 0 },
1757	{ P_GPLL0, 1 },
1758	{ P_GPLL6, 2 },
1759	{ P_GPLL0_DIV2, 4 },
1760};
1761
1762static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1763	.cmd_rcgr = 0x5d000,
1764	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
1765	.mnd_width = 8,
1766	.hid_width = 5,
1767	.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1768	.clkr.hw.init = &(struct clk_init_data){
1769		.name = "sdcc1_ice_core_clk_src",
1770		.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
1771		.num_parents = 4,
1772		.ops = &clk_rcg2_ops,
1773	},
1774};
1775
1776static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1777	F(24000000, P_XO, 1, 0, 0),
1778	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1779	F(100000000, P_GPLL0, 8, 0, 0),
1780	F(200000000, P_GPLL0, 4, 0, 0),
1781	{ }
1782};
1783
1784static struct clk_rcg2 qdss_stm_clk_src = {
1785	.cmd_rcgr = 0x2902C,
1786	.freq_tbl = ftbl_qdss_stm_clk_src,
1787	.hid_width = 5,
1788	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1789	.clkr.hw.init = &(struct clk_init_data){
1790		.name = "qdss_stm_clk_src",
1791		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1792		.num_parents = 3,
1793		.ops = &clk_rcg2_ops,
1794	},
1795};
1796
1797static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1798	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1799	F(160000000, P_GPLL0, 5, 0, 0),
1800	F(300000000, P_GPLL4, 4, 0, 0),
1801	{ }
1802};
1803
1804static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
1805	{ .fw_name = "xo" },
1806	{ .hw = &gpll4.clkr.hw },
1807	{ .hw = &gpll0.clkr.hw },
1808	{ .hw = &gpll0_out_main_div2.hw },
1809};
1810
1811static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
1812	{ P_XO, 0 },
1813	{ P_GPLL4, 1 },
1814	{ P_GPLL0, 2 },
1815	{ P_GPLL0_DIV2, 4 },
1816};
1817
1818static struct clk_rcg2 qdss_traceclkin_clk_src = {
1819	.cmd_rcgr = 0x29048,
1820	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
1821	.hid_width = 5,
1822	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
1823	.clkr.hw.init = &(struct clk_init_data){
1824		.name = "qdss_traceclkin_clk_src",
1825		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
1826		.num_parents = 4,
1827		.ops = &clk_rcg2_ops,
1828	},
1829};
1830
1831static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1832	.cmd_rcgr = 0x3f020,
1833	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
1834	.mnd_width = 8,
1835	.hid_width = 5,
1836	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1837	.clkr.hw.init = &(struct clk_init_data){
1838		.name = "usb1_mock_utmi_clk_src",
1839		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1840		.num_parents = 4,
1841		.ops = &clk_rcg2_ops,
1842	},
1843};
1844
1845static struct clk_branch gcc_adss_pwm_clk = {
1846	.halt_reg = 0x1c020,
1847	.clkr = {
1848		.enable_reg = 0x1c020,
1849		.enable_mask = BIT(0),
1850		.hw.init = &(struct clk_init_data){
1851			.name = "gcc_adss_pwm_clk",
1852			.parent_hws = (const struct clk_hw *[]){
1853					&adss_pwm_clk_src.clkr.hw },
1854			.num_parents = 1,
1855			.flags = CLK_SET_RATE_PARENT,
1856			.ops = &clk_branch2_ops,
1857		},
1858	},
1859};
1860
1861static struct clk_branch gcc_apss_ahb_clk = {
1862	.halt_reg = 0x4601c,
1863	.halt_check = BRANCH_HALT_VOTED,
1864	.clkr = {
1865		.enable_reg = 0x0b004,
1866		.enable_mask = BIT(14),
1867		.hw.init = &(struct clk_init_data){
1868			.name = "gcc_apss_ahb_clk",
1869			.parent_hws = (const struct clk_hw *[]){
1870					&apss_ahb_postdiv_clk_src.clkr.hw },
1871			.num_parents = 1,
1872			.flags = CLK_SET_RATE_PARENT,
1873			.ops = &clk_branch2_ops,
1874		},
1875	},
1876};
1877
1878static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1879	F(24000000, P_XO, 1, 0, 0),
1880	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1881	F(100000000, P_GPLL0, 8, 0, 0),
1882	F(133333333, P_GPLL0, 6, 0, 0),
1883	F(160000000, P_GPLL0, 5, 0, 0),
1884	F(200000000, P_GPLL0, 4, 0, 0),
1885	F(266666667, P_GPLL0, 3, 0, 0),
1886	{ }
1887};
1888
1889static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1890	.cmd_rcgr = 0x26004,
1891	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1892	.hid_width = 5,
1893	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1894	.clkr.hw.init = &(struct clk_init_data){
1895		.name = "system_noc_bfdcd_clk_src",
1896		.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1897		.num_parents = 4,
1898		.ops = &clk_rcg2_ops,
1899	},
1900};
1901
1902static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
1903	F(24000000, P_XO, 1, 0, 0),
1904	F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1905	F(533333333, P_GPLL0, 1.5, 0, 0),
1906	{ }
1907};
1908
1909static const struct clk_parent_data
1910			gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
1911	{ .fw_name = "xo" },
1912	{ .hw = &gpll0.clkr.hw },
1913	{ .hw = &gpll2.clkr.hw },
1914	{ .fw_name = "bias_pll_nss_noc_clk" },
1915};
1916
1917static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
1918	{ P_XO, 0 },
1919	{ P_GPLL0, 1 },
1920	{ P_GPLL2, 3 },
1921	{ P_BIAS_PLL_NSS_NOC, 4 },
1922};
1923
1924static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
1925	.cmd_rcgr = 0x68088,
1926	.freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
1927	.hid_width = 5,
1928	.parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
1929	.clkr.hw.init = &(struct clk_init_data){
1930		.name = "ubi32_mem_noc_bfdcd_clk_src",
1931		.parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
1932		.num_parents = 4,
1933		.ops = &clk_rcg2_ops,
1934	},
1935};
1936
1937static struct clk_branch gcc_apss_axi_clk = {
1938	.halt_reg = 0x46020,
1939	.halt_check = BRANCH_HALT_VOTED,
1940	.clkr = {
1941		.enable_reg = 0x0b004,
1942		.enable_mask = BIT(13),
1943		.hw.init = &(struct clk_init_data){
1944			.name = "gcc_apss_axi_clk",
1945			.parent_hws = (const struct clk_hw *[]){
1946					&apss_axi_clk_src.clkr.hw },
1947			.num_parents = 1,
1948			.flags = CLK_SET_RATE_PARENT,
1949			.ops = &clk_branch2_ops,
1950		},
1951	},
1952};
1953
1954static struct clk_branch gcc_blsp1_ahb_clk = {
1955	.halt_reg = 0x01008,
1956	.halt_check = BRANCH_HALT_VOTED,
1957	.clkr = {
1958		.enable_reg = 0x0b004,
1959		.enable_mask = BIT(10),
1960		.hw.init = &(struct clk_init_data){
1961			.name = "gcc_blsp1_ahb_clk",
1962			.parent_hws = (const struct clk_hw *[]){
1963					&pcnoc_bfdcd_clk_src.clkr.hw },
1964			.num_parents = 1,
1965			.flags = CLK_SET_RATE_PARENT,
1966			.ops = &clk_branch2_ops,
1967		},
1968	},
1969};
1970
1971static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1972	.halt_reg = 0x02008,
1973	.clkr = {
1974		.enable_reg = 0x02008,
1975		.enable_mask = BIT(0),
1976		.hw.init = &(struct clk_init_data){
1977			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1978			.parent_hws = (const struct clk_hw *[]){
1979					&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1980			.num_parents = 1,
1981			.flags = CLK_SET_RATE_PARENT,
1982			.ops = &clk_branch2_ops,
1983		},
1984	},
1985};
1986
1987static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1988	.halt_reg = 0x02004,
1989	.clkr = {
1990		.enable_reg = 0x02004,
1991		.enable_mask = BIT(0),
1992		.hw.init = &(struct clk_init_data){
1993			.name = "gcc_blsp1_qup1_spi_apps_clk",
1994			.parent_hws = (const struct clk_hw *[]){
1995					&blsp1_qup1_spi_apps_clk_src.clkr.hw },
1996			.num_parents = 1,
1997			.flags = CLK_SET_RATE_PARENT,
1998			.ops = &clk_branch2_ops,
1999		},
2000	},
2001};
2002
2003static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2004	.halt_reg = 0x03010,
2005	.clkr = {
2006		.enable_reg = 0x03010,
2007		.enable_mask = BIT(0),
2008		.hw.init = &(struct clk_init_data){
2009			.name = "gcc_blsp1_qup2_i2c_apps_clk",
2010			.parent_hws = (const struct clk_hw *[]){
2011					&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2012			.num_parents = 1,
2013			.flags = CLK_SET_RATE_PARENT,
2014			.ops = &clk_branch2_ops,
2015		},
2016	},
2017};
2018
2019static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2020	.halt_reg = 0x0300c,
2021	.clkr = {
2022		.enable_reg = 0x0300c,
2023		.enable_mask = BIT(0),
2024		.hw.init = &(struct clk_init_data){
2025			.name = "gcc_blsp1_qup2_spi_apps_clk",
2026			.parent_hws = (const struct clk_hw *[]){
2027					&blsp1_qup2_spi_apps_clk_src.clkr.hw },
2028			.num_parents = 1,
2029			.flags = CLK_SET_RATE_PARENT,
2030			.ops = &clk_branch2_ops,
2031		},
2032	},
2033};
2034
2035static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2036	.halt_reg = 0x04010,
2037	.clkr = {
2038		.enable_reg = 0x04010,
2039		.enable_mask = BIT(0),
2040		.hw.init = &(struct clk_init_data){
2041			.name = "gcc_blsp1_qup3_i2c_apps_clk",
2042			.parent_hws = (const struct clk_hw *[]){
2043					&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2044			.num_parents = 1,
2045			.flags = CLK_SET_RATE_PARENT,
2046			.ops = &clk_branch2_ops,
2047		},
2048	},
2049};
2050
2051static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2052	.halt_reg = 0x0400c,
2053	.clkr = {
2054		.enable_reg = 0x0400c,
2055		.enable_mask = BIT(0),
2056		.hw.init = &(struct clk_init_data){
2057			.name = "gcc_blsp1_qup3_spi_apps_clk",
2058			.parent_hws = (const struct clk_hw *[]){
2059					&blsp1_qup3_spi_apps_clk_src.clkr.hw },
2060			.num_parents = 1,
2061			.flags = CLK_SET_RATE_PARENT,
2062			.ops = &clk_branch2_ops,
2063		},
2064	},
2065};
2066
2067static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2068	.halt_reg = 0x05010,
2069	.clkr = {
2070		.enable_reg = 0x05010,
2071		.enable_mask = BIT(0),
2072		.hw.init = &(struct clk_init_data){
2073			.name = "gcc_blsp1_qup4_i2c_apps_clk",
2074			.parent_hws = (const struct clk_hw *[]){
2075					&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2076			.num_parents = 1,
2077			.flags = CLK_SET_RATE_PARENT,
2078			.ops = &clk_branch2_ops,
2079		},
2080	},
2081};
2082
2083static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2084	.halt_reg = 0x0500c,
2085	.clkr = {
2086		.enable_reg = 0x0500c,
2087		.enable_mask = BIT(0),
2088		.hw.init = &(struct clk_init_data){
2089			.name = "gcc_blsp1_qup4_spi_apps_clk",
2090			.parent_hws = (const struct clk_hw *[]){
2091					&blsp1_qup4_spi_apps_clk_src.clkr.hw },
2092			.num_parents = 1,
2093			.flags = CLK_SET_RATE_PARENT,
2094			.ops = &clk_branch2_ops,
2095		},
2096	},
2097};
2098
2099static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2100	.halt_reg = 0x06010,
2101	.clkr = {
2102		.enable_reg = 0x06010,
2103		.enable_mask = BIT(0),
2104		.hw.init = &(struct clk_init_data){
2105			.name = "gcc_blsp1_qup5_i2c_apps_clk",
2106			.parent_hws = (const struct clk_hw *[]){
2107					&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2108			.num_parents = 1,
2109			.flags = CLK_SET_RATE_PARENT,
2110			.ops = &clk_branch2_ops,
2111		},
2112	},
2113};
2114
2115static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2116	.halt_reg = 0x0600c,
2117	.clkr = {
2118		.enable_reg = 0x0600c,
2119		.enable_mask = BIT(0),
2120		.hw.init = &(struct clk_init_data){
2121			.name = "gcc_blsp1_qup5_spi_apps_clk",
2122			.parent_hws = (const struct clk_hw *[]){
2123					&blsp1_qup5_spi_apps_clk_src.clkr.hw },
2124			.num_parents = 1,
2125			.flags = CLK_SET_RATE_PARENT,
2126			.ops = &clk_branch2_ops,
2127		},
2128	},
2129};
2130
2131static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2132	.halt_reg = 0x0700c,
2133	.clkr = {
2134		.enable_reg = 0x0700c,
2135		.enable_mask = BIT(0),
2136		.hw.init = &(struct clk_init_data){
2137			.name = "gcc_blsp1_qup6_spi_apps_clk",
2138			.parent_hws = (const struct clk_hw *[]){
2139					&blsp1_qup6_spi_apps_clk_src.clkr.hw },
2140			.num_parents = 1,
2141			.flags = CLK_SET_RATE_PARENT,
2142			.ops = &clk_branch2_ops,
2143		},
2144	},
2145};
2146
2147static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2148	.halt_reg = 0x0203c,
2149	.clkr = {
2150		.enable_reg = 0x0203c,
2151		.enable_mask = BIT(0),
2152		.hw.init = &(struct clk_init_data){
2153			.name = "gcc_blsp1_uart1_apps_clk",
2154			.parent_hws = (const struct clk_hw *[]){
2155					&blsp1_uart1_apps_clk_src.clkr.hw },
2156			.num_parents = 1,
2157			.flags = CLK_SET_RATE_PARENT,
2158			.ops = &clk_branch2_ops,
2159		},
2160	},
2161};
2162
2163static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2164	.halt_reg = 0x0302c,
2165	.clkr = {
2166		.enable_reg = 0x0302c,
2167		.enable_mask = BIT(0),
2168		.hw.init = &(struct clk_init_data){
2169			.name = "gcc_blsp1_uart2_apps_clk",
2170			.parent_hws = (const struct clk_hw *[]){
2171					&blsp1_uart2_apps_clk_src.clkr.hw },
2172			.num_parents = 1,
2173			.flags = CLK_SET_RATE_PARENT,
2174			.ops = &clk_branch2_ops,
2175		},
2176	},
2177};
2178
2179static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2180	.halt_reg = 0x0402c,
2181	.clkr = {
2182		.enable_reg = 0x0402c,
2183		.enable_mask = BIT(0),
2184		.hw.init = &(struct clk_init_data){
2185			.name = "gcc_blsp1_uart3_apps_clk",
2186			.parent_hws = (const struct clk_hw *[]){
2187					&blsp1_uart3_apps_clk_src.clkr.hw },
2188			.num_parents = 1,
2189			.flags = CLK_SET_RATE_PARENT,
2190			.ops = &clk_branch2_ops,
2191		},
2192	},
2193};
2194
2195static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2196	.halt_reg = 0x0502c,
2197	.clkr = {
2198		.enable_reg = 0x0502c,
2199		.enable_mask = BIT(0),
2200		.hw.init = &(struct clk_init_data){
2201			.name = "gcc_blsp1_uart4_apps_clk",
2202			.parent_hws = (const struct clk_hw *[]){
2203					&blsp1_uart4_apps_clk_src.clkr.hw },
2204			.num_parents = 1,
2205			.flags = CLK_SET_RATE_PARENT,
2206			.ops = &clk_branch2_ops,
2207		},
2208	},
2209};
2210
2211static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2212	.halt_reg = 0x0602c,
2213	.clkr = {
2214		.enable_reg = 0x0602c,
2215		.enable_mask = BIT(0),
2216		.hw.init = &(struct clk_init_data){
2217			.name = "gcc_blsp1_uart5_apps_clk",
2218			.parent_hws = (const struct clk_hw *[]){
2219					&blsp1_uart5_apps_clk_src.clkr.hw },
2220			.num_parents = 1,
2221			.flags = CLK_SET_RATE_PARENT,
2222			.ops = &clk_branch2_ops,
2223		},
2224	},
2225};
2226
2227static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2228	.halt_reg = 0x0702c,
2229	.clkr = {
2230		.enable_reg = 0x0702c,
2231		.enable_mask = BIT(0),
2232		.hw.init = &(struct clk_init_data){
2233			.name = "gcc_blsp1_uart6_apps_clk",
2234			.parent_hws = (const struct clk_hw *[]){
2235					&blsp1_uart6_apps_clk_src.clkr.hw },
2236			.num_parents = 1,
2237			.flags = CLK_SET_RATE_PARENT,
2238			.ops = &clk_branch2_ops,
2239		},
2240	},
2241};
2242
2243static struct clk_branch gcc_crypto_ahb_clk = {
2244	.halt_reg = 0x16024,
2245	.halt_check = BRANCH_HALT_VOTED,
2246	.clkr = {
2247		.enable_reg = 0x0b004,
2248		.enable_mask = BIT(0),
2249		.hw.init = &(struct clk_init_data){
2250			.name = "gcc_crypto_ahb_clk",
2251			.parent_hws = (const struct clk_hw *[]){
2252					&pcnoc_bfdcd_clk_src.clkr.hw },
2253			.num_parents = 1,
2254			.flags = CLK_SET_RATE_PARENT,
2255			.ops = &clk_branch2_ops,
2256		},
2257	},
2258};
2259
2260static struct clk_branch gcc_crypto_axi_clk = {
2261	.halt_reg = 0x16020,
2262	.halt_check = BRANCH_HALT_VOTED,
2263	.clkr = {
2264		.enable_reg = 0x0b004,
2265		.enable_mask = BIT(1),
2266		.hw.init = &(struct clk_init_data){
2267			.name = "gcc_crypto_axi_clk",
2268			.parent_hws = (const struct clk_hw *[]){
2269					&pcnoc_bfdcd_clk_src.clkr.hw },
2270			.num_parents = 1,
2271			.flags = CLK_SET_RATE_PARENT,
2272			.ops = &clk_branch2_ops,
2273		},
2274	},
2275};
2276
2277static struct clk_branch gcc_crypto_clk = {
2278	.halt_reg = 0x1601c,
2279	.halt_check = BRANCH_HALT_VOTED,
2280	.clkr = {
2281		.enable_reg = 0x0b004,
2282		.enable_mask = BIT(2),
2283		.hw.init = &(struct clk_init_data){
2284			.name = "gcc_crypto_clk",
2285			.parent_hws = (const struct clk_hw *[]){
2286					&crypto_clk_src.clkr.hw },
2287			.num_parents = 1,
2288			.flags = CLK_SET_RATE_PARENT,
2289			.ops = &clk_branch2_ops,
2290		},
2291	},
2292};
2293
2294static struct clk_fixed_factor gpll6_out_main_div2 = {
2295	.mult = 1,
2296	.div = 2,
2297	.hw.init = &(struct clk_init_data){
2298		.name = "gpll6_out_main_div2",
2299		.parent_hws = (const struct clk_hw *[]){
2300				&gpll6_main.clkr.hw },
2301		.num_parents = 1,
2302		.ops = &clk_fixed_factor_ops,
2303		.flags = CLK_SET_RATE_PARENT,
2304	},
2305};
2306
2307static struct clk_branch gcc_xo_clk = {
2308	.halt_reg = 0x30030,
2309	.clkr = {
2310		.enable_reg = 0x30030,
2311		.enable_mask = BIT(0),
2312		.hw.init = &(struct clk_init_data){
2313			.name = "gcc_xo_clk",
2314			.parent_hws = (const struct clk_hw *[]){
2315					&gcc_xo_clk_src.clkr.hw },
2316			.num_parents = 1,
2317			.flags = CLK_SET_RATE_PARENT,
2318			.ops = &clk_branch2_ops,
2319		},
2320	},
2321};
2322
2323static struct clk_branch gcc_gp1_clk = {
2324	.halt_reg = 0x08000,
2325	.clkr = {
2326		.enable_reg = 0x08000,
2327		.enable_mask = BIT(0),
2328		.hw.init = &(struct clk_init_data){
2329			.name = "gcc_gp1_clk",
2330			.parent_hws = (const struct clk_hw *[]){
2331					&gp1_clk_src.clkr.hw },
2332			.num_parents = 1,
2333			.flags = CLK_SET_RATE_PARENT,
2334			.ops = &clk_branch2_ops,
2335		},
2336	},
2337};
2338
2339static struct clk_branch gcc_gp2_clk = {
2340	.halt_reg = 0x09000,
2341	.clkr = {
2342		.enable_reg = 0x09000,
2343		.enable_mask = BIT(0),
2344		.hw.init = &(struct clk_init_data){
2345			.name = "gcc_gp2_clk",
2346			.parent_hws = (const struct clk_hw *[]){
2347					&gp2_clk_src.clkr.hw },
2348			.num_parents = 1,
2349			.flags = CLK_SET_RATE_PARENT,
2350			.ops = &clk_branch2_ops,
2351		},
2352	},
2353};
2354
2355static struct clk_branch gcc_gp3_clk = {
2356	.halt_reg = 0x0a000,
2357	.clkr = {
2358		.enable_reg = 0x0a000,
2359		.enable_mask = BIT(0),
2360		.hw.init = &(struct clk_init_data){
2361			.name = "gcc_gp3_clk",
2362			.parent_hws = (const struct clk_hw *[]){
2363					&gp3_clk_src.clkr.hw },
2364			.num_parents = 1,
2365			.flags = CLK_SET_RATE_PARENT,
2366			.ops = &clk_branch2_ops,
2367		},
2368	},
2369};
2370
2371static struct clk_branch gcc_mdio_ahb_clk = {
2372	.halt_reg = 0x58004,
2373	.clkr = {
2374		.enable_reg = 0x58004,
2375		.enable_mask = BIT(0),
2376		.hw.init = &(struct clk_init_data){
2377			.name = "gcc_mdio_ahb_clk",
2378			.parent_hws = (const struct clk_hw *[]){
2379					&pcnoc_bfdcd_clk_src.clkr.hw },
2380			.num_parents = 1,
2381			.flags = CLK_SET_RATE_PARENT,
2382			.ops = &clk_branch2_ops,
2383		},
2384	},
2385};
2386
2387static struct clk_branch gcc_crypto_ppe_clk = {
2388	.halt_reg = 0x68310,
2389	.clkr = {
2390		.enable_reg = 0x68310,
2391		.enable_mask = BIT(0),
2392		.hw.init = &(struct clk_init_data){
2393			.name = "gcc_crypto_ppe_clk",
2394			.parent_hws = (const struct clk_hw *[]){
2395					&nss_ppe_clk_src.clkr.hw },
2396			.num_parents = 1,
2397			.flags = CLK_SET_RATE_PARENT,
2398			.ops = &clk_branch2_ops,
2399		},
2400	},
2401};
2402
2403static struct clk_branch gcc_nss_ce_apb_clk = {
2404	.halt_reg = 0x68174,
2405	.clkr = {
2406		.enable_reg = 0x68174,
2407		.enable_mask = BIT(0),
2408		.hw.init = &(struct clk_init_data){
2409			.name = "gcc_nss_ce_apb_clk",
2410			.parent_hws = (const struct clk_hw *[]){
2411					&nss_ce_clk_src.clkr.hw },
2412			.num_parents = 1,
2413			.flags = CLK_SET_RATE_PARENT,
2414			.ops = &clk_branch2_ops,
2415		},
2416	},
2417};
2418
2419static struct clk_branch gcc_nss_ce_axi_clk = {
2420	.halt_reg = 0x68170,
2421	.clkr = {
2422		.enable_reg = 0x68170,
2423		.enable_mask = BIT(0),
2424		.hw.init = &(struct clk_init_data){
2425			.name = "gcc_nss_ce_axi_clk",
2426			.parent_hws = (const struct clk_hw *[]){
2427					&nss_ce_clk_src.clkr.hw },
2428			.num_parents = 1,
2429			.flags = CLK_SET_RATE_PARENT,
2430			.ops = &clk_branch2_ops,
2431		},
2432	},
2433};
2434
2435static struct clk_branch gcc_nss_cfg_clk = {
2436	.halt_reg = 0x68160,
2437	.clkr = {
2438		.enable_reg = 0x68160,
2439		.enable_mask = BIT(0),
2440		.hw.init = &(struct clk_init_data){
2441			.name = "gcc_nss_cfg_clk",
2442			.parent_hws = (const struct clk_hw *[]){
2443					&pcnoc_bfdcd_clk_src.clkr.hw },
2444			.num_parents = 1,
2445			.flags = CLK_SET_RATE_PARENT,
2446			.ops = &clk_branch2_ops,
2447		},
2448	},
2449};
2450
2451static struct clk_branch gcc_nss_crypto_clk = {
2452	.halt_reg = 0x68164,
2453	.clkr = {
2454		.enable_reg = 0x68164,
2455		.enable_mask = BIT(0),
2456		.hw.init = &(struct clk_init_data){
2457			.name = "gcc_nss_crypto_clk",
2458			.parent_hws = (const struct clk_hw *[]){
2459					&nss_crypto_clk_src.clkr.hw },
2460			.num_parents = 1,
2461			.flags = CLK_SET_RATE_PARENT,
2462			.ops = &clk_branch2_ops,
2463		},
2464	},
2465};
2466
2467static struct clk_branch gcc_nss_csr_clk = {
2468	.halt_reg = 0x68318,
2469	.clkr = {
2470		.enable_reg = 0x68318,
2471		.enable_mask = BIT(0),
2472		.hw.init = &(struct clk_init_data){
2473			.name = "gcc_nss_csr_clk",
2474			.parent_hws = (const struct clk_hw *[]){
2475					&nss_ce_clk_src.clkr.hw },
2476			.num_parents = 1,
2477			.flags = CLK_SET_RATE_PARENT,
2478			.ops = &clk_branch2_ops,
2479		},
2480	},
2481};
2482
2483static struct clk_branch gcc_nss_edma_cfg_clk = {
2484	.halt_reg = 0x6819C,
2485	.clkr = {
2486		.enable_reg = 0x6819C,
2487		.enable_mask = BIT(0),
2488		.hw.init = &(struct clk_init_data){
2489			.name = "gcc_nss_edma_cfg_clk",
2490			.parent_hws = (const struct clk_hw *[]){
2491					&nss_ppe_clk_src.clkr.hw },
2492			.num_parents = 1,
2493			.flags = CLK_SET_RATE_PARENT,
2494			.ops = &clk_branch2_ops,
2495		},
2496	},
2497};
2498
2499static struct clk_branch gcc_nss_edma_clk = {
2500	.halt_reg = 0x68198,
2501	.clkr = {
2502		.enable_reg = 0x68198,
2503		.enable_mask = BIT(0),
2504		.hw.init = &(struct clk_init_data){
2505			.name = "gcc_nss_edma_clk",
2506			.parent_hws = (const struct clk_hw *[]){
2507					&nss_ppe_clk_src.clkr.hw },
2508			.num_parents = 1,
2509			.flags = CLK_SET_RATE_PARENT,
2510			.ops = &clk_branch2_ops,
2511		},
2512	},
2513};
2514
2515static struct clk_branch gcc_nss_noc_clk = {
2516	.halt_reg = 0x68168,
2517	.clkr = {
2518		.enable_reg = 0x68168,
2519		.enable_mask = BIT(0),
2520		.hw.init = &(struct clk_init_data){
2521			.name = "gcc_nss_noc_clk",
2522			.parent_hws = (const struct clk_hw *[]){
2523					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2524			.num_parents = 1,
2525			.flags = CLK_SET_RATE_PARENT,
2526			.ops = &clk_branch2_ops,
2527		},
2528	},
2529};
2530
2531static struct clk_branch gcc_ubi0_utcm_clk = {
2532	.halt_reg = 0x2606c,
2533	.clkr = {
2534		.enable_reg = 0x2606c,
2535		.enable_mask = BIT(0),
2536		.hw.init = &(struct clk_init_data){
2537			.name = "gcc_ubi0_utcm_clk",
2538			.parent_hws = (const struct clk_hw *[]){
2539					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2540			.num_parents = 1,
2541			.flags = CLK_SET_RATE_PARENT,
2542			.ops = &clk_branch2_ops,
2543		},
2544	},
2545};
2546
2547static struct clk_branch gcc_snoc_nssnoc_clk = {
2548	.halt_reg = 0x26070,
2549	.clkr = {
2550		.enable_reg = 0x26070,
2551		.enable_mask = BIT(0),
2552		.hw.init = &(struct clk_init_data){
2553			.name = "gcc_snoc_nssnoc_clk",
2554			.parent_hws = (const struct clk_hw *[]){
2555					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2556			.num_parents = 1,
2557			.flags = CLK_SET_RATE_PARENT,
2558			.ops = &clk_branch2_ops,
2559		},
2560	},
2561};
2562
2563static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2564	F(24000000, P_XO, 1, 0, 0),
2565	F(133333333, P_GPLL0, 6, 0, 0),
2566	{ }
2567};
2568
2569static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
2570	F(24000000, P_XO, 1, 0, 0),
2571	F(400000000, P_GPLL0, 2, 0, 0),
2572	{ }
2573};
2574
2575static struct clk_rcg2 wcss_ahb_clk_src = {
2576	.cmd_rcgr = 0x59020,
2577	.freq_tbl = ftbl_wcss_ahb_clk_src,
2578	.hid_width = 5,
2579	.parent_map = gcc_xo_gpll0_map,
2580	.clkr.hw.init = &(struct clk_init_data){
2581		.name = "wcss_ahb_clk_src",
2582		.parent_data = gcc_xo_gpll0,
2583		.num_parents = 2,
2584		.ops = &clk_rcg2_ops,
2585	},
2586};
2587
2588static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
2589	{ .fw_name = "xo" },
2590	{ .hw = &gpll0.clkr.hw },
2591	{ .hw = &gpll2.clkr.hw },
2592	{ .hw = &gpll4.clkr.hw },
2593	{ .hw = &gpll6.clkr.hw },
2594};
2595
2596static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
2597	{ P_XO, 0 },
2598	{ P_GPLL0, 1 },
2599	{ P_GPLL2, 2 },
2600	{ P_GPLL4, 3 },
2601	{ P_GPLL6, 4 },
2602};
2603
2604static struct clk_rcg2 q6_axi_clk_src = {
2605	.cmd_rcgr = 0x59120,
2606	.freq_tbl = ftbl_q6_axi_clk_src,
2607	.hid_width = 5,
2608	.parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
2609	.clkr.hw.init = &(struct clk_init_data){
2610		.name = "q6_axi_clk_src",
2611		.parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
2612		.num_parents = 5,
2613		.ops = &clk_rcg2_ops,
2614	},
2615};
2616
2617static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
2618	F(24000000, P_XO, 1, 0, 0),
2619	F(100000000, P_GPLL0, 8, 0, 0),
2620	{ }
2621};
2622
2623static struct clk_rcg2 lpass_core_axim_clk_src = {
2624	.cmd_rcgr = 0x1F020,
2625	.freq_tbl = ftbl_lpass_core_axim_clk_src,
2626	.hid_width = 5,
2627	.parent_map = gcc_xo_gpll0_map,
2628	.clkr.hw.init = &(struct clk_init_data){
2629		.name = "lpass_core_axim_clk_src",
2630		.parent_data = gcc_xo_gpll0,
2631		.num_parents = 2,
2632		.ops = &clk_rcg2_ops,
2633	},
2634};
2635
2636static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
2637	F(24000000, P_XO, 1, 0, 0),
2638	F(266666667, P_GPLL0, 3, 0, 0),
2639	{ }
2640};
2641
2642static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
2643	.cmd_rcgr = 0x1F040,
2644	.freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
2645	.hid_width = 5,
2646	.parent_map = gcc_xo_gpll0_map,
2647	.clkr.hw.init = &(struct clk_init_data){
2648		.name = "lpass_snoc_cfg_clk_src",
2649		.parent_data = gcc_xo_gpll0,
2650		.num_parents = 2,
2651		.ops = &clk_rcg2_ops,
2652	},
2653};
2654
2655static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
2656	F(24000000, P_XO, 1, 0, 0),
2657	F(400000000, P_GPLL0, 2, 0, 0),
2658	{ }
2659};
2660
2661static struct clk_rcg2 lpass_q6_axim_clk_src = {
2662	.cmd_rcgr = 0x1F008,
2663	.freq_tbl = ftbl_lpass_q6_axim_clk_src,
2664	.hid_width = 5,
2665	.parent_map = gcc_xo_gpll0_map,
2666	.clkr.hw.init = &(struct clk_init_data){
2667		.name = "lpass_q6_axim_clk_src",
2668		.parent_data = gcc_xo_gpll0,
2669		.num_parents = 2,
2670		.ops = &clk_rcg2_ops,
2671	},
2672};
2673
2674static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
2675	F(24000000, P_XO, 1, 0, 0),
2676	F(50000000, P_GPLL0, 16, 0, 0),
2677	{ }
2678};
2679
2680static struct clk_rcg2 rbcpr_wcss_clk_src = {
2681	.cmd_rcgr = 0x3a00c,
2682	.freq_tbl = ftbl_rbcpr_wcss_clk_src,
2683	.hid_width = 5,
2684	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
2685	.clkr.hw.init = &(struct clk_init_data){
2686		.name = "rbcpr_wcss_clk_src",
2687		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
2688		.num_parents = 3,
2689		.ops = &clk_rcg2_ops,
2690	},
2691};
2692
2693static struct clk_branch gcc_lpass_core_axim_clk = {
2694	.halt_reg = 0x1F028,
2695	.clkr = {
2696		.enable_reg = 0x1F028,
2697		.enable_mask = BIT(0),
2698		.hw.init = &(struct clk_init_data){
2699			.name = "gcc_lpass_core_axim_clk",
2700			.parent_hws = (const struct clk_hw *[]){
2701					&lpass_core_axim_clk_src.clkr.hw },
2702			.num_parents = 1,
2703			.flags = CLK_SET_RATE_PARENT,
2704			.ops = &clk_branch2_ops,
2705		},
2706	},
2707};
2708
2709static struct clk_branch gcc_lpass_snoc_cfg_clk = {
2710	.halt_reg = 0x1F048,
2711	.clkr = {
2712		.enable_reg = 0x1F048,
2713		.enable_mask = BIT(0),
2714		.hw.init = &(struct clk_init_data){
2715			.name = "gcc_lpass_snoc_cfg_clk",
2716			.parent_hws = (const struct clk_hw *[]){
2717					&lpass_snoc_cfg_clk_src.clkr.hw },
2718			.num_parents = 1,
2719			.flags = CLK_SET_RATE_PARENT,
2720			.ops = &clk_branch2_ops,
2721		},
2722	},
2723};
2724
2725static struct clk_branch gcc_lpass_q6_axim_clk = {
2726	.halt_reg = 0x1F010,
2727	.clkr = {
2728		.enable_reg = 0x1F010,
2729		.enable_mask = BIT(0),
2730		.hw.init = &(struct clk_init_data){
2731			.name = "gcc_lpass_q6_axim_clk",
2732			.parent_hws = (const struct clk_hw *[]){
2733					&lpass_q6_axim_clk_src.clkr.hw },
2734			.num_parents = 1,
2735			.flags = CLK_SET_RATE_PARENT,
2736			.ops = &clk_branch2_ops,
2737		},
2738	},
2739};
2740
2741static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
2742	.halt_reg = 0x1F018,
2743	.clkr = {
2744		.enable_reg = 0x1F018,
2745		.enable_mask = BIT(0),
2746		.hw.init = &(struct clk_init_data){
2747			.name = "gcc_lpass_q6_atbm_at_clk",
2748			.parent_hws = (const struct clk_hw *[]){
2749					&qdss_at_clk_src.clkr.hw },
2750			.num_parents = 1,
2751			.flags = CLK_SET_RATE_PARENT,
2752			.ops = &clk_branch2_ops,
2753		},
2754	},
2755};
2756
2757static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
2758	.halt_reg = 0x1F01C,
2759	.clkr = {
2760		.enable_reg = 0x1F01C,
2761		.enable_mask = BIT(0),
2762		.hw.init = &(struct clk_init_data){
2763			.name = "gcc_lpass_q6_pclkdbg_clk",
2764			.parent_hws = (const struct clk_hw *[]){
2765					&qdss_dap_sync_clk_src.hw },
2766			.num_parents = 1,
2767			.flags = CLK_SET_RATE_PARENT,
2768			.ops = &clk_branch2_ops,
2769		},
2770	},
2771};
2772
2773static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
2774	.halt_reg = 0x1F014,
2775	.clkr = {
2776		.enable_reg = 0x1F014,
2777		.enable_mask = BIT(0),
2778		.hw.init = &(struct clk_init_data){
2779			.name = "gcc_lpass_q6ss_tsctr_1to2_clk",
2780			.parent_hws = (const struct clk_hw *[]){
2781					&qdss_tsctr_div2_clk_src.hw },
2782			.num_parents = 1,
2783			.flags = CLK_SET_RATE_PARENT,
2784			.ops = &clk_branch2_ops,
2785		},
2786	},
2787};
2788
2789static struct clk_branch gcc_lpass_q6ss_trig_clk = {
2790	.halt_reg = 0x1F038,
2791	.clkr = {
2792		.enable_reg = 0x1F038,
2793		.enable_mask = BIT(0),
2794		.hw.init = &(struct clk_init_data){
2795			.name = "gcc_lpass_q6ss_trig_clk",
2796			.parent_hws = (const struct clk_hw *[]){
2797					&qdss_dap_sync_clk_src.hw },
2798			.num_parents = 1,
2799			.flags = CLK_SET_RATE_PARENT,
2800			.ops = &clk_branch2_ops,
2801		},
2802	},
2803};
2804
2805static struct clk_branch gcc_lpass_tbu_clk = {
2806	.halt_reg = 0x12094,
2807	.clkr = {
2808		.enable_reg = 0xb00c,
2809		.enable_mask = BIT(10),
2810		.hw.init = &(struct clk_init_data){
2811			.name = "gcc_lpass_tbu_clk",
2812			.parent_hws = (const struct clk_hw *[]){
2813					&lpass_q6_axim_clk_src.clkr.hw },
2814			.num_parents = 1,
2815			.flags = CLK_SET_RATE_PARENT,
2816			.ops = &clk_branch2_ops,
2817		},
2818	},
2819};
2820
2821static struct clk_branch gcc_pcnoc_lpass_clk = {
2822	.halt_reg = 0x27020,
2823	.clkr = {
2824		.enable_reg = 0x27020,
2825		.enable_mask = BIT(0),
2826		.hw.init = &(struct clk_init_data){
2827			.name = "gcc_pcnoc_lpass_clk",
2828			.parent_hws = (const struct clk_hw *[]){
2829					&lpass_core_axim_clk_src.clkr.hw },
2830			.num_parents = 1,
2831			.flags = CLK_SET_RATE_PARENT,
2832			.ops = &clk_branch2_ops,
2833		},
2834	},
2835};
2836
2837static struct clk_branch gcc_mem_noc_lpass_clk = {
2838	.halt_reg = 0x1D044,
2839	.clkr = {
2840		.enable_reg = 0x1D044,
2841		.enable_mask = BIT(0),
2842		.hw.init = &(struct clk_init_data){
2843			.name = "gcc_mem_noc_lpass_clk",
2844			.parent_hws = (const struct clk_hw *[]){
2845					&lpass_q6_axim_clk_src.clkr.hw },
2846			.num_parents = 1,
2847			.flags = CLK_SET_RATE_PARENT,
2848			.ops = &clk_branch2_ops,
2849		},
2850	},
2851};
2852
2853static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2854	.halt_reg = 0x26074,
2855	.clkr = {
2856		.enable_reg = 0x26074,
2857		.enable_mask = BIT(0),
2858		.hw.init = &(struct clk_init_data){
2859			.name = "gcc_snoc_lpass_cfg_clk",
2860			.parent_hws = (const struct clk_hw *[]){
2861					&lpass_snoc_cfg_clk_src.clkr.hw },
2862			.num_parents = 1,
2863			.flags = CLK_SET_RATE_PARENT,
2864			.ops = &clk_branch2_ops,
2865		},
2866	},
2867};
2868
2869static struct clk_branch gcc_mem_noc_ubi32_clk = {
2870	.halt_reg = 0x1D03C,
2871	.clkr = {
2872		.enable_reg = 0x1D03C,
2873		.enable_mask = BIT(0),
2874		.hw.init = &(struct clk_init_data){
2875			.name = "gcc_mem_noc_ubi32_clk",
2876			.parent_hws = (const struct clk_hw *[]){
2877					&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
2878			.num_parents = 1,
2879			.flags = CLK_SET_RATE_PARENT,
2880			.ops = &clk_branch2_ops,
2881		},
2882	},
2883};
2884
2885static struct clk_branch gcc_nss_port1_rx_clk = {
2886	.halt_reg = 0x68240,
2887	.clkr = {
2888		.enable_reg = 0x68240,
2889		.enable_mask = BIT(0),
2890		.hw.init = &(struct clk_init_data){
2891			.name = "gcc_nss_port1_rx_clk",
2892			.parent_hws = (const struct clk_hw *[]){
2893					&nss_port1_rx_div_clk_src.clkr.hw },
2894			.num_parents = 1,
2895			.flags = CLK_SET_RATE_PARENT,
2896			.ops = &clk_branch2_ops,
2897		},
2898	},
2899};
2900
2901static struct clk_branch gcc_nss_port1_tx_clk = {
2902	.halt_reg = 0x68244,
2903	.clkr = {
2904		.enable_reg = 0x68244,
2905		.enable_mask = BIT(0),
2906		.hw.init = &(struct clk_init_data){
2907			.name = "gcc_nss_port1_tx_clk",
2908			.parent_hws = (const struct clk_hw *[]){
2909					&nss_port1_tx_div_clk_src.clkr.hw },
2910			.num_parents = 1,
2911			.flags = CLK_SET_RATE_PARENT,
2912			.ops = &clk_branch2_ops,
2913		},
2914	},
2915};
2916
2917static struct clk_branch gcc_nss_port2_rx_clk = {
2918	.halt_reg = 0x68248,
2919	.clkr = {
2920		.enable_reg = 0x68248,
2921		.enable_mask = BIT(0),
2922		.hw.init = &(struct clk_init_data){
2923			.name = "gcc_nss_port2_rx_clk",
2924			.parent_hws = (const struct clk_hw *[]){
2925					&nss_port2_rx_div_clk_src.clkr.hw },
2926			.num_parents = 1,
2927			.flags = CLK_SET_RATE_PARENT,
2928			.ops = &clk_branch2_ops,
2929		},
2930	},
2931};
2932
2933static struct clk_branch gcc_nss_port2_tx_clk = {
2934	.halt_reg = 0x6824c,
2935	.clkr = {
2936		.enable_reg = 0x6824c,
2937		.enable_mask = BIT(0),
2938		.hw.init = &(struct clk_init_data){
2939			.name = "gcc_nss_port2_tx_clk",
2940			.parent_hws = (const struct clk_hw *[]){
2941					&nss_port2_tx_div_clk_src.clkr.hw },
2942			.num_parents = 1,
2943			.flags = CLK_SET_RATE_PARENT,
2944			.ops = &clk_branch2_ops,
2945		},
2946	},
2947};
2948
2949static struct clk_branch gcc_nss_port3_rx_clk = {
2950	.halt_reg = 0x68250,
2951	.clkr = {
2952		.enable_reg = 0x68250,
2953		.enable_mask = BIT(0),
2954		.hw.init = &(struct clk_init_data){
2955			.name = "gcc_nss_port3_rx_clk",
2956			.parent_hws = (const struct clk_hw *[]){
2957					&nss_port3_rx_div_clk_src.clkr.hw },
2958			.num_parents = 1,
2959			.flags = CLK_SET_RATE_PARENT,
2960			.ops = &clk_branch2_ops,
2961		},
2962	},
2963};
2964
2965static struct clk_branch gcc_nss_port3_tx_clk = {
2966	.halt_reg = 0x68254,
2967	.clkr = {
2968		.enable_reg = 0x68254,
2969		.enable_mask = BIT(0),
2970		.hw.init = &(struct clk_init_data){
2971			.name = "gcc_nss_port3_tx_clk",
2972			.parent_hws = (const struct clk_hw *[]){
2973					&nss_port3_tx_div_clk_src.clkr.hw },
2974			.num_parents = 1,
2975			.flags = CLK_SET_RATE_PARENT,
2976			.ops = &clk_branch2_ops,
2977		},
2978	},
2979};
2980
2981static struct clk_branch gcc_nss_port4_rx_clk = {
2982	.halt_reg = 0x68258,
2983	.clkr = {
2984		.enable_reg = 0x68258,
2985		.enable_mask = BIT(0),
2986		.hw.init = &(struct clk_init_data){
2987			.name = "gcc_nss_port4_rx_clk",
2988			.parent_hws = (const struct clk_hw *[]){
2989					&nss_port4_rx_div_clk_src.clkr.hw },
2990			.num_parents = 1,
2991			.flags = CLK_SET_RATE_PARENT,
2992			.ops = &clk_branch2_ops,
2993		},
2994	},
2995};
2996
2997static struct clk_branch gcc_nss_port4_tx_clk = {
2998	.halt_reg = 0x6825c,
2999	.clkr = {
3000		.enable_reg = 0x6825c,
3001		.enable_mask = BIT(0),
3002		.hw.init = &(struct clk_init_data){
3003			.name = "gcc_nss_port4_tx_clk",
3004			.parent_hws = (const struct clk_hw *[]){
3005					&nss_port4_tx_div_clk_src.clkr.hw },
3006			.num_parents = 1,
3007			.flags = CLK_SET_RATE_PARENT,
3008			.ops = &clk_branch2_ops,
3009		},
3010	},
3011};
3012
3013static struct clk_branch gcc_nss_port5_rx_clk = {
3014	.halt_reg = 0x68260,
3015	.clkr = {
3016		.enable_reg = 0x68260,
3017		.enable_mask = BIT(0),
3018		.hw.init = &(struct clk_init_data){
3019			.name = "gcc_nss_port5_rx_clk",
3020			.parent_hws = (const struct clk_hw *[]){
3021					&nss_port5_rx_div_clk_src.clkr.hw },
3022			.num_parents = 1,
3023			.flags = CLK_SET_RATE_PARENT,
3024			.ops = &clk_branch2_ops,
3025		},
3026	},
3027};
3028
3029static struct clk_branch gcc_nss_port5_tx_clk = {
3030	.halt_reg = 0x68264,
3031	.clkr = {
3032		.enable_reg = 0x68264,
3033		.enable_mask = BIT(0),
3034		.hw.init = &(struct clk_init_data){
3035			.name = "gcc_nss_port5_tx_clk",
3036			.parent_hws = (const struct clk_hw *[]){
3037					&nss_port5_tx_div_clk_src.clkr.hw },
3038			.num_parents = 1,
3039			.flags = CLK_SET_RATE_PARENT,
3040			.ops = &clk_branch2_ops,
3041		},
3042	},
3043};
3044
3045static struct clk_branch gcc_nss_ppe_cfg_clk = {
3046	.halt_reg = 0x68194,
3047	.clkr = {
3048		.enable_reg = 0x68194,
3049		.enable_mask = BIT(0),
3050		.hw.init = &(struct clk_init_data){
3051			.name = "gcc_nss_ppe_cfg_clk",
3052			.parent_hws = (const struct clk_hw *[]){
3053					&nss_ppe_clk_src.clkr.hw },
3054			.num_parents = 1,
3055			.flags = CLK_SET_RATE_PARENT,
3056			.ops = &clk_branch2_ops,
3057		},
3058	},
3059};
3060
3061static struct clk_branch gcc_nss_ppe_clk = {
3062	.halt_reg = 0x68190,
3063	.clkr = {
3064		.enable_reg = 0x68190,
3065		.enable_mask = BIT(0),
3066		.hw.init = &(struct clk_init_data){
3067			.name = "gcc_nss_ppe_clk",
3068			.parent_hws = (const struct clk_hw *[]){
3069					&nss_ppe_clk_src.clkr.hw },
3070			.num_parents = 1,
3071			.flags = CLK_SET_RATE_PARENT,
3072			.ops = &clk_branch2_ops,
3073		},
3074	},
3075};
3076
3077static struct clk_branch gcc_nss_ppe_ipe_clk = {
3078	.halt_reg = 0x68338,
3079	.clkr = {
3080		.enable_reg = 0x68338,
3081		.enable_mask = BIT(0),
3082		.hw.init = &(struct clk_init_data){
3083			.name = "gcc_nss_ppe_ipe_clk",
3084			.parent_hws = (const struct clk_hw *[]){
3085					&nss_ppe_clk_src.clkr.hw },
3086			.num_parents = 1,
3087			.flags = CLK_SET_RATE_PARENT,
3088			.ops = &clk_branch2_ops,
3089		},
3090	},
3091};
3092
3093static struct clk_branch gcc_nss_ptp_ref_clk = {
3094	.halt_reg = 0x6816C,
3095	.clkr = {
3096		.enable_reg = 0x6816C,
3097		.enable_mask = BIT(0),
3098		.hw.init = &(struct clk_init_data){
3099			.name = "gcc_nss_ptp_ref_clk",
3100			.parent_hws = (const struct clk_hw *[]){
3101					&nss_ppe_cdiv_clk_src.hw },
3102			.num_parents = 1,
3103			.flags = CLK_SET_RATE_PARENT,
3104			.ops = &clk_branch2_ops,
3105		},
3106	},
3107};
3108
3109static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3110	.halt_reg = 0x6830C,
3111	.clkr = {
3112		.enable_reg = 0x6830C,
3113		.enable_mask = BIT(0),
3114		.hw.init = &(struct clk_init_data){
3115			.name = "gcc_nssnoc_ce_apb_clk",
3116			.parent_hws = (const struct clk_hw *[]){
3117					&nss_ce_clk_src.clkr.hw },
3118			.num_parents = 1,
3119			.flags = CLK_SET_RATE_PARENT,
3120			.ops = &clk_branch2_ops,
3121		},
3122	},
3123};
3124
3125static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3126	.halt_reg = 0x68308,
3127	.clkr = {
3128		.enable_reg = 0x68308,
3129		.enable_mask = BIT(0),
3130		.hw.init = &(struct clk_init_data){
3131			.name = "gcc_nssnoc_ce_axi_clk",
3132			.parent_hws = (const struct clk_hw *[]){
3133					&nss_ce_clk_src.clkr.hw },
3134			.num_parents = 1,
3135			.flags = CLK_SET_RATE_PARENT,
3136			.ops = &clk_branch2_ops,
3137		},
3138	},
3139};
3140
3141static struct clk_branch gcc_nssnoc_crypto_clk = {
3142	.halt_reg = 0x68314,
3143	.clkr = {
3144		.enable_reg = 0x68314,
3145		.enable_mask = BIT(0),
3146		.hw.init = &(struct clk_init_data){
3147			.name = "gcc_nssnoc_crypto_clk",
3148			.parent_hws = (const struct clk_hw *[]){
3149					&nss_crypto_clk_src.clkr.hw },
3150			.num_parents = 1,
3151			.flags = CLK_SET_RATE_PARENT,
3152			.ops = &clk_branch2_ops,
3153		},
3154	},
3155};
3156
3157static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3158	.halt_reg = 0x68304,
3159	.clkr = {
3160		.enable_reg = 0x68304,
3161		.enable_mask = BIT(0),
3162		.hw.init = &(struct clk_init_data){
3163			.name = "gcc_nssnoc_ppe_cfg_clk",
3164			.parent_hws = (const struct clk_hw *[]){
3165					&nss_ppe_clk_src.clkr.hw },
3166			.flags = CLK_SET_RATE_PARENT,
3167			.ops = &clk_branch2_ops,
3168		},
3169	},
3170};
3171
3172static struct clk_branch gcc_nssnoc_ppe_clk = {
3173	.halt_reg = 0x68300,
3174	.clkr = {
3175		.enable_reg = 0x68300,
3176		.enable_mask = BIT(0),
3177		.hw.init = &(struct clk_init_data){
3178			.name = "gcc_nssnoc_ppe_clk",
3179			.parent_hws = (const struct clk_hw *[]){
3180					&nss_ppe_clk_src.clkr.hw },
3181			.num_parents = 1,
3182			.flags = CLK_SET_RATE_PARENT,
3183			.ops = &clk_branch2_ops,
3184		},
3185	},
3186};
3187
3188static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3189	.halt_reg = 0x68180,
3190	.clkr = {
3191		.enable_reg = 0x68180,
3192		.enable_mask = BIT(0),
3193		.hw.init = &(struct clk_init_data){
3194			.name = "gcc_nssnoc_qosgen_ref_clk",
3195			.parent_hws = (const struct clk_hw *[]){
3196					&gcc_xo_clk_src.clkr.hw },
3197			.num_parents = 1,
3198			.flags = CLK_SET_RATE_PARENT,
3199			.ops = &clk_branch2_ops,
3200		},
3201	},
3202};
3203
3204static struct clk_branch gcc_nssnoc_snoc_clk = {
3205	.halt_reg = 0x68188,
3206	.clkr = {
3207		.enable_reg = 0x68188,
3208		.enable_mask = BIT(0),
3209		.hw.init = &(struct clk_init_data){
3210			.name = "gcc_nssnoc_snoc_clk",
3211			.parent_hws = (const struct clk_hw *[]){
3212					&system_noc_bfdcd_clk_src.clkr.hw },
3213			.num_parents = 1,
3214			.flags = CLK_SET_RATE_PARENT,
3215			.ops = &clk_branch2_ops,
3216		},
3217	},
3218};
3219
3220static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3221	.halt_reg = 0x68184,
3222	.clkr = {
3223		.enable_reg = 0x68184,
3224		.enable_mask = BIT(0),
3225		.hw.init = &(struct clk_init_data){
3226			.name = "gcc_nssnoc_timeout_ref_clk",
3227			.parent_hws = (const struct clk_hw *[]){
3228					&gcc_xo_div4_clk_src.hw },
3229			.num_parents = 1,
3230			.flags = CLK_SET_RATE_PARENT,
3231			.ops = &clk_branch2_ops,
3232		},
3233	},
3234};
3235
3236static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3237	.halt_reg = 0x68270,
3238	.clkr = {
3239		.enable_reg = 0x68270,
3240		.enable_mask = BIT(0),
3241		.hw.init = &(struct clk_init_data){
3242			.name = "gcc_nssnoc_ubi0_ahb_clk",
3243			.parent_hws = (const struct clk_hw *[]){
3244					&nss_ce_clk_src.clkr.hw },
3245			.num_parents = 1,
3246			.flags = CLK_SET_RATE_PARENT,
3247			.ops = &clk_branch2_ops,
3248		},
3249	},
3250};
3251
3252static struct clk_branch gcc_port1_mac_clk = {
3253	.halt_reg = 0x68320,
3254	.clkr = {
3255		.enable_reg = 0x68320,
3256		.enable_mask = BIT(0),
3257		.hw.init = &(struct clk_init_data){
3258			.name = "gcc_port1_mac_clk",
3259			.parent_hws = (const struct clk_hw *[]){
3260					&nss_ppe_clk_src.clkr.hw },
3261			.num_parents = 1,
3262			.flags = CLK_SET_RATE_PARENT,
3263			.ops = &clk_branch2_ops,
3264		},
3265	},
3266};
3267
3268static struct clk_branch gcc_port2_mac_clk = {
3269	.halt_reg = 0x68324,
3270	.clkr = {
3271		.enable_reg = 0x68324,
3272		.enable_mask = BIT(0),
3273		.hw.init = &(struct clk_init_data){
3274			.name = "gcc_port2_mac_clk",
3275			.parent_hws = (const struct clk_hw *[]){
3276					&nss_ppe_clk_src.clkr.hw },
3277			.num_parents = 1,
3278			.flags = CLK_SET_RATE_PARENT,
3279			.ops = &clk_branch2_ops,
3280		},
3281	},
3282};
3283
3284static struct clk_branch gcc_port3_mac_clk = {
3285	.halt_reg = 0x68328,
3286	.clkr = {
3287		.enable_reg = 0x68328,
3288		.enable_mask = BIT(0),
3289		.hw.init = &(struct clk_init_data){
3290			.name = "gcc_port3_mac_clk",
3291			.parent_hws = (const struct clk_hw *[]){
3292					&nss_ppe_clk_src.clkr.hw },
3293			.num_parents = 1,
3294			.flags = CLK_SET_RATE_PARENT,
3295			.ops = &clk_branch2_ops,
3296		},
3297	},
3298};
3299
3300static struct clk_branch gcc_port4_mac_clk = {
3301	.halt_reg = 0x6832c,
3302	.clkr = {
3303		.enable_reg = 0x6832c,
3304		.enable_mask = BIT(0),
3305		.hw.init = &(struct clk_init_data){
3306			.name = "gcc_port4_mac_clk",
3307			.parent_hws = (const struct clk_hw *[]){
3308					&nss_ppe_clk_src.clkr.hw },
3309			.num_parents = 1,
3310			.flags = CLK_SET_RATE_PARENT,
3311			.ops = &clk_branch2_ops,
3312		},
3313	},
3314};
3315
3316static struct clk_branch gcc_port5_mac_clk = {
3317	.halt_reg = 0x68330,
3318	.clkr = {
3319		.enable_reg = 0x68330,
3320		.enable_mask = BIT(0),
3321		.hw.init = &(struct clk_init_data){
3322			.name = "gcc_port5_mac_clk",
3323			.parent_hws = (const struct clk_hw *[]){
3324					&nss_ppe_clk_src.clkr.hw },
3325			.num_parents = 1,
3326			.flags = CLK_SET_RATE_PARENT,
3327			.ops = &clk_branch2_ops,
3328		},
3329	},
3330};
3331
3332static struct clk_branch gcc_ubi0_ahb_clk = {
3333	.halt_reg = 0x6820C,
3334	.halt_check = BRANCH_HALT_DELAY,
3335	.clkr = {
3336		.enable_reg = 0x6820C,
3337		.enable_mask = BIT(0),
3338		.hw.init = &(struct clk_init_data){
3339			.name = "gcc_ubi0_ahb_clk",
3340			.parent_hws = (const struct clk_hw *[]){
3341					&nss_ce_clk_src.clkr.hw },
3342			.num_parents = 1,
3343			.flags = CLK_SET_RATE_PARENT,
3344			.ops = &clk_branch2_ops,
3345		},
3346	},
3347};
3348
3349static struct clk_branch gcc_ubi0_axi_clk = {
3350	.halt_reg = 0x68200,
3351	.halt_check = BRANCH_HALT_DELAY,
3352	.clkr = {
3353		.enable_reg = 0x68200,
3354		.enable_mask = BIT(0),
3355		.hw.init = &(struct clk_init_data){
3356			.name = "gcc_ubi0_axi_clk",
3357			.parent_hws = (const struct clk_hw *[]){
3358					&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
3359			.num_parents = 1,
3360			.flags = CLK_SET_RATE_PARENT,
3361			.ops = &clk_branch2_ops,
3362		},
3363	},
3364};
3365
3366static struct clk_branch gcc_ubi0_nc_axi_clk = {
3367	.halt_reg = 0x68204,
3368	.halt_check = BRANCH_HALT_DELAY,
3369	.clkr = {
3370		.enable_reg = 0x68204,
3371		.enable_mask = BIT(0),
3372		.hw.init = &(struct clk_init_data){
3373			.name = "gcc_ubi0_nc_axi_clk",
3374			.parent_hws = (const struct clk_hw *[]){
3375					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
3376			.num_parents = 1,
3377			.flags = CLK_SET_RATE_PARENT,
3378			.ops = &clk_branch2_ops,
3379		},
3380	},
3381};
3382
3383static struct clk_branch gcc_ubi0_core_clk = {
3384	.halt_reg = 0x68210,
3385	.halt_check = BRANCH_HALT_DELAY,
3386	.clkr = {
3387		.enable_reg = 0x68210,
3388		.enable_mask = BIT(0),
3389		.hw.init = &(struct clk_init_data){
3390			.name = "gcc_ubi0_core_clk",
3391			.parent_hws = (const struct clk_hw *[]){
3392					&nss_ubi0_div_clk_src.clkr.hw },
3393			.num_parents = 1,
3394			.flags = CLK_SET_RATE_PARENT,
3395			.ops = &clk_branch2_ops,
3396		},
3397	},
3398};
3399
3400static struct clk_branch gcc_pcie0_ahb_clk = {
3401	.halt_reg = 0x75010,
3402	.clkr = {
3403		.enable_reg = 0x75010,
3404		.enable_mask = BIT(0),
3405		.hw.init = &(struct clk_init_data){
3406			.name = "gcc_pcie0_ahb_clk",
3407			.parent_hws = (const struct clk_hw *[]){
3408					&pcnoc_bfdcd_clk_src.clkr.hw },
3409			.num_parents = 1,
3410			.flags = CLK_SET_RATE_PARENT,
3411			.ops = &clk_branch2_ops,
3412		},
3413	},
3414};
3415
3416static struct clk_branch gcc_pcie0_aux_clk = {
3417	.halt_reg = 0x75014,
3418	.clkr = {
3419		.enable_reg = 0x75014,
3420		.enable_mask = BIT(0),
3421		.hw.init = &(struct clk_init_data){
3422			.name = "gcc_pcie0_aux_clk",
3423			.parent_hws = (const struct clk_hw *[]){
3424					&pcie0_aux_clk_src.clkr.hw },
3425			.num_parents = 1,
3426			.flags = CLK_SET_RATE_PARENT,
3427			.ops = &clk_branch2_ops,
3428		},
3429	},
3430};
3431
3432static struct clk_branch gcc_pcie0_axi_m_clk = {
3433	.halt_reg = 0x75008,
3434	.clkr = {
3435		.enable_reg = 0x75008,
3436		.enable_mask = BIT(0),
3437		.hw.init = &(struct clk_init_data){
3438			.name = "gcc_pcie0_axi_m_clk",
3439			.parent_hws = (const struct clk_hw *[]){
3440					&pcie0_axi_clk_src.clkr.hw },
3441			.num_parents = 1,
3442			.flags = CLK_SET_RATE_PARENT,
3443			.ops = &clk_branch2_ops,
3444		},
3445	},
3446};
3447
3448static struct clk_branch gcc_pcie0_axi_s_clk = {
3449	.halt_reg = 0x7500c,
3450	.clkr = {
3451		.enable_reg = 0x7500c,
3452		.enable_mask = BIT(0),
3453		.hw.init = &(struct clk_init_data){
3454			.name = "gcc_pcie0_axi_s_clk",
3455			.parent_hws = (const struct clk_hw *[]){
3456					&pcie0_axi_clk_src.clkr.hw },
3457			.num_parents = 1,
3458			.flags = CLK_SET_RATE_PARENT,
3459			.ops = &clk_branch2_ops,
3460		},
3461	},
3462};
3463
3464static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
3465	.halt_reg = 0x26048,
3466	.clkr = {
3467		.enable_reg = 0x26048,
3468		.enable_mask = BIT(0),
3469		.hw.init = &(struct clk_init_data){
3470			.name = "gcc_sys_noc_pcie0_axi_clk",
3471			.parent_hws = (const struct clk_hw *[]){
3472					&pcie0_axi_clk_src.clkr.hw },
3473			.num_parents = 1,
3474			.flags = CLK_SET_RATE_PARENT,
3475			.ops = &clk_branch2_ops,
3476		},
3477	},
3478};
3479
3480static struct clk_branch gcc_pcie0_pipe_clk = {
3481	.halt_reg = 0x75018,
3482	.halt_check = BRANCH_HALT_DELAY,
3483	.clkr = {
3484		.enable_reg = 0x75018,
3485		.enable_mask = BIT(0),
3486		.hw.init = &(struct clk_init_data){
3487			.name = "gcc_pcie0_pipe_clk",
3488			.parent_hws = (const struct clk_hw *[]){
3489					&pcie0_pipe_clk_src.clkr.hw },
3490			.num_parents = 1,
3491			.flags = CLK_SET_RATE_PARENT,
3492			.ops = &clk_branch2_ops,
3493		},
3494	},
3495};
3496
3497static struct clk_branch gcc_prng_ahb_clk = {
3498	.halt_reg = 0x13004,
3499	.halt_check = BRANCH_HALT_VOTED,
3500	.clkr = {
3501		.enable_reg = 0x0b004,
3502		.enable_mask = BIT(8),
3503		.hw.init = &(struct clk_init_data){
3504			.name = "gcc_prng_ahb_clk",
3505			.parent_hws = (const struct clk_hw *[]){
3506					&pcnoc_bfdcd_clk_src.clkr.hw },
3507			.num_parents = 1,
3508			.flags = CLK_SET_RATE_PARENT,
3509			.ops = &clk_branch2_ops,
3510		},
3511	},
3512};
3513
3514static struct clk_branch gcc_qdss_dap_clk = {
3515	.halt_reg = 0x29084,
3516	.clkr = {
3517		.enable_reg = 0x29084,
3518		.enable_mask = BIT(0),
3519		.hw.init = &(struct clk_init_data){
3520			.name = "gcc_qdss_dap_clk",
3521			.parent_hws = (const struct clk_hw *[]){
3522					&qdss_dap_sync_clk_src.hw },
3523			.num_parents = 1,
3524			.flags = CLK_SET_RATE_PARENT,
3525			.ops = &clk_branch2_ops,
3526		},
3527	},
3528};
3529
3530static struct clk_branch gcc_qpic_ahb_clk = {
3531	.halt_reg = 0x57024,
3532	.clkr = {
3533		.enable_reg = 0x57024,
3534		.enable_mask = BIT(0),
3535		.hw.init = &(struct clk_init_data){
3536			.name = "gcc_qpic_ahb_clk",
3537			.parent_hws = (const struct clk_hw *[]){
3538					&pcnoc_bfdcd_clk_src.clkr.hw },
3539			.num_parents = 1,
3540			.flags = CLK_SET_RATE_PARENT,
3541			.ops = &clk_branch2_ops,
3542		},
3543	},
3544};
3545
3546static struct clk_branch gcc_qpic_clk = {
3547	.halt_reg = 0x57020,
3548	.clkr = {
3549		.enable_reg = 0x57020,
3550		.enable_mask = BIT(0),
3551		.hw.init = &(struct clk_init_data){
3552			.name = "gcc_qpic_clk",
3553			.parent_hws = (const struct clk_hw *[]){
3554					&pcnoc_bfdcd_clk_src.clkr.hw },
3555			.num_parents = 1,
3556			.flags = CLK_SET_RATE_PARENT,
3557			.ops = &clk_branch2_ops,
3558		},
3559	},
3560};
3561
3562static struct clk_branch gcc_sdcc1_ahb_clk = {
3563	.halt_reg = 0x4201c,
3564	.clkr = {
3565		.enable_reg = 0x4201c,
3566		.enable_mask = BIT(0),
3567		.hw.init = &(struct clk_init_data){
3568			.name = "gcc_sdcc1_ahb_clk",
3569			.parent_hws = (const struct clk_hw *[]){
3570					&pcnoc_bfdcd_clk_src.clkr.hw },
3571			.num_parents = 1,
3572			.flags = CLK_SET_RATE_PARENT,
3573			.ops = &clk_branch2_ops,
3574		},
3575	},
3576};
3577
3578static struct clk_branch gcc_sdcc1_apps_clk = {
3579	.halt_reg = 0x42018,
3580	.clkr = {
3581		.enable_reg = 0x42018,
3582		.enable_mask = BIT(0),
3583		.hw.init = &(struct clk_init_data){
3584			.name = "gcc_sdcc1_apps_clk",
3585			.parent_hws = (const struct clk_hw *[]){
3586					&sdcc1_apps_clk_src.clkr.hw },
3587			.num_parents = 1,
3588			.flags = CLK_SET_RATE_PARENT,
3589			.ops = &clk_branch2_ops,
3590		},
3591	},
3592};
3593
3594static struct clk_branch gcc_uniphy0_ahb_clk = {
3595	.halt_reg = 0x56008,
3596	.clkr = {
3597		.enable_reg = 0x56008,
3598		.enable_mask = BIT(0),
3599		.hw.init = &(struct clk_init_data){
3600			.name = "gcc_uniphy0_ahb_clk",
3601			.parent_hws = (const struct clk_hw *[]){
3602					&pcnoc_bfdcd_clk_src.clkr.hw },
3603			.num_parents = 1,
3604			.flags = CLK_SET_RATE_PARENT,
3605			.ops = &clk_branch2_ops,
3606		},
3607	},
3608};
3609
3610static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3611	.halt_reg = 0x56010,
3612	.clkr = {
3613		.enable_reg = 0x56010,
3614		.enable_mask = BIT(0),
3615		.hw.init = &(struct clk_init_data){
3616			.name = "gcc_uniphy0_port1_rx_clk",
3617			.parent_hws = (const struct clk_hw *[]){
3618					&nss_port1_rx_div_clk_src.clkr.hw },
3619			.num_parents = 1,
3620			.flags = CLK_SET_RATE_PARENT,
3621			.ops = &clk_branch2_ops,
3622		},
3623	},
3624};
3625
3626static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3627	.halt_reg = 0x56014,
3628	.clkr = {
3629		.enable_reg = 0x56014,
3630		.enable_mask = BIT(0),
3631		.hw.init = &(struct clk_init_data){
3632			.name = "gcc_uniphy0_port1_tx_clk",
3633			.parent_hws = (const struct clk_hw *[]){
3634					&nss_port1_tx_div_clk_src.clkr.hw },
3635			.num_parents = 1,
3636			.flags = CLK_SET_RATE_PARENT,
3637			.ops = &clk_branch2_ops,
3638		},
3639	},
3640};
3641
3642static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3643	.halt_reg = 0x56018,
3644	.clkr = {
3645		.enable_reg = 0x56018,
3646		.enable_mask = BIT(0),
3647		.hw.init = &(struct clk_init_data){
3648			.name = "gcc_uniphy0_port2_rx_clk",
3649			.parent_hws = (const struct clk_hw *[]){
3650					&nss_port2_rx_div_clk_src.clkr.hw },
3651			.num_parents = 1,
3652			.flags = CLK_SET_RATE_PARENT,
3653			.ops = &clk_branch2_ops,
3654		},
3655	},
3656};
3657
3658static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3659	.halt_reg = 0x5601c,
3660	.clkr = {
3661		.enable_reg = 0x5601c,
3662		.enable_mask = BIT(0),
3663		.hw.init = &(struct clk_init_data){
3664			.name = "gcc_uniphy0_port2_tx_clk",
3665			.parent_hws = (const struct clk_hw *[]){
3666					&nss_port2_tx_div_clk_src.clkr.hw },
3667			.num_parents = 1,
3668			.flags = CLK_SET_RATE_PARENT,
3669			.ops = &clk_branch2_ops,
3670		},
3671	},
3672};
3673
3674static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3675	.halt_reg = 0x56020,
3676	.clkr = {
3677		.enable_reg = 0x56020,
3678		.enable_mask = BIT(0),
3679		.hw.init = &(struct clk_init_data){
3680			.name = "gcc_uniphy0_port3_rx_clk",
3681			.parent_hws = (const struct clk_hw *[]){
3682					&nss_port3_rx_div_clk_src.clkr.hw },
3683			.num_parents = 1,
3684			.flags = CLK_SET_RATE_PARENT,
3685			.ops = &clk_branch2_ops,
3686		},
3687	},
3688};
3689
3690static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3691	.halt_reg = 0x56024,
3692	.clkr = {
3693		.enable_reg = 0x56024,
3694		.enable_mask = BIT(0),
3695		.hw.init = &(struct clk_init_data){
3696			.name = "gcc_uniphy0_port3_tx_clk",
3697			.parent_hws = (const struct clk_hw *[]){
3698					&nss_port3_tx_div_clk_src.clkr.hw },
3699			.num_parents = 1,
3700			.flags = CLK_SET_RATE_PARENT,
3701			.ops = &clk_branch2_ops,
3702		},
3703	},
3704};
3705
3706static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3707	.halt_reg = 0x56028,
3708	.clkr = {
3709		.enable_reg = 0x56028,
3710		.enable_mask = BIT(0),
3711		.hw.init = &(struct clk_init_data){
3712			.name = "gcc_uniphy0_port4_rx_clk",
3713			.parent_hws = (const struct clk_hw *[]){
3714					&nss_port4_rx_div_clk_src.clkr.hw },
3715			.num_parents = 1,
3716			.flags = CLK_SET_RATE_PARENT,
3717			.ops = &clk_branch2_ops,
3718		},
3719	},
3720};
3721
3722static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3723	.halt_reg = 0x5602c,
3724	.clkr = {
3725		.enable_reg = 0x5602c,
3726		.enable_mask = BIT(0),
3727		.hw.init = &(struct clk_init_data){
3728			.name = "gcc_uniphy0_port4_tx_clk",
3729			.parent_hws = (const struct clk_hw *[]){
3730					&nss_port4_tx_div_clk_src.clkr.hw },
3731			.num_parents = 1,
3732			.flags = CLK_SET_RATE_PARENT,
3733			.ops = &clk_branch2_ops,
3734		},
3735	},
3736};
3737
3738static struct clk_branch gcc_uniphy0_port5_rx_clk = {
3739	.halt_reg = 0x56030,
3740	.clkr = {
3741		.enable_reg = 0x56030,
3742		.enable_mask = BIT(0),
3743		.hw.init = &(struct clk_init_data){
3744			.name = "gcc_uniphy0_port5_rx_clk",
3745			.parent_hws = (const struct clk_hw *[]){
3746					&nss_port5_rx_div_clk_src.clkr.hw },
3747			.num_parents = 1,
3748			.flags = CLK_SET_RATE_PARENT,
3749			.ops = &clk_branch2_ops,
3750		},
3751	},
3752};
3753
3754static struct clk_branch gcc_uniphy0_port5_tx_clk = {
3755	.halt_reg = 0x56034,
3756	.clkr = {
3757		.enable_reg = 0x56034,
3758		.enable_mask = BIT(0),
3759		.hw.init = &(struct clk_init_data){
3760			.name = "gcc_uniphy0_port5_tx_clk",
3761			.parent_hws = (const struct clk_hw *[]){
3762					&nss_port5_tx_div_clk_src.clkr.hw },
3763			.num_parents = 1,
3764			.flags = CLK_SET_RATE_PARENT,
3765			.ops = &clk_branch2_ops,
3766		},
3767	},
3768};
3769
3770static struct clk_branch gcc_uniphy0_sys_clk = {
3771	.halt_reg = 0x5600C,
3772	.clkr = {
3773		.enable_reg = 0x5600C,
3774		.enable_mask = BIT(0),
3775		.hw.init = &(struct clk_init_data){
3776			.name = "gcc_uniphy0_sys_clk",
3777			.parent_hws = (const struct clk_hw *[]){
3778					&gcc_xo_clk_src.clkr.hw },
3779			.num_parents = 1,
3780			.flags = CLK_SET_RATE_PARENT,
3781			.ops = &clk_branch2_ops,
3782		},
3783	},
3784};
3785
3786static struct clk_branch gcc_uniphy1_ahb_clk = {
3787	.halt_reg = 0x56108,
3788	.clkr = {
3789		.enable_reg = 0x56108,
3790		.enable_mask = BIT(0),
3791		.hw.init = &(struct clk_init_data){
3792			.name = "gcc_uniphy1_ahb_clk",
3793			.parent_hws = (const struct clk_hw *[]){
3794					&pcnoc_bfdcd_clk_src.clkr.hw },
3795			.num_parents = 1,
3796			.flags = CLK_SET_RATE_PARENT,
3797			.ops = &clk_branch2_ops,
3798		},
3799	},
3800};
3801
3802static struct clk_branch gcc_uniphy1_port5_rx_clk = {
3803	.halt_reg = 0x56110,
3804	.clkr = {
3805		.enable_reg = 0x56110,
3806		.enable_mask = BIT(0),
3807		.hw.init = &(struct clk_init_data){
3808			.name = "gcc_uniphy1_port5_rx_clk",
3809			.parent_hws = (const struct clk_hw *[]){
3810					&nss_port5_rx_div_clk_src.clkr.hw },
3811			.num_parents = 1,
3812			.flags = CLK_SET_RATE_PARENT,
3813			.ops = &clk_branch2_ops,
3814		},
3815	},
3816};
3817
3818static struct clk_branch gcc_uniphy1_port5_tx_clk = {
3819	.halt_reg = 0x56114,
3820	.clkr = {
3821		.enable_reg = 0x56114,
3822		.enable_mask = BIT(0),
3823		.hw.init = &(struct clk_init_data){
3824			.name = "gcc_uniphy1_port5_tx_clk",
3825			.parent_hws = (const struct clk_hw *[]){
3826					&nss_port5_tx_div_clk_src.clkr.hw },
3827			.num_parents = 1,
3828			.flags = CLK_SET_RATE_PARENT,
3829			.ops = &clk_branch2_ops,
3830		},
3831	},
3832};
3833
3834static struct clk_branch gcc_uniphy1_sys_clk = {
3835	.halt_reg = 0x5610C,
3836	.clkr = {
3837		.enable_reg = 0x5610C,
3838		.enable_mask = BIT(0),
3839		.hw.init = &(struct clk_init_data){
3840			.name = "gcc_uniphy1_sys_clk",
3841			.parent_hws = (const struct clk_hw *[]){
3842					&gcc_xo_clk_src.clkr.hw },
3843			.num_parents = 1,
3844			.flags = CLK_SET_RATE_PARENT,
3845			.ops = &clk_branch2_ops,
3846		},
3847	},
3848};
3849
3850static struct clk_branch gcc_usb0_aux_clk = {
3851	.halt_reg = 0x3e044,
3852	.clkr = {
3853		.enable_reg = 0x3e044,
3854		.enable_mask = BIT(0),
3855		.hw.init = &(struct clk_init_data){
3856			.name = "gcc_usb0_aux_clk",
3857			.parent_hws = (const struct clk_hw *[]){
3858					&usb0_aux_clk_src.clkr.hw },
3859			.num_parents = 1,
3860			.flags = CLK_SET_RATE_PARENT,
3861			.ops = &clk_branch2_ops,
3862		},
3863	},
3864};
3865
3866static struct clk_branch gcc_usb0_master_clk = {
3867	.halt_reg = 0x3e000,
3868	.clkr = {
3869		.enable_reg = 0x3e000,
3870		.enable_mask = BIT(0),
3871		.hw.init = &(struct clk_init_data){
3872			.name = "gcc_usb0_master_clk",
3873			.parent_hws = (const struct clk_hw *[]){
3874					&usb0_master_clk_src.clkr.hw },
3875			.num_parents = 1,
3876			.flags = CLK_SET_RATE_PARENT,
3877			.ops = &clk_branch2_ops,
3878		},
3879	},
3880};
3881
3882static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
3883	.halt_reg = 0x47014,
3884	.clkr = {
3885		.enable_reg = 0x47014,
3886		.enable_mask = BIT(0),
3887		.hw.init = &(struct clk_init_data){
3888			.name = "gcc_snoc_bus_timeout2_ahb_clk",
3889			.parent_hws = (const struct clk_hw *[]){
3890					&usb0_master_clk_src.clkr.hw },
3891			.num_parents = 1,
3892			.flags = CLK_SET_RATE_PARENT,
3893			.ops = &clk_branch2_ops,
3894		},
3895	},
3896};
3897
3898static struct clk_rcg2 pcie0_rchng_clk_src = {
3899	.cmd_rcgr = 0x75070,
3900	.freq_tbl = ftbl_pcie_rchng_clk_src,
3901	.hid_width = 5,
3902	.parent_map = gcc_xo_gpll0_map,
3903	.clkr.hw.init = &(struct clk_init_data){
3904		.name = "pcie0_rchng_clk_src",
3905		.parent_data = gcc_xo_gpll0,
3906		.num_parents = 2,
3907		.ops = &clk_rcg2_ops,
3908	},
3909};
3910
3911static struct clk_branch gcc_pcie0_rchng_clk = {
3912	.halt_reg = 0x75070,
3913	.clkr = {
3914		.enable_reg = 0x75070,
3915		.enable_mask = BIT(1),
3916		.hw.init = &(struct clk_init_data){
3917			.name = "gcc_pcie0_rchng_clk",
3918			.parent_hws = (const struct clk_hw *[]){
3919					&pcie0_rchng_clk_src.clkr.hw },
3920			.num_parents = 1,
3921			.flags = CLK_SET_RATE_PARENT,
3922			.ops = &clk_branch2_ops,
3923		},
3924	},
3925};
3926
3927static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
3928	.halt_reg = 0x75048,
3929	.clkr = {
3930		.enable_reg = 0x75048,
3931		.enable_mask = BIT(0),
3932		.hw.init = &(struct clk_init_data){
3933			.name = "gcc_pcie0_axi_s_bridge_clk",
3934			.parent_hws = (const struct clk_hw *[]){
3935					&pcie0_axi_clk_src.clkr.hw },
3936			.num_parents = 1,
3937			.flags = CLK_SET_RATE_PARENT,
3938			.ops = &clk_branch2_ops,
3939		},
3940	},
3941};
3942
3943static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
3944	.halt_reg = 0x26040,
3945	.clkr = {
3946		.enable_reg = 0x26040,
3947		.enable_mask = BIT(0),
3948		.hw.init = &(struct clk_init_data){
3949			.name = "gcc_sys_noc_usb0_axi_clk",
3950			.parent_hws = (const struct clk_hw *[]){
3951					&usb0_master_clk_src.clkr.hw },
3952			.num_parents = 1,
3953			.flags = CLK_SET_RATE_PARENT,
3954			.ops = &clk_branch2_ops,
3955		},
3956	},
3957};
3958
3959static struct clk_branch gcc_usb0_mock_utmi_clk = {
3960	.halt_reg = 0x3e008,
3961	.clkr = {
3962		.enable_reg = 0x3e008,
3963		.enable_mask = BIT(0),
3964		.hw.init = &(struct clk_init_data){
3965			.name = "gcc_usb0_mock_utmi_clk",
3966			.parent_hws = (const struct clk_hw *[]){
3967					&usb0_mock_utmi_clk_src.clkr.hw },
3968			.num_parents = 1,
3969			.flags = CLK_SET_RATE_PARENT,
3970			.ops = &clk_branch2_ops,
3971		},
3972	},
3973};
3974
3975static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3976	.halt_reg = 0x3e080,
3977	.clkr = {
3978		.enable_reg = 0x3e080,
3979		.enable_mask = BIT(0),
3980		.hw.init = &(struct clk_init_data){
3981			.name = "gcc_usb0_phy_cfg_ahb_clk",
3982			.parent_hws = (const struct clk_hw *[]){
3983					&pcnoc_bfdcd_clk_src.clkr.hw },
3984			.num_parents = 1,
3985			.flags = CLK_SET_RATE_PARENT,
3986			.ops = &clk_branch2_ops,
3987		},
3988	},
3989};
3990
3991static struct clk_branch gcc_usb0_pipe_clk = {
3992	.halt_reg = 0x3e040,
3993	.halt_check = BRANCH_HALT_DELAY,
3994	.clkr = {
3995		.enable_reg = 0x3e040,
3996		.enable_mask = BIT(0),
3997		.hw.init = &(struct clk_init_data){
3998			.name = "gcc_usb0_pipe_clk",
3999			.parent_hws = (const struct clk_hw *[]){
4000					&usb0_pipe_clk_src.clkr.hw },
4001			.num_parents = 1,
4002			.flags = CLK_SET_RATE_PARENT,
4003			.ops = &clk_branch2_ops,
4004		},
4005	},
4006};
4007
4008static struct clk_branch gcc_usb0_sleep_clk = {
4009	.halt_reg = 0x3e004,
4010	.clkr = {
4011		.enable_reg = 0x3e004,
4012		.enable_mask = BIT(0),
4013		.hw.init = &(struct clk_init_data){
4014			.name = "gcc_usb0_sleep_clk",
4015			.parent_hws = (const struct clk_hw *[]){
4016					&gcc_sleep_clk_src.clkr.hw },
4017			.num_parents = 1,
4018			.flags = CLK_SET_RATE_PARENT,
4019			.ops = &clk_branch2_ops,
4020		},
4021	},
4022};
4023
4024static struct clk_branch gcc_usb1_master_clk = {
4025	.halt_reg = 0x3f000,
4026	.clkr = {
4027		.enable_reg = 0x3f000,
4028		.enable_mask = BIT(0),
4029		.hw.init = &(struct clk_init_data){
4030			.name = "gcc_usb1_master_clk",
4031			.parent_hws = (const struct clk_hw *[]){
4032					&pcnoc_bfdcd_clk_src.clkr.hw },
4033			.num_parents = 1,
4034			.flags = CLK_SET_RATE_PARENT,
4035			.ops = &clk_branch2_ops,
4036		},
4037	},
4038};
4039
4040static struct clk_branch gcc_usb1_mock_utmi_clk = {
4041	.halt_reg = 0x3f008,
4042	.clkr = {
4043		.enable_reg = 0x3f008,
4044		.enable_mask = BIT(0),
4045		.hw.init = &(struct clk_init_data){
4046			.name = "gcc_usb1_mock_utmi_clk",
4047			.parent_hws = (const struct clk_hw *[]){
4048					&usb1_mock_utmi_clk_src.clkr.hw },
4049			.num_parents = 1,
4050			.flags = CLK_SET_RATE_PARENT,
4051			.ops = &clk_branch2_ops,
4052		},
4053	},
4054};
4055
4056static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
4057	.halt_reg = 0x3f080,
4058	.clkr = {
4059		.enable_reg = 0x3f080,
4060		.enable_mask = BIT(0),
4061		.hw.init = &(struct clk_init_data){
4062			.name = "gcc_usb1_phy_cfg_ahb_clk",
4063			.parent_hws = (const struct clk_hw *[]){
4064					&pcnoc_bfdcd_clk_src.clkr.hw },
4065			.num_parents = 1,
4066			.flags = CLK_SET_RATE_PARENT,
4067			.ops = &clk_branch2_ops,
4068		},
4069	},
4070};
4071
4072static struct clk_branch gcc_usb1_sleep_clk = {
4073	.halt_reg = 0x3f004,
4074	.clkr = {
4075		.enable_reg = 0x3f004,
4076		.enable_mask = BIT(0),
4077		.hw.init = &(struct clk_init_data){
4078			.name = "gcc_usb1_sleep_clk",
4079			.parent_hws = (const struct clk_hw *[]){
4080					&gcc_sleep_clk_src.clkr.hw },
4081			.num_parents = 1,
4082			.flags = CLK_SET_RATE_PARENT,
4083			.ops = &clk_branch2_ops,
4084		},
4085	},
4086};
4087
4088static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
4089	.halt_reg = 0x56308,
4090	.clkr = {
4091		.enable_reg = 0x56308,
4092		.enable_mask = BIT(0),
4093		.hw.init = &(struct clk_init_data){
4094			.name = "gcc_cmn_12gpll_ahb_clk",
4095			.parent_hws = (const struct clk_hw *[]){
4096					&pcnoc_bfdcd_clk_src.clkr.hw },
4097			.num_parents = 1,
4098			.flags = CLK_SET_RATE_PARENT,
4099			.ops = &clk_branch2_ops,
4100		},
4101	},
4102};
4103
4104static struct clk_branch gcc_cmn_12gpll_sys_clk = {
4105	.halt_reg = 0x5630c,
4106	.clkr = {
4107		.enable_reg = 0x5630c,
4108		.enable_mask = BIT(0),
4109		.hw.init = &(struct clk_init_data){
4110			.name = "gcc_cmn_12gpll_sys_clk",
4111			.parent_hws = (const struct clk_hw *[]){
4112					&gcc_xo_clk_src.clkr.hw },
4113			.num_parents = 1,
4114			.flags = CLK_SET_RATE_PARENT,
4115			.ops = &clk_branch2_ops,
4116		},
4117	},
4118};
4119
4120static struct clk_branch gcc_sdcc1_ice_core_clk = {
4121	.halt_reg = 0x5d014,
4122	.clkr = {
4123		.enable_reg = 0x5d014,
4124		.enable_mask = BIT(0),
4125		.hw.init = &(struct clk_init_data){
4126			.name = "gcc_sdcc1_ice_core_clk",
4127			.parent_hws = (const struct clk_hw *[]){
4128					&sdcc1_ice_core_clk_src.clkr.hw },
4129			.num_parents = 1,
4130			.flags = CLK_SET_RATE_PARENT,
4131			.ops = &clk_branch2_ops,
4132		},
4133	},
4134};
4135
4136static struct clk_branch gcc_dcc_clk = {
4137	.halt_reg = 0x77004,
4138	.clkr = {
4139		.enable_reg = 0x77004,
4140		.enable_mask = BIT(0),
4141		.hw.init = &(struct clk_init_data){
4142			.name = "gcc_dcc_clk",
4143			.parent_hws = (const struct clk_hw *[]){
4144					&pcnoc_bfdcd_clk_src.clkr.hw },
4145			.num_parents = 1,
4146			.flags = CLK_SET_RATE_PARENT,
4147			.ops = &clk_branch2_ops,
4148		},
4149	},
4150};
4151
4152static const struct alpha_pll_config ubi32_pll_config = {
4153	.l = 0x3e,
4154	.alpha = 0x57,
4155	.config_ctl_val = 0x240d6aa8,
4156	.config_ctl_hi_val = 0x3c2,
4157	.main_output_mask = BIT(0),
4158	.aux_output_mask = BIT(1),
4159	.pre_div_val = 0x0,
4160	.pre_div_mask = BIT(12),
4161	.post_div_val = 0x0,
4162	.post_div_mask = GENMASK(9, 8),
4163};
4164
4165static const struct alpha_pll_config nss_crypto_pll_config = {
4166	.l = 0x32,
4167	.alpha = 0x0,
4168	.alpha_hi = 0x0,
4169	.config_ctl_val = 0x4001055b,
4170	.main_output_mask = BIT(0),
4171	.pre_div_val = 0x0,
4172	.pre_div_mask = GENMASK(14, 12),
4173	.post_div_val = 0x1 << 8,
4174	.post_div_mask = GENMASK(11, 8),
4175	.vco_mask = GENMASK(21, 20),
4176	.vco_val = 0x0,
4177	.alpha_en_mask = BIT(24),
4178};
4179
4180static struct clk_hw *gcc_ipq6018_hws[] = {
4181	&gpll0_out_main_div2.hw,
4182	&gcc_xo_div4_clk_src.hw,
4183	&nss_ppe_cdiv_clk_src.hw,
4184	&gpll6_out_main_div2.hw,
4185	&qdss_dap_sync_clk_src.hw,
4186	&qdss_tsctr_div2_clk_src.hw,
4187};
4188
4189static struct clk_regmap *gcc_ipq6018_clks[] = {
4190	[GPLL0_MAIN] = &gpll0_main.clkr,
4191	[GPLL0] = &gpll0.clkr,
4192	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4193	[UBI32_PLL] = &ubi32_pll.clkr,
4194	[GPLL6_MAIN] = &gpll6_main.clkr,
4195	[GPLL6] = &gpll6.clkr,
4196	[GPLL4_MAIN] = &gpll4_main.clkr,
4197	[GPLL4] = &gpll4.clkr,
4198	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4199	[GPLL2_MAIN] = &gpll2_main.clkr,
4200	[GPLL2] = &gpll2.clkr,
4201	[NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4202	[NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4203	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4204	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4205	[NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4206	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4207	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4208	[SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
4209	[NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4210	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4211	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
4212	[NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4213	[NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4214	[UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
4215	[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4216	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4217	[APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
4218	[NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4219	[NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4220	[NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4221	[NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4222	[NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4223	[NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4224	[NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4225	[NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4226	[NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4227	[NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4228	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
4229	[NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4230	[NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4231	[NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4232	[NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4233	[NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4234	[NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4235	[NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4236	[NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4237	[NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4238	[NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4239	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4240	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4241	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4242	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4243	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4244	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4245	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4246	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4247	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4248	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4249	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4250	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4251	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4252	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4253	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4254	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4255	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4256	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4257	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4258	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4259	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4260	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4261	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4262	[NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4263	[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4264	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4265	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4266	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4267	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4268	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4269	[USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4270	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4271	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
4272	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
4273	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4274	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4275	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4276	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4277	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4278	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4279	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4280	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4281	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4282	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4283	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4284	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4285	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4286	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4287	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4288	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4289	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4290	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4291	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4292	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4293	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4294	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
4295	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4296	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4297	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4298	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4299	[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4300	[GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4301	[GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4302	[GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4303	[GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4304	[GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4305	[GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4306	[GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4307	[GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4308	[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
4309	[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
4310	[GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4311	[GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4312	[GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4313	[GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4314	[GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4315	[GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4316	[GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4317	[GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4318	[GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4319	[GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4320	[GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4321	[GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4322	[GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4323	[GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4324	[GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4325	[GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4326	[GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4327	[GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4328	[GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4329	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4330	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4331	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4332	[GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4333	[GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4334	[GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4335	[GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4336	[GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4337	[GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4338	[GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4339	[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4340	[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4341	[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4342	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4343	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4344	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4345	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4346	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4347	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4348	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4349	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4350	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4351	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4352	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4353	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4354	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4355	[GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4356	[GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4357	[GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4358	[GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4359	[GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4360	[GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4361	[GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4362	[GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4363	[GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4364	[GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4365	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4366	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4367	[GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4368	[GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4369	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4370	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4371	[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4372	[GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
4373	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4374	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4375	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4376	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4377	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4378	[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4379	[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4380	[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4381	[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4382	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4383	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4384	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4385	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4386	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4387	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4388	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4389	[PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4390	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4391	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4392	[RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
4393	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
4394	[LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
4395	[GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
4396	[LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
4397	[GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
4398	[LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
4399	[GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
4400	[GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
4401	[GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
4402	[GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
4403	[GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
4404	[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
4405	[GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
4406	[GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
4407	[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
4408	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4409	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4410};
4411
4412static const struct qcom_reset_map gcc_ipq6018_resets[] = {
4413	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4414	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4415	[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4416	[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4417	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4418	[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4419	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4420	[GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4421	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4422	[GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4423	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4424	[GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4425	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4426	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4427	[GCC_SMMU_BCR] = { 0x12000, 0 },
4428	[GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4429	[GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4430	[GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4431	[GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4432	[GCC_PRNG_BCR] = { 0x13000, 0 },
4433	[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4434	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4435	[GCC_WCSS_BCR] = { 0x18000, 0 },
4436	[GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4437	[GCC_NSS_BCR] = { 0x19000, 0 },
4438	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4439	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4440	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
4441	[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4442	[GCC_PCNOC_BCR] = { 0x27018, 0 },
4443	[GCC_TCSR_BCR] = { 0x28000, 0 },
4444	[GCC_QDSS_BCR] = { 0x29000, 0 },
4445	[GCC_DCD_BCR] = { 0x2a000, 0 },
4446	[GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4447	[GCC_MPM_BCR] = { 0x2c000, 0 },
4448	[GCC_SPDM_BCR] = { 0x2f000, 0 },
4449	[GCC_RBCPR_BCR] = { 0x33000, 0 },
4450	[GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4451	[GCC_TLMM_BCR] = { 0x34000, 0 },
4452	[GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4453	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4454	[GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4455	[GCC_USB0_BCR] = { 0x3e070, 0 },
4456	[GCC_USB1_BCR] = { 0x3f070, 0 },
4457	[GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4458	[GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4459	[GCC_SDCC1_BCR] = { 0x42000, 0 },
4460	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4461	[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4462	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4463	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4464	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4465	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4466	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4467	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4468	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4469	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4470	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4471	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4472	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4473	[GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4474	[GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4475	[GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4476	[GCC_QPIC_BCR] = { 0x57018, 0 },
4477	[GCC_MDIO_BCR] = { 0x58000, 0 },
4478	[GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4479	[GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4480	[GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4481	[GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4482	[GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4483	[GCC_PCIE0_BCR] = { 0x75004, 0 },
4484	[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4485	[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4486	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4487	[GCC_DCC_BCR] = { 0x77000, 0 },
4488	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4489	[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4490	[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4491	[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4492	[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4493	[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4494	[GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4495	[GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4496	[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4497	[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4498	[GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4499	[GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4500	[GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4501	[GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4502	[GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4503	[GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4504	[GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4505	[GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4506	[GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4507	[GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4508	[GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4509	[GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4510	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4511	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4512	[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4513	[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4514	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4515	[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4516	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4517	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4518	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4519	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4520	[GCC_PPE_FULL_RESET] = { 0x68014, 0 },
4521	[GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
4522	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4523	[GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
4524	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4525	[GCC_EDMA_HW_RESET] = { 0x68014, 0 },
4526	[GCC_NSSPORT1_RESET] = { 0x68014, 0 },
4527	[GCC_NSSPORT2_RESET] = { 0x68014, 0 },
4528	[GCC_NSSPORT3_RESET] = { 0x68014, 0 },
4529	[GCC_NSSPORT4_RESET] = { 0x68014, 0 },
4530	[GCC_NSSPORT5_RESET] = { 0x68014, 0 },
4531	[GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
4532	[GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
4533	[GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
4534	[GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
4535	[GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
4536	[GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
4537	[GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
4538	[GCC_LPASS_BCR] = {0x1F000, 0},
4539	[GCC_UBI32_TBU_BCR] = {0x65000, 0},
4540	[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4541	[GCC_WCSSAON_RESET] = {0x59010, 0},
4542	[GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4543	[GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4544	[GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4545	[GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4546	[GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4547	[GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4548	[GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4549	[GCC_WCSS_DBG_ARES] = {0x59008, 0},
4550	[GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4551	[GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4552	[GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4553	[GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4554	[GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4555	[GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4556	[GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4557	[GCC_Q6_AHB_ARES] = {0x59110, 2},
4558	[GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4559	[GCC_Q6_AXIM_ARES] = {0x59110, 4},
4560};
4561
4562static const struct of_device_id gcc_ipq6018_match_table[] = {
4563	{ .compatible = "qcom,gcc-ipq6018" },
4564	{ }
4565};
4566MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
4567
4568static const struct regmap_config gcc_ipq6018_regmap_config = {
4569	.reg_bits       = 32,
4570	.reg_stride     = 4,
4571	.val_bits       = 32,
4572	.max_register   = 0x7fffc,
4573	.fast_io	= true,
4574};
4575
4576static const struct qcom_cc_desc gcc_ipq6018_desc = {
4577	.config = &gcc_ipq6018_regmap_config,
4578	.clks = gcc_ipq6018_clks,
4579	.num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
4580	.resets = gcc_ipq6018_resets,
4581	.num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
4582	.clk_hws = gcc_ipq6018_hws,
4583	.num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
4584};
4585
4586static int gcc_ipq6018_probe(struct platform_device *pdev)
4587{
4588	struct regmap *regmap;
4589
4590	regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc);
4591	if (IS_ERR(regmap))
4592		return PTR_ERR(regmap);
4593
4594	/* Disable SW_COLLAPSE for USB0 GDSCR */
4595	regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
4596	/* Enable SW_OVERRIDE for USB0 GDSCR */
4597	regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
4598	/* Disable SW_COLLAPSE for USB1 GDSCR */
4599	regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
4600	/* Enable SW_OVERRIDE for USB1 GDSCR */
4601	regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
4602
4603	/* SW Workaround for UBI Huyara PLL */
4604	regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4605
4606	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4607
4608	clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4609				&nss_crypto_pll_config);
4610
4611	return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
4612}
4613
4614static struct platform_driver gcc_ipq6018_driver = {
4615	.probe = gcc_ipq6018_probe,
4616	.driver = {
4617		.name   = "qcom,gcc-ipq6018",
4618		.of_match_table = gcc_ipq6018_match_table,
4619	},
4620};
4621
4622static int __init gcc_ipq6018_init(void)
4623{
4624	return platform_driver_register(&gcc_ipq6018_driver);
4625}
4626core_initcall(gcc_ipq6018_init);
4627
4628static void __exit gcc_ipq6018_exit(void)
4629{
4630	platform_driver_unregister(&gcc_ipq6018_driver);
4631}
4632module_exit(gcc_ipq6018_exit);
4633
4634MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
4635MODULE_LICENSE("GPL v2");