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1#include <linux/errno.h>
2#include <linux/kernel.h>
3#include <linux/mm.h>
4#include <linux/smp.h>
5#include <linux/prctl.h>
6#include <linux/slab.h>
7#include <linux/sched.h>
8#include <linux/module.h>
9#include <linux/pm.h>
10#include <linux/clockchips.h>
11#include <linux/random.h>
12#include <linux/user-return-notifier.h>
13#include <linux/dmi.h>
14#include <linux/utsname.h>
15#include <linux/stackprotector.h>
16#include <linux/tick.h>
17#include <linux/cpuidle.h>
18#include <trace/events/power.h>
19#include <linux/hw_breakpoint.h>
20#include <asm/cpu.h>
21#include <asm/apic.h>
22#include <asm/syscalls.h>
23#include <asm/idle.h>
24#include <asm/uaccess.h>
25#include <asm/i387.h>
26#include <asm/fpu-internal.h>
27#include <asm/debugreg.h>
28#include <asm/nmi.h>
29
30/*
31 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
32 * no more per-task TSS's. The TSS size is kept cacheline-aligned
33 * so they are allowed to end up in the .data..cacheline_aligned
34 * section. Since TSS's are completely CPU-local, we want them
35 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
36 */
37DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
38
39#ifdef CONFIG_X86_64
40static DEFINE_PER_CPU(unsigned char, is_idle);
41static ATOMIC_NOTIFIER_HEAD(idle_notifier);
42
43void idle_notifier_register(struct notifier_block *n)
44{
45 atomic_notifier_chain_register(&idle_notifier, n);
46}
47EXPORT_SYMBOL_GPL(idle_notifier_register);
48
49void idle_notifier_unregister(struct notifier_block *n)
50{
51 atomic_notifier_chain_unregister(&idle_notifier, n);
52}
53EXPORT_SYMBOL_GPL(idle_notifier_unregister);
54#endif
55
56struct kmem_cache *task_xstate_cachep;
57EXPORT_SYMBOL_GPL(task_xstate_cachep);
58
59/*
60 * this gets called so that we can store lazy state into memory and copy the
61 * current task into the new thread.
62 */
63int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
64{
65 int ret;
66
67 unlazy_fpu(src);
68
69 *dst = *src;
70 if (fpu_allocated(&src->thread.fpu)) {
71 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
72 ret = fpu_alloc(&dst->thread.fpu);
73 if (ret)
74 return ret;
75 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
76 }
77 return 0;
78}
79
80void free_thread_xstate(struct task_struct *tsk)
81{
82 fpu_free(&tsk->thread.fpu);
83}
84
85void arch_release_task_struct(struct task_struct *tsk)
86{
87 free_thread_xstate(tsk);
88}
89
90void arch_task_cache_init(void)
91{
92 task_xstate_cachep =
93 kmem_cache_create("task_xstate", xstate_size,
94 __alignof__(union thread_xstate),
95 SLAB_PANIC | SLAB_NOTRACK, NULL);
96}
97
98static inline void drop_fpu(struct task_struct *tsk)
99{
100 /*
101 * Forget coprocessor state..
102 */
103 tsk->fpu_counter = 0;
104 clear_fpu(tsk);
105 clear_used_math();
106}
107
108/*
109 * Free current thread data structures etc..
110 */
111void exit_thread(void)
112{
113 struct task_struct *me = current;
114 struct thread_struct *t = &me->thread;
115 unsigned long *bp = t->io_bitmap_ptr;
116
117 if (bp) {
118 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
119
120 t->io_bitmap_ptr = NULL;
121 clear_thread_flag(TIF_IO_BITMAP);
122 /*
123 * Careful, clear this in the TSS too:
124 */
125 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
126 t->io_bitmap_max = 0;
127 put_cpu();
128 kfree(bp);
129 }
130
131 drop_fpu(me);
132}
133
134void show_regs_common(void)
135{
136 const char *vendor, *product, *board;
137
138 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
139 if (!vendor)
140 vendor = "";
141 product = dmi_get_system_info(DMI_PRODUCT_NAME);
142 if (!product)
143 product = "";
144
145 /* Board Name is optional */
146 board = dmi_get_system_info(DMI_BOARD_NAME);
147
148 printk(KERN_CONT "\n");
149 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
150 current->pid, current->comm, print_tainted(),
151 init_utsname()->release,
152 (int)strcspn(init_utsname()->version, " "),
153 init_utsname()->version);
154 printk(KERN_CONT " %s %s", vendor, product);
155 if (board)
156 printk(KERN_CONT "/%s", board);
157 printk(KERN_CONT "\n");
158}
159
160void flush_thread(void)
161{
162 struct task_struct *tsk = current;
163
164 flush_ptrace_hw_breakpoint(tsk);
165 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
166 drop_fpu(tsk);
167}
168
169static void hard_disable_TSC(void)
170{
171 write_cr4(read_cr4() | X86_CR4_TSD);
172}
173
174void disable_TSC(void)
175{
176 preempt_disable();
177 if (!test_and_set_thread_flag(TIF_NOTSC))
178 /*
179 * Must flip the CPU state synchronously with
180 * TIF_NOTSC in the current running context.
181 */
182 hard_disable_TSC();
183 preempt_enable();
184}
185
186static void hard_enable_TSC(void)
187{
188 write_cr4(read_cr4() & ~X86_CR4_TSD);
189}
190
191static void enable_TSC(void)
192{
193 preempt_disable();
194 if (test_and_clear_thread_flag(TIF_NOTSC))
195 /*
196 * Must flip the CPU state synchronously with
197 * TIF_NOTSC in the current running context.
198 */
199 hard_enable_TSC();
200 preempt_enable();
201}
202
203int get_tsc_mode(unsigned long adr)
204{
205 unsigned int val;
206
207 if (test_thread_flag(TIF_NOTSC))
208 val = PR_TSC_SIGSEGV;
209 else
210 val = PR_TSC_ENABLE;
211
212 return put_user(val, (unsigned int __user *)adr);
213}
214
215int set_tsc_mode(unsigned int val)
216{
217 if (val == PR_TSC_SIGSEGV)
218 disable_TSC();
219 else if (val == PR_TSC_ENABLE)
220 enable_TSC();
221 else
222 return -EINVAL;
223
224 return 0;
225}
226
227void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
228 struct tss_struct *tss)
229{
230 struct thread_struct *prev, *next;
231
232 prev = &prev_p->thread;
233 next = &next_p->thread;
234
235 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
236 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
237 unsigned long debugctl = get_debugctlmsr();
238
239 debugctl &= ~DEBUGCTLMSR_BTF;
240 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
241 debugctl |= DEBUGCTLMSR_BTF;
242
243 update_debugctlmsr(debugctl);
244 }
245
246 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
247 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
248 /* prev and next are different */
249 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
250 hard_disable_TSC();
251 else
252 hard_enable_TSC();
253 }
254
255 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
256 /*
257 * Copy the relevant range of the IO bitmap.
258 * Normally this is 128 bytes or less:
259 */
260 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
261 max(prev->io_bitmap_max, next->io_bitmap_max));
262 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
263 /*
264 * Clear any possible leftover bits:
265 */
266 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
267 }
268 propagate_user_return_notify(prev_p, next_p);
269}
270
271int sys_fork(struct pt_regs *regs)
272{
273 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
274}
275
276/*
277 * This is trivial, and on the face of it looks like it
278 * could equally well be done in user mode.
279 *
280 * Not so, for quite unobvious reasons - register pressure.
281 * In user mode vfork() cannot have a stack frame, and if
282 * done by calling the "clone()" system call directly, you
283 * do not have enough call-clobbered registers to hold all
284 * the information you need.
285 */
286int sys_vfork(struct pt_regs *regs)
287{
288 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
289 NULL, NULL);
290}
291
292long
293sys_clone(unsigned long clone_flags, unsigned long newsp,
294 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
295{
296 if (!newsp)
297 newsp = regs->sp;
298 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
299}
300
301/*
302 * This gets run with %si containing the
303 * function to call, and %di containing
304 * the "args".
305 */
306extern void kernel_thread_helper(void);
307
308/*
309 * Create a kernel thread
310 */
311int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
312{
313 struct pt_regs regs;
314
315 memset(®s, 0, sizeof(regs));
316
317 regs.si = (unsigned long) fn;
318 regs.di = (unsigned long) arg;
319
320#ifdef CONFIG_X86_32
321 regs.ds = __USER_DS;
322 regs.es = __USER_DS;
323 regs.fs = __KERNEL_PERCPU;
324 regs.gs = __KERNEL_STACK_CANARY;
325#else
326 regs.ss = __KERNEL_DS;
327#endif
328
329 regs.orig_ax = -1;
330 regs.ip = (unsigned long) kernel_thread_helper;
331 regs.cs = __KERNEL_CS | get_kernel_rpl();
332 regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
333
334 /* Ok, create the new process.. */
335 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
336}
337EXPORT_SYMBOL(kernel_thread);
338
339/*
340 * sys_execve() executes a new program.
341 */
342long sys_execve(const char __user *name,
343 const char __user *const __user *argv,
344 const char __user *const __user *envp, struct pt_regs *regs)
345{
346 long error;
347 char *filename;
348
349 filename = getname(name);
350 error = PTR_ERR(filename);
351 if (IS_ERR(filename))
352 return error;
353 error = do_execve(filename, argv, envp, regs);
354
355#ifdef CONFIG_X86_32
356 if (error == 0) {
357 /* Make sure we don't return using sysenter.. */
358 set_thread_flag(TIF_IRET);
359 }
360#endif
361
362 putname(filename);
363 return error;
364}
365
366/*
367 * Idle related variables and functions
368 */
369unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
370EXPORT_SYMBOL(boot_option_idle_override);
371
372/*
373 * Powermanagement idle function, if any..
374 */
375void (*pm_idle)(void);
376#ifdef CONFIG_APM_MODULE
377EXPORT_SYMBOL(pm_idle);
378#endif
379
380static inline int hlt_use_halt(void)
381{
382 return 1;
383}
384
385#ifndef CONFIG_SMP
386static inline void play_dead(void)
387{
388 BUG();
389}
390#endif
391
392#ifdef CONFIG_X86_64
393void enter_idle(void)
394{
395 this_cpu_write(is_idle, 1);
396 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
397}
398
399static void __exit_idle(void)
400{
401 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
402 return;
403 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
404}
405
406/* Called from interrupts to signify idle end */
407void exit_idle(void)
408{
409 /* idle loop has pid 0 */
410 if (current->pid)
411 return;
412 __exit_idle();
413}
414#endif
415
416/*
417 * The idle thread. There's no useful work to be
418 * done, so just try to conserve power and have a
419 * low exit latency (ie sit in a loop waiting for
420 * somebody to say that they'd like to reschedule)
421 */
422void cpu_idle(void)
423{
424 /*
425 * If we're the non-boot CPU, nothing set the stack canary up
426 * for us. CPU0 already has it initialized but no harm in
427 * doing it again. This is a good place for updating it, as
428 * we wont ever return from this function (so the invalid
429 * canaries already on the stack wont ever trigger).
430 */
431 boot_init_stack_canary();
432 current_thread_info()->status |= TS_POLLING;
433
434 while (1) {
435 tick_nohz_idle_enter();
436
437 while (!need_resched()) {
438 rmb();
439
440 if (cpu_is_offline(smp_processor_id()))
441 play_dead();
442
443 /*
444 * Idle routines should keep interrupts disabled
445 * from here on, until they go to idle.
446 * Otherwise, idle callbacks can misfire.
447 */
448 local_touch_nmi();
449 local_irq_disable();
450
451 enter_idle();
452
453 /* Don't trace irqs off for idle */
454 stop_critical_timings();
455
456 /* enter_idle() needs rcu for notifiers */
457 rcu_idle_enter();
458
459 if (cpuidle_idle_call())
460 pm_idle();
461
462 rcu_idle_exit();
463 start_critical_timings();
464
465 /* In many cases the interrupt that ended idle
466 has already called exit_idle. But some idle
467 loops can be woken up without interrupt. */
468 __exit_idle();
469 }
470
471 tick_nohz_idle_exit();
472 preempt_enable_no_resched();
473 schedule();
474 preempt_disable();
475 }
476}
477
478/*
479 * We use this if we don't have any better
480 * idle routine..
481 */
482void default_idle(void)
483{
484 if (hlt_use_halt()) {
485 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
486 trace_cpu_idle_rcuidle(1, smp_processor_id());
487 current_thread_info()->status &= ~TS_POLLING;
488 /*
489 * TS_POLLING-cleared state must be visible before we
490 * test NEED_RESCHED:
491 */
492 smp_mb();
493
494 if (!need_resched())
495 safe_halt(); /* enables interrupts racelessly */
496 else
497 local_irq_enable();
498 current_thread_info()->status |= TS_POLLING;
499 trace_power_end_rcuidle(smp_processor_id());
500 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
501 } else {
502 local_irq_enable();
503 /* loop is done by the caller */
504 cpu_relax();
505 }
506}
507#ifdef CONFIG_APM_MODULE
508EXPORT_SYMBOL(default_idle);
509#endif
510
511bool set_pm_idle_to_default(void)
512{
513 bool ret = !!pm_idle;
514
515 pm_idle = default_idle;
516
517 return ret;
518}
519void stop_this_cpu(void *dummy)
520{
521 local_irq_disable();
522 /*
523 * Remove this CPU:
524 */
525 set_cpu_online(smp_processor_id(), false);
526 disable_local_APIC();
527
528 for (;;) {
529 if (hlt_works(smp_processor_id()))
530 halt();
531 }
532}
533
534/* Default MONITOR/MWAIT with no hints, used for default C1 state */
535static void mwait_idle(void)
536{
537 if (!need_resched()) {
538 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
539 trace_cpu_idle_rcuidle(1, smp_processor_id());
540 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
541 clflush((void *)¤t_thread_info()->flags);
542
543 __monitor((void *)¤t_thread_info()->flags, 0, 0);
544 smp_mb();
545 if (!need_resched())
546 __sti_mwait(0, 0);
547 else
548 local_irq_enable();
549 trace_power_end_rcuidle(smp_processor_id());
550 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
551 } else
552 local_irq_enable();
553}
554
555/*
556 * On SMP it's slightly faster (but much more power-consuming!)
557 * to poll the ->work.need_resched flag instead of waiting for the
558 * cross-CPU IPI to arrive. Use this option with caution.
559 */
560static void poll_idle(void)
561{
562 trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id());
563 trace_cpu_idle_rcuidle(0, smp_processor_id());
564 local_irq_enable();
565 while (!need_resched())
566 cpu_relax();
567 trace_power_end_rcuidle(smp_processor_id());
568 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
569}
570
571/*
572 * mwait selection logic:
573 *
574 * It depends on the CPU. For AMD CPUs that support MWAIT this is
575 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
576 * then depend on a clock divisor and current Pstate of the core. If
577 * all cores of a processor are in halt state (C1) the processor can
578 * enter the C1E (C1 enhanced) state. If mwait is used this will never
579 * happen.
580 *
581 * idle=mwait overrides this decision and forces the usage of mwait.
582 */
583
584#define MWAIT_INFO 0x05
585#define MWAIT_ECX_EXTENDED_INFO 0x01
586#define MWAIT_EDX_C1 0xf0
587
588int mwait_usable(const struct cpuinfo_x86 *c)
589{
590 u32 eax, ebx, ecx, edx;
591
592 /* Use mwait if idle=mwait boot option is given */
593 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
594 return 1;
595
596 /*
597 * Any idle= boot option other than idle=mwait means that we must not
598 * use mwait. Eg: idle=halt or idle=poll or idle=nomwait
599 */
600 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
601 return 0;
602
603 if (c->cpuid_level < MWAIT_INFO)
604 return 0;
605
606 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
607 /* Check, whether EDX has extended info about MWAIT */
608 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
609 return 1;
610
611 /*
612 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
613 * C1 supports MWAIT
614 */
615 return (edx & MWAIT_EDX_C1);
616}
617
618bool amd_e400_c1e_detected;
619EXPORT_SYMBOL(amd_e400_c1e_detected);
620
621static cpumask_var_t amd_e400_c1e_mask;
622
623void amd_e400_remove_cpu(int cpu)
624{
625 if (amd_e400_c1e_mask != NULL)
626 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
627}
628
629/*
630 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
631 * pending message MSR. If we detect C1E, then we handle it the same
632 * way as C3 power states (local apic timer and TSC stop)
633 */
634static void amd_e400_idle(void)
635{
636 if (need_resched())
637 return;
638
639 if (!amd_e400_c1e_detected) {
640 u32 lo, hi;
641
642 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
643
644 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
645 amd_e400_c1e_detected = true;
646 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
647 mark_tsc_unstable("TSC halt in AMD C1E");
648 printk(KERN_INFO "System has AMD C1E enabled\n");
649 }
650 }
651
652 if (amd_e400_c1e_detected) {
653 int cpu = smp_processor_id();
654
655 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
656 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
657 /*
658 * Force broadcast so ACPI can not interfere.
659 */
660 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
661 &cpu);
662 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
663 cpu);
664 }
665 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
666
667 default_idle();
668
669 /*
670 * The switch back from broadcast mode needs to be
671 * called with interrupts disabled.
672 */
673 local_irq_disable();
674 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
675 local_irq_enable();
676 } else
677 default_idle();
678}
679
680void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
681{
682#ifdef CONFIG_SMP
683 if (pm_idle == poll_idle && smp_num_siblings > 1) {
684 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
685 " performance may degrade.\n");
686 }
687#endif
688 if (pm_idle)
689 return;
690
691 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
692 /*
693 * One CPU supports mwait => All CPUs supports mwait
694 */
695 printk(KERN_INFO "using mwait in idle threads.\n");
696 pm_idle = mwait_idle;
697 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
698 /* E400: APIC timer interrupt does not wake up CPU from C1e */
699 printk(KERN_INFO "using AMD E400 aware idle routine\n");
700 pm_idle = amd_e400_idle;
701 } else
702 pm_idle = default_idle;
703}
704
705void __init init_amd_e400_c1e_mask(void)
706{
707 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
708 if (pm_idle == amd_e400_idle)
709 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
710}
711
712static int __init idle_setup(char *str)
713{
714 if (!str)
715 return -EINVAL;
716
717 if (!strcmp(str, "poll")) {
718 printk("using polling idle threads.\n");
719 pm_idle = poll_idle;
720 boot_option_idle_override = IDLE_POLL;
721 } else if (!strcmp(str, "mwait")) {
722 boot_option_idle_override = IDLE_FORCE_MWAIT;
723 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
724 } else if (!strcmp(str, "halt")) {
725 /*
726 * When the boot option of idle=halt is added, halt is
727 * forced to be used for CPU idle. In such case CPU C2/C3
728 * won't be used again.
729 * To continue to load the CPU idle driver, don't touch
730 * the boot_option_idle_override.
731 */
732 pm_idle = default_idle;
733 boot_option_idle_override = IDLE_HALT;
734 } else if (!strcmp(str, "nomwait")) {
735 /*
736 * If the boot option of "idle=nomwait" is added,
737 * it means that mwait will be disabled for CPU C2/C3
738 * states. In such case it won't touch the variable
739 * of boot_option_idle_override.
740 */
741 boot_option_idle_override = IDLE_NOMWAIT;
742 } else
743 return -1;
744
745 return 0;
746}
747early_param("idle", idle_setup);
748
749unsigned long arch_align_stack(unsigned long sp)
750{
751 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
752 sp -= get_random_int() % 8192;
753 return sp & ~0xf;
754}
755
756unsigned long arch_randomize_brk(struct mm_struct *mm)
757{
758 unsigned long range_end = mm->brk + 0x02000000;
759 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
760}
761
1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <linux/uaccess.h>
32#include <asm/mwait.h>
33#include <asm/fpu/api.h>
34#include <asm/fpu/sched.h>
35#include <asm/fpu/xstate.h>
36#include <asm/debugreg.h>
37#include <asm/nmi.h>
38#include <asm/tlbflush.h>
39#include <asm/mce.h>
40#include <asm/vm86.h>
41#include <asm/switch_to.h>
42#include <asm/desc.h>
43#include <asm/prctl.h>
44#include <asm/spec-ctrl.h>
45#include <asm/io_bitmap.h>
46#include <asm/proto.h>
47#include <asm/frame.h>
48#include <asm/unwind.h>
49#include <asm/tdx.h>
50
51#include "process.h"
52
53/*
54 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
55 * no more per-task TSS's. The TSS size is kept cacheline-aligned
56 * so they are allowed to end up in the .data..cacheline_aligned
57 * section. Since TSS's are completely CPU-local, we want them
58 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
59 */
60__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
61 .x86_tss = {
62 /*
63 * .sp0 is only used when entering ring 0 from a lower
64 * privilege level. Since the init task never runs anything
65 * but ring 0 code, there is no need for a valid value here.
66 * Poison it.
67 */
68 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
69
70#ifdef CONFIG_X86_32
71 .sp1 = TOP_OF_INIT_STACK,
72
73 .ss0 = __KERNEL_DS,
74 .ss1 = __KERNEL_CS,
75#endif
76 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
77 },
78};
79EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
80
81DEFINE_PER_CPU(bool, __tss_limit_invalid);
82EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
83
84/*
85 * this gets called so that we can store lazy state into memory and copy the
86 * current task into the new thread.
87 */
88int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
89{
90 memcpy(dst, src, arch_task_struct_size);
91#ifdef CONFIG_VM86
92 dst->thread.vm86 = NULL;
93#endif
94 /* Drop the copied pointer to current's fpstate */
95 dst->thread.fpu.fpstate = NULL;
96
97 return 0;
98}
99
100#ifdef CONFIG_X86_64
101void arch_release_task_struct(struct task_struct *tsk)
102{
103 if (fpu_state_size_dynamic())
104 fpstate_free(&tsk->thread.fpu);
105}
106#endif
107
108/*
109 * Free thread data structures etc..
110 */
111void exit_thread(struct task_struct *tsk)
112{
113 struct thread_struct *t = &tsk->thread;
114 struct fpu *fpu = &t->fpu;
115
116 if (test_thread_flag(TIF_IO_BITMAP))
117 io_bitmap_exit(tsk);
118
119 free_vm86(t);
120
121 fpu__drop(fpu);
122}
123
124static int set_new_tls(struct task_struct *p, unsigned long tls)
125{
126 struct user_desc __user *utls = (struct user_desc __user *)tls;
127
128 if (in_ia32_syscall())
129 return do_set_thread_area(p, -1, utls, 0);
130 else
131 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
132}
133
134int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
135{
136 unsigned long clone_flags = args->flags;
137 unsigned long sp = args->stack;
138 unsigned long tls = args->tls;
139 struct inactive_task_frame *frame;
140 struct fork_frame *fork_frame;
141 struct pt_regs *childregs;
142 int ret = 0;
143
144 childregs = task_pt_regs(p);
145 fork_frame = container_of(childregs, struct fork_frame, regs);
146 frame = &fork_frame->frame;
147
148 frame->bp = encode_frame_pointer(childregs);
149 frame->ret_addr = (unsigned long) ret_from_fork;
150 p->thread.sp = (unsigned long) fork_frame;
151 p->thread.io_bitmap = NULL;
152 p->thread.iopl_warn = 0;
153 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
154
155#ifdef CONFIG_X86_64
156 current_save_fsgs();
157 p->thread.fsindex = current->thread.fsindex;
158 p->thread.fsbase = current->thread.fsbase;
159 p->thread.gsindex = current->thread.gsindex;
160 p->thread.gsbase = current->thread.gsbase;
161
162 savesegment(es, p->thread.es);
163 savesegment(ds, p->thread.ds);
164#else
165 p->thread.sp0 = (unsigned long) (childregs + 1);
166 savesegment(gs, p->thread.gs);
167 /*
168 * Clear all status flags including IF and set fixed bit. 64bit
169 * does not have this initialization as the frame does not contain
170 * flags. The flags consistency (especially vs. AC) is there
171 * ensured via objtool, which lacks 32bit support.
172 */
173 frame->flags = X86_EFLAGS_FIXED;
174#endif
175
176 fpu_clone(p, clone_flags, args->fn);
177
178 /* Kernel thread ? */
179 if (unlikely(p->flags & PF_KTHREAD)) {
180 p->thread.pkru = pkru_get_init_value();
181 memset(childregs, 0, sizeof(struct pt_regs));
182 kthread_frame_init(frame, args->fn, args->fn_arg);
183 return 0;
184 }
185
186 /*
187 * Clone current's PKRU value from hardware. tsk->thread.pkru
188 * is only valid when scheduled out.
189 */
190 p->thread.pkru = read_pkru();
191
192 frame->bx = 0;
193 *childregs = *current_pt_regs();
194 childregs->ax = 0;
195 if (sp)
196 childregs->sp = sp;
197
198 if (unlikely(args->fn)) {
199 /*
200 * A user space thread, but it doesn't return to
201 * ret_after_fork().
202 *
203 * In order to indicate that to tools like gdb,
204 * we reset the stack and instruction pointers.
205 *
206 * It does the same kernel frame setup to return to a kernel
207 * function that a kernel thread does.
208 */
209 childregs->sp = 0;
210 childregs->ip = 0;
211 kthread_frame_init(frame, args->fn, args->fn_arg);
212 return 0;
213 }
214
215 /* Set a new TLS for the child thread? */
216 if (clone_flags & CLONE_SETTLS)
217 ret = set_new_tls(p, tls);
218
219 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
220 io_bitmap_share(p);
221
222 return ret;
223}
224
225static void pkru_flush_thread(void)
226{
227 /*
228 * If PKRU is enabled the default PKRU value has to be loaded into
229 * the hardware right here (similar to context switch).
230 */
231 pkru_write_default();
232}
233
234void flush_thread(void)
235{
236 struct task_struct *tsk = current;
237
238 flush_ptrace_hw_breakpoint(tsk);
239 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
240
241 fpu_flush_thread();
242 pkru_flush_thread();
243}
244
245void disable_TSC(void)
246{
247 preempt_disable();
248 if (!test_and_set_thread_flag(TIF_NOTSC))
249 /*
250 * Must flip the CPU state synchronously with
251 * TIF_NOTSC in the current running context.
252 */
253 cr4_set_bits(X86_CR4_TSD);
254 preempt_enable();
255}
256
257static void enable_TSC(void)
258{
259 preempt_disable();
260 if (test_and_clear_thread_flag(TIF_NOTSC))
261 /*
262 * Must flip the CPU state synchronously with
263 * TIF_NOTSC in the current running context.
264 */
265 cr4_clear_bits(X86_CR4_TSD);
266 preempt_enable();
267}
268
269int get_tsc_mode(unsigned long adr)
270{
271 unsigned int val;
272
273 if (test_thread_flag(TIF_NOTSC))
274 val = PR_TSC_SIGSEGV;
275 else
276 val = PR_TSC_ENABLE;
277
278 return put_user(val, (unsigned int __user *)adr);
279}
280
281int set_tsc_mode(unsigned int val)
282{
283 if (val == PR_TSC_SIGSEGV)
284 disable_TSC();
285 else if (val == PR_TSC_ENABLE)
286 enable_TSC();
287 else
288 return -EINVAL;
289
290 return 0;
291}
292
293DEFINE_PER_CPU(u64, msr_misc_features_shadow);
294
295static void set_cpuid_faulting(bool on)
296{
297 u64 msrval;
298
299 msrval = this_cpu_read(msr_misc_features_shadow);
300 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
301 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
302 this_cpu_write(msr_misc_features_shadow, msrval);
303 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
304}
305
306static void disable_cpuid(void)
307{
308 preempt_disable();
309 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
310 /*
311 * Must flip the CPU state synchronously with
312 * TIF_NOCPUID in the current running context.
313 */
314 set_cpuid_faulting(true);
315 }
316 preempt_enable();
317}
318
319static void enable_cpuid(void)
320{
321 preempt_disable();
322 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
323 /*
324 * Must flip the CPU state synchronously with
325 * TIF_NOCPUID in the current running context.
326 */
327 set_cpuid_faulting(false);
328 }
329 preempt_enable();
330}
331
332static int get_cpuid_mode(void)
333{
334 return !test_thread_flag(TIF_NOCPUID);
335}
336
337static int set_cpuid_mode(unsigned long cpuid_enabled)
338{
339 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
340 return -ENODEV;
341
342 if (cpuid_enabled)
343 enable_cpuid();
344 else
345 disable_cpuid();
346
347 return 0;
348}
349
350/*
351 * Called immediately after a successful exec.
352 */
353void arch_setup_new_exec(void)
354{
355 /* If cpuid was previously disabled for this task, re-enable it. */
356 if (test_thread_flag(TIF_NOCPUID))
357 enable_cpuid();
358
359 /*
360 * Don't inherit TIF_SSBD across exec boundary when
361 * PR_SPEC_DISABLE_NOEXEC is used.
362 */
363 if (test_thread_flag(TIF_SSBD) &&
364 task_spec_ssb_noexec(current)) {
365 clear_thread_flag(TIF_SSBD);
366 task_clear_spec_ssb_disable(current);
367 task_clear_spec_ssb_noexec(current);
368 speculation_ctrl_update(read_thread_flags());
369 }
370}
371
372#ifdef CONFIG_X86_IOPL_IOPERM
373static inline void switch_to_bitmap(unsigned long tifp)
374{
375 /*
376 * Invalidate I/O bitmap if the previous task used it. This prevents
377 * any possible leakage of an active I/O bitmap.
378 *
379 * If the next task has an I/O bitmap it will handle it on exit to
380 * user mode.
381 */
382 if (tifp & _TIF_IO_BITMAP)
383 tss_invalidate_io_bitmap();
384}
385
386static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
387{
388 /*
389 * Copy at least the byte range of the incoming tasks bitmap which
390 * covers the permitted I/O ports.
391 *
392 * If the previous task which used an I/O bitmap had more bits
393 * permitted, then the copy needs to cover those as well so they
394 * get turned off.
395 */
396 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
397 max(tss->io_bitmap.prev_max, iobm->max));
398
399 /*
400 * Store the new max and the sequence number of this bitmap
401 * and a pointer to the bitmap itself.
402 */
403 tss->io_bitmap.prev_max = iobm->max;
404 tss->io_bitmap.prev_sequence = iobm->sequence;
405}
406
407/**
408 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode
409 */
410void native_tss_update_io_bitmap(void)
411{
412 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
413 struct thread_struct *t = ¤t->thread;
414 u16 *base = &tss->x86_tss.io_bitmap_base;
415
416 if (!test_thread_flag(TIF_IO_BITMAP)) {
417 native_tss_invalidate_io_bitmap();
418 return;
419 }
420
421 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
422 *base = IO_BITMAP_OFFSET_VALID_ALL;
423 } else {
424 struct io_bitmap *iobm = t->io_bitmap;
425
426 /*
427 * Only copy bitmap data when the sequence number differs. The
428 * update time is accounted to the incoming task.
429 */
430 if (tss->io_bitmap.prev_sequence != iobm->sequence)
431 tss_copy_io_bitmap(tss, iobm);
432
433 /* Enable the bitmap */
434 *base = IO_BITMAP_OFFSET_VALID_MAP;
435 }
436
437 /*
438 * Make sure that the TSS limit is covering the IO bitmap. It might have
439 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
440 * access from user space to trigger a #GP because tbe bitmap is outside
441 * the TSS limit.
442 */
443 refresh_tss_limit();
444}
445#else /* CONFIG_X86_IOPL_IOPERM */
446static inline void switch_to_bitmap(unsigned long tifp) { }
447#endif
448
449#ifdef CONFIG_SMP
450
451struct ssb_state {
452 struct ssb_state *shared_state;
453 raw_spinlock_t lock;
454 unsigned int disable_state;
455 unsigned long local_state;
456};
457
458#define LSTATE_SSB 0
459
460static DEFINE_PER_CPU(struct ssb_state, ssb_state);
461
462void speculative_store_bypass_ht_init(void)
463{
464 struct ssb_state *st = this_cpu_ptr(&ssb_state);
465 unsigned int this_cpu = smp_processor_id();
466 unsigned int cpu;
467
468 st->local_state = 0;
469
470 /*
471 * Shared state setup happens once on the first bringup
472 * of the CPU. It's not destroyed on CPU hotunplug.
473 */
474 if (st->shared_state)
475 return;
476
477 raw_spin_lock_init(&st->lock);
478
479 /*
480 * Go over HT siblings and check whether one of them has set up the
481 * shared state pointer already.
482 */
483 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
484 if (cpu == this_cpu)
485 continue;
486
487 if (!per_cpu(ssb_state, cpu).shared_state)
488 continue;
489
490 /* Link it to the state of the sibling: */
491 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
492 return;
493 }
494
495 /*
496 * First HT sibling to come up on the core. Link shared state of
497 * the first HT sibling to itself. The siblings on the same core
498 * which come up later will see the shared state pointer and link
499 * themselves to the state of this CPU.
500 */
501 st->shared_state = st;
502}
503
504/*
505 * Logic is: First HT sibling enables SSBD for both siblings in the core
506 * and last sibling to disable it, disables it for the whole core. This how
507 * MSR_SPEC_CTRL works in "hardware":
508 *
509 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
510 */
511static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
512{
513 struct ssb_state *st = this_cpu_ptr(&ssb_state);
514 u64 msr = x86_amd_ls_cfg_base;
515
516 if (!static_cpu_has(X86_FEATURE_ZEN)) {
517 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
518 wrmsrl(MSR_AMD64_LS_CFG, msr);
519 return;
520 }
521
522 if (tifn & _TIF_SSBD) {
523 /*
524 * Since this can race with prctl(), block reentry on the
525 * same CPU.
526 */
527 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
528 return;
529
530 msr |= x86_amd_ls_cfg_ssbd_mask;
531
532 raw_spin_lock(&st->shared_state->lock);
533 /* First sibling enables SSBD: */
534 if (!st->shared_state->disable_state)
535 wrmsrl(MSR_AMD64_LS_CFG, msr);
536 st->shared_state->disable_state++;
537 raw_spin_unlock(&st->shared_state->lock);
538 } else {
539 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
540 return;
541
542 raw_spin_lock(&st->shared_state->lock);
543 st->shared_state->disable_state--;
544 if (!st->shared_state->disable_state)
545 wrmsrl(MSR_AMD64_LS_CFG, msr);
546 raw_spin_unlock(&st->shared_state->lock);
547 }
548}
549#else
550static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
551{
552 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
553
554 wrmsrl(MSR_AMD64_LS_CFG, msr);
555}
556#endif
557
558static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
559{
560 /*
561 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
562 * so ssbd_tif_to_spec_ctrl() just works.
563 */
564 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
565}
566
567/*
568 * Update the MSRs managing speculation control, during context switch.
569 *
570 * tifp: Previous task's thread flags
571 * tifn: Next task's thread flags
572 */
573static __always_inline void __speculation_ctrl_update(unsigned long tifp,
574 unsigned long tifn)
575{
576 unsigned long tif_diff = tifp ^ tifn;
577 u64 msr = x86_spec_ctrl_base;
578 bool updmsr = false;
579
580 lockdep_assert_irqs_disabled();
581
582 /* Handle change of TIF_SSBD depending on the mitigation method. */
583 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
584 if (tif_diff & _TIF_SSBD)
585 amd_set_ssb_virt_state(tifn);
586 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
587 if (tif_diff & _TIF_SSBD)
588 amd_set_core_ssb_state(tifn);
589 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
590 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
591 updmsr |= !!(tif_diff & _TIF_SSBD);
592 msr |= ssbd_tif_to_spec_ctrl(tifn);
593 }
594
595 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
596 if (IS_ENABLED(CONFIG_SMP) &&
597 static_branch_unlikely(&switch_to_cond_stibp)) {
598 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
599 msr |= stibp_tif_to_spec_ctrl(tifn);
600 }
601
602 if (updmsr)
603 update_spec_ctrl_cond(msr);
604}
605
606static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
607{
608 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
609 if (task_spec_ssb_disable(tsk))
610 set_tsk_thread_flag(tsk, TIF_SSBD);
611 else
612 clear_tsk_thread_flag(tsk, TIF_SSBD);
613
614 if (task_spec_ib_disable(tsk))
615 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
616 else
617 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
618 }
619 /* Return the updated threadinfo flags*/
620 return read_task_thread_flags(tsk);
621}
622
623void speculation_ctrl_update(unsigned long tif)
624{
625 unsigned long flags;
626
627 /* Forced update. Make sure all relevant TIF flags are different */
628 local_irq_save(flags);
629 __speculation_ctrl_update(~tif, tif);
630 local_irq_restore(flags);
631}
632
633/* Called from seccomp/prctl update */
634void speculation_ctrl_update_current(void)
635{
636 preempt_disable();
637 speculation_ctrl_update(speculation_ctrl_update_tif(current));
638 preempt_enable();
639}
640
641static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
642{
643 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
644
645 newval = cr4 ^ mask;
646 if (newval != cr4) {
647 this_cpu_write(cpu_tlbstate.cr4, newval);
648 __write_cr4(newval);
649 }
650}
651
652void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
653{
654 unsigned long tifp, tifn;
655
656 tifn = read_task_thread_flags(next_p);
657 tifp = read_task_thread_flags(prev_p);
658
659 switch_to_bitmap(tifp);
660
661 propagate_user_return_notify(prev_p, next_p);
662
663 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
664 arch_has_block_step()) {
665 unsigned long debugctl, msk;
666
667 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
668 debugctl &= ~DEBUGCTLMSR_BTF;
669 msk = tifn & _TIF_BLOCKSTEP;
670 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
671 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
672 }
673
674 if ((tifp ^ tifn) & _TIF_NOTSC)
675 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
676
677 if ((tifp ^ tifn) & _TIF_NOCPUID)
678 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
679
680 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
681 __speculation_ctrl_update(tifp, tifn);
682 } else {
683 speculation_ctrl_update_tif(prev_p);
684 tifn = speculation_ctrl_update_tif(next_p);
685
686 /* Enforce MSR update to ensure consistent state */
687 __speculation_ctrl_update(~tifn, tifn);
688 }
689}
690
691/*
692 * Idle related variables and functions
693 */
694unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
695EXPORT_SYMBOL(boot_option_idle_override);
696
697static void (*x86_idle)(void);
698
699#ifndef CONFIG_SMP
700static inline void play_dead(void)
701{
702 BUG();
703}
704#endif
705
706void arch_cpu_idle_enter(void)
707{
708 tsc_verify_tsc_adjust(false);
709 local_touch_nmi();
710}
711
712void arch_cpu_idle_dead(void)
713{
714 play_dead();
715}
716
717/*
718 * Called from the generic idle code.
719 */
720void arch_cpu_idle(void)
721{
722 x86_idle();
723}
724
725/*
726 * We use this if we don't have any better idle routine..
727 */
728void __cpuidle default_idle(void)
729{
730 raw_safe_halt();
731}
732#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
733EXPORT_SYMBOL(default_idle);
734#endif
735
736#ifdef CONFIG_XEN
737bool xen_set_default_idle(void)
738{
739 bool ret = !!x86_idle;
740
741 x86_idle = default_idle;
742
743 return ret;
744}
745#endif
746
747void __noreturn stop_this_cpu(void *dummy)
748{
749 local_irq_disable();
750 /*
751 * Remove this CPU:
752 */
753 set_cpu_online(smp_processor_id(), false);
754 disable_local_APIC();
755 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
756
757 /*
758 * Use wbinvd on processors that support SME. This provides support
759 * for performing a successful kexec when going from SME inactive
760 * to SME active (or vice-versa). The cache must be cleared so that
761 * if there are entries with the same physical address, both with and
762 * without the encryption bit, they don't race each other when flushed
763 * and potentially end up with the wrong entry being committed to
764 * memory.
765 *
766 * Test the CPUID bit directly because the machine might've cleared
767 * X86_FEATURE_SME due to cmdline options.
768 */
769 if (cpuid_eax(0x8000001f) & BIT(0))
770 native_wbinvd();
771 for (;;) {
772 /*
773 * Use native_halt() so that memory contents don't change
774 * (stack usage and variables) after possibly issuing the
775 * native_wbinvd() above.
776 */
777 native_halt();
778 }
779}
780
781/*
782 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
783 * states (local apic timer and TSC stop).
784 *
785 * XXX this function is completely buggered vs RCU and tracing.
786 */
787static void amd_e400_idle(void)
788{
789 /*
790 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
791 * gets set after static_cpu_has() places have been converted via
792 * alternatives.
793 */
794 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
795 default_idle();
796 return;
797 }
798
799 tick_broadcast_enter();
800
801 default_idle();
802
803 /*
804 * The switch back from broadcast mode needs to be called with
805 * interrupts disabled.
806 */
807 raw_local_irq_disable();
808 tick_broadcast_exit();
809 raw_local_irq_enable();
810}
811
812/*
813 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf
814 * exists and whenever MONITOR/MWAIT extensions are present there is at
815 * least one C1 substate.
816 *
817 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait
818 * is passed to kernel commandline parameter.
819 */
820static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
821{
822 u32 eax, ebx, ecx, edx;
823
824 /* User has disallowed the use of MWAIT. Fallback to HALT */
825 if (boot_option_idle_override == IDLE_NOMWAIT)
826 return 0;
827
828 /* MWAIT is not supported on this platform. Fallback to HALT */
829 if (!cpu_has(c, X86_FEATURE_MWAIT))
830 return 0;
831
832 /* Monitor has a bug. Fallback to HALT */
833 if (boot_cpu_has_bug(X86_BUG_MONITOR))
834 return 0;
835
836 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
837
838 /*
839 * If MWAIT extensions are not available, it is safe to use MWAIT
840 * with EAX=0, ECX=0.
841 */
842 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED))
843 return 1;
844
845 /*
846 * If MWAIT extensions are available, there should be at least one
847 * MWAIT C1 substate present.
848 */
849 return (edx & MWAIT_C1_SUBSTATE_MASK);
850}
851
852/*
853 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
854 * with interrupts enabled and no flags, which is backwards compatible with the
855 * original MWAIT implementation.
856 */
857static __cpuidle void mwait_idle(void)
858{
859 if (!current_set_polling_and_test()) {
860 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
861 mb(); /* quirk */
862 clflush((void *)¤t_thread_info()->flags);
863 mb(); /* quirk */
864 }
865
866 __monitor((void *)¤t_thread_info()->flags, 0, 0);
867 if (!need_resched())
868 __sti_mwait(0, 0);
869 else
870 raw_local_irq_enable();
871 } else {
872 raw_local_irq_enable();
873 }
874 __current_clr_polling();
875}
876
877void select_idle_routine(const struct cpuinfo_x86 *c)
878{
879#ifdef CONFIG_SMP
880 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
881 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
882#endif
883 if (x86_idle || boot_option_idle_override == IDLE_POLL)
884 return;
885
886 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
887 pr_info("using AMD E400 aware idle routine\n");
888 x86_idle = amd_e400_idle;
889 } else if (prefer_mwait_c1_over_halt(c)) {
890 pr_info("using mwait in idle threads\n");
891 x86_idle = mwait_idle;
892 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
893 pr_info("using TDX aware idle routine\n");
894 x86_idle = tdx_safe_halt;
895 } else
896 x86_idle = default_idle;
897}
898
899void amd_e400_c1e_apic_setup(void)
900{
901 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
902 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
903 local_irq_disable();
904 tick_broadcast_force();
905 local_irq_enable();
906 }
907}
908
909void __init arch_post_acpi_subsys_init(void)
910{
911 u32 lo, hi;
912
913 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
914 return;
915
916 /*
917 * AMD E400 detection needs to happen after ACPI has been enabled. If
918 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
919 * MSR_K8_INT_PENDING_MSG.
920 */
921 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
922 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
923 return;
924
925 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
926
927 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
928 mark_tsc_unstable("TSC halt in AMD C1E");
929 pr_info("System has AMD C1E enabled\n");
930}
931
932static int __init idle_setup(char *str)
933{
934 if (!str)
935 return -EINVAL;
936
937 if (!strcmp(str, "poll")) {
938 pr_info("using polling idle threads\n");
939 boot_option_idle_override = IDLE_POLL;
940 cpu_idle_poll_ctrl(true);
941 } else if (!strcmp(str, "halt")) {
942 /*
943 * When the boot option of idle=halt is added, halt is
944 * forced to be used for CPU idle. In such case CPU C2/C3
945 * won't be used again.
946 * To continue to load the CPU idle driver, don't touch
947 * the boot_option_idle_override.
948 */
949 x86_idle = default_idle;
950 boot_option_idle_override = IDLE_HALT;
951 } else if (!strcmp(str, "nomwait")) {
952 /*
953 * If the boot option of "idle=nomwait" is added,
954 * it means that mwait will be disabled for CPU C1/C2/C3
955 * states.
956 */
957 boot_option_idle_override = IDLE_NOMWAIT;
958 } else
959 return -1;
960
961 return 0;
962}
963early_param("idle", idle_setup);
964
965unsigned long arch_align_stack(unsigned long sp)
966{
967 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
968 sp -= get_random_u32_below(8192);
969 return sp & ~0xf;
970}
971
972unsigned long arch_randomize_brk(struct mm_struct *mm)
973{
974 return randomize_page(mm->brk, 0x02000000);
975}
976
977/*
978 * Called from fs/proc with a reference on @p to find the function
979 * which called into schedule(). This needs to be done carefully
980 * because the task might wake up and we might look at a stack
981 * changing under us.
982 */
983unsigned long __get_wchan(struct task_struct *p)
984{
985 struct unwind_state state;
986 unsigned long addr = 0;
987
988 if (!try_get_task_stack(p))
989 return 0;
990
991 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state);
992 unwind_next_frame(&state)) {
993 addr = unwind_get_return_address(&state);
994 if (!addr)
995 break;
996 if (in_sched_functions(addr))
997 continue;
998 break;
999 }
1000
1001 put_task_stack(p);
1002
1003 return addr;
1004}
1005
1006long do_arch_prctl_common(int option, unsigned long arg2)
1007{
1008 switch (option) {
1009 case ARCH_GET_CPUID:
1010 return get_cpuid_mode();
1011 case ARCH_SET_CPUID:
1012 return set_cpuid_mode(arg2);
1013 case ARCH_GET_XCOMP_SUPP:
1014 case ARCH_GET_XCOMP_PERM:
1015 case ARCH_REQ_XCOMP_PERM:
1016 case ARCH_GET_XCOMP_GUEST_PERM:
1017 case ARCH_REQ_XCOMP_GUEST_PERM:
1018 return fpu_xstate_prctl(option, arg2);
1019 }
1020
1021 return -EINVAL;
1022}