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1/*
2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
3 *
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
9 */
10
11
12#include <linux/linkage.h>
13#include <linux/threads.h>
14#include <linux/init.h>
15#include <asm/segment.h>
16#include <asm/pgtable.h>
17#include <asm/page.h>
18#include <asm/msr.h>
19#include <asm/cache.h>
20#include <asm/processor-flags.h>
21#include <asm/percpu.h>
22#include <asm/nops.h>
23
24#ifdef CONFIG_PARAVIRT
25#include <asm/asm-offsets.h>
26#include <asm/paravirt.h>
27#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
28#else
29#define GET_CR2_INTO(reg) movq %cr2, reg
30#define INTERRUPT_RETURN iretq
31#endif
32
33/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
34 * because we need identity-mapped pages.
35 *
36 */
37
38#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
39
40L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
41L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
42L4_START_KERNEL = pgd_index(__START_KERNEL_map)
43L3_START_KERNEL = pud_index(__START_KERNEL_map)
44
45 .text
46 __HEAD
47 .code64
48 .globl startup_64
49startup_64:
50
51 /*
52 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
53 * and someone has loaded an identity mapped page table
54 * for us. These identity mapped page tables map all of the
55 * kernel pages and possibly all of memory.
56 *
57 * %esi holds a physical pointer to real_mode_data.
58 *
59 * We come here either directly from a 64bit bootloader, or from
60 * arch/x86_64/boot/compressed/head.S.
61 *
62 * We only come here initially at boot nothing else comes here.
63 *
64 * Since we may be loaded at an address different from what we were
65 * compiled to run at we first fixup the physical addresses in our page
66 * tables and then reload them.
67 */
68
69 /* Compute the delta between the address I am compiled to run at and the
70 * address I am actually running at.
71 */
72 leaq _text(%rip), %rbp
73 subq $_text - __START_KERNEL_map, %rbp
74
75 /* Is the address not 2M aligned? */
76 movq %rbp, %rax
77 andl $~PMD_PAGE_MASK, %eax
78 testl %eax, %eax
79 jnz bad_address
80
81 /* Is the address too large? */
82 leaq _text(%rip), %rdx
83 movq $PGDIR_SIZE, %rax
84 cmpq %rax, %rdx
85 jae bad_address
86
87 /* Fixup the physical addresses in the page table
88 */
89 addq %rbp, init_level4_pgt + 0(%rip)
90 addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
91 addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
92
93 addq %rbp, level3_ident_pgt + 0(%rip)
94
95 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
96 addq %rbp, level3_kernel_pgt + (511*8)(%rip)
97
98 addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
99
100 /* Add an Identity mapping if I am above 1G */
101 leaq _text(%rip), %rdi
102 andq $PMD_PAGE_MASK, %rdi
103
104 movq %rdi, %rax
105 shrq $PUD_SHIFT, %rax
106 andq $(PTRS_PER_PUD - 1), %rax
107 jz ident_complete
108
109 leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
110 leaq level3_ident_pgt(%rip), %rbx
111 movq %rdx, 0(%rbx, %rax, 8)
112
113 movq %rdi, %rax
114 shrq $PMD_SHIFT, %rax
115 andq $(PTRS_PER_PMD - 1), %rax
116 leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
117 leaq level2_spare_pgt(%rip), %rbx
118 movq %rdx, 0(%rbx, %rax, 8)
119ident_complete:
120
121 /*
122 * Fixup the kernel text+data virtual addresses. Note that
123 * we might write invalid pmds, when the kernel is relocated
124 * cleanup_highmap() fixes this up along with the mappings
125 * beyond _end.
126 */
127
128 leaq level2_kernel_pgt(%rip), %rdi
129 leaq 4096(%rdi), %r8
130 /* See if it is a valid page table entry */
1311: testq $1, 0(%rdi)
132 jz 2f
133 addq %rbp, 0(%rdi)
134 /* Go to the next page */
1352: addq $8, %rdi
136 cmp %r8, %rdi
137 jne 1b
138
139 /* Fixup phys_base */
140 addq %rbp, phys_base(%rip)
141
142 /* Due to ENTRY(), sometimes the empty space gets filled with
143 * zeros. Better take a jmp than relying on empty space being
144 * filled with 0x90 (nop)
145 */
146 jmp secondary_startup_64
147ENTRY(secondary_startup_64)
148 /*
149 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
150 * and someone has loaded a mapped page table.
151 *
152 * %esi holds a physical pointer to real_mode_data.
153 *
154 * We come here either from startup_64 (using physical addresses)
155 * or from trampoline.S (using virtual addresses).
156 *
157 * Using virtual addresses from trampoline.S removes the need
158 * to have any identity mapped pages in the kernel page table
159 * after the boot processor executes this code.
160 */
161
162 /* Enable PAE mode and PGE */
163 movl $(X86_CR4_PAE | X86_CR4_PGE), %eax
164 movq %rax, %cr4
165
166 /* Setup early boot stage 4 level pagetables. */
167 movq $(init_level4_pgt - __START_KERNEL_map), %rax
168 addq phys_base(%rip), %rax
169 movq %rax, %cr3
170
171 /* Ensure I am executing from virtual addresses */
172 movq $1f, %rax
173 jmp *%rax
1741:
175
176 /* Check if nx is implemented */
177 movl $0x80000001, %eax
178 cpuid
179 movl %edx,%edi
180
181 /* Setup EFER (Extended Feature Enable Register) */
182 movl $MSR_EFER, %ecx
183 rdmsr
184 btsl $_EFER_SCE, %eax /* Enable System Call */
185 btl $20,%edi /* No Execute supported? */
186 jnc 1f
187 btsl $_EFER_NX, %eax
1881: wrmsr /* Make changes effective */
189
190 /* Setup cr0 */
191#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
192 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
193 X86_CR0_PG)
194 movl $CR0_STATE, %eax
195 /* Make changes effective */
196 movq %rax, %cr0
197
198 /* Setup a boot time stack */
199 movq stack_start(%rip),%rsp
200
201 /* zero EFLAGS after setting rsp */
202 pushq $0
203 popfq
204
205 /*
206 * We must switch to a new descriptor in kernel space for the GDT
207 * because soon the kernel won't have access anymore to the userspace
208 * addresses where we're currently running on. We have to do that here
209 * because in 32bit we couldn't load a 64bit linear address.
210 */
211 lgdt early_gdt_descr(%rip)
212
213 /* set up data segments */
214 xorl %eax,%eax
215 movl %eax,%ds
216 movl %eax,%ss
217 movl %eax,%es
218
219 /*
220 * We don't really need to load %fs or %gs, but load them anyway
221 * to kill any stale realmode selectors. This allows execution
222 * under VT hardware.
223 */
224 movl %eax,%fs
225 movl %eax,%gs
226
227 /* Set up %gs.
228 *
229 * The base of %gs always points to the bottom of the irqstack
230 * union. If the stack protector canary is enabled, it is
231 * located at %gs:40. Note that, on SMP, the boot cpu uses
232 * init data section till per cpu areas are set up.
233 */
234 movl $MSR_GS_BASE,%ecx
235 movl initial_gs(%rip),%eax
236 movl initial_gs+4(%rip),%edx
237 wrmsr
238
239 /* esi is pointer to real mode structure with interesting info.
240 pass it to C */
241 movl %esi, %edi
242
243 /* Finally jump to run C code and to be on real kernel address
244 * Since we are running on identity-mapped space we have to jump
245 * to the full 64bit address, this is only possible as indirect
246 * jump. In addition we need to ensure %cs is set so we make this
247 * a far return.
248 */
249 movq initial_code(%rip),%rax
250 pushq $0 # fake return address to stop unwinder
251 pushq $__KERNEL_CS # set correct cs
252 pushq %rax # target address in negative space
253 lretq
254
255 /* SMP bootup changes these two */
256 __REFDATA
257 .align 8
258 ENTRY(initial_code)
259 .quad x86_64_start_kernel
260 ENTRY(initial_gs)
261 .quad INIT_PER_CPU_VAR(irq_stack_union)
262
263 ENTRY(stack_start)
264 .quad init_thread_union+THREAD_SIZE-8
265 .word 0
266 __FINITDATA
267
268bad_address:
269 jmp bad_address
270
271 .section ".init.text","ax"
272 .globl early_idt_handlers
273early_idt_handlers:
274 # 104(%rsp) %rflags
275 # 96(%rsp) %cs
276 # 88(%rsp) %rip
277 # 80(%rsp) error code
278 i = 0
279 .rept NUM_EXCEPTION_VECTORS
280 .if (EXCEPTION_ERRCODE_MASK >> i) & 1
281 ASM_NOP2
282 .else
283 pushq $0 # Dummy error code, to make stack frame uniform
284 .endif
285 pushq $i # 72(%rsp) Vector number
286 jmp early_idt_handler
287 i = i + 1
288 .endr
289
290ENTRY(early_idt_handler)
291 cld
292
293 cmpl $2,early_recursion_flag(%rip)
294 jz 1f
295 incl early_recursion_flag(%rip)
296
297 pushq %rax # 64(%rsp)
298 pushq %rcx # 56(%rsp)
299 pushq %rdx # 48(%rsp)
300 pushq %rsi # 40(%rsp)
301 pushq %rdi # 32(%rsp)
302 pushq %r8 # 24(%rsp)
303 pushq %r9 # 16(%rsp)
304 pushq %r10 # 8(%rsp)
305 pushq %r11 # 0(%rsp)
306
307 cmpl $__KERNEL_CS,96(%rsp)
308 jne 10f
309
310 leaq 88(%rsp),%rdi # Pointer to %rip
311 call early_fixup_exception
312 andl %eax,%eax
313 jnz 20f # Found an exception entry
314
31510:
316#ifdef CONFIG_EARLY_PRINTK
317 GET_CR2_INTO(%r9) # can clobber any volatile register if pv
318 movl 80(%rsp),%r8d # error code
319 movl 72(%rsp),%esi # vector number
320 movl 96(%rsp),%edx # %cs
321 movq 88(%rsp),%rcx # %rip
322 xorl %eax,%eax
323 leaq early_idt_msg(%rip),%rdi
324 call early_printk
325 cmpl $2,early_recursion_flag(%rip)
326 jz 1f
327 call dump_stack
328#ifdef CONFIG_KALLSYMS
329 leaq early_idt_ripmsg(%rip),%rdi
330 movq 40(%rsp),%rsi # %rip again
331 call __print_symbol
332#endif
333#endif /* EARLY_PRINTK */
3341: hlt
335 jmp 1b
336
33720: # Exception table entry found
338 popq %r11
339 popq %r10
340 popq %r9
341 popq %r8
342 popq %rdi
343 popq %rsi
344 popq %rdx
345 popq %rcx
346 popq %rax
347 addq $16,%rsp # drop vector number and error code
348 decl early_recursion_flag(%rip)
349 INTERRUPT_RETURN
350
351 .balign 4
352early_recursion_flag:
353 .long 0
354
355#ifdef CONFIG_EARLY_PRINTK
356early_idt_msg:
357 .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
358early_idt_ripmsg:
359 .asciz "RIP %s\n"
360#endif /* CONFIG_EARLY_PRINTK */
361 .previous
362
363#define NEXT_PAGE(name) \
364 .balign PAGE_SIZE; \
365ENTRY(name)
366
367/* Automate the creation of 1 to 1 mapping pmd entries */
368#define PMDS(START, PERM, COUNT) \
369 i = 0 ; \
370 .rept (COUNT) ; \
371 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
372 i = i + 1 ; \
373 .endr
374
375 .data
376 /*
377 * This default setting generates an ident mapping at address 0x100000
378 * and a mapping for the kernel that precisely maps virtual address
379 * 0xffffffff80000000 to physical address 0x000000. (always using
380 * 2Mbyte large pages provided by PAE mode)
381 */
382NEXT_PAGE(init_level4_pgt)
383 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
384 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0
385 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
386 .org init_level4_pgt + L4_START_KERNEL*8, 0
387 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
388 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
389
390NEXT_PAGE(level3_ident_pgt)
391 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
392 .fill 511,8,0
393
394NEXT_PAGE(level3_kernel_pgt)
395 .fill L3_START_KERNEL,8,0
396 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
397 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
398 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
399
400NEXT_PAGE(level2_fixmap_pgt)
401 .fill 506,8,0
402 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
403 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
404 .fill 5,8,0
405
406NEXT_PAGE(level1_fixmap_pgt)
407 .fill 512,8,0
408
409NEXT_PAGE(level2_ident_pgt)
410 /* Since I easily can, map the first 1G.
411 * Don't set NX because code runs from these pages.
412 */
413 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
414
415NEXT_PAGE(level2_kernel_pgt)
416 /*
417 * 512 MB kernel mapping. We spend a full page on this pagetable
418 * anyway.
419 *
420 * The kernel code+data+bss must not be bigger than that.
421 *
422 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
423 * If you want to increase this then increase MODULES_VADDR
424 * too.)
425 */
426 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
427 KERNEL_IMAGE_SIZE/PMD_SIZE)
428
429NEXT_PAGE(level2_spare_pgt)
430 .fill 512, 8, 0
431
432#undef PMDS
433#undef NEXT_PAGE
434
435 .data
436 .align 16
437 .globl early_gdt_descr
438early_gdt_descr:
439 .word GDT_ENTRIES*8-1
440early_gdt_descr_base:
441 .quad INIT_PER_CPU_VAR(gdt_page)
442
443ENTRY(phys_base)
444 /* This must match the first entry in level2_kernel_pgt */
445 .quad 0x0000000000000000
446
447#include "../../x86/xen/xen-head.S"
448
449 .section .bss, "aw", @nobits
450 .align L1_CACHE_BYTES
451ENTRY(idt_table)
452 .skip IDT_ENTRIES * 16
453
454 .align L1_CACHE_BYTES
455ENTRY(nmi_idt_table)
456 .skip IDT_ENTRIES * 16
457
458 __PAGE_ALIGNED_BSS
459 .align PAGE_SIZE
460ENTRY(empty_zero_page)
461 .skip PAGE_SIZE
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <linux/pgtable.h>
17#include <asm/segment.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/export.h>
26#include <asm/nospec-branch.h>
27#include <asm/fixmap.h>
28
29/*
30 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
31 * because we need identity-mapped pages.
32 */
33#define l4_index(x) (((x) >> 39) & 511)
34#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
35
36L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
37L4_START_KERNEL = l4_index(__START_KERNEL_map)
38
39L3_START_KERNEL = pud_index(__START_KERNEL_map)
40
41 .text
42 __HEAD
43 .code64
44SYM_CODE_START_NOALIGN(startup_64)
45 UNWIND_HINT_EMPTY
46 /*
47 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
48 * and someone has loaded an identity mapped page table
49 * for us. These identity mapped page tables map all of the
50 * kernel pages and possibly all of memory.
51 *
52 * %rsi holds a physical pointer to real_mode_data.
53 *
54 * We come here either directly from a 64bit bootloader, or from
55 * arch/x86/boot/compressed/head_64.S.
56 *
57 * We only come here initially at boot nothing else comes here.
58 *
59 * Since we may be loaded at an address different from what we were
60 * compiled to run at we first fixup the physical addresses in our page
61 * tables and then reload them.
62 */
63
64 /* Set up the stack for verify_cpu(), similar to initial_stack below */
65 leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp
66
67 leaq _text(%rip), %rdi
68
69 /*
70 * initial_gs points to initial fixed_percpu_data struct with storage for
71 * the stack protector canary. Global pointer fixups are needed at this
72 * stage, so apply them as is done in fixup_pointer(), and initialize %gs
73 * such that the canary can be accessed at %gs:40 for subsequent C calls.
74 */
75 movl $MSR_GS_BASE, %ecx
76 movq initial_gs(%rip), %rax
77 movq $_text, %rdx
78 subq %rdx, %rax
79 addq %rdi, %rax
80 movq %rax, %rdx
81 shrq $32, %rdx
82 wrmsr
83
84 pushq %rsi
85 call startup_64_setup_env
86 popq %rsi
87
88#ifdef CONFIG_AMD_MEM_ENCRYPT
89 /*
90 * Activate SEV/SME memory encryption if supported/enabled. This needs to
91 * be done now, since this also includes setup of the SEV-SNP CPUID table,
92 * which needs to be done before any CPUID instructions are executed in
93 * subsequent code.
94 */
95 movq %rsi, %rdi
96 pushq %rsi
97 call sme_enable
98 popq %rsi
99#endif
100
101 /* Now switch to __KERNEL_CS so IRET works reliably */
102 pushq $__KERNEL_CS
103 leaq .Lon_kernel_cs(%rip), %rax
104 pushq %rax
105 lretq
106
107.Lon_kernel_cs:
108 UNWIND_HINT_EMPTY
109
110 /* Sanitize CPU configuration */
111 call verify_cpu
112
113 /*
114 * Perform pagetable fixups. Additionally, if SME is active, encrypt
115 * the kernel and retrieve the modifier (SME encryption mask if SME
116 * is active) to be added to the initial pgdir entry that will be
117 * programmed into CR3.
118 */
119 leaq _text(%rip), %rdi
120 pushq %rsi
121 call __startup_64
122 popq %rsi
123
124 /* Form the CR3 value being sure to include the CR3 modifier */
125 addq $(early_top_pgt - __START_KERNEL_map), %rax
126 jmp 1f
127SYM_CODE_END(startup_64)
128
129SYM_CODE_START(secondary_startup_64)
130 UNWIND_HINT_EMPTY
131 ANNOTATE_NOENDBR
132 /*
133 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
134 * and someone has loaded a mapped page table.
135 *
136 * %rsi holds a physical pointer to real_mode_data.
137 *
138 * We come here either from startup_64 (using physical addresses)
139 * or from trampoline.S (using virtual addresses).
140 *
141 * Using virtual addresses from trampoline.S removes the need
142 * to have any identity mapped pages in the kernel page table
143 * after the boot processor executes this code.
144 */
145
146 /* Sanitize CPU configuration */
147 call verify_cpu
148
149 /*
150 * The secondary_startup_64_no_verify entry point is only used by
151 * SEV-ES guests. In those guests the call to verify_cpu() would cause
152 * #VC exceptions which can not be handled at this stage of secondary
153 * CPU bringup.
154 *
155 * All non SEV-ES systems, especially Intel systems, need to execute
156 * verify_cpu() above to make sure NX is enabled.
157 */
158SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
159 UNWIND_HINT_EMPTY
160 ANNOTATE_NOENDBR
161
162 /*
163 * Retrieve the modifier (SME encryption mask if SME is active) to be
164 * added to the initial pgdir entry that will be programmed into CR3.
165 */
166#ifdef CONFIG_AMD_MEM_ENCRYPT
167 movq sme_me_mask, %rax
168#else
169 xorq %rax, %rax
170#endif
171
172 /* Form the CR3 value being sure to include the CR3 modifier */
173 addq $(init_top_pgt - __START_KERNEL_map), %rax
1741:
175
176#ifdef CONFIG_X86_MCE
177 /*
178 * Preserve CR4.MCE if the kernel will enable #MC support.
179 * Clearing MCE may fault in some environments (that also force #MC
180 * support). Any machine check that occurs before #MC support is fully
181 * configured will crash the system regardless of the CR4.MCE value set
182 * here.
183 */
184 movq %cr4, %rcx
185 andl $X86_CR4_MCE, %ecx
186#else
187 movl $0, %ecx
188#endif
189
190 /* Enable PAE mode, PGE and LA57 */
191 orl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
192#ifdef CONFIG_X86_5LEVEL
193 testl $1, __pgtable_l5_enabled(%rip)
194 jz 1f
195 orl $X86_CR4_LA57, %ecx
1961:
197#endif
198 movq %rcx, %cr4
199
200 /* Setup early boot stage 4-/5-level pagetables. */
201 addq phys_base(%rip), %rax
202
203 /*
204 * For SEV guests: Verify that the C-bit is correct. A malicious
205 * hypervisor could lie about the C-bit position to perform a ROP
206 * attack on the guest by writing to the unencrypted stack and wait for
207 * the next RET instruction.
208 * %rsi carries pointer to realmode data and is callee-clobbered. Save
209 * and restore it.
210 */
211 pushq %rsi
212 movq %rax, %rdi
213 call sev_verify_cbit
214 popq %rsi
215
216 /*
217 * Switch to new page-table
218 *
219 * For the boot CPU this switches to early_top_pgt which still has the
220 * indentity mappings present. The secondary CPUs will switch to the
221 * init_top_pgt here, away from the trampoline_pgd and unmap the
222 * indentity mapped ranges.
223 */
224 movq %rax, %cr3
225
226 /*
227 * Do a global TLB flush after the CR3 switch to make sure the TLB
228 * entries from the identity mapping are flushed.
229 */
230 movq %cr4, %rcx
231 movq %rcx, %rax
232 xorq $X86_CR4_PGE, %rcx
233 movq %rcx, %cr4
234 movq %rax, %cr4
235
236 /* Ensure I am executing from virtual addresses */
237 movq $1f, %rax
238 ANNOTATE_RETPOLINE_SAFE
239 jmp *%rax
2401:
241 UNWIND_HINT_EMPTY
242 ANNOTATE_NOENDBR // above
243
244 /*
245 * We must switch to a new descriptor in kernel space for the GDT
246 * because soon the kernel won't have access anymore to the userspace
247 * addresses where we're currently running on. We have to do that here
248 * because in 32bit we couldn't load a 64bit linear address.
249 */
250 lgdt early_gdt_descr(%rip)
251
252 /* set up data segments */
253 xorl %eax,%eax
254 movl %eax,%ds
255 movl %eax,%ss
256 movl %eax,%es
257
258 /*
259 * We don't really need to load %fs or %gs, but load them anyway
260 * to kill any stale realmode selectors. This allows execution
261 * under VT hardware.
262 */
263 movl %eax,%fs
264 movl %eax,%gs
265
266 /* Set up %gs.
267 *
268 * The base of %gs always points to fixed_percpu_data. If the
269 * stack protector canary is enabled, it is located at %gs:40.
270 * Note that, on SMP, the boot cpu uses init data section until
271 * the per cpu areas are set up.
272 */
273 movl $MSR_GS_BASE,%ecx
274 movl initial_gs(%rip),%eax
275 movl initial_gs+4(%rip),%edx
276 wrmsr
277
278 /*
279 * Setup a boot time stack - Any secondary CPU will have lost its stack
280 * by now because the cr3-switch above unmaps the real-mode stack
281 */
282 movq initial_stack(%rip), %rsp
283
284 /* Setup and Load IDT */
285 pushq %rsi
286 call early_setup_idt
287 popq %rsi
288
289 /* Check if nx is implemented */
290 movl $0x80000001, %eax
291 cpuid
292 movl %edx,%edi
293
294 /* Setup EFER (Extended Feature Enable Register) */
295 movl $MSR_EFER, %ecx
296 rdmsr
297 /*
298 * Preserve current value of EFER for comparison and to skip
299 * EFER writes if no change was made (for TDX guest)
300 */
301 movl %eax, %edx
302 btsl $_EFER_SCE, %eax /* Enable System Call */
303 btl $20,%edi /* No Execute supported? */
304 jnc 1f
305 btsl $_EFER_NX, %eax
306 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
307
308 /* Avoid writing EFER if no change was made (for TDX guest) */
3091: cmpl %edx, %eax
310 je 1f
311 xor %edx, %edx
312 wrmsr /* Make changes effective */
3131:
314 /* Setup cr0 */
315 movl $CR0_STATE, %eax
316 /* Make changes effective */
317 movq %rax, %cr0
318
319 /* zero EFLAGS after setting rsp */
320 pushq $0
321 popfq
322
323 /* rsi is pointer to real mode structure with interesting info.
324 pass it to C */
325 movq %rsi, %rdi
326
327.Ljump_to_C_code:
328 /*
329 * Jump to run C code and to be on a real kernel address.
330 * Since we are running on identity-mapped space we have to jump
331 * to the full 64bit address, this is only possible as indirect
332 * jump. In addition we need to ensure %cs is set so we make this
333 * a far return.
334 *
335 * Note: do not change to far jump indirect with 64bit offset.
336 *
337 * AMD does not support far jump indirect with 64bit offset.
338 * AMD64 Architecture Programmer's Manual, Volume 3: states only
339 * JMP FAR mem16:16 FF /5 Far jump indirect,
340 * with the target specified by a far pointer in memory.
341 * JMP FAR mem16:32 FF /5 Far jump indirect,
342 * with the target specified by a far pointer in memory.
343 *
344 * Intel64 does support 64bit offset.
345 * Software Developer Manual Vol 2: states:
346 * FF /5 JMP m16:16 Jump far, absolute indirect,
347 * address given in m16:16
348 * FF /5 JMP m16:32 Jump far, absolute indirect,
349 * address given in m16:32.
350 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
351 * address given in m16:64.
352 */
353 pushq $.Lafter_lret # put return address on stack for unwinder
354 xorl %ebp, %ebp # clear frame pointer
355 movq initial_code(%rip), %rax
356 pushq $__KERNEL_CS # set correct cs
357 pushq %rax # target address in negative space
358 lretq
359.Lafter_lret:
360 ANNOTATE_NOENDBR
361SYM_CODE_END(secondary_startup_64)
362
363#include "verify_cpu.S"
364#include "sev_verify_cbit.S"
365
366#ifdef CONFIG_HOTPLUG_CPU
367/*
368 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
369 * up already except stack. We just set up stack here. Then call
370 * start_secondary() via .Ljump_to_C_code.
371 */
372SYM_CODE_START(start_cpu0)
373 ANNOTATE_NOENDBR
374 UNWIND_HINT_EMPTY
375 movq initial_stack(%rip), %rsp
376 jmp .Ljump_to_C_code
377SYM_CODE_END(start_cpu0)
378#endif
379
380#ifdef CONFIG_AMD_MEM_ENCRYPT
381/*
382 * VC Exception handler used during early boot when running on kernel
383 * addresses, but before the switch to the idt_table can be made.
384 * The early_idt_handler_array can't be used here because it calls into a lot
385 * of __init code and this handler is also used during CPU offlining/onlining.
386 * Therefore this handler ends up in the .text section so that it stays around
387 * when .init.text is freed.
388 */
389SYM_CODE_START_NOALIGN(vc_boot_ghcb)
390 UNWIND_HINT_IRET_REGS offset=8
391 ENDBR
392
393 ANNOTATE_UNRET_END
394
395 /* Build pt_regs */
396 PUSH_AND_CLEAR_REGS
397
398 /* Call C handler */
399 movq %rsp, %rdi
400 movq ORIG_RAX(%rsp), %rsi
401 movq initial_vc_handler(%rip), %rax
402 ANNOTATE_RETPOLINE_SAFE
403 call *%rax
404
405 /* Unwind pt_regs */
406 POP_REGS
407
408 /* Remove Error Code */
409 addq $8, %rsp
410
411 iretq
412SYM_CODE_END(vc_boot_ghcb)
413#endif
414
415 /* Both SMP bootup and ACPI suspend change these variables */
416 __REFDATA
417 .balign 8
418SYM_DATA(initial_code, .quad x86_64_start_kernel)
419SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data))
420#ifdef CONFIG_AMD_MEM_ENCRYPT
421SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb)
422#endif
423
424/*
425 * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder
426 * reliably detect the end of the stack.
427 */
428SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE)
429 __FINITDATA
430
431 __INIT
432SYM_CODE_START(early_idt_handler_array)
433 i = 0
434 .rept NUM_EXCEPTION_VECTORS
435 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
436 UNWIND_HINT_IRET_REGS
437 ENDBR
438 pushq $0 # Dummy error code, to make stack frame uniform
439 .else
440 UNWIND_HINT_IRET_REGS offset=8
441 ENDBR
442 .endif
443 pushq $i # 72(%rsp) Vector number
444 jmp early_idt_handler_common
445 UNWIND_HINT_IRET_REGS
446 i = i + 1
447 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
448 .endr
449SYM_CODE_END(early_idt_handler_array)
450 ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS]
451
452SYM_CODE_START_LOCAL(early_idt_handler_common)
453 UNWIND_HINT_IRET_REGS offset=16
454 ANNOTATE_UNRET_END
455 /*
456 * The stack is the hardware frame, an error code or zero, and the
457 * vector number.
458 */
459 cld
460
461 incl early_recursion_flag(%rip)
462
463 /* The vector number is currently in the pt_regs->di slot. */
464 pushq %rsi /* pt_regs->si */
465 movq 8(%rsp), %rsi /* RSI = vector number */
466 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
467 pushq %rdx /* pt_regs->dx */
468 pushq %rcx /* pt_regs->cx */
469 pushq %rax /* pt_regs->ax */
470 pushq %r8 /* pt_regs->r8 */
471 pushq %r9 /* pt_regs->r9 */
472 pushq %r10 /* pt_regs->r10 */
473 pushq %r11 /* pt_regs->r11 */
474 pushq %rbx /* pt_regs->bx */
475 pushq %rbp /* pt_regs->bp */
476 pushq %r12 /* pt_regs->r12 */
477 pushq %r13 /* pt_regs->r13 */
478 pushq %r14 /* pt_regs->r14 */
479 pushq %r15 /* pt_regs->r15 */
480 UNWIND_HINT_REGS
481
482 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
483 call do_early_exception
484
485 decl early_recursion_flag(%rip)
486 jmp restore_regs_and_return_to_kernel
487SYM_CODE_END(early_idt_handler_common)
488
489#ifdef CONFIG_AMD_MEM_ENCRYPT
490/*
491 * VC Exception handler used during very early boot. The
492 * early_idt_handler_array can't be used because it returns via the
493 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
494 *
495 * XXX it does, fix this.
496 *
497 * This handler will end up in the .init.text section and not be
498 * available to boot secondary CPUs.
499 */
500SYM_CODE_START_NOALIGN(vc_no_ghcb)
501 UNWIND_HINT_IRET_REGS offset=8
502 ENDBR
503
504 ANNOTATE_UNRET_END
505
506 /* Build pt_regs */
507 PUSH_AND_CLEAR_REGS
508
509 /* Call C handler */
510 movq %rsp, %rdi
511 movq ORIG_RAX(%rsp), %rsi
512 call do_vc_no_ghcb
513
514 /* Unwind pt_regs */
515 POP_REGS
516
517 /* Remove Error Code */
518 addq $8, %rsp
519
520 /* Pure iret required here - don't use INTERRUPT_RETURN */
521 iretq
522SYM_CODE_END(vc_no_ghcb)
523#endif
524
525#define SYM_DATA_START_PAGE_ALIGNED(name) \
526 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
527
528#ifdef CONFIG_PAGE_TABLE_ISOLATION
529/*
530 * Each PGD needs to be 8k long and 8k aligned. We do not
531 * ever go out to userspace with these, so we do not
532 * strictly *need* the second page, but this allows us to
533 * have a single set_pgd() implementation that does not
534 * need to worry about whether it has 4k or 8k to work
535 * with.
536 *
537 * This ensures PGDs are 8k long:
538 */
539#define PTI_USER_PGD_FILL 512
540/* This ensures they are 8k-aligned: */
541#define SYM_DATA_START_PTI_ALIGNED(name) \
542 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
543#else
544#define SYM_DATA_START_PTI_ALIGNED(name) \
545 SYM_DATA_START_PAGE_ALIGNED(name)
546#define PTI_USER_PGD_FILL 0
547#endif
548
549/* Automate the creation of 1 to 1 mapping pmd entries */
550#define PMDS(START, PERM, COUNT) \
551 i = 0 ; \
552 .rept (COUNT) ; \
553 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
554 i = i + 1 ; \
555 .endr
556
557 __INITDATA
558 .balign 4
559
560SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
561 .fill 512,8,0
562 .fill PTI_USER_PGD_FILL,8,0
563SYM_DATA_END(early_top_pgt)
564
565SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
566 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
567SYM_DATA_END(early_dynamic_pgts)
568
569SYM_DATA(early_recursion_flag, .long 0)
570
571 .data
572
573#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
574SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
575 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
576 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
577 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
578 .org init_top_pgt + L4_START_KERNEL*8, 0
579 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
580 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
581 .fill PTI_USER_PGD_FILL,8,0
582SYM_DATA_END(init_top_pgt)
583
584SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
585 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
586 .fill 511, 8, 0
587SYM_DATA_END(level3_ident_pgt)
588SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
589 /*
590 * Since I easily can, map the first 1G.
591 * Don't set NX because code runs from these pages.
592 *
593 * Note: This sets _PAGE_GLOBAL despite whether
594 * the CPU supports it or it is enabled. But,
595 * the CPU should ignore the bit.
596 */
597 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
598SYM_DATA_END(level2_ident_pgt)
599#else
600SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
601 .fill 512,8,0
602 .fill PTI_USER_PGD_FILL,8,0
603SYM_DATA_END(init_top_pgt)
604#endif
605
606#ifdef CONFIG_X86_5LEVEL
607SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
608 .fill 511,8,0
609 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
610SYM_DATA_END(level4_kernel_pgt)
611#endif
612
613SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
614 .fill L3_START_KERNEL,8,0
615 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
616 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
617 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
618SYM_DATA_END(level3_kernel_pgt)
619
620SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
621 /*
622 * Kernel high mapping.
623 *
624 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in
625 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled,
626 * 512 MiB otherwise.
627 *
628 * (NOTE: after that starts the module area, see MODULES_VADDR.)
629 *
630 * This table is eventually used by the kernel during normal runtime.
631 * Care must be taken to clear out undesired bits later, like _PAGE_RW
632 * or _PAGE_GLOBAL in some cases.
633 */
634 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
635SYM_DATA_END(level2_kernel_pgt)
636
637SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
638 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
639 pgtno = 0
640 .rept (FIXMAP_PMD_NUM)
641 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
642 + _PAGE_TABLE_NOENC;
643 pgtno = pgtno + 1
644 .endr
645 /* 6 MB reserved space + a 2MB hole */
646 .fill 4,8,0
647SYM_DATA_END(level2_fixmap_pgt)
648
649SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
650 .rept (FIXMAP_PMD_NUM)
651 .fill 512,8,0
652 .endr
653SYM_DATA_END(level1_fixmap_pgt)
654
655#undef PMDS
656
657 .data
658 .align 16
659
660SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1)
661SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page))
662
663 .align 16
664/* This must match the first entry in level2_kernel_pgt */
665SYM_DATA(phys_base, .quad 0x0)
666EXPORT_SYMBOL(phys_base)
667
668#include "../../x86/xen/xen-head.S"
669
670 __PAGE_ALIGNED_BSS
671SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
672 .skip PAGE_SIZE
673SYM_DATA_END(empty_zero_page)
674EXPORT_SYMBOL(empty_zero_page)
675