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1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
5#include <linux/export.h>
6#include <linux/io.h>
7#include <linux/irqdomain.h>
8#include <linux/interrupt.h>
9#include <linux/list.h>
10#include <linux/of.h>
11#include <linux/of_fdt.h>
12#include <linux/of_address.h>
13#include <linux/of_platform.h>
14#include <linux/of_irq.h>
15#include <linux/slab.h>
16#include <linux/pci.h>
17#include <linux/of_pci.h>
18#include <linux/initrd.h>
19
20#include <asm/hpet.h>
21#include <asm/apic.h>
22#include <asm/pci_x86.h>
23
24__initdata u64 initial_dtb;
25char __initdata cmd_line[COMMAND_LINE_SIZE];
26
27int __initdata of_ioapic;
28
29unsigned long pci_address_to_pio(phys_addr_t address)
30{
31 /*
32 * The ioport address can be directly used by inX / outX
33 */
34 BUG_ON(address >= (1 << 16));
35 return (unsigned long)address;
36}
37EXPORT_SYMBOL_GPL(pci_address_to_pio);
38
39void __init early_init_dt_scan_chosen_arch(unsigned long node)
40{
41 BUG();
42}
43
44void __init early_init_dt_add_memory_arch(u64 base, u64 size)
45{
46 BUG();
47}
48
49void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
50{
51 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
52}
53
54#ifdef CONFIG_BLK_DEV_INITRD
55void __init early_init_dt_setup_initrd_arch(unsigned long start,
56 unsigned long end)
57{
58 initrd_start = (unsigned long)__va(start);
59 initrd_end = (unsigned long)__va(end);
60 initrd_below_start_ok = 1;
61}
62#endif
63
64void __init add_dtb(u64 data)
65{
66 initial_dtb = data + offsetof(struct setup_data, data);
67}
68
69/*
70 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
71 */
72static struct of_device_id __initdata ce4100_ids[] = {
73 { .compatible = "intel,ce4100-cp", },
74 { .compatible = "isa", },
75 { .compatible = "pci", },
76 {},
77};
78
79static int __init add_bus_probe(void)
80{
81 if (!of_have_populated_dt())
82 return 0;
83
84 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
85}
86module_init(add_bus_probe);
87
88#ifdef CONFIG_PCI
89struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
90{
91 struct device_node *np;
92
93 for_each_node_by_type(np, "pci") {
94 const void *prop;
95 unsigned int bus_min;
96
97 prop = of_get_property(np, "bus-range", NULL);
98 if (!prop)
99 continue;
100 bus_min = be32_to_cpup(prop);
101 if (bus->number == bus_min)
102 return np;
103 }
104 return NULL;
105}
106
107static int x86_of_pci_irq_enable(struct pci_dev *dev)
108{
109 struct of_irq oirq;
110 u32 virq;
111 int ret;
112 u8 pin;
113
114 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
115 if (ret)
116 return ret;
117 if (!pin)
118 return 0;
119
120 ret = of_irq_map_pci(dev, &oirq);
121 if (ret)
122 return ret;
123
124 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
125 oirq.size);
126 if (virq == 0)
127 return -EINVAL;
128 dev->irq = virq;
129 return 0;
130}
131
132static void x86_of_pci_irq_disable(struct pci_dev *dev)
133{
134}
135
136void __cpuinit x86_of_pci_init(void)
137{
138 pcibios_enable_irq = x86_of_pci_irq_enable;
139 pcibios_disable_irq = x86_of_pci_irq_disable;
140}
141#endif
142
143static void __init dtb_setup_hpet(void)
144{
145#ifdef CONFIG_HPET_TIMER
146 struct device_node *dn;
147 struct resource r;
148 int ret;
149
150 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
151 if (!dn)
152 return;
153 ret = of_address_to_resource(dn, 0, &r);
154 if (ret) {
155 WARN_ON(1);
156 return;
157 }
158 hpet_address = r.start;
159#endif
160}
161
162static void __init dtb_lapic_setup(void)
163{
164#ifdef CONFIG_X86_LOCAL_APIC
165 struct device_node *dn;
166 struct resource r;
167 int ret;
168
169 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
170 if (!dn)
171 return;
172
173 ret = of_address_to_resource(dn, 0, &r);
174 if (WARN_ON(ret))
175 return;
176
177 /* Did the boot loader setup the local APIC ? */
178 if (!cpu_has_apic) {
179 if (apic_force_enable(r.start))
180 return;
181 }
182 smp_found_config = 1;
183 pic_mode = 1;
184 register_lapic_address(r.start);
185 generic_processor_info(boot_cpu_physical_apicid,
186 GET_APIC_VERSION(apic_read(APIC_LVR)));
187#endif
188}
189
190#ifdef CONFIG_X86_IO_APIC
191static unsigned int ioapic_id;
192
193static void __init dtb_add_ioapic(struct device_node *dn)
194{
195 struct resource r;
196 int ret;
197
198 ret = of_address_to_resource(dn, 0, &r);
199 if (ret) {
200 printk(KERN_ERR "Can't obtain address from node %s.\n",
201 dn->full_name);
202 return;
203 }
204 mp_register_ioapic(++ioapic_id, r.start, gsi_top);
205}
206
207static void __init dtb_ioapic_setup(void)
208{
209 struct device_node *dn;
210
211 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
212 dtb_add_ioapic(dn);
213
214 if (nr_ioapics) {
215 of_ioapic = 1;
216 return;
217 }
218 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
219}
220#else
221static void __init dtb_ioapic_setup(void) {}
222#endif
223
224static void __init dtb_apic_setup(void)
225{
226 dtb_lapic_setup();
227 dtb_ioapic_setup();
228}
229
230#ifdef CONFIG_OF_FLATTREE
231static void __init x86_flattree_get_config(void)
232{
233 u32 size, map_len;
234 void *new_dtb;
235
236 if (!initial_dtb)
237 return;
238
239 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
240 (u64)sizeof(struct boot_param_header));
241
242 initial_boot_params = early_memremap(initial_dtb, map_len);
243 size = be32_to_cpu(initial_boot_params->totalsize);
244 if (map_len < size) {
245 early_iounmap(initial_boot_params, map_len);
246 initial_boot_params = early_memremap(initial_dtb, size);
247 map_len = size;
248 }
249
250 new_dtb = alloc_bootmem(size);
251 memcpy(new_dtb, initial_boot_params, size);
252 early_iounmap(initial_boot_params, map_len);
253
254 initial_boot_params = new_dtb;
255
256 /* root level address cells */
257 of_scan_flat_dt(early_init_dt_scan_root, NULL);
258
259 unflatten_device_tree();
260}
261#else
262static inline void x86_flattree_get_config(void) { }
263#endif
264
265void __init x86_dtb_init(void)
266{
267 x86_flattree_get_config();
268
269 if (!of_have_populated_dt())
270 return;
271
272 dtb_setup_hpet();
273 dtb_apic_setup();
274}
275
276#ifdef CONFIG_X86_IO_APIC
277
278struct of_ioapic_type {
279 u32 out_type;
280 u32 trigger;
281 u32 polarity;
282};
283
284static struct of_ioapic_type of_ioapic_type[] =
285{
286 {
287 .out_type = IRQ_TYPE_EDGE_RISING,
288 .trigger = IOAPIC_EDGE,
289 .polarity = 1,
290 },
291 {
292 .out_type = IRQ_TYPE_LEVEL_LOW,
293 .trigger = IOAPIC_LEVEL,
294 .polarity = 0,
295 },
296 {
297 .out_type = IRQ_TYPE_LEVEL_HIGH,
298 .trigger = IOAPIC_LEVEL,
299 .polarity = 1,
300 },
301 {
302 .out_type = IRQ_TYPE_EDGE_FALLING,
303 .trigger = IOAPIC_EDGE,
304 .polarity = 0,
305 },
306};
307
308static int ioapic_xlate(struct irq_domain *domain,
309 struct device_node *controller,
310 const u32 *intspec, u32 intsize,
311 irq_hw_number_t *out_hwirq, u32 *out_type)
312{
313 struct io_apic_irq_attr attr;
314 struct of_ioapic_type *it;
315 u32 line, idx;
316 int rc;
317
318 if (WARN_ON(intsize < 2))
319 return -EINVAL;
320
321 line = intspec[0];
322
323 if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
324 return -EINVAL;
325
326 it = &of_ioapic_type[intspec[1]];
327
328 idx = (u32) domain->host_data;
329 set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
330
331 rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
332 cpu_to_node(0), &attr);
333 if (rc)
334 return rc;
335
336 *out_hwirq = line;
337 *out_type = it->out_type;
338 return 0;
339}
340
341const struct irq_domain_ops ioapic_irq_domain_ops = {
342 .xlate = ioapic_xlate,
343};
344
345static void __init ioapic_add_ofnode(struct device_node *np)
346{
347 struct resource r;
348 int i, ret;
349
350 ret = of_address_to_resource(np, 0, &r);
351 if (ret) {
352 printk(KERN_ERR "Failed to obtain address for %s\n",
353 np->full_name);
354 return;
355 }
356
357 for (i = 0; i < nr_ioapics; i++) {
358 if (r.start == mpc_ioapic_addr(i)) {
359 struct irq_domain *id;
360 struct mp_ioapic_gsi *gsi_cfg;
361
362 gsi_cfg = mp_ioapic_gsi_routing(i);
363
364 id = irq_domain_add_legacy(np, 32, gsi_cfg->gsi_base, 0,
365 &ioapic_irq_domain_ops,
366 (void*)i);
367 BUG_ON(!id);
368 return;
369 }
370 }
371 printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
372}
373
374void __init x86_add_irq_domains(void)
375{
376 struct device_node *dp;
377
378 if (!of_have_populated_dt())
379 return;
380
381 for_each_node_with_property(dp, "interrupt-controller") {
382 if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
383 ioapic_add_ofnode(dp);
384 }
385}
386#else
387void __init x86_add_irq_domains(void) { }
388#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Architecture specific OF callbacks.
4 */
5#include <linux/export.h>
6#include <linux/io.h>
7#include <linux/interrupt.h>
8#include <linux/list.h>
9#include <linux/of.h>
10#include <linux/of_fdt.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/of_irq.h>
14#include <linux/libfdt.h>
15#include <linux/slab.h>
16#include <linux/pci.h>
17#include <linux/of_pci.h>
18#include <linux/initrd.h>
19
20#include <asm/irqdomain.h>
21#include <asm/hpet.h>
22#include <asm/apic.h>
23#include <asm/io_apic.h>
24#include <asm/pci_x86.h>
25#include <asm/setup.h>
26#include <asm/i8259.h>
27#include <asm/prom.h>
28
29__initdata u64 initial_dtb;
30char __initdata cmd_line[COMMAND_LINE_SIZE];
31
32int __initdata of_ioapic;
33
34void __init add_dtb(u64 data)
35{
36 initial_dtb = data + offsetof(struct setup_data, data);
37}
38
39/*
40 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
41 */
42static struct of_device_id __initdata ce4100_ids[] = {
43 { .compatible = "intel,ce4100-cp", },
44 { .compatible = "isa", },
45 { .compatible = "pci", },
46 {},
47};
48
49static int __init add_bus_probe(void)
50{
51 if (!of_have_populated_dt())
52 return 0;
53
54 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
55}
56device_initcall(add_bus_probe);
57
58#ifdef CONFIG_PCI
59struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
60{
61 struct device_node *np;
62
63 for_each_node_by_type(np, "pci") {
64 const void *prop;
65 unsigned int bus_min;
66
67 prop = of_get_property(np, "bus-range", NULL);
68 if (!prop)
69 continue;
70 bus_min = be32_to_cpup(prop);
71 if (bus->number == bus_min)
72 return np;
73 }
74 return NULL;
75}
76
77static int x86_of_pci_irq_enable(struct pci_dev *dev)
78{
79 u32 virq;
80 int ret;
81 u8 pin;
82
83 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
84 if (ret)
85 return ret;
86 if (!pin)
87 return 0;
88
89 virq = of_irq_parse_and_map_pci(dev, 0, 0);
90 if (virq == 0)
91 return -EINVAL;
92 dev->irq = virq;
93 return 0;
94}
95
96static void x86_of_pci_irq_disable(struct pci_dev *dev)
97{
98}
99
100void x86_of_pci_init(void)
101{
102 pcibios_enable_irq = x86_of_pci_irq_enable;
103 pcibios_disable_irq = x86_of_pci_irq_disable;
104}
105#endif
106
107static void __init dtb_setup_hpet(void)
108{
109#ifdef CONFIG_HPET_TIMER
110 struct device_node *dn;
111 struct resource r;
112 int ret;
113
114 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
115 if (!dn)
116 return;
117 ret = of_address_to_resource(dn, 0, &r);
118 if (ret) {
119 WARN_ON(1);
120 return;
121 }
122 hpet_address = r.start;
123#endif
124}
125
126#ifdef CONFIG_X86_LOCAL_APIC
127
128static void __init dtb_cpu_setup(void)
129{
130 struct device_node *dn;
131 u32 apic_id, version;
132
133 version = GET_APIC_VERSION(apic_read(APIC_LVR));
134 for_each_of_cpu_node(dn) {
135 apic_id = of_get_cpu_hwid(dn, 0);
136 if (apic_id == ~0U) {
137 pr_warn("%pOF: missing local APIC ID\n", dn);
138 continue;
139 }
140 generic_processor_info(apic_id, version);
141 }
142}
143
144static void __init dtb_lapic_setup(void)
145{
146 struct device_node *dn;
147 struct resource r;
148 unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
149 int ret;
150
151 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
152 if (dn) {
153 ret = of_address_to_resource(dn, 0, &r);
154 if (WARN_ON(ret))
155 return;
156 lapic_addr = r.start;
157 }
158
159 /* Did the boot loader setup the local APIC ? */
160 if (!boot_cpu_has(X86_FEATURE_APIC)) {
161 if (apic_force_enable(lapic_addr))
162 return;
163 }
164 smp_found_config = 1;
165 if (of_property_read_bool(dn, "intel,virtual-wire-mode")) {
166 pr_info("Virtual Wire compatibility mode.\n");
167 pic_mode = 0;
168 } else {
169 pr_info("IMCR and PIC compatibility mode.\n");
170 pic_mode = 1;
171 }
172
173 register_lapic_address(lapic_addr);
174}
175
176#endif /* CONFIG_X86_LOCAL_APIC */
177
178#ifdef CONFIG_X86_IO_APIC
179static unsigned int ioapic_id;
180
181struct of_ioapic_type {
182 u32 out_type;
183 u32 is_level;
184 u32 active_low;
185};
186
187static struct of_ioapic_type of_ioapic_type[] =
188{
189 {
190 .out_type = IRQ_TYPE_EDGE_FALLING,
191 .is_level = 0,
192 .active_low = 1,
193 },
194 {
195 .out_type = IRQ_TYPE_LEVEL_HIGH,
196 .is_level = 1,
197 .active_low = 0,
198 },
199 {
200 .out_type = IRQ_TYPE_LEVEL_LOW,
201 .is_level = 1,
202 .active_low = 1,
203 },
204 {
205 .out_type = IRQ_TYPE_EDGE_RISING,
206 .is_level = 0,
207 .active_low = 0,
208 },
209};
210
211static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
212 unsigned int nr_irqs, void *arg)
213{
214 struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
215 struct of_ioapic_type *it;
216 struct irq_alloc_info tmp;
217 int type_index;
218
219 if (WARN_ON(fwspec->param_count < 2))
220 return -EINVAL;
221
222 type_index = fwspec->param[1];
223 if (type_index >= ARRAY_SIZE(of_ioapic_type))
224 return -EINVAL;
225
226 it = &of_ioapic_type[type_index];
227 ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->is_level, it->active_low);
228 tmp.devid = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
229 tmp.ioapic.pin = fwspec->param[0];
230
231 return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
232}
233
234static const struct irq_domain_ops ioapic_irq_domain_ops = {
235 .alloc = dt_irqdomain_alloc,
236 .free = mp_irqdomain_free,
237 .activate = mp_irqdomain_activate,
238 .deactivate = mp_irqdomain_deactivate,
239};
240
241static void __init dtb_add_ioapic(struct device_node *dn)
242{
243 struct resource r;
244 int ret;
245 struct ioapic_domain_cfg cfg = {
246 .type = IOAPIC_DOMAIN_DYNAMIC,
247 .ops = &ioapic_irq_domain_ops,
248 .dev = dn,
249 };
250
251 ret = of_address_to_resource(dn, 0, &r);
252 if (ret) {
253 pr_err("Can't obtain address from device node %pOF.\n", dn);
254 return;
255 }
256 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
257}
258
259static void __init dtb_ioapic_setup(void)
260{
261 struct device_node *dn;
262
263 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
264 dtb_add_ioapic(dn);
265
266 if (nr_ioapics) {
267 of_ioapic = 1;
268 return;
269 }
270 pr_err("Error: No information about IO-APIC in OF.\n");
271}
272#else
273static void __init dtb_ioapic_setup(void) {}
274#endif
275
276static void __init dtb_apic_setup(void)
277{
278#ifdef CONFIG_X86_LOCAL_APIC
279 dtb_lapic_setup();
280 dtb_cpu_setup();
281#endif
282 dtb_ioapic_setup();
283}
284
285#ifdef CONFIG_OF_EARLY_FLATTREE
286static void __init x86_flattree_get_config(void)
287{
288 u32 size, map_len;
289 void *dt;
290
291 if (!initial_dtb)
292 return;
293
294 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
295
296 dt = early_memremap(initial_dtb, map_len);
297 size = fdt_totalsize(dt);
298 if (map_len < size) {
299 early_memunmap(dt, map_len);
300 dt = early_memremap(initial_dtb, size);
301 map_len = size;
302 }
303
304 early_init_dt_verify(dt);
305 unflatten_and_copy_device_tree();
306 early_memunmap(dt, map_len);
307}
308#else
309static inline void x86_flattree_get_config(void) { }
310#endif
311
312void __init x86_dtb_init(void)
313{
314 x86_flattree_get_config();
315
316 if (!of_have_populated_dt())
317 return;
318
319 dtb_setup_hpet();
320 dtb_apic_setup();
321}