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1/*
2 * pcic.c: MicroSPARC-IIep PCI controller support
3 *
4 * Copyright (C) 1998 V. Roganov and G. Raiko
5 *
6 * Code is derived from Ultra/PCI PSYCHO controller support, see that
7 * for author info.
8 *
9 * Support for diverse IIep based platforms by Pete Zaitcev.
10 * CP-1200 by Eric Brower.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/slab.h>
18#include <linux/jiffies.h>
19
20#include <asm/swift.h> /* for cache flushing. */
21#include <asm/io.h>
22
23#include <linux/ctype.h>
24#include <linux/pci.h>
25#include <linux/time.h>
26#include <linux/timex.h>
27#include <linux/interrupt.h>
28#include <linux/export.h>
29
30#include <asm/irq.h>
31#include <asm/oplib.h>
32#include <asm/prom.h>
33#include <asm/pcic.h>
34#include <asm/timex.h>
35#include <asm/timer.h>
36#include <asm/uaccess.h>
37#include <asm/irq_regs.h>
38
39#include "irq.h"
40
41/*
42 * I studied different documents and many live PROMs both from 2.30
43 * family and 3.xx versions. I came to the amazing conclusion: there is
44 * absolutely no way to route interrupts in IIep systems relying on
45 * information which PROM presents. We must hardcode interrupt routing
46 * schematics. And this actually sucks. -- zaitcev 1999/05/12
47 *
48 * To find irq for a device we determine which routing map
49 * is in effect or, in other words, on which machine we are running.
50 * We use PROM name for this although other techniques may be used
51 * in special cases (Gleb reports a PROMless IIep based system).
52 * Once we know the map we take device configuration address and
53 * find PCIC pin number where INT line goes. Then we may either program
54 * preferred irq into the PCIC or supply the preexisting irq to the device.
55 */
56struct pcic_ca2irq {
57 unsigned char busno; /* PCI bus number */
58 unsigned char devfn; /* Configuration address */
59 unsigned char pin; /* PCIC external interrupt pin */
60 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
61 unsigned int force; /* Enforce preferred IRQ */
62};
63
64struct pcic_sn2list {
65 char *sysname;
66 struct pcic_ca2irq *intmap;
67 int mapdim;
68};
69
70/*
71 * JavaEngine-1 apparently has different versions.
72 *
73 * According to communications with Sun folks, for P2 build 501-4628-03:
74 * pin 0 - parallel, audio;
75 * pin 1 - Ethernet;
76 * pin 2 - su;
77 * pin 3 - PS/2 kbd and mouse.
78 *
79 * OEM manual (805-1486):
80 * pin 0: Ethernet
81 * pin 1: All EBus
82 * pin 2: IGA (unused)
83 * pin 3: Not connected
84 * OEM manual says that 501-4628 & 501-4811 are the same thing,
85 * only the latter has NAND flash in place.
86 *
87 * So far unofficial Sun wins over the OEM manual. Poor OEMs...
88 */
89static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
90 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
91 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
92 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
93};
94
95/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
96static struct pcic_ca2irq pcic_i_jse[] = {
97 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
98 { 0, 0x01, 1, 6, 0 }, /* hme */
99 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
100 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
101 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
102 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
103 { 0, 0x80, 5, 11, 0 }, /* EIDE */
104 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
105 { 0, 0xA0, 4, 9, 0 }, /* USB */
106 /*
107 * Some pins belong to non-PCI devices, we hardcode them in drivers.
108 * sun4m timers - irq 10, 14
109 * PC style RTC - pin 7, irq 4 ?
110 * Smart card, Parallel - pin 4 shared with USB, ISA
111 * audio - pin 3, irq 5 ?
112 */
113};
114
115/* SPARCengine-6 was the original release name of CP1200.
116 * The documentation differs between the two versions
117 */
118static struct pcic_ca2irq pcic_i_se6[] = {
119 { 0, 0x08, 0, 2, 0 }, /* SCSI */
120 { 0, 0x01, 1, 6, 0 }, /* HME */
121 { 0, 0x00, 3, 13, 0 }, /* EBus */
122};
123
124/*
125 * Krups (courtesy of Varol Kaptan)
126 * No documentation available, but it was easy to guess
127 * because it was very similar to Espresso.
128 *
129 * pin 0 - kbd, mouse, serial;
130 * pin 1 - Ethernet;
131 * pin 2 - igs (we do not use it);
132 * pin 3 - audio;
133 * pin 4,5,6 - unused;
134 * pin 7 - RTC (from P2 onwards as David B. says).
135 */
136static struct pcic_ca2irq pcic_i_jk[] = {
137 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
138 { 0, 0x01, 1, 6, 0 }, /* hme */
139};
140
141/*
142 * Several entries in this list may point to the same routing map
143 * as several PROMs may be installed on the same physical board.
144 */
145#define SN2L_INIT(name, map) \
146 { name, map, ARRAY_SIZE(map) }
147
148static struct pcic_sn2list pcic_known_sysnames[] = {
149 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
150 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
151 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
152 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
153 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
154 { NULL, NULL, 0 }
155};
156
157/*
158 * Only one PCIC per IIep,
159 * and since we have no SMP IIep, only one per system.
160 */
161static int pcic0_up;
162static struct linux_pcic pcic0;
163
164void __iomem *pcic_regs;
165volatile int pcic_speculative;
166volatile int pcic_trapped;
167
168/* forward */
169unsigned int pcic_build_device_irq(struct platform_device *op,
170 unsigned int real_irq);
171
172#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
173
174static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
175 int where, u32 *value)
176{
177 struct linux_pcic *pcic;
178 unsigned long flags;
179
180 pcic = &pcic0;
181
182 local_irq_save(flags);
183#if 0 /* does not fail here */
184 pcic_speculative = 1;
185 pcic_trapped = 0;
186#endif
187 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
188#if 0 /* does not fail here */
189 nop();
190 if (pcic_trapped) {
191 local_irq_restore(flags);
192 *value = ~0;
193 return 0;
194 }
195#endif
196 pcic_speculative = 2;
197 pcic_trapped = 0;
198 *value = readl(pcic->pcic_config_space_data + (where&4));
199 nop();
200 if (pcic_trapped) {
201 pcic_speculative = 0;
202 local_irq_restore(flags);
203 *value = ~0;
204 return 0;
205 }
206 pcic_speculative = 0;
207 local_irq_restore(flags);
208 return 0;
209}
210
211static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
212 int where, int size, u32 *val)
213{
214 unsigned int v;
215
216 if (bus->number != 0) return -EINVAL;
217 switch (size) {
218 case 1:
219 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
220 *val = 0xff & (v >> (8*(where & 3)));
221 return 0;
222 case 2:
223 if (where&1) return -EINVAL;
224 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
225 *val = 0xffff & (v >> (8*(where & 3)));
226 return 0;
227 case 4:
228 if (where&3) return -EINVAL;
229 pcic_read_config_dword(bus->number, devfn, where&~3, val);
230 return 0;
231 }
232 return -EINVAL;
233}
234
235static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
236 int where, u32 value)
237{
238 struct linux_pcic *pcic;
239 unsigned long flags;
240
241 pcic = &pcic0;
242
243 local_irq_save(flags);
244 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
245 writel(value, pcic->pcic_config_space_data + (where&4));
246 local_irq_restore(flags);
247 return 0;
248}
249
250static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
251 int where, int size, u32 val)
252{
253 unsigned int v;
254
255 if (bus->number != 0) return -EINVAL;
256 switch (size) {
257 case 1:
258 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
259 v = (v & ~(0xff << (8*(where&3)))) |
260 ((0xff&val) << (8*(where&3)));
261 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
262 case 2:
263 if (where&1) return -EINVAL;
264 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
265 v = (v & ~(0xffff << (8*(where&3)))) |
266 ((0xffff&val) << (8*(where&3)));
267 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
268 case 4:
269 if (where&3) return -EINVAL;
270 return pcic_write_config_dword(bus->number, devfn, where, val);
271 }
272 return -EINVAL;
273}
274
275static struct pci_ops pcic_ops = {
276 .read = pcic_read_config,
277 .write = pcic_write_config,
278};
279
280/*
281 * On sparc64 pcibios_init() calls pci_controller_probe().
282 * We want PCIC probed little ahead so that interrupt controller
283 * would be operational.
284 */
285int __init pcic_probe(void)
286{
287 struct linux_pcic *pcic;
288 struct linux_prom_registers regs[PROMREG_MAX];
289 struct linux_pbm_info* pbm;
290 char namebuf[64];
291 phandle node;
292 int err;
293
294 if (pcic0_up) {
295 prom_printf("PCIC: called twice!\n");
296 prom_halt();
297 }
298 pcic = &pcic0;
299
300 node = prom_getchild (prom_root_node);
301 node = prom_searchsiblings (node, "pci");
302 if (node == 0)
303 return -ENODEV;
304 /*
305 * Map in PCIC register set, config space, and IO base
306 */
307 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
308 if (err == 0 || err == -1) {
309 prom_printf("PCIC: Error, cannot get PCIC registers "
310 "from PROM.\n");
311 prom_halt();
312 }
313
314 pcic0_up = 1;
315
316 pcic->pcic_res_regs.name = "pcic_registers";
317 pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
318 if (!pcic->pcic_regs) {
319 prom_printf("PCIC: Error, cannot map PCIC registers.\n");
320 prom_halt();
321 }
322
323 pcic->pcic_res_io.name = "pcic_io";
324 if ((pcic->pcic_io = (unsigned long)
325 ioremap(regs[1].phys_addr, 0x10000)) == 0) {
326 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
327 prom_halt();
328 }
329
330 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
331 if ((pcic->pcic_config_space_addr =
332 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) {
333 prom_printf("PCIC: Error, cannot map "
334 "PCI Configuration Space Address.\n");
335 prom_halt();
336 }
337
338 /*
339 * Docs say three least significant bits in address and data
340 * must be the same. Thus, we need adjust size of data.
341 */
342 pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
343 if ((pcic->pcic_config_space_data =
344 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) {
345 prom_printf("PCIC: Error, cannot map "
346 "PCI Configuration Space Data.\n");
347 prom_halt();
348 }
349
350 pbm = &pcic->pbm;
351 pbm->prom_node = node;
352 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
353 strcpy(pbm->prom_name, namebuf);
354
355 {
356 extern volatile int t_nmi[4];
357 extern int pcic_nmi_trap_patch[4];
358
359 t_nmi[0] = pcic_nmi_trap_patch[0];
360 t_nmi[1] = pcic_nmi_trap_patch[1];
361 t_nmi[2] = pcic_nmi_trap_patch[2];
362 t_nmi[3] = pcic_nmi_trap_patch[3];
363 swift_flush_dcache();
364 pcic_regs = pcic->pcic_regs;
365 }
366
367 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
368 {
369 struct pcic_sn2list *p;
370
371 for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
372 if (strcmp(namebuf, p->sysname) == 0)
373 break;
374 }
375 pcic->pcic_imap = p->intmap;
376 pcic->pcic_imdim = p->mapdim;
377 }
378 if (pcic->pcic_imap == NULL) {
379 /*
380 * We do not panic here for the sake of embedded systems.
381 */
382 printk("PCIC: System %s is unknown, cannot route interrupts\n",
383 namebuf);
384 }
385
386 return 0;
387}
388
389static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
390{
391 struct linux_pbm_info *pbm = &pcic->pbm;
392
393 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
394#if 0 /* deadwood transplanted from sparc64 */
395 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
396 pci_record_assignments(pbm, pbm->pci_bus);
397 pci_assign_unassigned(pbm, pbm->pci_bus);
398 pci_fixup_irq(pbm, pbm->pci_bus);
399#endif
400}
401
402/*
403 * Main entry point from the PCI subsystem.
404 */
405static int __init pcic_init(void)
406{
407 struct linux_pcic *pcic;
408
409 /*
410 * PCIC should be initialized at start of the timer.
411 * So, here we report the presence of PCIC and do some magic passes.
412 */
413 if(!pcic0_up)
414 return 0;
415 pcic = &pcic0;
416
417 /*
418 * Switch off IOTLB translation.
419 */
420 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
421 pcic->pcic_regs+PCI_DVMA_CONTROL);
422
423 /*
424 * Increase mapped size for PCI memory space (DMA access).
425 * Should be done in that order (size first, address second).
426 * Why we couldn't set up 4GB and forget about it? XXX
427 */
428 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
429 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
430 pcic->pcic_regs+PCI_BASE_ADDRESS_0);
431
432 pcic_pbm_scan_bus(pcic);
433
434 return 0;
435}
436
437int pcic_present(void)
438{
439 return pcic0_up;
440}
441
442static int __devinit pdev_to_pnode(struct linux_pbm_info *pbm,
443 struct pci_dev *pdev)
444{
445 struct linux_prom_pci_registers regs[PROMREG_MAX];
446 int err;
447 phandle node = prom_getchild(pbm->prom_node);
448
449 while(node) {
450 err = prom_getproperty(node, "reg",
451 (char *)®s[0], sizeof(regs));
452 if(err != 0 && err != -1) {
453 unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
454 if(devfn == pdev->devfn)
455 return node;
456 }
457 node = prom_getsibling(node);
458 }
459 return 0;
460}
461
462static inline struct pcidev_cookie *pci_devcookie_alloc(void)
463{
464 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
465}
466
467static void pcic_map_pci_device(struct linux_pcic *pcic,
468 struct pci_dev *dev, int node)
469{
470 char namebuf[64];
471 unsigned long address;
472 unsigned long flags;
473 int j;
474
475 if (node == 0 || node == -1) {
476 strcpy(namebuf, "???");
477 } else {
478 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
479 }
480
481 for (j = 0; j < 6; j++) {
482 address = dev->resource[j].start;
483 if (address == 0) break; /* are sequential */
484 flags = dev->resource[j].flags;
485 if ((flags & IORESOURCE_IO) != 0) {
486 if (address < 0x10000) {
487 /*
488 * A device responds to I/O cycles on PCI.
489 * We generate these cycles with memory
490 * access into the fixed map (phys 0x30000000).
491 *
492 * Since a device driver does not want to
493 * do ioremap() before accessing PC-style I/O,
494 * we supply virtual, ready to access address.
495 *
496 * Note that request_region()
497 * works for these devices.
498 *
499 * XXX Neat trick, but it's a *bad* idea
500 * to shit into regions like that.
501 * What if we want to allocate one more
502 * PCI base address...
503 */
504 dev->resource[j].start =
505 pcic->pcic_io + address;
506 dev->resource[j].end = 1; /* XXX */
507 dev->resource[j].flags =
508 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
509 } else {
510 /*
511 * OOPS... PCI Spec allows this. Sun does
512 * not have any devices getting above 64K
513 * so it must be user with a weird I/O
514 * board in a PCI slot. We must remap it
515 * under 64K but it is not done yet. XXX
516 */
517 printk("PCIC: Skipping I/O space at 0x%lx, "
518 "this will Oops if a driver attaches "
519 "device '%s' at %02x:%02x)\n", address,
520 namebuf, dev->bus->number, dev->devfn);
521 }
522 }
523 }
524}
525
526static void
527pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
528{
529 struct pcic_ca2irq *p;
530 unsigned int real_irq;
531 int i, ivec;
532 char namebuf[64];
533
534 if (node == 0 || node == -1) {
535 strcpy(namebuf, "???");
536 } else {
537 prom_getstring(node, "name", namebuf, sizeof(namebuf));
538 }
539
540 if ((p = pcic->pcic_imap) == 0) {
541 dev->irq = 0;
542 return;
543 }
544 for (i = 0; i < pcic->pcic_imdim; i++) {
545 if (p->busno == dev->bus->number && p->devfn == dev->devfn)
546 break;
547 p++;
548 }
549 if (i >= pcic->pcic_imdim) {
550 printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
551 namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim);
552 dev->irq = 0;
553 return;
554 }
555
556 i = p->pin;
557 if (i >= 0 && i < 4) {
558 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
559 real_irq = ivec >> (i << 2) & 0xF;
560 } else if (i >= 4 && i < 8) {
561 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
562 real_irq = ivec >> ((i-4) << 2) & 0xF;
563 } else { /* Corrupted map */
564 printk("PCIC: BAD PIN %d\n", i); for (;;) {}
565 }
566/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
567
568 /* real_irq means PROM did not bother to program the upper
569 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
570 */
571 if (real_irq == 0 || p->force) {
572 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
573 printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
574 }
575 printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n",
576 p->irq, p->pin, dev->bus->number, dev->devfn);
577 real_irq = p->irq;
578
579 i = p->pin;
580 if (i >= 4) {
581 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
582 ivec &= ~(0xF << ((i - 4) << 2));
583 ivec |= p->irq << ((i - 4) << 2);
584 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
585 } else {
586 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
587 ivec &= ~(0xF << (i << 2));
588 ivec |= p->irq << (i << 2);
589 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
590 }
591 }
592 dev->irq = pcic_build_device_irq(NULL, real_irq);
593}
594
595/*
596 * Normally called from {do_}pci_scan_bus...
597 */
598void __devinit pcibios_fixup_bus(struct pci_bus *bus)
599{
600 struct pci_dev *dev;
601 int i, has_io, has_mem;
602 unsigned int cmd;
603 struct linux_pcic *pcic;
604 /* struct linux_pbm_info* pbm = &pcic->pbm; */
605 int node;
606 struct pcidev_cookie *pcp;
607
608 if (!pcic0_up) {
609 printk("pcibios_fixup_bus: no PCIC\n");
610 return;
611 }
612 pcic = &pcic0;
613
614 /*
615 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
616 */
617 if (bus->number != 0) {
618 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number);
619 return;
620 }
621
622 list_for_each_entry(dev, &bus->devices, bus_list) {
623
624 /*
625 * Comment from i386 branch:
626 * There are buggy BIOSes that forget to enable I/O and memory
627 * access to PCI devices. We try to fix this, but we need to
628 * be sure that the BIOS didn't forget to assign an address
629 * to the device. [mj]
630 * OBP is a case of such BIOS :-)
631 */
632 has_io = has_mem = 0;
633 for(i=0; i<6; i++) {
634 unsigned long f = dev->resource[i].flags;
635 if (f & IORESOURCE_IO) {
636 has_io = 1;
637 } else if (f & IORESOURCE_MEM)
638 has_mem = 1;
639 }
640 pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
641 if (has_io && !(cmd & PCI_COMMAND_IO)) {
642 printk("PCIC: Enabling I/O for device %02x:%02x\n",
643 dev->bus->number, dev->devfn);
644 cmd |= PCI_COMMAND_IO;
645 pcic_write_config(dev->bus, dev->devfn,
646 PCI_COMMAND, 2, cmd);
647 }
648 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
649 printk("PCIC: Enabling memory for device %02x:%02x\n",
650 dev->bus->number, dev->devfn);
651 cmd |= PCI_COMMAND_MEMORY;
652 pcic_write_config(dev->bus, dev->devfn,
653 PCI_COMMAND, 2, cmd);
654 }
655
656 node = pdev_to_pnode(&pcic->pbm, dev);
657 if(node == 0)
658 node = -1;
659
660 /* cookies */
661 pcp = pci_devcookie_alloc();
662 pcp->pbm = &pcic->pbm;
663 pcp->prom_node = of_find_node_by_phandle(node);
664 dev->sysdata = pcp;
665
666 /* fixing I/O to look like memory */
667 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
668 pcic_map_pci_device(pcic, dev, node);
669
670 pcic_fill_irq(pcic, dev, node);
671 }
672}
673
674/*
675 * pcic_pin_to_irq() is exported to bus probing code
676 */
677unsigned int
678pcic_pin_to_irq(unsigned int pin, const char *name)
679{
680 struct linux_pcic *pcic = &pcic0;
681 unsigned int irq;
682 unsigned int ivec;
683
684 if (pin < 4) {
685 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
686 irq = ivec >> (pin << 2) & 0xF;
687 } else if (pin < 8) {
688 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
689 irq = ivec >> ((pin-4) << 2) & 0xF;
690 } else { /* Corrupted map */
691 printk("PCIC: BAD PIN %d FOR %s\n", pin, name);
692 for (;;) {} /* XXX Cannot panic properly in case of PROLL */
693 }
694/* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */
695 return irq;
696}
697
698/* Makes compiler happy */
699static volatile int pcic_timer_dummy;
700
701static void pcic_clear_clock_irq(void)
702{
703 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
704}
705
706/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
707#define USECS_PER_JIFFY (1000000 / HZ)
708#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
709
710static unsigned int pcic_cycles_offset(void)
711{
712 u32 value, count;
713
714 value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
715 count = value & ~PCI_SYS_COUNTER_OVERFLOW;
716
717 if (value & PCI_SYS_COUNTER_OVERFLOW)
718 count += TICK_TIMER_LIMIT;
719 /*
720 * We divide all by HZ
721 * to have microsecond resolution and to avoid overflow
722 */
723 count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
724
725 /* Coordinate with the sparc_config.clock_rate setting */
726 return count * 2;
727}
728
729void __init pci_time_init(void)
730{
731 struct linux_pcic *pcic = &pcic0;
732 unsigned long v;
733 int timer_irq, irq;
734 int err;
735
736#ifndef CONFIG_SMP
737 /*
738 * The clock_rate is in SBUS dimension.
739 * We take into account this in pcic_cycles_offset()
740 */
741 sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
742 sparc_config.features |= FEAT_L10_CLOCKEVENT;
743#endif
744 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
745 sparc_config.get_cycles_offset = pcic_cycles_offset;
746
747 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
748 /* PROM should set appropriate irq */
749 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
750 timer_irq = PCI_COUNTER_IRQ_SYS(v);
751 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
752 pcic->pcic_regs+PCI_COUNTER_IRQ);
753 irq = pcic_build_device_irq(NULL, timer_irq);
754 err = request_irq(irq, timer_interrupt,
755 IRQF_TIMER, "timer", NULL);
756 if (err) {
757 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
758 prom_halt();
759 }
760 local_irq_enable();
761}
762
763
764#if 0
765static void watchdog_reset() {
766 writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
767}
768#endif
769
770/*
771 * Other archs parse arguments here.
772 */
773char * __devinit pcibios_setup(char *str)
774{
775 return str;
776}
777
778resource_size_t pcibios_align_resource(void *data, const struct resource *res,
779 resource_size_t size, resource_size_t align)
780{
781 return res->start;
782}
783
784int pcibios_enable_device(struct pci_dev *pdev, int mask)
785{
786 return 0;
787}
788
789/*
790 * NMI
791 */
792void pcic_nmi(unsigned int pend, struct pt_regs *regs)
793{
794
795 pend = flip_dword(pend);
796
797 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
798 /*
799 * XXX On CP-1200 PCI #SERR may happen, we do not know
800 * what to do about it yet.
801 */
802 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
803 pend, (int)regs->pc, pcic_speculative);
804 for (;;) { }
805 }
806 pcic_speculative = 0;
807 pcic_trapped = 1;
808 regs->pc = regs->npc;
809 regs->npc += 4;
810}
811
812static inline unsigned long get_irqmask(int irq_nr)
813{
814 return 1 << irq_nr;
815}
816
817static void pcic_mask_irq(struct irq_data *data)
818{
819 unsigned long mask, flags;
820
821 mask = (unsigned long)data->chip_data;
822 local_irq_save(flags);
823 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
824 local_irq_restore(flags);
825}
826
827static void pcic_unmask_irq(struct irq_data *data)
828{
829 unsigned long mask, flags;
830
831 mask = (unsigned long)data->chip_data;
832 local_irq_save(flags);
833 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
834 local_irq_restore(flags);
835}
836
837static unsigned int pcic_startup_irq(struct irq_data *data)
838{
839 irq_link(data->irq);
840 pcic_unmask_irq(data);
841 return 0;
842}
843
844static struct irq_chip pcic_irq = {
845 .name = "pcic",
846 .irq_startup = pcic_startup_irq,
847 .irq_mask = pcic_mask_irq,
848 .irq_unmask = pcic_unmask_irq,
849};
850
851unsigned int pcic_build_device_irq(struct platform_device *op,
852 unsigned int real_irq)
853{
854 unsigned int irq;
855 unsigned long mask;
856
857 irq = 0;
858 mask = get_irqmask(real_irq);
859 if (mask == 0)
860 goto out;
861
862 irq = irq_alloc(real_irq, real_irq);
863 if (irq == 0)
864 goto out;
865
866 irq_set_chip_and_handler_name(irq, &pcic_irq,
867 handle_level_irq, "PCIC");
868 irq_set_chip_data(irq, (void *)mask);
869
870out:
871 return irq;
872}
873
874
875static void pcic_load_profile_irq(int cpu, unsigned int limit)
876{
877 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
878}
879
880void __init sun4m_pci_init_IRQ(void)
881{
882 sparc_config.build_device_irq = pcic_build_device_irq;
883 sparc_config.clear_clock_irq = pcic_clear_clock_irq;
884 sparc_config.load_profile_irq = pcic_load_profile_irq;
885}
886
887int pcibios_assign_resource(struct pci_dev *pdev, int resource)
888{
889 return -ENXIO;
890}
891
892/*
893 * This probably belongs here rather than ioport.c because
894 * we do not want this crud linked into SBus kernels.
895 * Also, think for a moment about likes of floppy.c that
896 * include architecture specific parts. They may want to redefine ins/outs.
897 *
898 * We do not use horrible macros here because we want to
899 * advance pointer by sizeof(size).
900 */
901void outsb(unsigned long addr, const void *src, unsigned long count)
902{
903 while (count) {
904 count -= 1;
905 outb(*(const char *)src, addr);
906 src += 1;
907 /* addr += 1; */
908 }
909}
910EXPORT_SYMBOL(outsb);
911
912void outsw(unsigned long addr, const void *src, unsigned long count)
913{
914 while (count) {
915 count -= 2;
916 outw(*(const short *)src, addr);
917 src += 2;
918 /* addr += 2; */
919 }
920}
921EXPORT_SYMBOL(outsw);
922
923void outsl(unsigned long addr, const void *src, unsigned long count)
924{
925 while (count) {
926 count -= 4;
927 outl(*(const long *)src, addr);
928 src += 4;
929 /* addr += 4; */
930 }
931}
932EXPORT_SYMBOL(outsl);
933
934void insb(unsigned long addr, void *dst, unsigned long count)
935{
936 while (count) {
937 count -= 1;
938 *(unsigned char *)dst = inb(addr);
939 dst += 1;
940 /* addr += 1; */
941 }
942}
943EXPORT_SYMBOL(insb);
944
945void insw(unsigned long addr, void *dst, unsigned long count)
946{
947 while (count) {
948 count -= 2;
949 *(unsigned short *)dst = inw(addr);
950 dst += 2;
951 /* addr += 2; */
952 }
953}
954EXPORT_SYMBOL(insw);
955
956void insl(unsigned long addr, void *dst, unsigned long count)
957{
958 while (count) {
959 count -= 4;
960 /*
961 * XXX I am sure we are in for an unaligned trap here.
962 */
963 *(unsigned long *)dst = inl(addr);
964 dst += 4;
965 /* addr += 4; */
966 }
967}
968EXPORT_SYMBOL(insl);
969
970subsys_initcall(pcic_init);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pcic.c: MicroSPARC-IIep PCI controller support
4 *
5 * Copyright (C) 1998 V. Roganov and G. Raiko
6 *
7 * Code is derived from Ultra/PCI PSYCHO controller support, see that
8 * for author info.
9 *
10 * Support for diverse IIep based platforms by Pete Zaitcev.
11 * CP-1200 by Eric Brower.
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/mm.h>
18#include <linux/slab.h>
19#include <linux/jiffies.h>
20
21#include <asm/swift.h> /* for cache flushing. */
22#include <asm/io.h>
23
24#include <linux/ctype.h>
25#include <linux/pci.h>
26#include <linux/time.h>
27#include <linux/timex.h>
28#include <linux/interrupt.h>
29#include <linux/export.h>
30
31#include <asm/irq.h>
32#include <asm/oplib.h>
33#include <asm/prom.h>
34#include <asm/pcic.h>
35#include <asm/timex.h>
36#include <asm/timer.h>
37#include <linux/uaccess.h>
38#include <asm/irq_regs.h>
39
40#include "kernel.h"
41#include "irq.h"
42
43/*
44 * I studied different documents and many live PROMs both from 2.30
45 * family and 3.xx versions. I came to the amazing conclusion: there is
46 * absolutely no way to route interrupts in IIep systems relying on
47 * information which PROM presents. We must hardcode interrupt routing
48 * schematics. And this actually sucks. -- zaitcev 1999/05/12
49 *
50 * To find irq for a device we determine which routing map
51 * is in effect or, in other words, on which machine we are running.
52 * We use PROM name for this although other techniques may be used
53 * in special cases (Gleb reports a PROMless IIep based system).
54 * Once we know the map we take device configuration address and
55 * find PCIC pin number where INT line goes. Then we may either program
56 * preferred irq into the PCIC or supply the preexisting irq to the device.
57 */
58struct pcic_ca2irq {
59 unsigned char busno; /* PCI bus number */
60 unsigned char devfn; /* Configuration address */
61 unsigned char pin; /* PCIC external interrupt pin */
62 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
63 unsigned int force; /* Enforce preferred IRQ */
64};
65
66struct pcic_sn2list {
67 char *sysname;
68 struct pcic_ca2irq *intmap;
69 int mapdim;
70};
71
72/*
73 * JavaEngine-1 apparently has different versions.
74 *
75 * According to communications with Sun folks, for P2 build 501-4628-03:
76 * pin 0 - parallel, audio;
77 * pin 1 - Ethernet;
78 * pin 2 - su;
79 * pin 3 - PS/2 kbd and mouse.
80 *
81 * OEM manual (805-1486):
82 * pin 0: Ethernet
83 * pin 1: All EBus
84 * pin 2: IGA (unused)
85 * pin 3: Not connected
86 * OEM manual says that 501-4628 & 501-4811 are the same thing,
87 * only the latter has NAND flash in place.
88 *
89 * So far unofficial Sun wins over the OEM manual. Poor OEMs...
90 */
91static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
92 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
93 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
94 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
95};
96
97/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
98static struct pcic_ca2irq pcic_i_jse[] = {
99 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
100 { 0, 0x01, 1, 6, 0 }, /* hme */
101 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
102 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
103 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
104 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
105 { 0, 0x80, 5, 11, 0 }, /* EIDE */
106 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
107 { 0, 0xA0, 4, 9, 0 }, /* USB */
108 /*
109 * Some pins belong to non-PCI devices, we hardcode them in drivers.
110 * sun4m timers - irq 10, 14
111 * PC style RTC - pin 7, irq 4 ?
112 * Smart card, Parallel - pin 4 shared with USB, ISA
113 * audio - pin 3, irq 5 ?
114 */
115};
116
117/* SPARCengine-6 was the original release name of CP1200.
118 * The documentation differs between the two versions
119 */
120static struct pcic_ca2irq pcic_i_se6[] = {
121 { 0, 0x08, 0, 2, 0 }, /* SCSI */
122 { 0, 0x01, 1, 6, 0 }, /* HME */
123 { 0, 0x00, 3, 13, 0 }, /* EBus */
124};
125
126/*
127 * Krups (courtesy of Varol Kaptan)
128 * No documentation available, but it was easy to guess
129 * because it was very similar to Espresso.
130 *
131 * pin 0 - kbd, mouse, serial;
132 * pin 1 - Ethernet;
133 * pin 2 - igs (we do not use it);
134 * pin 3 - audio;
135 * pin 4,5,6 - unused;
136 * pin 7 - RTC (from P2 onwards as David B. says).
137 */
138static struct pcic_ca2irq pcic_i_jk[] = {
139 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
140 { 0, 0x01, 1, 6, 0 }, /* hme */
141};
142
143/*
144 * Several entries in this list may point to the same routing map
145 * as several PROMs may be installed on the same physical board.
146 */
147#define SN2L_INIT(name, map) \
148 { name, map, ARRAY_SIZE(map) }
149
150static struct pcic_sn2list pcic_known_sysnames[] = {
151 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
152 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
153 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
154 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
155 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
156 { NULL, NULL, 0 }
157};
158
159/*
160 * Only one PCIC per IIep,
161 * and since we have no SMP IIep, only one per system.
162 */
163static int pcic0_up;
164static struct linux_pcic pcic0;
165
166void __iomem *pcic_regs;
167static volatile int pcic_speculative;
168static volatile int pcic_trapped;
169
170/* forward */
171unsigned int pcic_build_device_irq(struct platform_device *op,
172 unsigned int real_irq);
173
174#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
175
176static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
177 int where, u32 *value)
178{
179 struct linux_pcic *pcic;
180 unsigned long flags;
181
182 pcic = &pcic0;
183
184 local_irq_save(flags);
185#if 0 /* does not fail here */
186 pcic_speculative = 1;
187 pcic_trapped = 0;
188#endif
189 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
190#if 0 /* does not fail here */
191 nop();
192 if (pcic_trapped) {
193 local_irq_restore(flags);
194 *value = ~0;
195 return 0;
196 }
197#endif
198 pcic_speculative = 2;
199 pcic_trapped = 0;
200 *value = readl(pcic->pcic_config_space_data + (where&4));
201 nop();
202 if (pcic_trapped) {
203 pcic_speculative = 0;
204 local_irq_restore(flags);
205 *value = ~0;
206 return 0;
207 }
208 pcic_speculative = 0;
209 local_irq_restore(flags);
210 return 0;
211}
212
213static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
214 int where, int size, u32 *val)
215{
216 unsigned int v;
217
218 if (bus->number != 0) return -EINVAL;
219 switch (size) {
220 case 1:
221 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
222 *val = 0xff & (v >> (8*(where & 3)));
223 return 0;
224 case 2:
225 if (where&1) return -EINVAL;
226 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
227 *val = 0xffff & (v >> (8*(where & 3)));
228 return 0;
229 case 4:
230 if (where&3) return -EINVAL;
231 pcic_read_config_dword(bus->number, devfn, where&~3, val);
232 return 0;
233 }
234 return -EINVAL;
235}
236
237static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
238 int where, u32 value)
239{
240 struct linux_pcic *pcic;
241 unsigned long flags;
242
243 pcic = &pcic0;
244
245 local_irq_save(flags);
246 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
247 writel(value, pcic->pcic_config_space_data + (where&4));
248 local_irq_restore(flags);
249 return 0;
250}
251
252static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
253 int where, int size, u32 val)
254{
255 unsigned int v;
256
257 if (bus->number != 0) return -EINVAL;
258 switch (size) {
259 case 1:
260 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
261 v = (v & ~(0xff << (8*(where&3)))) |
262 ((0xff&val) << (8*(where&3)));
263 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
264 case 2:
265 if (where&1) return -EINVAL;
266 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
267 v = (v & ~(0xffff << (8*(where&3)))) |
268 ((0xffff&val) << (8*(where&3)));
269 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
270 case 4:
271 if (where&3) return -EINVAL;
272 return pcic_write_config_dword(bus->number, devfn, where, val);
273 }
274 return -EINVAL;
275}
276
277static struct pci_ops pcic_ops = {
278 .read = pcic_read_config,
279 .write = pcic_write_config,
280};
281
282/*
283 * On sparc64 pcibios_init() calls pci_controller_probe().
284 * We want PCIC probed little ahead so that interrupt controller
285 * would be operational.
286 */
287int __init pcic_probe(void)
288{
289 struct linux_pcic *pcic;
290 struct linux_prom_registers regs[PROMREG_MAX];
291 struct linux_pbm_info* pbm;
292 char namebuf[64];
293 phandle node;
294 int err;
295
296 if (pcic0_up) {
297 prom_printf("PCIC: called twice!\n");
298 prom_halt();
299 }
300 pcic = &pcic0;
301
302 node = prom_getchild (prom_root_node);
303 node = prom_searchsiblings (node, "pci");
304 if (node == 0)
305 return -ENODEV;
306 /*
307 * Map in PCIC register set, config space, and IO base
308 */
309 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
310 if (err == 0 || err == -1) {
311 prom_printf("PCIC: Error, cannot get PCIC registers "
312 "from PROM.\n");
313 prom_halt();
314 }
315
316 pcic0_up = 1;
317
318 pcic->pcic_res_regs.name = "pcic_registers";
319 pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
320 if (!pcic->pcic_regs) {
321 prom_printf("PCIC: Error, cannot map PCIC registers.\n");
322 prom_halt();
323 }
324
325 pcic->pcic_res_io.name = "pcic_io";
326 if ((pcic->pcic_io = (unsigned long)
327 ioremap(regs[1].phys_addr, 0x10000)) == 0) {
328 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
329 prom_halt();
330 }
331
332 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
333 if ((pcic->pcic_config_space_addr =
334 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
335 prom_printf("PCIC: Error, cannot map "
336 "PCI Configuration Space Address.\n");
337 prom_halt();
338 }
339
340 /*
341 * Docs say three least significant bits in address and data
342 * must be the same. Thus, we need adjust size of data.
343 */
344 pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
345 if ((pcic->pcic_config_space_data =
346 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
347 prom_printf("PCIC: Error, cannot map "
348 "PCI Configuration Space Data.\n");
349 prom_halt();
350 }
351
352 pbm = &pcic->pbm;
353 pbm->prom_node = node;
354 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
355 strcpy(pbm->prom_name, namebuf);
356
357 {
358 extern int pcic_nmi_trap_patch[4];
359
360 t_nmi[0] = pcic_nmi_trap_patch[0];
361 t_nmi[1] = pcic_nmi_trap_patch[1];
362 t_nmi[2] = pcic_nmi_trap_patch[2];
363 t_nmi[3] = pcic_nmi_trap_patch[3];
364 swift_flush_dcache();
365 pcic_regs = pcic->pcic_regs;
366 }
367
368 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
369 {
370 struct pcic_sn2list *p;
371
372 for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
373 if (strcmp(namebuf, p->sysname) == 0)
374 break;
375 }
376 pcic->pcic_imap = p->intmap;
377 pcic->pcic_imdim = p->mapdim;
378 }
379 if (pcic->pcic_imap == NULL) {
380 /*
381 * We do not panic here for the sake of embedded systems.
382 */
383 printk("PCIC: System %s is unknown, cannot route interrupts\n",
384 namebuf);
385 }
386
387 return 0;
388}
389
390static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
391{
392 struct linux_pbm_info *pbm = &pcic->pbm;
393
394 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
395 if (!pbm->pci_bus)
396 return;
397
398#if 0 /* deadwood transplanted from sparc64 */
399 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
400 pci_record_assignments(pbm, pbm->pci_bus);
401 pci_assign_unassigned(pbm, pbm->pci_bus);
402 pci_fixup_irq(pbm, pbm->pci_bus);
403#endif
404 pci_bus_add_devices(pbm->pci_bus);
405}
406
407/*
408 * Main entry point from the PCI subsystem.
409 */
410static int __init pcic_init(void)
411{
412 struct linux_pcic *pcic;
413
414 /*
415 * PCIC should be initialized at start of the timer.
416 * So, here we report the presence of PCIC and do some magic passes.
417 */
418 if(!pcic0_up)
419 return 0;
420 pcic = &pcic0;
421
422 /*
423 * Switch off IOTLB translation.
424 */
425 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
426 pcic->pcic_regs+PCI_DVMA_CONTROL);
427
428 /*
429 * Increase mapped size for PCI memory space (DMA access).
430 * Should be done in that order (size first, address second).
431 * Why we couldn't set up 4GB and forget about it? XXX
432 */
433 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
434 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
435 pcic->pcic_regs+PCI_BASE_ADDRESS_0);
436
437 pcic_pbm_scan_bus(pcic);
438
439 return 0;
440}
441
442int pcic_present(void)
443{
444 return pcic0_up;
445}
446
447static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
448{
449 struct linux_prom_pci_registers regs[PROMREG_MAX];
450 int err;
451 phandle node = prom_getchild(pbm->prom_node);
452
453 while(node) {
454 err = prom_getproperty(node, "reg",
455 (char *)®s[0], sizeof(regs));
456 if(err != 0 && err != -1) {
457 unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
458 if(devfn == pdev->devfn)
459 return node;
460 }
461 node = prom_getsibling(node);
462 }
463 return 0;
464}
465
466static inline struct pcidev_cookie *pci_devcookie_alloc(void)
467{
468 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
469}
470
471static void pcic_map_pci_device(struct linux_pcic *pcic,
472 struct pci_dev *dev, int node)
473{
474 char namebuf[64];
475 unsigned long address;
476 unsigned long flags;
477 int j;
478
479 if (node == 0 || node == -1) {
480 strcpy(namebuf, "???");
481 } else {
482 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
483 }
484
485 for (j = 0; j < 6; j++) {
486 address = dev->resource[j].start;
487 if (address == 0) break; /* are sequential */
488 flags = dev->resource[j].flags;
489 if ((flags & IORESOURCE_IO) != 0) {
490 if (address < 0x10000) {
491 /*
492 * A device responds to I/O cycles on PCI.
493 * We generate these cycles with memory
494 * access into the fixed map (phys 0x30000000).
495 *
496 * Since a device driver does not want to
497 * do ioremap() before accessing PC-style I/O,
498 * we supply virtual, ready to access address.
499 *
500 * Note that request_region()
501 * works for these devices.
502 *
503 * XXX Neat trick, but it's a *bad* idea
504 * to shit into regions like that.
505 * What if we want to allocate one more
506 * PCI base address...
507 */
508 dev->resource[j].start =
509 pcic->pcic_io + address;
510 dev->resource[j].end = 1; /* XXX */
511 dev->resource[j].flags =
512 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
513 } else {
514 /*
515 * OOPS... PCI Spec allows this. Sun does
516 * not have any devices getting above 64K
517 * so it must be user with a weird I/O
518 * board in a PCI slot. We must remap it
519 * under 64K but it is not done yet. XXX
520 */
521 pci_info(dev, "PCIC: Skipping I/O space at "
522 "0x%lx, this will Oops if a driver "
523 "attaches device '%s'\n", address,
524 namebuf);
525 }
526 }
527 }
528}
529
530static void
531pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
532{
533 struct pcic_ca2irq *p;
534 unsigned int real_irq;
535 int i, ivec;
536 char namebuf[64];
537
538 if (node == 0 || node == -1) {
539 strcpy(namebuf, "???");
540 } else {
541 prom_getstring(node, "name", namebuf, sizeof(namebuf));
542 }
543
544 if ((p = pcic->pcic_imap) == NULL) {
545 dev->irq = 0;
546 return;
547 }
548 for (i = 0; i < pcic->pcic_imdim; i++) {
549 if (p->busno == dev->bus->number && p->devfn == dev->devfn)
550 break;
551 p++;
552 }
553 if (i >= pcic->pcic_imdim) {
554 pci_info(dev, "PCIC: device %s not found in %d\n", namebuf,
555 pcic->pcic_imdim);
556 dev->irq = 0;
557 return;
558 }
559
560 i = p->pin;
561 if (i >= 0 && i < 4) {
562 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
563 real_irq = ivec >> (i << 2) & 0xF;
564 } else if (i >= 4 && i < 8) {
565 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
566 real_irq = ivec >> ((i-4) << 2) & 0xF;
567 } else { /* Corrupted map */
568 pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {}
569 }
570/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
571
572 /* real_irq means PROM did not bother to program the upper
573 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
574 */
575 if (real_irq == 0 || p->force) {
576 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
577 pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
578 }
579 pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq,
580 p->pin);
581 real_irq = p->irq;
582
583 i = p->pin;
584 if (i >= 4) {
585 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
586 ivec &= ~(0xF << ((i - 4) << 2));
587 ivec |= p->irq << ((i - 4) << 2);
588 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
589 } else {
590 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
591 ivec &= ~(0xF << (i << 2));
592 ivec |= p->irq << (i << 2);
593 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
594 }
595 }
596 dev->irq = pcic_build_device_irq(NULL, real_irq);
597}
598
599/*
600 * Normally called from {do_}pci_scan_bus...
601 */
602void pcibios_fixup_bus(struct pci_bus *bus)
603{
604 struct pci_dev *dev;
605 struct linux_pcic *pcic;
606 /* struct linux_pbm_info* pbm = &pcic->pbm; */
607 int node;
608 struct pcidev_cookie *pcp;
609
610 if (!pcic0_up) {
611 pci_info(bus, "pcibios_fixup_bus: no PCIC\n");
612 return;
613 }
614 pcic = &pcic0;
615
616 /*
617 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
618 */
619 if (bus->number != 0) {
620 pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n",
621 bus->number);
622 return;
623 }
624
625 list_for_each_entry(dev, &bus->devices, bus_list) {
626 node = pdev_to_pnode(&pcic->pbm, dev);
627 if(node == 0)
628 node = -1;
629
630 /* cookies */
631 pcp = pci_devcookie_alloc();
632 pcp->pbm = &pcic->pbm;
633 pcp->prom_node = of_find_node_by_phandle(node);
634 dev->sysdata = pcp;
635
636 /* fixing I/O to look like memory */
637 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
638 pcic_map_pci_device(pcic, dev, node);
639
640 pcic_fill_irq(pcic, dev, node);
641 }
642}
643
644int pcibios_enable_device(struct pci_dev *dev, int mask)
645{
646 u16 cmd, oldcmd;
647 int i;
648
649 pci_read_config_word(dev, PCI_COMMAND, &cmd);
650 oldcmd = cmd;
651
652 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
653 struct resource *res = &dev->resource[i];
654
655 /* Only set up the requested stuff */
656 if (!(mask & (1<<i)))
657 continue;
658
659 if (res->flags & IORESOURCE_IO)
660 cmd |= PCI_COMMAND_IO;
661 if (res->flags & IORESOURCE_MEM)
662 cmd |= PCI_COMMAND_MEMORY;
663 }
664
665 if (cmd != oldcmd) {
666 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
667 pci_write_config_word(dev, PCI_COMMAND, cmd);
668 }
669 return 0;
670}
671
672/* Makes compiler happy */
673static volatile int pcic_timer_dummy;
674
675static void pcic_clear_clock_irq(void)
676{
677 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
678}
679
680/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
681#define USECS_PER_JIFFY (1000000 / HZ)
682#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
683
684static unsigned int pcic_cycles_offset(void)
685{
686 u32 value, count;
687
688 value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
689 count = value & ~PCI_SYS_COUNTER_OVERFLOW;
690
691 if (value & PCI_SYS_COUNTER_OVERFLOW)
692 count += TICK_TIMER_LIMIT;
693 /*
694 * We divide all by HZ
695 * to have microsecond resolution and to avoid overflow
696 */
697 count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
698
699 /* Coordinate with the sparc_config.clock_rate setting */
700 return count * 2;
701}
702
703void __init pci_time_init(void)
704{
705 struct linux_pcic *pcic = &pcic0;
706 unsigned long v;
707 int timer_irq, irq;
708 int err;
709
710#ifndef CONFIG_SMP
711 /*
712 * The clock_rate is in SBUS dimension.
713 * We take into account this in pcic_cycles_offset()
714 */
715 sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
716 sparc_config.features |= FEAT_L10_CLOCKEVENT;
717#endif
718 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
719 sparc_config.get_cycles_offset = pcic_cycles_offset;
720
721 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
722 /* PROM should set appropriate irq */
723 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
724 timer_irq = PCI_COUNTER_IRQ_SYS(v);
725 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
726 pcic->pcic_regs+PCI_COUNTER_IRQ);
727 irq = pcic_build_device_irq(NULL, timer_irq);
728 err = request_irq(irq, timer_interrupt,
729 IRQF_TIMER, "timer", NULL);
730 if (err) {
731 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
732 prom_halt();
733 }
734 local_irq_enable();
735}
736
737
738#if 0
739static void watchdog_reset() {
740 writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
741}
742#endif
743
744/*
745 * NMI
746 */
747void pcic_nmi(unsigned int pend, struct pt_regs *regs)
748{
749 pend = swab32(pend);
750
751 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
752 /*
753 * XXX On CP-1200 PCI #SERR may happen, we do not know
754 * what to do about it yet.
755 */
756 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
757 pend, (int)regs->pc, pcic_speculative);
758 for (;;) { }
759 }
760 pcic_speculative = 0;
761 pcic_trapped = 1;
762 regs->pc = regs->npc;
763 regs->npc += 4;
764}
765
766static inline unsigned long get_irqmask(int irq_nr)
767{
768 return 1 << irq_nr;
769}
770
771static void pcic_mask_irq(struct irq_data *data)
772{
773 unsigned long mask, flags;
774
775 mask = (unsigned long)data->chip_data;
776 local_irq_save(flags);
777 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
778 local_irq_restore(flags);
779}
780
781static void pcic_unmask_irq(struct irq_data *data)
782{
783 unsigned long mask, flags;
784
785 mask = (unsigned long)data->chip_data;
786 local_irq_save(flags);
787 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
788 local_irq_restore(flags);
789}
790
791static unsigned int pcic_startup_irq(struct irq_data *data)
792{
793 irq_link(data->irq);
794 pcic_unmask_irq(data);
795 return 0;
796}
797
798static struct irq_chip pcic_irq = {
799 .name = "pcic",
800 .irq_startup = pcic_startup_irq,
801 .irq_mask = pcic_mask_irq,
802 .irq_unmask = pcic_unmask_irq,
803};
804
805unsigned int pcic_build_device_irq(struct platform_device *op,
806 unsigned int real_irq)
807{
808 unsigned int irq;
809 unsigned long mask;
810
811 irq = 0;
812 mask = get_irqmask(real_irq);
813 if (mask == 0)
814 goto out;
815
816 irq = irq_alloc(real_irq, real_irq);
817 if (irq == 0)
818 goto out;
819
820 irq_set_chip_and_handler_name(irq, &pcic_irq,
821 handle_level_irq, "PCIC");
822 irq_set_chip_data(irq, (void *)mask);
823
824out:
825 return irq;
826}
827
828
829static void pcic_load_profile_irq(int cpu, unsigned int limit)
830{
831 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
832}
833
834void __init sun4m_pci_init_IRQ(void)
835{
836 sparc_config.build_device_irq = pcic_build_device_irq;
837 sparc_config.clear_clock_irq = pcic_clear_clock_irq;
838 sparc_config.load_profile_irq = pcic_load_profile_irq;
839}
840
841subsys_initcall(pcic_init);