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1/*
2 * June 2006 steve.glendinning@smsc.com
3 *
4 * Polaris-specific resource declaration
5 *
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/platform_device.h>
12#include <linux/smsc911x.h>
13#include <linux/io.h>
14#include <asm/irq.h>
15#include <asm/machvec.h>
16#include <asm/heartbeat.h>
17#include <cpu/gpio.h>
18#include <mach-se/mach/se.h>
19
20#define BCR2 (0xFFFFFF62)
21#define WCR2 (0xFFFFFF66)
22#define AREA5_WAIT_CTRL (0x1C00)
23#define WAIT_STATES_10 (0x7)
24
25static struct resource smsc911x_resources[] = {
26 [0] = {
27 .name = "smsc911x-memory",
28 .start = PA_EXT5,
29 .end = PA_EXT5 + 0x1fff,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .name = "smsc911x-irq",
34 .start = IRQ0_IRQ,
35 .end = IRQ0_IRQ,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static struct smsc911x_platform_config smsc911x_config = {
41 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
42 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
43 .flags = SMSC911X_USE_32BIT,
44 .phy_interface = PHY_INTERFACE_MODE_MII,
45};
46
47static struct platform_device smsc911x_device = {
48 .name = "smsc911x",
49 .id = 0,
50 .num_resources = ARRAY_SIZE(smsc911x_resources),
51 .resource = smsc911x_resources,
52 .dev = {
53 .platform_data = &smsc911x_config,
54 },
55};
56
57static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
58
59static struct heartbeat_data heartbeat_data = {
60 .bit_pos = heartbeat_bit_pos,
61 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
62};
63
64static struct resource heartbeat_resource = {
65 .start = PORT_PCDR,
66 .end = PORT_PCDR,
67 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
68};
69
70static struct platform_device heartbeat_device = {
71 .name = "heartbeat",
72 .id = -1,
73 .dev = {
74 .platform_data = &heartbeat_data,
75 },
76 .num_resources = 1,
77 .resource = &heartbeat_resource,
78};
79
80static struct platform_device *polaris_devices[] __initdata = {
81 &smsc911x_device,
82 &heartbeat_device,
83};
84
85static int __init polaris_initialise(void)
86{
87 u16 wcr, bcr_mask;
88
89 printk(KERN_INFO "Configuring Polaris external bus\n");
90
91 /* Configure area 5 with 2 wait states */
92 wcr = __raw_readw(WCR2);
93 wcr &= (~AREA5_WAIT_CTRL);
94 wcr |= (WAIT_STATES_10 << 10);
95 __raw_writew(wcr, WCR2);
96
97 /* Configure area 5 for 32-bit access */
98 bcr_mask = __raw_readw(BCR2);
99 bcr_mask |= 1 << 10;
100 __raw_writew(bcr_mask, BCR2);
101
102 return platform_add_devices(polaris_devices,
103 ARRAY_SIZE(polaris_devices));
104}
105arch_initcall(polaris_initialise);
106
107static struct ipr_data ipr_irq_table[] = {
108 /* External IRQs */
109 { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
110 { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
111};
112
113static unsigned long ipr_offsets[] = {
114 INTC_IPRC
115};
116
117static struct ipr_desc ipr_irq_desc = {
118 .ipr_offsets = ipr_offsets,
119 .nr_offsets = ARRAY_SIZE(ipr_offsets),
120
121 .ipr_data = ipr_irq_table,
122 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
123 .chip = {
124 .name = "sh7709-ext",
125 },
126};
127
128static void __init init_polaris_irq(void)
129{
130 /* Disable all interrupts */
131 __raw_writew(0, BCR_ILCRA);
132 __raw_writew(0, BCR_ILCRB);
133 __raw_writew(0, BCR_ILCRC);
134 __raw_writew(0, BCR_ILCRD);
135 __raw_writew(0, BCR_ILCRE);
136 __raw_writew(0, BCR_ILCRF);
137 __raw_writew(0, BCR_ILCRG);
138
139 register_ipr_controller(&ipr_irq_desc);
140}
141
142static struct sh_machine_vector mv_polaris __initmv = {
143 .mv_name = "Polaris",
144 .mv_init_irq = init_polaris_irq,
145};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * June 2006 Steve Glendinning <steve.glendinning@shawell.net>
4 *
5 * Polaris-specific resource declaration
6 *
7 */
8
9#include <linux/init.h>
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <linux/platform_device.h>
13#include <linux/regulator/fixed.h>
14#include <linux/regulator/machine.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
17#include <asm/irq.h>
18#include <asm/machvec.h>
19#include <asm/heartbeat.h>
20#include <cpu/gpio.h>
21#include <mach-se/mach/se.h>
22
23#define BCR2 (0xFFFFFF62)
24#define WCR2 (0xFFFFFF66)
25#define AREA5_WAIT_CTRL (0x1C00)
26#define WAIT_STATES_10 (0x7)
27
28/* Dummy supplies, where voltage doesn't matter */
29static struct regulator_consumer_supply dummy_supplies[] = {
30 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
31 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
32};
33
34static struct resource smsc911x_resources[] = {
35 [0] = {
36 .name = "smsc911x-memory",
37 .start = PA_EXT5,
38 .end = PA_EXT5 + 0x1fff,
39 .flags = IORESOURCE_MEM,
40 },
41 [1] = {
42 .name = "smsc911x-irq",
43 .start = IRQ0_IRQ,
44 .end = IRQ0_IRQ,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49static struct smsc911x_platform_config smsc911x_config = {
50 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
51 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
52 .flags = SMSC911X_USE_32BIT,
53 .phy_interface = PHY_INTERFACE_MODE_MII,
54};
55
56static struct platform_device smsc911x_device = {
57 .name = "smsc911x",
58 .id = 0,
59 .num_resources = ARRAY_SIZE(smsc911x_resources),
60 .resource = smsc911x_resources,
61 .dev = {
62 .platform_data = &smsc911x_config,
63 },
64};
65
66static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
67
68static struct heartbeat_data heartbeat_data = {
69 .bit_pos = heartbeat_bit_pos,
70 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
71};
72
73static struct resource heartbeat_resource = {
74 .start = PORT_PCDR,
75 .end = PORT_PCDR,
76 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
77};
78
79static struct platform_device heartbeat_device = {
80 .name = "heartbeat",
81 .id = -1,
82 .dev = {
83 .platform_data = &heartbeat_data,
84 },
85 .num_resources = 1,
86 .resource = &heartbeat_resource,
87};
88
89static struct platform_device *polaris_devices[] __initdata = {
90 &smsc911x_device,
91 &heartbeat_device,
92};
93
94static int __init polaris_initialise(void)
95{
96 u16 wcr, bcr_mask;
97
98 printk(KERN_INFO "Configuring Polaris external bus\n");
99
100 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
101
102 /* Configure area 5 with 2 wait states */
103 wcr = __raw_readw(WCR2);
104 wcr &= (~AREA5_WAIT_CTRL);
105 wcr |= (WAIT_STATES_10 << 10);
106 __raw_writew(wcr, WCR2);
107
108 /* Configure area 5 for 32-bit access */
109 bcr_mask = __raw_readw(BCR2);
110 bcr_mask |= 1 << 10;
111 __raw_writew(bcr_mask, BCR2);
112
113 return platform_add_devices(polaris_devices,
114 ARRAY_SIZE(polaris_devices));
115}
116arch_initcall(polaris_initialise);
117
118static struct ipr_data ipr_irq_table[] = {
119 /* External IRQs */
120 { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
121 { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
122};
123
124static unsigned long ipr_offsets[] = {
125 INTC_IPRC
126};
127
128static struct ipr_desc ipr_irq_desc = {
129 .ipr_offsets = ipr_offsets,
130 .nr_offsets = ARRAY_SIZE(ipr_offsets),
131
132 .ipr_data = ipr_irq_table,
133 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
134 .chip = {
135 .name = "sh7709-ext",
136 },
137};
138
139static void __init init_polaris_irq(void)
140{
141 /* Disable all interrupts */
142 __raw_writew(0, BCR_ILCRA);
143 __raw_writew(0, BCR_ILCRB);
144 __raw_writew(0, BCR_ILCRC);
145 __raw_writew(0, BCR_ILCRD);
146 __raw_writew(0, BCR_ILCRE);
147 __raw_writew(0, BCR_ILCRF);
148 __raw_writew(0, BCR_ILCRG);
149
150 register_ipr_controller(&ipr_irq_desc);
151}
152
153static struct sh_machine_vector mv_polaris __initmv = {
154 .mv_name = "Polaris",
155 .mv_init_irq = init_polaris_irq,
156};