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1/*
2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
3 * Copyright (C) 2005 Mips Technologies, Inc
4 */
5
6#include <linux/device.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/export.h>
10#include <linux/interrupt.h>
11#include <linux/security.h>
12
13#include <asm/cpu.h>
14#include <asm/processor.h>
15#include <linux/atomic.h>
16#include <asm/hardirq.h>
17#include <asm/mmu_context.h>
18#include <asm/mipsmtregs.h>
19#include <asm/r4kcache.h>
20#include <asm/cacheflush.h>
21
22int vpelimit;
23
24static int __init maxvpes(char *str)
25{
26 get_option(&str, &vpelimit);
27
28 return 1;
29}
30
31__setup("maxvpes=", maxvpes);
32
33int tclimit;
34
35static int __init maxtcs(char *str)
36{
37 get_option(&str, &tclimit);
38
39 return 1;
40}
41
42__setup("maxtcs=", maxtcs);
43
44/*
45 * Dump new MIPS MT state for the core. Does not leave TCs halted.
46 * Takes an argument which taken to be a pre-call MVPControl value.
47 */
48
49void mips_mt_regdump(unsigned long mvpctl)
50{
51 unsigned long flags;
52 unsigned long vpflags;
53 unsigned long mvpconf0;
54 int nvpe;
55 int ntc;
56 int i;
57 int tc;
58 unsigned long haltval;
59 unsigned long tcstatval;
60#ifdef CONFIG_MIPS_MT_SMTC
61 void smtc_soft_dump(void);
62#endif /* CONFIG_MIPT_MT_SMTC */
63
64 local_irq_save(flags);
65 vpflags = dvpe();
66 printk("=== MIPS MT State Dump ===\n");
67 printk("-- Global State --\n");
68 printk(" MVPControl Passed: %08lx\n", mvpctl);
69 printk(" MVPControl Read: %08lx\n", vpflags);
70 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
71 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
72 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
73 printk("-- per-VPE State --\n");
74 for (i = 0; i < nvpe; i++) {
75 for (tc = 0; tc < ntc; tc++) {
76 settc(tc);
77 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
78 printk(" VPE %d\n", i);
79 printk(" VPEControl : %08lx\n",
80 read_vpe_c0_vpecontrol());
81 printk(" VPEConf0 : %08lx\n",
82 read_vpe_c0_vpeconf0());
83 printk(" VPE%d.Status : %08lx\n",
84 i, read_vpe_c0_status());
85 printk(" VPE%d.EPC : %08lx %pS\n",
86 i, read_vpe_c0_epc(),
87 (void *) read_vpe_c0_epc());
88 printk(" VPE%d.Cause : %08lx\n",
89 i, read_vpe_c0_cause());
90 printk(" VPE%d.Config7 : %08lx\n",
91 i, read_vpe_c0_config7());
92 break; /* Next VPE */
93 }
94 }
95 }
96 printk("-- per-TC State --\n");
97 for (tc = 0; tc < ntc; tc++) {
98 settc(tc);
99 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
100 /* Are we dumping ourself? */
101 haltval = 0; /* Then we're not halted, and mustn't be */
102 tcstatval = flags; /* And pre-dump TCStatus is flags */
103 printk(" TC %d (current TC with VPE EPC above)\n", tc);
104 } else {
105 haltval = read_tc_c0_tchalt();
106 write_tc_c0_tchalt(1);
107 tcstatval = read_tc_c0_tcstatus();
108 printk(" TC %d\n", tc);
109 }
110 printk(" TCStatus : %08lx\n", tcstatval);
111 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
112 printk(" TCRestart : %08lx %pS\n",
113 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
114 printk(" TCHalt : %08lx\n", haltval);
115 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
116 if (!haltval)
117 write_tc_c0_tchalt(0);
118 }
119#ifdef CONFIG_MIPS_MT_SMTC
120 smtc_soft_dump();
121#endif /* CONFIG_MIPT_MT_SMTC */
122 printk("===========================\n");
123 evpe(vpflags);
124 local_irq_restore(flags);
125}
126
127static int mt_opt_norps;
128static int mt_opt_rpsctl = -1;
129static int mt_opt_nblsu = -1;
130static int mt_opt_forceconfig7;
131static int mt_opt_config7 = -1;
132
133static int __init rps_disable(char *s)
134{
135 mt_opt_norps = 1;
136 return 1;
137}
138__setup("norps", rps_disable);
139
140static int __init rpsctl_set(char *str)
141{
142 get_option(&str, &mt_opt_rpsctl);
143 return 1;
144}
145__setup("rpsctl=", rpsctl_set);
146
147static int __init nblsu_set(char *str)
148{
149 get_option(&str, &mt_opt_nblsu);
150 return 1;
151}
152__setup("nblsu=", nblsu_set);
153
154static int __init config7_set(char *str)
155{
156 get_option(&str, &mt_opt_config7);
157 mt_opt_forceconfig7 = 1;
158 return 1;
159}
160__setup("config7=", config7_set);
161
162/* Experimental cache flush control parameters that should go away some day */
163int mt_protiflush;
164int mt_protdflush;
165int mt_n_iflushes = 1;
166int mt_n_dflushes = 1;
167
168static int __init set_protiflush(char *s)
169{
170 mt_protiflush = 1;
171 return 1;
172}
173__setup("protiflush", set_protiflush);
174
175static int __init set_protdflush(char *s)
176{
177 mt_protdflush = 1;
178 return 1;
179}
180__setup("protdflush", set_protdflush);
181
182static int __init niflush(char *s)
183{
184 get_option(&s, &mt_n_iflushes);
185 return 1;
186}
187__setup("niflush=", niflush);
188
189static int __init ndflush(char *s)
190{
191 get_option(&s, &mt_n_dflushes);
192 return 1;
193}
194__setup("ndflush=", ndflush);
195
196static unsigned int itc_base;
197
198static int __init set_itc_base(char *str)
199{
200 get_option(&str, &itc_base);
201 return 1;
202}
203
204__setup("itcbase=", set_itc_base);
205
206void mips_mt_set_cpuoptions(void)
207{
208 unsigned int oconfig7 = read_c0_config7();
209 unsigned int nconfig7 = oconfig7;
210
211 if (mt_opt_norps) {
212 printk("\"norps\" option deprecated: use \"rpsctl=\"\n");
213 }
214 if (mt_opt_rpsctl >= 0) {
215 printk("34K return prediction stack override set to %d.\n",
216 mt_opt_rpsctl);
217 if (mt_opt_rpsctl)
218 nconfig7 |= (1 << 2);
219 else
220 nconfig7 &= ~(1 << 2);
221 }
222 if (mt_opt_nblsu >= 0) {
223 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
224 if (mt_opt_nblsu)
225 nconfig7 |= (1 << 5);
226 else
227 nconfig7 &= ~(1 << 5);
228 }
229 if (mt_opt_forceconfig7) {
230 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
231 nconfig7 = mt_opt_config7;
232 }
233 if (oconfig7 != nconfig7) {
234 __asm__ __volatile("sync");
235 write_c0_config7(nconfig7);
236 ehb();
237 printk("Config7: 0x%08x\n", read_c0_config7());
238 }
239
240 /* Report Cache management debug options */
241 if (mt_protiflush)
242 printk("I-cache flushes single-threaded\n");
243 if (mt_protdflush)
244 printk("D-cache flushes single-threaded\n");
245 if (mt_n_iflushes != 1)
246 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
247 if (mt_n_dflushes != 1)
248 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
249
250 if (itc_base != 0) {
251 /*
252 * Configure ITC mapping. This code is very
253 * specific to the 34K core family, which uses
254 * a special mode bit ("ITC") in the ErrCtl
255 * register to enable access to ITC control
256 * registers via cache "tag" operations.
257 */
258 unsigned long ectlval;
259 unsigned long itcblkgrn;
260
261 /* ErrCtl register is known as "ecc" to Linux */
262 ectlval = read_c0_ecc();
263 write_c0_ecc(ectlval | (0x1 << 26));
264 ehb();
265#define INDEX_0 (0x80000000)
266#define INDEX_8 (0x80000008)
267 /* Read "cache tag" for Dcache pseudo-index 8 */
268 cache_op(Index_Load_Tag_D, INDEX_8);
269 ehb();
270 itcblkgrn = read_c0_dtaglo();
271 itcblkgrn &= 0xfffe0000;
272 /* Set for 128 byte pitch of ITC cells */
273 itcblkgrn |= 0x00000c00;
274 /* Stage in Tag register */
275 write_c0_dtaglo(itcblkgrn);
276 ehb();
277 /* Write out to ITU with CACHE op */
278 cache_op(Index_Store_Tag_D, INDEX_8);
279 /* Now set base address, and turn ITC on with 0x1 bit */
280 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
281 ehb();
282 /* Write out to ITU with CACHE op */
283 cache_op(Index_Store_Tag_D, INDEX_0);
284 write_c0_ecc(ectlval);
285 ehb();
286 printk("Mapped %ld ITC cells starting at 0x%08x\n",
287 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
288 }
289}
290
291/*
292 * Function to protect cache flushes from concurrent execution
293 * depends on MP software model chosen.
294 */
295
296void mt_cflush_lockdown(void)
297{
298#ifdef CONFIG_MIPS_MT_SMTC
299 void smtc_cflush_lockdown(void);
300
301 smtc_cflush_lockdown();
302#endif /* CONFIG_MIPS_MT_SMTC */
303 /* FILL IN VSMP and AP/SP VERSIONS HERE */
304}
305
306void mt_cflush_release(void)
307{
308#ifdef CONFIG_MIPS_MT_SMTC
309 void smtc_cflush_release(void);
310
311 smtc_cflush_release();
312#endif /* CONFIG_MIPS_MT_SMTC */
313 /* FILL IN VSMP and AP/SP VERSIONS HERE */
314}
315
316struct class *mt_class;
317
318static int __init mt_init(void)
319{
320 struct class *mtc;
321
322 mtc = class_create(THIS_MODULE, "mt");
323 if (IS_ERR(mtc))
324 return PTR_ERR(mtc);
325
326 mt_class = mtc;
327
328 return 0;
329}
330
331subsys_initcall(mt_init);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc
5 */
6
7#include <linux/device.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/export.h>
11#include <linux/interrupt.h>
12#include <linux/security.h>
13
14#include <asm/cpu.h>
15#include <asm/processor.h>
16#include <linux/atomic.h>
17#include <asm/hardirq.h>
18#include <asm/mmu_context.h>
19#include <asm/mipsmtregs.h>
20#include <asm/r4kcache.h>
21#include <asm/cacheflush.h>
22
23int vpelimit;
24
25static int __init maxvpes(char *str)
26{
27 get_option(&str, &vpelimit);
28
29 return 1;
30}
31
32__setup("maxvpes=", maxvpes);
33
34int tclimit;
35
36static int __init maxtcs(char *str)
37{
38 get_option(&str, &tclimit);
39
40 return 1;
41}
42
43__setup("maxtcs=", maxtcs);
44
45/*
46 * Dump new MIPS MT state for the core. Does not leave TCs halted.
47 * Takes an argument which taken to be a pre-call MVPControl value.
48 */
49
50void mips_mt_regdump(unsigned long mvpctl)
51{
52 unsigned long flags;
53 unsigned long vpflags;
54 unsigned long mvpconf0;
55 int nvpe;
56 int ntc;
57 int i;
58 int tc;
59 unsigned long haltval;
60 unsigned long tcstatval;
61
62 local_irq_save(flags);
63 vpflags = dvpe();
64 printk("=== MIPS MT State Dump ===\n");
65 printk("-- Global State --\n");
66 printk(" MVPControl Passed: %08lx\n", mvpctl);
67 printk(" MVPControl Read: %08lx\n", vpflags);
68 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
69 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
70 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
71 printk("-- per-VPE State --\n");
72 for (i = 0; i < nvpe; i++) {
73 for (tc = 0; tc < ntc; tc++) {
74 settc(tc);
75 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
76 printk(" VPE %d\n", i);
77 printk(" VPEControl : %08lx\n",
78 read_vpe_c0_vpecontrol());
79 printk(" VPEConf0 : %08lx\n",
80 read_vpe_c0_vpeconf0());
81 printk(" VPE%d.Status : %08lx\n",
82 i, read_vpe_c0_status());
83 printk(" VPE%d.EPC : %08lx %pS\n",
84 i, read_vpe_c0_epc(),
85 (void *) read_vpe_c0_epc());
86 printk(" VPE%d.Cause : %08lx\n",
87 i, read_vpe_c0_cause());
88 printk(" VPE%d.Config7 : %08lx\n",
89 i, read_vpe_c0_config7());
90 break; /* Next VPE */
91 }
92 }
93 }
94 printk("-- per-TC State --\n");
95 for (tc = 0; tc < ntc; tc++) {
96 settc(tc);
97 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
98 /* Are we dumping ourself? */
99 haltval = 0; /* Then we're not halted, and mustn't be */
100 tcstatval = flags; /* And pre-dump TCStatus is flags */
101 printk(" TC %d (current TC with VPE EPC above)\n", tc);
102 } else {
103 haltval = read_tc_c0_tchalt();
104 write_tc_c0_tchalt(1);
105 tcstatval = read_tc_c0_tcstatus();
106 printk(" TC %d\n", tc);
107 }
108 printk(" TCStatus : %08lx\n", tcstatval);
109 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
110 printk(" TCRestart : %08lx %pS\n",
111 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
112 printk(" TCHalt : %08lx\n", haltval);
113 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
114 if (!haltval)
115 write_tc_c0_tchalt(0);
116 }
117 printk("===========================\n");
118 evpe(vpflags);
119 local_irq_restore(flags);
120}
121
122static int mt_opt_rpsctl = -1;
123static int mt_opt_nblsu = -1;
124static int mt_opt_forceconfig7;
125static int mt_opt_config7 = -1;
126
127static int __init rpsctl_set(char *str)
128{
129 get_option(&str, &mt_opt_rpsctl);
130 return 1;
131}
132__setup("rpsctl=", rpsctl_set);
133
134static int __init nblsu_set(char *str)
135{
136 get_option(&str, &mt_opt_nblsu);
137 return 1;
138}
139__setup("nblsu=", nblsu_set);
140
141static int __init config7_set(char *str)
142{
143 get_option(&str, &mt_opt_config7);
144 mt_opt_forceconfig7 = 1;
145 return 1;
146}
147__setup("config7=", config7_set);
148
149static unsigned int itc_base;
150
151static int __init set_itc_base(char *str)
152{
153 get_option(&str, &itc_base);
154 return 1;
155}
156
157__setup("itcbase=", set_itc_base);
158
159void mips_mt_set_cpuoptions(void)
160{
161 unsigned int oconfig7 = read_c0_config7();
162 unsigned int nconfig7 = oconfig7;
163
164 if (mt_opt_rpsctl >= 0) {
165 printk("34K return prediction stack override set to %d.\n",
166 mt_opt_rpsctl);
167 if (mt_opt_rpsctl)
168 nconfig7 |= (1 << 2);
169 else
170 nconfig7 &= ~(1 << 2);
171 }
172 if (mt_opt_nblsu >= 0) {
173 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
174 if (mt_opt_nblsu)
175 nconfig7 |= (1 << 5);
176 else
177 nconfig7 &= ~(1 << 5);
178 }
179 if (mt_opt_forceconfig7) {
180 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
181 nconfig7 = mt_opt_config7;
182 }
183 if (oconfig7 != nconfig7) {
184 __asm__ __volatile("sync");
185 write_c0_config7(nconfig7);
186 ehb();
187 printk("Config7: 0x%08x\n", read_c0_config7());
188 }
189
190 if (itc_base != 0) {
191 /*
192 * Configure ITC mapping. This code is very
193 * specific to the 34K core family, which uses
194 * a special mode bit ("ITC") in the ErrCtl
195 * register to enable access to ITC control
196 * registers via cache "tag" operations.
197 */
198 unsigned long ectlval;
199 unsigned long itcblkgrn;
200
201 /* ErrCtl register is known as "ecc" to Linux */
202 ectlval = read_c0_ecc();
203 write_c0_ecc(ectlval | (0x1 << 26));
204 ehb();
205#define INDEX_0 (0x80000000)
206#define INDEX_8 (0x80000008)
207 /* Read "cache tag" for Dcache pseudo-index 8 */
208 cache_op(Index_Load_Tag_D, INDEX_8);
209 ehb();
210 itcblkgrn = read_c0_dtaglo();
211 itcblkgrn &= 0xfffe0000;
212 /* Set for 128 byte pitch of ITC cells */
213 itcblkgrn |= 0x00000c00;
214 /* Stage in Tag register */
215 write_c0_dtaglo(itcblkgrn);
216 ehb();
217 /* Write out to ITU with CACHE op */
218 cache_op(Index_Store_Tag_D, INDEX_8);
219 /* Now set base address, and turn ITC on with 0x1 bit */
220 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
221 ehb();
222 /* Write out to ITU with CACHE op */
223 cache_op(Index_Store_Tag_D, INDEX_0);
224 write_c0_ecc(ectlval);
225 ehb();
226 printk("Mapped %ld ITC cells starting at 0x%08x\n",
227 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
228 }
229}
230
231struct class *mt_class;
232
233static int __init mips_mt_init(void)
234{
235 struct class *mtc;
236
237 mtc = class_create(THIS_MODULE, "mt");
238 if (IS_ERR(mtc))
239 return PTR_ERR(mtc);
240
241 mt_class = mtc;
242
243 return 0;
244}
245
246subsys_initcall(mips_mt_init);