1/*
 2 * NetLogic DB1300 board constants
 3 */
 4
 5#ifndef _DB1300_H_
 6#define _DB1300_H_
 7
 8/* FPGA (external mux) interrupt sources */
 9#define DB1300_FIRST_INT	(ALCHEMY_GPIC_INT_LAST + 1)
10#define DB1300_IDE_INT		(DB1300_FIRST_INT + 0)
11#define DB1300_ETH_INT		(DB1300_FIRST_INT + 1)
12#define DB1300_CF_INT		(DB1300_FIRST_INT + 2)
13#define DB1300_VIDEO_INT	(DB1300_FIRST_INT + 4)
14#define DB1300_HDMI_INT		(DB1300_FIRST_INT + 5)
15#define DB1300_DC_INT		(DB1300_FIRST_INT + 6)
16#define DB1300_FLASH_INT	(DB1300_FIRST_INT + 7)
17#define DB1300_CF_INSERT_INT	(DB1300_FIRST_INT + 8)
18#define DB1300_CF_EJECT_INT	(DB1300_FIRST_INT + 9)
19#define DB1300_AC97_INT		(DB1300_FIRST_INT + 10)
20#define DB1300_AC97_PEN_INT	(DB1300_FIRST_INT + 11)
21#define DB1300_SD1_INSERT_INT	(DB1300_FIRST_INT + 12)
22#define DB1300_SD1_EJECT_INT	(DB1300_FIRST_INT + 13)
23#define DB1300_OTG_VBUS_OC_INT	(DB1300_FIRST_INT + 14)
24#define DB1300_HOST_VBUS_OC_INT	(DB1300_FIRST_INT + 15)
25#define DB1300_LAST_INT		(DB1300_FIRST_INT + 15)
26
27/* SMSC9210 CS */
28#define DB1300_ETH_PHYS_ADDR	0x19000000
29#define DB1300_ETH_PHYS_END	0x197fffff
30
31/* ATA CS */
32#define DB1300_IDE_PHYS_ADDR	0x18800000
33#define DB1300_IDE_REG_SHIFT	5
34#define DB1300_IDE_PHYS_LEN	(16 << DB1300_IDE_REG_SHIFT)
35
36/* NAND CS */
37#define DB1300_NAND_PHYS_ADDR	0x20000000
38#define DB1300_NAND_PHYS_END	0x20000fff
39
40#endif	/* _DB1300_H_ */