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1/*
2 * OMAP3/4 - specific DPLL control functions
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
9 *
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
11 * Menon
12 *
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/device.h>
23#include <linux/list.h>
24#include <linux/errno.h>
25#include <linux/delay.h>
26#include <linux/clk.h>
27#include <linux/io.h>
28#include <linux/bitops.h>
29#include <linux/clkdev.h>
30
31#include <plat/cpu.h>
32#include <plat/clock.h>
33
34#include "clock.h"
35#include "cm2xxx_3xxx.h"
36#include "cm-regbits-34xx.h"
37
38/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
39#define DPLL_AUTOIDLE_DISABLE 0x0
40#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
41
42#define MAX_DPLL_WAIT_TRIES 1000000
43
44/* Private functions */
45
46/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
47static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
48{
49 const struct dpll_data *dd;
50 u32 v;
51
52 dd = clk->dpll_data;
53
54 v = __raw_readl(dd->control_reg);
55 v &= ~dd->enable_mask;
56 v |= clken_bits << __ffs(dd->enable_mask);
57 __raw_writel(v, dd->control_reg);
58}
59
60/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
61static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
62{
63 const struct dpll_data *dd;
64 int i = 0;
65 int ret = -EINVAL;
66
67 dd = clk->dpll_data;
68
69 state <<= __ffs(dd->idlest_mask);
70
71 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
72 i < MAX_DPLL_WAIT_TRIES) {
73 i++;
74 udelay(1);
75 }
76
77 if (i == MAX_DPLL_WAIT_TRIES) {
78 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
79 clk->name, (state) ? "locked" : "bypassed");
80 } else {
81 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk->name, (state) ? "locked" : "bypassed", i);
83
84 ret = 0;
85 }
86
87 return ret;
88}
89
90/* From 3430 TRM ES2 4.7.6.2 */
91static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
92{
93 unsigned long fint;
94 u16 f = 0;
95
96 fint = clk->dpll_data->clk_ref->rate / n;
97
98 pr_debug("clock: fint is %lu\n", fint);
99
100 if (fint >= 750000 && fint <= 1000000)
101 f = 0x3;
102 else if (fint > 1000000 && fint <= 1250000)
103 f = 0x4;
104 else if (fint > 1250000 && fint <= 1500000)
105 f = 0x5;
106 else if (fint > 1500000 && fint <= 1750000)
107 f = 0x6;
108 else if (fint > 1750000 && fint <= 2100000)
109 f = 0x7;
110 else if (fint > 7500000 && fint <= 10000000)
111 f = 0xB;
112 else if (fint > 10000000 && fint <= 12500000)
113 f = 0xC;
114 else if (fint > 12500000 && fint <= 15000000)
115 f = 0xD;
116 else if (fint > 15000000 && fint <= 17500000)
117 f = 0xE;
118 else if (fint > 17500000 && fint <= 21000000)
119 f = 0xF;
120 else
121 pr_debug("clock: unknown freqsel setting for %d\n", n);
122
123 return f;
124}
125
126/*
127 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
128 * @clk: pointer to a DPLL struct clk
129 *
130 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
131 * readiness before returning. Will save and restore the DPLL's
132 * autoidle state across the enable, per the CDP code. If the DPLL
133 * locked successfully, return 0; if the DPLL did not lock in the time
134 * allotted, or DPLL3 was passed in, return -EINVAL.
135 */
136static int _omap3_noncore_dpll_lock(struct clk *clk)
137{
138 u8 ai;
139 int r;
140
141 pr_debug("clock: locking DPLL %s\n", clk->name);
142
143 ai = omap3_dpll_autoidle_read(clk);
144
145 if (ai)
146 omap3_dpll_deny_idle(clk);
147
148 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
149
150 r = _omap3_wait_dpll_status(clk, 1);
151
152 if (ai)
153 omap3_dpll_allow_idle(clk);
154
155 return r;
156}
157
158/*
159 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
160 * @clk: pointer to a DPLL struct clk
161 *
162 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
163 * bypass mode, the DPLL's rate is set equal to its parent clock's
164 * rate. Waits for the DPLL to report readiness before returning.
165 * Will save and restore the DPLL's autoidle state across the enable,
166 * per the CDP code. If the DPLL entered bypass mode successfully,
167 * return 0; if the DPLL did not enter bypass in the time allotted, or
168 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
169 * return -EINVAL.
170 */
171static int _omap3_noncore_dpll_bypass(struct clk *clk)
172{
173 int r;
174 u8 ai;
175
176 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
177 return -EINVAL;
178
179 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
180 clk->name);
181
182 ai = omap3_dpll_autoidle_read(clk);
183
184 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
185
186 r = _omap3_wait_dpll_status(clk, 0);
187
188 if (ai)
189 omap3_dpll_allow_idle(clk);
190
191 return r;
192}
193
194/*
195 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
196 * @clk: pointer to a DPLL struct clk
197 *
198 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
199 * restore the DPLL's autoidle state across the stop, per the CDP
200 * code. If DPLL3 was passed in, or the DPLL does not support
201 * low-power stop, return -EINVAL; otherwise, return 0.
202 */
203static int _omap3_noncore_dpll_stop(struct clk *clk)
204{
205 u8 ai;
206
207 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
208 return -EINVAL;
209
210 pr_debug("clock: stopping DPLL %s\n", clk->name);
211
212 ai = omap3_dpll_autoidle_read(clk);
213
214 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
215
216 if (ai)
217 omap3_dpll_allow_idle(clk);
218
219 return 0;
220}
221
222/**
223 * _lookup_dco - Lookup DCO used by j-type DPLL
224 * @clk: pointer to a DPLL struct clk
225 * @dco: digital control oscillator selector
226 * @m: DPLL multiplier to set
227 * @n: DPLL divider to set
228 *
229 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
230 *
231 * XXX This code is not needed for 3430/AM35xx; can it be optimized
232 * out in non-multi-OMAP builds for those chips?
233 */
234static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
235{
236 unsigned long fint, clkinp; /* watch out for overflow */
237
238 clkinp = clk->parent->rate;
239 fint = (clkinp / n) * m;
240
241 if (fint < 1000000000)
242 *dco = 2;
243 else
244 *dco = 4;
245}
246
247/**
248 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
249 * @clk: pointer to a DPLL struct clk
250 * @sd_div: target sigma-delta divider
251 * @m: DPLL multiplier to set
252 * @n: DPLL divider to set
253 *
254 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
255 *
256 * XXX This code is not needed for 3430/AM35xx; can it be optimized
257 * out in non-multi-OMAP builds for those chips?
258 */
259static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
260{
261 unsigned long clkinp, sd; /* watch out for overflow */
262 int mod1, mod2;
263
264 clkinp = clk->parent->rate;
265
266 /*
267 * target sigma-delta to near 250MHz
268 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
269 */
270 clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
271 mod1 = (clkinp * m) % (250 * n);
272 sd = (clkinp * m) / (250 * n);
273 mod2 = sd % 10;
274 sd /= 10;
275
276 if (mod1 || mod2)
277 sd++;
278 *sd_div = sd;
279}
280
281/*
282 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
283 * @clk: struct clk * of DPLL to set
284 * @m: DPLL multiplier to set
285 * @n: DPLL divider to set
286 * @freqsel: FREQSEL value to set
287 *
288 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
289 * lock.. Returns -EINVAL upon error, or 0 upon success.
290 */
291static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
292{
293 struct dpll_data *dd = clk->dpll_data;
294 u8 dco, sd_div;
295 u32 v;
296
297 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
298 _omap3_noncore_dpll_bypass(clk);
299
300 /*
301 * Set jitter correction. No jitter correction for OMAP4 and 3630
302 * since freqsel field is no longer present
303 */
304 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
305 v = __raw_readl(dd->control_reg);
306 v &= ~dd->freqsel_mask;
307 v |= freqsel << __ffs(dd->freqsel_mask);
308 __raw_writel(v, dd->control_reg);
309 }
310
311 /* Set DPLL multiplier, divider */
312 v = __raw_readl(dd->mult_div1_reg);
313 v &= ~(dd->mult_mask | dd->div1_mask);
314 v |= m << __ffs(dd->mult_mask);
315 v |= (n - 1) << __ffs(dd->div1_mask);
316
317 /* Configure dco and sd_div for dplls that have these fields */
318 if (dd->dco_mask) {
319 _lookup_dco(clk, &dco, m, n);
320 v &= ~(dd->dco_mask);
321 v |= dco << __ffs(dd->dco_mask);
322 }
323 if (dd->sddiv_mask) {
324 _lookup_sddiv(clk, &sd_div, m, n);
325 v &= ~(dd->sddiv_mask);
326 v |= sd_div << __ffs(dd->sddiv_mask);
327 }
328
329 __raw_writel(v, dd->mult_div1_reg);
330
331 /* We let the clock framework set the other output dividers later */
332
333 /* REVISIT: Set ramp-up delay? */
334
335 _omap3_noncore_dpll_lock(clk);
336
337 return 0;
338}
339
340/* Public functions */
341
342/**
343 * omap3_dpll_recalc - recalculate DPLL rate
344 * @clk: DPLL struct clk
345 *
346 * Recalculate and propagate the DPLL rate.
347 */
348unsigned long omap3_dpll_recalc(struct clk *clk)
349{
350 return omap2_get_dpll_rate(clk);
351}
352
353/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
354
355/**
356 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
357 * @clk: pointer to a DPLL struct clk
358 *
359 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
360 * The choice of modes depends on the DPLL's programmed rate: if it is
361 * the same as the DPLL's parent clock, it will enter bypass;
362 * otherwise, it will enter lock. This code will wait for the DPLL to
363 * indicate readiness before returning, unless the DPLL takes too long
364 * to enter the target state. Intended to be used as the struct clk's
365 * enable function. If DPLL3 was passed in, or the DPLL does not
366 * support low-power stop, or if the DPLL took too long to enter
367 * bypass or lock, return -EINVAL; otherwise, return 0.
368 */
369int omap3_noncore_dpll_enable(struct clk *clk)
370{
371 int r;
372 struct dpll_data *dd;
373
374 dd = clk->dpll_data;
375 if (!dd)
376 return -EINVAL;
377
378 if (clk->rate == dd->clk_bypass->rate) {
379 WARN_ON(clk->parent != dd->clk_bypass);
380 r = _omap3_noncore_dpll_bypass(clk);
381 } else {
382 WARN_ON(clk->parent != dd->clk_ref);
383 r = _omap3_noncore_dpll_lock(clk);
384 }
385 /*
386 *FIXME: this is dubious - if clk->rate has changed, what about
387 * propagating?
388 */
389 if (!r)
390 clk->rate = (clk->recalc) ? clk->recalc(clk) :
391 omap2_get_dpll_rate(clk);
392
393 return r;
394}
395
396/**
397 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
398 * @clk: pointer to a DPLL struct clk
399 *
400 * Instructs a non-CORE DPLL to enter low-power stop. This function is
401 * intended for use in struct clkops. No return value.
402 */
403void omap3_noncore_dpll_disable(struct clk *clk)
404{
405 _omap3_noncore_dpll_stop(clk);
406}
407
408
409/* Non-CORE DPLL rate set code */
410
411/**
412 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
413 * @clk: struct clk * of DPLL to set
414 * @rate: rounded target rate
415 *
416 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
417 * low-power bypass, and the target rate is the bypass source clock
418 * rate, then configure the DPLL for bypass. Otherwise, round the
419 * target rate if it hasn't been done already, then program and lock
420 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
421 */
422int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
423{
424 struct clk *new_parent = NULL;
425 unsigned long hw_rate;
426 u16 freqsel = 0;
427 struct dpll_data *dd;
428 int ret;
429
430 if (!clk || !rate)
431 return -EINVAL;
432
433 dd = clk->dpll_data;
434 if (!dd)
435 return -EINVAL;
436
437 hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
438 if (rate == hw_rate)
439 return 0;
440
441 /*
442 * Ensure both the bypass and ref clocks are enabled prior to
443 * doing anything; we need the bypass clock running to reprogram
444 * the DPLL.
445 */
446 omap2_clk_enable(dd->clk_bypass);
447 omap2_clk_enable(dd->clk_ref);
448
449 if (dd->clk_bypass->rate == rate &&
450 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
451 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
452
453 ret = _omap3_noncore_dpll_bypass(clk);
454 if (!ret)
455 new_parent = dd->clk_bypass;
456 } else {
457 if (dd->last_rounded_rate != rate)
458 rate = clk->round_rate(clk, rate);
459
460 if (dd->last_rounded_rate == 0)
461 return -EINVAL;
462
463 /* No freqsel on OMAP4 and OMAP3630 */
464 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
465 freqsel = _omap3_dpll_compute_freqsel(clk,
466 dd->last_rounded_n);
467 if (!freqsel)
468 WARN_ON(1);
469 }
470
471 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
472 clk->name, rate);
473
474 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
475 dd->last_rounded_n, freqsel);
476 if (!ret)
477 new_parent = dd->clk_ref;
478 }
479 if (!ret) {
480 /*
481 * Switch the parent clock in the hierarchy, and make sure
482 * that the new parent's usecount is correct. Note: we
483 * enable the new parent before disabling the old to avoid
484 * any unnecessary hardware disable->enable transitions.
485 */
486 if (clk->usecount) {
487 omap2_clk_enable(new_parent);
488 omap2_clk_disable(clk->parent);
489 }
490 clk_reparent(clk, new_parent);
491 clk->rate = rate;
492 }
493 omap2_clk_disable(dd->clk_ref);
494 omap2_clk_disable(dd->clk_bypass);
495
496 return 0;
497}
498
499/* DPLL autoidle read/set code */
500
501/**
502 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
503 * @clk: struct clk * of the DPLL to read
504 *
505 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
506 * -EINVAL if passed a null pointer or if the struct clk does not
507 * appear to refer to a DPLL.
508 */
509u32 omap3_dpll_autoidle_read(struct clk *clk)
510{
511 const struct dpll_data *dd;
512 u32 v;
513
514 if (!clk || !clk->dpll_data)
515 return -EINVAL;
516
517 dd = clk->dpll_data;
518
519 if (!dd->autoidle_reg)
520 return -EINVAL;
521
522 v = __raw_readl(dd->autoidle_reg);
523 v &= dd->autoidle_mask;
524 v >>= __ffs(dd->autoidle_mask);
525
526 return v;
527}
528
529/**
530 * omap3_dpll_allow_idle - enable DPLL autoidle bits
531 * @clk: struct clk * of the DPLL to operate on
532 *
533 * Enable DPLL automatic idle control. This automatic idle mode
534 * switching takes effect only when the DPLL is locked, at least on
535 * OMAP3430. The DPLL will enter low-power stop when its downstream
536 * clocks are gated. No return value.
537 */
538void omap3_dpll_allow_idle(struct clk *clk)
539{
540 const struct dpll_data *dd;
541 u32 v;
542
543 if (!clk || !clk->dpll_data)
544 return;
545
546 dd = clk->dpll_data;
547
548 if (!dd->autoidle_reg) {
549 pr_debug("clock: DPLL %s: autoidle not supported\n",
550 clk->name);
551 return;
552 }
553
554 /*
555 * REVISIT: CORE DPLL can optionally enter low-power bypass
556 * by writing 0x5 instead of 0x1. Add some mechanism to
557 * optionally enter this mode.
558 */
559 v = __raw_readl(dd->autoidle_reg);
560 v &= ~dd->autoidle_mask;
561 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
562 __raw_writel(v, dd->autoidle_reg);
563
564}
565
566/**
567 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
568 * @clk: struct clk * of the DPLL to operate on
569 *
570 * Disable DPLL automatic idle control. No return value.
571 */
572void omap3_dpll_deny_idle(struct clk *clk)
573{
574 const struct dpll_data *dd;
575 u32 v;
576
577 if (!clk || !clk->dpll_data)
578 return;
579
580 dd = clk->dpll_data;
581
582 if (!dd->autoidle_reg) {
583 pr_debug("clock: DPLL %s: autoidle not supported\n",
584 clk->name);
585 return;
586 }
587
588 v = __raw_readl(dd->autoidle_reg);
589 v &= ~dd->autoidle_mask;
590 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
591 __raw_writel(v, dd->autoidle_reg);
592
593}
594
595/* Clock control for DPLL outputs */
596
597/**
598 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
599 * @clk: DPLL output struct clk
600 *
601 * Using parent clock DPLL data, look up DPLL state. If locked, set our
602 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
603 */
604unsigned long omap3_clkoutx2_recalc(struct clk *clk)
605{
606 const struct dpll_data *dd;
607 unsigned long rate;
608 u32 v;
609 struct clk *pclk;
610
611 /* Walk up the parents of clk, looking for a DPLL */
612 pclk = clk->parent;
613 while (pclk && !pclk->dpll_data)
614 pclk = pclk->parent;
615
616 /* clk does not have a DPLL as a parent? */
617 WARN_ON(!pclk);
618
619 dd = pclk->dpll_data;
620
621 WARN_ON(!dd->enable_mask);
622
623 v = __raw_readl(dd->control_reg) & dd->enable_mask;
624 v >>= __ffs(dd->enable_mask);
625 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
626 rate = clk->parent->rate;
627 else
628 rate = clk->parent->rate * 2;
629 return rate;
630}