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1/*
2 * OMAP4 CPU idle Routines
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Rajendra Nayak <rnayak@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/sched.h>
14#include <linux/cpuidle.h>
15#include <linux/cpu_pm.h>
16#include <linux/export.h>
17#include <linux/clockchips.h>
18
19#include <asm/proc-fns.h>
20
21#include "common.h"
22#include "pm.h"
23#include "prm.h"
24
25#ifdef CONFIG_CPU_IDLE
26
27/* Machine specific information */
28struct omap4_idle_statedata {
29 u32 cpu_state;
30 u32 mpu_logic_state;
31 u32 mpu_state;
32};
33
34static struct omap4_idle_statedata omap4_idle_data[] = {
35 {
36 .cpu_state = PWRDM_POWER_ON,
37 .mpu_state = PWRDM_POWER_ON,
38 .mpu_logic_state = PWRDM_POWER_RET,
39 },
40 {
41 .cpu_state = PWRDM_POWER_OFF,
42 .mpu_state = PWRDM_POWER_RET,
43 .mpu_logic_state = PWRDM_POWER_RET,
44 },
45 {
46 .cpu_state = PWRDM_POWER_OFF,
47 .mpu_state = PWRDM_POWER_RET,
48 .mpu_logic_state = PWRDM_POWER_OFF,
49 },
50};
51
52static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
53
54/**
55 * omap4_enter_idle - Programs OMAP4 to enter the specified state
56 * @dev: cpuidle device
57 * @drv: cpuidle driver
58 * @index: the index of state to be entered
59 *
60 * Called from the CPUidle framework to program the device to the
61 * specified low power state selected by the governor.
62 * Returns the amount of time spent in the low power state.
63 */
64static int omap4_enter_idle(struct cpuidle_device *dev,
65 struct cpuidle_driver *drv,
66 int index)
67{
68 struct omap4_idle_statedata *cx = &omap4_idle_data[index];
69 u32 cpu1_state;
70 int cpu_id = smp_processor_id();
71
72 local_fiq_disable();
73
74 /*
75 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
76 * This is necessary to honour hardware recommondation
77 * of triggeing all the possible low power modes once CPU1 is
78 * out of coherency and in OFF mode.
79 * Update dev->last_state so that governor stats reflects right
80 * data.
81 */
82 cpu1_state = pwrdm_read_pwrst(cpu1_pd);
83 if (cpu1_state != PWRDM_POWER_OFF) {
84 index = drv->safe_state_index;
85 cx = &omap4_idle_data[index];
86 }
87
88 if (index > 0)
89 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
90
91 /*
92 * Call idle CPU PM enter notifier chain so that
93 * VFP and per CPU interrupt context is saved.
94 */
95 if (cx->cpu_state == PWRDM_POWER_OFF)
96 cpu_pm_enter();
97
98 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
99 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
100
101 /*
102 * Call idle CPU cluster PM enter notifier chain
103 * to save GIC and wakeupgen context.
104 */
105 if ((cx->mpu_state == PWRDM_POWER_RET) &&
106 (cx->mpu_logic_state == PWRDM_POWER_OFF))
107 cpu_cluster_pm_enter();
108
109 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
110
111 /*
112 * Call idle CPU PM exit notifier chain to restore
113 * VFP and per CPU IRQ context. Only CPU0 state is
114 * considered since CPU1 is managed by CPU hotplug.
115 */
116 if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
117 cpu_pm_exit();
118
119 /*
120 * Call idle CPU cluster PM exit notifier chain
121 * to restore GIC and wakeupgen context.
122 */
123 if (omap4_mpuss_read_prev_context_state())
124 cpu_cluster_pm_exit();
125
126 if (index > 0)
127 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
128
129 local_fiq_enable();
130
131 return index;
132}
133
134DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
135
136struct cpuidle_driver omap4_idle_driver = {
137 .name = "omap4_idle",
138 .owner = THIS_MODULE,
139 .en_core_tk_irqen = 1,
140 .states = {
141 {
142 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
143 .exit_latency = 2 + 2,
144 .target_residency = 5,
145 .flags = CPUIDLE_FLAG_TIME_VALID,
146 .enter = omap4_enter_idle,
147 .name = "C1",
148 .desc = "MPUSS ON"
149 },
150 {
151 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
152 .exit_latency = 328 + 440,
153 .target_residency = 960,
154 .flags = CPUIDLE_FLAG_TIME_VALID,
155 .enter = omap4_enter_idle,
156 .name = "C2",
157 .desc = "MPUSS CSWR",
158 },
159 {
160 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
161 .exit_latency = 460 + 518,
162 .target_residency = 1100,
163 .flags = CPUIDLE_FLAG_TIME_VALID,
164 .enter = omap4_enter_idle,
165 .name = "C3",
166 .desc = "MPUSS OSWR",
167 },
168 },
169 .state_count = ARRAY_SIZE(omap4_idle_data),
170 .safe_state_index = 0,
171};
172
173/**
174 * omap4_idle_init - Init routine for OMAP4 idle
175 *
176 * Registers the OMAP4 specific cpuidle driver to the cpuidle
177 * framework with the valid set of states.
178 */
179int __init omap4_idle_init(void)
180{
181 struct cpuidle_device *dev;
182 unsigned int cpu_id = 0;
183
184 mpu_pd = pwrdm_lookup("mpu_pwrdm");
185 cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
186 cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
187 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
188 return -ENODEV;
189
190 dev = &per_cpu(omap4_idle_dev, cpu_id);
191 dev->cpu = cpu_id;
192
193 cpuidle_register_driver(&omap4_idle_driver);
194
195 if (cpuidle_register_device(dev)) {
196 pr_err("%s: CPUidle register device failed\n", __func__);
197 return -EIO;
198 }
199
200 return 0;
201}
202#else
203int __init omap4_idle_init(void)
204{
205 return 0;
206}
207#endif /* CONFIG_CPU_IDLE */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * OMAP4+ CPU idle Routines
4 *
5 * Copyright (C) 2011-2013 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Rajendra Nayak <rnayak@ti.com>
8 */
9
10#include <linux/sched.h>
11#include <linux/cpuidle.h>
12#include <linux/cpu_pm.h>
13#include <linux/export.h>
14#include <linux/tick.h>
15
16#include <asm/cpuidle.h>
17
18#include "common.h"
19#include "pm.h"
20#include "prm.h"
21#include "soc.h"
22#include "clockdomain.h"
23
24#define MAX_CPUS 2
25
26/* Machine specific information */
27struct idle_statedata {
28 u32 cpu_state;
29 u32 mpu_logic_state;
30 u32 mpu_state;
31 u32 mpu_state_vote;
32};
33
34static struct idle_statedata omap4_idle_data[] = {
35 {
36 .cpu_state = PWRDM_POWER_ON,
37 .mpu_state = PWRDM_POWER_ON,
38 .mpu_logic_state = PWRDM_POWER_RET,
39 },
40 {
41 .cpu_state = PWRDM_POWER_OFF,
42 .mpu_state = PWRDM_POWER_RET,
43 .mpu_logic_state = PWRDM_POWER_RET,
44 },
45 {
46 .cpu_state = PWRDM_POWER_OFF,
47 .mpu_state = PWRDM_POWER_RET,
48 .mpu_logic_state = PWRDM_POWER_OFF,
49 },
50};
51
52static struct idle_statedata omap5_idle_data[] = {
53 {
54 .cpu_state = PWRDM_POWER_ON,
55 .mpu_state = PWRDM_POWER_ON,
56 .mpu_logic_state = PWRDM_POWER_ON,
57 },
58 {
59 .cpu_state = PWRDM_POWER_RET,
60 .mpu_state = PWRDM_POWER_RET,
61 .mpu_logic_state = PWRDM_POWER_RET,
62 },
63};
64
65static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
66static struct clockdomain *cpu_clkdm[MAX_CPUS];
67
68static atomic_t abort_barrier;
69static bool cpu_done[MAX_CPUS];
70static struct idle_statedata *state_ptr = &omap4_idle_data[0];
71static DEFINE_RAW_SPINLOCK(mpu_lock);
72
73/* Private functions */
74
75/**
76 * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
77 * @dev: cpuidle device
78 * @drv: cpuidle driver
79 * @index: the index of state to be entered
80 *
81 * Called from the CPUidle framework to program the device to the
82 * specified low power state selected by the governor.
83 * Returns the amount of time spent in the low power state.
84 */
85static int omap_enter_idle_simple(struct cpuidle_device *dev,
86 struct cpuidle_driver *drv,
87 int index)
88{
89 omap_do_wfi();
90 return index;
91}
92
93static int omap_enter_idle_smp(struct cpuidle_device *dev,
94 struct cpuidle_driver *drv,
95 int index)
96{
97 struct idle_statedata *cx = state_ptr + index;
98 unsigned long flag;
99
100 raw_spin_lock_irqsave(&mpu_lock, flag);
101 cx->mpu_state_vote++;
102 if (cx->mpu_state_vote == num_online_cpus()) {
103 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
104 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
105 }
106 raw_spin_unlock_irqrestore(&mpu_lock, flag);
107
108 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
109
110 raw_spin_lock_irqsave(&mpu_lock, flag);
111 if (cx->mpu_state_vote == num_online_cpus())
112 omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
113 cx->mpu_state_vote--;
114 raw_spin_unlock_irqrestore(&mpu_lock, flag);
115
116 return index;
117}
118
119static int omap_enter_idle_coupled(struct cpuidle_device *dev,
120 struct cpuidle_driver *drv,
121 int index)
122{
123 struct idle_statedata *cx = state_ptr + index;
124 u32 mpuss_can_lose_context = 0;
125 int error;
126
127 /*
128 * CPU0 has to wait and stay ON until CPU1 is OFF state.
129 * This is necessary to honour hardware recommondation
130 * of triggeing all the possible low power modes once CPU1 is
131 * out of coherency and in OFF mode.
132 */
133 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
134 while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
135 cpu_relax();
136
137 /*
138 * CPU1 could have already entered & exited idle
139 * without hitting off because of a wakeup
140 * or a failed attempt to hit off mode. Check for
141 * that here, otherwise we could spin forever
142 * waiting for CPU1 off.
143 */
144 if (cpu_done[1])
145 goto fail;
146
147 }
148 }
149
150 mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
151 (cx->mpu_logic_state == PWRDM_POWER_OFF);
152
153 /* Enter broadcast mode for periodic timers */
154 RCU_NONIDLE(tick_broadcast_enable());
155
156 /* Enter broadcast mode for one-shot timers */
157 RCU_NONIDLE(tick_broadcast_enter());
158
159 /*
160 * Call idle CPU PM enter notifier chain so that
161 * VFP and per CPU interrupt context is saved.
162 */
163 error = cpu_pm_enter();
164 if (error)
165 goto cpu_pm_out;
166
167 if (dev->cpu == 0) {
168 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
169 RCU_NONIDLE(omap_set_pwrdm_state(mpu_pd, cx->mpu_state));
170
171 /*
172 * Call idle CPU cluster PM enter notifier chain
173 * to save GIC and wakeupgen context.
174 */
175 if (mpuss_can_lose_context) {
176 error = cpu_cluster_pm_enter();
177 if (error) {
178 index = 0;
179 cx = state_ptr + index;
180 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
181 RCU_NONIDLE(omap_set_pwrdm_state(mpu_pd, cx->mpu_state));
182 mpuss_can_lose_context = 0;
183 }
184 }
185 }
186
187 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
188 cpu_done[dev->cpu] = true;
189
190 /* Wakeup CPU1 only if it is not offlined */
191 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
192
193 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
194 mpuss_can_lose_context)
195 gic_dist_disable();
196
197 RCU_NONIDLE(clkdm_deny_idle(cpu_clkdm[1]));
198 RCU_NONIDLE(omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON));
199 RCU_NONIDLE(clkdm_allow_idle(cpu_clkdm[1]));
200
201 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
202 mpuss_can_lose_context) {
203 while (gic_dist_disabled()) {
204 udelay(1);
205 cpu_relax();
206 }
207 gic_timer_retrigger();
208 }
209 }
210
211 /*
212 * Call idle CPU cluster PM exit notifier chain
213 * to restore GIC and wakeupgen context.
214 */
215 if (dev->cpu == 0 && mpuss_can_lose_context)
216 cpu_cluster_pm_exit();
217
218 /*
219 * Call idle CPU PM exit notifier chain to restore
220 * VFP and per CPU IRQ context.
221 */
222 cpu_pm_exit();
223
224cpu_pm_out:
225 RCU_NONIDLE(tick_broadcast_exit());
226
227fail:
228 cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
229 cpu_done[dev->cpu] = false;
230
231 return index;
232}
233
234static struct cpuidle_driver omap4_idle_driver = {
235 .name = "omap4_idle",
236 .owner = THIS_MODULE,
237 .states = {
238 {
239 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
240 .exit_latency = 2 + 2,
241 .target_residency = 5,
242 .enter = omap_enter_idle_simple,
243 .name = "C1",
244 .desc = "CPUx ON, MPUSS ON"
245 },
246 {
247 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
248 .exit_latency = 328 + 440,
249 .target_residency = 960,
250 .flags = CPUIDLE_FLAG_COUPLED,
251 .enter = omap_enter_idle_coupled,
252 .name = "C2",
253 .desc = "CPUx OFF, MPUSS CSWR",
254 },
255 {
256 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
257 .exit_latency = 460 + 518,
258 .target_residency = 1100,
259 .flags = CPUIDLE_FLAG_COUPLED,
260 .enter = omap_enter_idle_coupled,
261 .name = "C3",
262 .desc = "CPUx OFF, MPUSS OSWR",
263 },
264 },
265 .state_count = ARRAY_SIZE(omap4_idle_data),
266 .safe_state_index = 0,
267};
268
269static struct cpuidle_driver omap5_idle_driver = {
270 .name = "omap5_idle",
271 .owner = THIS_MODULE,
272 .states = {
273 {
274 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
275 .exit_latency = 2 + 2,
276 .target_residency = 5,
277 .enter = omap_enter_idle_simple,
278 .name = "C1",
279 .desc = "CPUx WFI, MPUSS ON"
280 },
281 {
282 /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
283 .exit_latency = 48 + 60,
284 .target_residency = 100,
285 .flags = CPUIDLE_FLAG_TIMER_STOP,
286 .enter = omap_enter_idle_smp,
287 .name = "C2",
288 .desc = "CPUx CSWR, MPUSS CSWR",
289 },
290 },
291 .state_count = ARRAY_SIZE(omap5_idle_data),
292 .safe_state_index = 0,
293};
294
295/* Public functions */
296
297/**
298 * omap4_idle_init - Init routine for OMAP4+ idle
299 *
300 * Registers the OMAP4+ specific cpuidle driver to the cpuidle
301 * framework with the valid set of states.
302 */
303int __init omap4_idle_init(void)
304{
305 struct cpuidle_driver *idle_driver;
306
307 if (soc_is_omap54xx()) {
308 state_ptr = &omap5_idle_data[0];
309 idle_driver = &omap5_idle_driver;
310 } else {
311 state_ptr = &omap4_idle_data[0];
312 idle_driver = &omap4_idle_driver;
313 }
314
315 mpu_pd = pwrdm_lookup("mpu_pwrdm");
316 cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
317 cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
318 if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
319 return -ENODEV;
320
321 cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
322 cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
323 if (!cpu_clkdm[0] || !cpu_clkdm[1])
324 return -ENODEV;
325
326 return cpuidle_register(idle_driver, cpu_online_mask);
327}