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1/*
2 * ARMv6 Performance counter handling code.
3 *
4 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
5 *
6 * ARMv6 has 2 configurable performance counters and a single cycle counter.
7 * They all share a single reset bit but can be written to zero so we can use
8 * that for a reset.
9 *
10 * The counters can't be individually enabled or disabled so when we remove
11 * one event and replace it with another we could get spurious counts from the
12 * wrong event. However, we can take advantage of the fact that the
13 * performance counters can export events to the event bus, and the event bus
14 * itself can be monitored. This requires that we *don't* export the events to
15 * the event bus. The procedure for disabling a configurable counter is:
16 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
17 * effectively stops the counter from counting.
18 * - disable the counter's interrupt generation (each counter has it's
19 * own interrupt enable bit).
20 * Once stopped, the counter value can be written as 0 to reset.
21 *
22 * To enable a counter:
23 * - enable the counter's interrupt generation.
24 * - set the new event type.
25 *
26 * Note: the dedicated cycle counter only counts cycles and can't be
27 * enabled/disabled independently of the others. When we want to disable the
28 * cycle counter, we have to just disable the interrupt reporting and start
29 * ignoring that counter. When re-enabling, we have to reset the value and
30 * enable the interrupt.
31 */
32
33#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
34enum armv6_perf_types {
35 ARMV6_PERFCTR_ICACHE_MISS = 0x0,
36 ARMV6_PERFCTR_IBUF_STALL = 0x1,
37 ARMV6_PERFCTR_DDEP_STALL = 0x2,
38 ARMV6_PERFCTR_ITLB_MISS = 0x3,
39 ARMV6_PERFCTR_DTLB_MISS = 0x4,
40 ARMV6_PERFCTR_BR_EXEC = 0x5,
41 ARMV6_PERFCTR_BR_MISPREDICT = 0x6,
42 ARMV6_PERFCTR_INSTR_EXEC = 0x7,
43 ARMV6_PERFCTR_DCACHE_HIT = 0x9,
44 ARMV6_PERFCTR_DCACHE_ACCESS = 0xA,
45 ARMV6_PERFCTR_DCACHE_MISS = 0xB,
46 ARMV6_PERFCTR_DCACHE_WBACK = 0xC,
47 ARMV6_PERFCTR_SW_PC_CHANGE = 0xD,
48 ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF,
49 ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10,
50 ARMV6_PERFCTR_LSU_FULL_STALL = 0x11,
51 ARMV6_PERFCTR_WBUF_DRAINED = 0x12,
52 ARMV6_PERFCTR_CPU_CYCLES = 0xFF,
53 ARMV6_PERFCTR_NOP = 0x20,
54};
55
56enum armv6_counters {
57 ARMV6_CYCLE_COUNTER = 0,
58 ARMV6_COUNTER0,
59 ARMV6_COUNTER1,
60};
61
62/*
63 * The hardware events that we support. We do support cache operations but
64 * we have harvard caches and no way to combine instruction and data
65 * accesses/misses in hardware.
66 */
67static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
68 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
69 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
70 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
71 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
72 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
73 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
74 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
75 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
76 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL,
77};
78
79static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
80 [PERF_COUNT_HW_CACHE_OP_MAX]
81 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
82 [C(L1D)] = {
83 /*
84 * The performance counters don't differentiate between read
85 * and write accesses/misses so this isn't strictly correct,
86 * but it's the best we can do. Writes and reads get
87 * combined.
88 */
89 [C(OP_READ)] = {
90 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
91 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
92 },
93 [C(OP_WRITE)] = {
94 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
95 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
96 },
97 [C(OP_PREFETCH)] = {
98 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
99 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
100 },
101 },
102 [C(L1I)] = {
103 [C(OP_READ)] = {
104 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
105 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
106 },
107 [C(OP_WRITE)] = {
108 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
109 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
110 },
111 [C(OP_PREFETCH)] = {
112 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
113 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
114 },
115 },
116 [C(LL)] = {
117 [C(OP_READ)] = {
118 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
119 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
120 },
121 [C(OP_WRITE)] = {
122 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
123 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
124 },
125 [C(OP_PREFETCH)] = {
126 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
127 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
128 },
129 },
130 [C(DTLB)] = {
131 /*
132 * The ARM performance counters can count micro DTLB misses,
133 * micro ITLB misses and main TLB misses. There isn't an event
134 * for TLB misses, so use the micro misses here and if users
135 * want the main TLB misses they can use a raw counter.
136 */
137 [C(OP_READ)] = {
138 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
139 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
140 },
141 [C(OP_WRITE)] = {
142 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
143 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
144 },
145 [C(OP_PREFETCH)] = {
146 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
147 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
148 },
149 },
150 [C(ITLB)] = {
151 [C(OP_READ)] = {
152 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
153 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
154 },
155 [C(OP_WRITE)] = {
156 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
157 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
158 },
159 [C(OP_PREFETCH)] = {
160 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
161 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
162 },
163 },
164 [C(BPU)] = {
165 [C(OP_READ)] = {
166 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
167 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
168 },
169 [C(OP_WRITE)] = {
170 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
171 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
172 },
173 [C(OP_PREFETCH)] = {
174 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
175 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
176 },
177 },
178 [C(NODE)] = {
179 [C(OP_READ)] = {
180 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
181 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
182 },
183 [C(OP_WRITE)] = {
184 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
185 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
186 },
187 [C(OP_PREFETCH)] = {
188 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
189 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
190 },
191 },
192};
193
194enum armv6mpcore_perf_types {
195 ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
196 ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
197 ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
198 ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
199 ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
200 ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
201 ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
202 ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
203 ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
204 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
205 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
206 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
207 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
208 ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
209 ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
210 ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
211 ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
212 ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
213 ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
214 ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
215};
216
217/*
218 * The hardware events that we support. We do support cache operations but
219 * we have harvard caches and no way to combine instruction and data
220 * accesses/misses in hardware.
221 */
222static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
223 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
224 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
225 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
226 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
227 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
228 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
229 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
230 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
231 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
232};
233
234static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
235 [PERF_COUNT_HW_CACHE_OP_MAX]
236 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
237 [C(L1D)] = {
238 [C(OP_READ)] = {
239 [C(RESULT_ACCESS)] =
240 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
241 [C(RESULT_MISS)] =
242 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
243 },
244 [C(OP_WRITE)] = {
245 [C(RESULT_ACCESS)] =
246 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
247 [C(RESULT_MISS)] =
248 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
249 },
250 [C(OP_PREFETCH)] = {
251 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
252 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
253 },
254 },
255 [C(L1I)] = {
256 [C(OP_READ)] = {
257 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
258 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
259 },
260 [C(OP_WRITE)] = {
261 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
262 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
263 },
264 [C(OP_PREFETCH)] = {
265 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
266 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
267 },
268 },
269 [C(LL)] = {
270 [C(OP_READ)] = {
271 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
272 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
273 },
274 [C(OP_WRITE)] = {
275 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
276 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
277 },
278 [C(OP_PREFETCH)] = {
279 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
280 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
281 },
282 },
283 [C(DTLB)] = {
284 /*
285 * The ARM performance counters can count micro DTLB misses,
286 * micro ITLB misses and main TLB misses. There isn't an event
287 * for TLB misses, so use the micro misses here and if users
288 * want the main TLB misses they can use a raw counter.
289 */
290 [C(OP_READ)] = {
291 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
292 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
293 },
294 [C(OP_WRITE)] = {
295 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
296 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
297 },
298 [C(OP_PREFETCH)] = {
299 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
300 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
301 },
302 },
303 [C(ITLB)] = {
304 [C(OP_READ)] = {
305 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
306 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
307 },
308 [C(OP_WRITE)] = {
309 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
310 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
311 },
312 [C(OP_PREFETCH)] = {
313 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
314 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
315 },
316 },
317 [C(BPU)] = {
318 [C(OP_READ)] = {
319 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
320 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
321 },
322 [C(OP_WRITE)] = {
323 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
324 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
325 },
326 [C(OP_PREFETCH)] = {
327 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
328 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
329 },
330 },
331 [C(NODE)] = {
332 [C(OP_READ)] = {
333 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
334 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
335 },
336 [C(OP_WRITE)] = {
337 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
338 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
339 },
340 [C(OP_PREFETCH)] = {
341 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
342 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
343 },
344 },
345};
346
347static inline unsigned long
348armv6_pmcr_read(void)
349{
350 u32 val;
351 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));
352 return val;
353}
354
355static inline void
356armv6_pmcr_write(unsigned long val)
357{
358 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val));
359}
360
361#define ARMV6_PMCR_ENABLE (1 << 0)
362#define ARMV6_PMCR_CTR01_RESET (1 << 1)
363#define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
364#define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
365#define ARMV6_PMCR_COUNT0_IEN (1 << 4)
366#define ARMV6_PMCR_COUNT1_IEN (1 << 5)
367#define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
368#define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
369#define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
370#define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
371#define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
372#define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
373#define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
374#define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
375
376#define ARMV6_PMCR_OVERFLOWED_MASK \
377 (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
378 ARMV6_PMCR_CCOUNT_OVERFLOW)
379
380static inline int
381armv6_pmcr_has_overflowed(unsigned long pmcr)
382{
383 return pmcr & ARMV6_PMCR_OVERFLOWED_MASK;
384}
385
386static inline int
387armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
388 enum armv6_counters counter)
389{
390 int ret = 0;
391
392 if (ARMV6_CYCLE_COUNTER == counter)
393 ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
394 else if (ARMV6_COUNTER0 == counter)
395 ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
396 else if (ARMV6_COUNTER1 == counter)
397 ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
398 else
399 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
400
401 return ret;
402}
403
404static inline u32
405armv6pmu_read_counter(int counter)
406{
407 unsigned long value = 0;
408
409 if (ARMV6_CYCLE_COUNTER == counter)
410 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value));
411 else if (ARMV6_COUNTER0 == counter)
412 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value));
413 else if (ARMV6_COUNTER1 == counter)
414 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value));
415 else
416 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
417
418 return value;
419}
420
421static inline void
422armv6pmu_write_counter(int counter,
423 u32 value)
424{
425 if (ARMV6_CYCLE_COUNTER == counter)
426 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
427 else if (ARMV6_COUNTER0 == counter)
428 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value));
429 else if (ARMV6_COUNTER1 == counter)
430 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value));
431 else
432 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
433}
434
435static void
436armv6pmu_enable_event(struct hw_perf_event *hwc,
437 int idx)
438{
439 unsigned long val, mask, evt, flags;
440 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
441
442 if (ARMV6_CYCLE_COUNTER == idx) {
443 mask = 0;
444 evt = ARMV6_PMCR_CCOUNT_IEN;
445 } else if (ARMV6_COUNTER0 == idx) {
446 mask = ARMV6_PMCR_EVT_COUNT0_MASK;
447 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
448 ARMV6_PMCR_COUNT0_IEN;
449 } else if (ARMV6_COUNTER1 == idx) {
450 mask = ARMV6_PMCR_EVT_COUNT1_MASK;
451 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
452 ARMV6_PMCR_COUNT1_IEN;
453 } else {
454 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
455 return;
456 }
457
458 /*
459 * Mask out the current event and set the counter to count the event
460 * that we're interested in.
461 */
462 raw_spin_lock_irqsave(&events->pmu_lock, flags);
463 val = armv6_pmcr_read();
464 val &= ~mask;
465 val |= evt;
466 armv6_pmcr_write(val);
467 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
468}
469
470static irqreturn_t
471armv6pmu_handle_irq(int irq_num,
472 void *dev)
473{
474 unsigned long pmcr = armv6_pmcr_read();
475 struct perf_sample_data data;
476 struct pmu_hw_events *cpuc;
477 struct pt_regs *regs;
478 int idx;
479
480 if (!armv6_pmcr_has_overflowed(pmcr))
481 return IRQ_NONE;
482
483 regs = get_irq_regs();
484
485 /*
486 * The interrupts are cleared by writing the overflow flags back to
487 * the control register. All of the other bits don't have any effect
488 * if they are rewritten, so write the whole value back.
489 */
490 armv6_pmcr_write(pmcr);
491
492 cpuc = &__get_cpu_var(cpu_hw_events);
493 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
494 struct perf_event *event = cpuc->events[idx];
495 struct hw_perf_event *hwc;
496
497 /* Ignore if we don't have an event. */
498 if (!event)
499 continue;
500
501 /*
502 * We have a single interrupt for all counters. Check that
503 * each counter has overflowed before we process it.
504 */
505 if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
506 continue;
507
508 hwc = &event->hw;
509 armpmu_event_update(event, hwc, idx);
510 perf_sample_data_init(&data, 0, hwc->last_period);
511 if (!armpmu_event_set_period(event, hwc, idx))
512 continue;
513
514 if (perf_event_overflow(event, &data, regs))
515 cpu_pmu->disable(hwc, idx);
516 }
517
518 /*
519 * Handle the pending perf events.
520 *
521 * Note: this call *must* be run with interrupts disabled. For
522 * platforms that can have the PMU interrupts raised as an NMI, this
523 * will not work.
524 */
525 irq_work_run();
526
527 return IRQ_HANDLED;
528}
529
530static void
531armv6pmu_start(void)
532{
533 unsigned long flags, val;
534 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
535
536 raw_spin_lock_irqsave(&events->pmu_lock, flags);
537 val = armv6_pmcr_read();
538 val |= ARMV6_PMCR_ENABLE;
539 armv6_pmcr_write(val);
540 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
541}
542
543static void
544armv6pmu_stop(void)
545{
546 unsigned long flags, val;
547 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
548
549 raw_spin_lock_irqsave(&events->pmu_lock, flags);
550 val = armv6_pmcr_read();
551 val &= ~ARMV6_PMCR_ENABLE;
552 armv6_pmcr_write(val);
553 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
554}
555
556static int
557armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
558 struct hw_perf_event *event)
559{
560 /* Always place a cycle counter into the cycle counter. */
561 if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
562 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
563 return -EAGAIN;
564
565 return ARMV6_CYCLE_COUNTER;
566 } else {
567 /*
568 * For anything other than a cycle counter, try and use
569 * counter0 and counter1.
570 */
571 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask))
572 return ARMV6_COUNTER1;
573
574 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask))
575 return ARMV6_COUNTER0;
576
577 /* The counters are all in use. */
578 return -EAGAIN;
579 }
580}
581
582static void
583armv6pmu_disable_event(struct hw_perf_event *hwc,
584 int idx)
585{
586 unsigned long val, mask, evt, flags;
587 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
588
589 if (ARMV6_CYCLE_COUNTER == idx) {
590 mask = ARMV6_PMCR_CCOUNT_IEN;
591 evt = 0;
592 } else if (ARMV6_COUNTER0 == idx) {
593 mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
594 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
595 } else if (ARMV6_COUNTER1 == idx) {
596 mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
597 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
598 } else {
599 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
600 return;
601 }
602
603 /*
604 * Mask out the current event and set the counter to count the number
605 * of ETM bus signal assertion cycles. The external reporting should
606 * be disabled and so this should never increment.
607 */
608 raw_spin_lock_irqsave(&events->pmu_lock, flags);
609 val = armv6_pmcr_read();
610 val &= ~mask;
611 val |= evt;
612 armv6_pmcr_write(val);
613 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
614}
615
616static void
617armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
618 int idx)
619{
620 unsigned long val, mask, flags, evt = 0;
621 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
622
623 if (ARMV6_CYCLE_COUNTER == idx) {
624 mask = ARMV6_PMCR_CCOUNT_IEN;
625 } else if (ARMV6_COUNTER0 == idx) {
626 mask = ARMV6_PMCR_COUNT0_IEN;
627 } else if (ARMV6_COUNTER1 == idx) {
628 mask = ARMV6_PMCR_COUNT1_IEN;
629 } else {
630 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
631 return;
632 }
633
634 /*
635 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
636 * simply disable the interrupt reporting.
637 */
638 raw_spin_lock_irqsave(&events->pmu_lock, flags);
639 val = armv6_pmcr_read();
640 val &= ~mask;
641 val |= evt;
642 armv6_pmcr_write(val);
643 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
644}
645
646static int armv6_map_event(struct perf_event *event)
647{
648 return map_cpu_event(event, &armv6_perf_map,
649 &armv6_perf_cache_map, 0xFF);
650}
651
652static struct arm_pmu armv6pmu = {
653 .id = ARM_PERF_PMU_ID_V6,
654 .name = "v6",
655 .handle_irq = armv6pmu_handle_irq,
656 .enable = armv6pmu_enable_event,
657 .disable = armv6pmu_disable_event,
658 .read_counter = armv6pmu_read_counter,
659 .write_counter = armv6pmu_write_counter,
660 .get_event_idx = armv6pmu_get_event_idx,
661 .start = armv6pmu_start,
662 .stop = armv6pmu_stop,
663 .map_event = armv6_map_event,
664 .num_events = 3,
665 .max_period = (1LLU << 32) - 1,
666};
667
668static struct arm_pmu *__init armv6pmu_init(void)
669{
670 return &armv6pmu;
671}
672
673/*
674 * ARMv6mpcore is almost identical to single core ARMv6 with the exception
675 * that some of the events have different enumerations and that there is no
676 * *hack* to stop the programmable counters. To stop the counters we simply
677 * disable the interrupt reporting and update the event. When unthrottling we
678 * reset the period and enable the interrupt reporting.
679 */
680
681static int armv6mpcore_map_event(struct perf_event *event)
682{
683 return map_cpu_event(event, &armv6mpcore_perf_map,
684 &armv6mpcore_perf_cache_map, 0xFF);
685}
686
687static struct arm_pmu armv6mpcore_pmu = {
688 .id = ARM_PERF_PMU_ID_V6MP,
689 .name = "v6mpcore",
690 .handle_irq = armv6pmu_handle_irq,
691 .enable = armv6pmu_enable_event,
692 .disable = armv6mpcore_pmu_disable_event,
693 .read_counter = armv6pmu_read_counter,
694 .write_counter = armv6pmu_write_counter,
695 .get_event_idx = armv6pmu_get_event_idx,
696 .start = armv6pmu_start,
697 .stop = armv6pmu_stop,
698 .map_event = armv6mpcore_map_event,
699 .num_events = 3,
700 .max_period = (1LLU << 32) - 1,
701};
702
703static struct arm_pmu *__init armv6mpcore_pmu_init(void)
704{
705 return &armv6mpcore_pmu;
706}
707#else
708static struct arm_pmu *__init armv6pmu_init(void)
709{
710 return NULL;
711}
712
713static struct arm_pmu *__init armv6mpcore_pmu_init(void)
714{
715 return NULL;
716}
717#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARMv6 Performance counter handling code.
4 *
5 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
6 *
7 * ARMv6 has 2 configurable performance counters and a single cycle counter.
8 * They all share a single reset bit but can be written to zero so we can use
9 * that for a reset.
10 *
11 * The counters can't be individually enabled or disabled so when we remove
12 * one event and replace it with another we could get spurious counts from the
13 * wrong event. However, we can take advantage of the fact that the
14 * performance counters can export events to the event bus, and the event bus
15 * itself can be monitored. This requires that we *don't* export the events to
16 * the event bus. The procedure for disabling a configurable counter is:
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
18 * effectively stops the counter from counting.
19 * - disable the counter's interrupt generation (each counter has it's
20 * own interrupt enable bit).
21 * Once stopped, the counter value can be written as 0 to reset.
22 *
23 * To enable a counter:
24 * - enable the counter's interrupt generation.
25 * - set the new event type.
26 *
27 * Note: the dedicated cycle counter only counts cycles and can't be
28 * enabled/disabled independently of the others. When we want to disable the
29 * cycle counter, we have to just disable the interrupt reporting and start
30 * ignoring that counter. When re-enabling, we have to reset the value and
31 * enable the interrupt.
32 */
33
34#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
35
36#include <asm/cputype.h>
37#include <asm/irq_regs.h>
38
39#include <linux/of.h>
40#include <linux/perf/arm_pmu.h>
41#include <linux/platform_device.h>
42
43enum armv6_perf_types {
44 ARMV6_PERFCTR_ICACHE_MISS = 0x0,
45 ARMV6_PERFCTR_IBUF_STALL = 0x1,
46 ARMV6_PERFCTR_DDEP_STALL = 0x2,
47 ARMV6_PERFCTR_ITLB_MISS = 0x3,
48 ARMV6_PERFCTR_DTLB_MISS = 0x4,
49 ARMV6_PERFCTR_BR_EXEC = 0x5,
50 ARMV6_PERFCTR_BR_MISPREDICT = 0x6,
51 ARMV6_PERFCTR_INSTR_EXEC = 0x7,
52 ARMV6_PERFCTR_DCACHE_HIT = 0x9,
53 ARMV6_PERFCTR_DCACHE_ACCESS = 0xA,
54 ARMV6_PERFCTR_DCACHE_MISS = 0xB,
55 ARMV6_PERFCTR_DCACHE_WBACK = 0xC,
56 ARMV6_PERFCTR_SW_PC_CHANGE = 0xD,
57 ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF,
58 ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10,
59 ARMV6_PERFCTR_LSU_FULL_STALL = 0x11,
60 ARMV6_PERFCTR_WBUF_DRAINED = 0x12,
61 ARMV6_PERFCTR_CPU_CYCLES = 0xFF,
62 ARMV6_PERFCTR_NOP = 0x20,
63};
64
65enum armv6_counters {
66 ARMV6_CYCLE_COUNTER = 0,
67 ARMV6_COUNTER0,
68 ARMV6_COUNTER1,
69};
70
71/*
72 * The hardware events that we support. We do support cache operations but
73 * we have harvard caches and no way to combine instruction and data
74 * accesses/misses in hardware.
75 */
76static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
77 PERF_MAP_ALL_UNSUPPORTED,
78 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
79 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
80 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
81 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
82 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
83 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL,
84};
85
86static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
87 [PERF_COUNT_HW_CACHE_OP_MAX]
88 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
89 PERF_CACHE_MAP_ALL_UNSUPPORTED,
90
91 /*
92 * The performance counters don't differentiate between read and write
93 * accesses/misses so this isn't strictly correct, but it's the best we
94 * can do. Writes and reads get combined.
95 */
96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
100
101 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
102
103 /*
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
107 * can use a raw counter.
108 */
109 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
110 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
111
112 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
113 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
114};
115
116enum armv6mpcore_perf_types {
117 ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
118 ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
119 ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
120 ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
121 ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
122 ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
123 ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
124 ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
125 ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
126 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
127 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
128 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
129 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
130 ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
131 ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
132 ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
133 ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
134 ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
135 ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
136 ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
137};
138
139/*
140 * The hardware events that we support. We do support cache operations but
141 * we have harvard caches and no way to combine instruction and data
142 * accesses/misses in hardware.
143 */
144static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
145 PERF_MAP_ALL_UNSUPPORTED,
146 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
147 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
148 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
149 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
150 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
151 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
152};
153
154static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
155 [PERF_COUNT_HW_CACHE_OP_MAX]
156 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
157 PERF_CACHE_MAP_ALL_UNSUPPORTED,
158
159 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
160 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
161 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
162 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
163
164 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
165
166 /*
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
168 * misses and main TLB misses. There isn't an event for TLB misses, so
169 * use the micro misses here and if users want the main TLB misses they
170 * can use a raw counter.
171 */
172 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
173 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
174
175 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
176 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
177};
178
179static inline unsigned long
180armv6_pmcr_read(void)
181{
182 u32 val;
183 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));
184 return val;
185}
186
187static inline void
188armv6_pmcr_write(unsigned long val)
189{
190 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val));
191}
192
193#define ARMV6_PMCR_ENABLE (1 << 0)
194#define ARMV6_PMCR_CTR01_RESET (1 << 1)
195#define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
196#define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
197#define ARMV6_PMCR_COUNT0_IEN (1 << 4)
198#define ARMV6_PMCR_COUNT1_IEN (1 << 5)
199#define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
200#define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
201#define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
202#define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
203#define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
204#define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
205#define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
206#define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
207
208#define ARMV6_PMCR_OVERFLOWED_MASK \
209 (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
210 ARMV6_PMCR_CCOUNT_OVERFLOW)
211
212static inline int
213armv6_pmcr_has_overflowed(unsigned long pmcr)
214{
215 return pmcr & ARMV6_PMCR_OVERFLOWED_MASK;
216}
217
218static inline int
219armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
220 enum armv6_counters counter)
221{
222 int ret = 0;
223
224 if (ARMV6_CYCLE_COUNTER == counter)
225 ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
226 else if (ARMV6_COUNTER0 == counter)
227 ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
228 else if (ARMV6_COUNTER1 == counter)
229 ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
230 else
231 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
232
233 return ret;
234}
235
236static inline u64 armv6pmu_read_counter(struct perf_event *event)
237{
238 struct hw_perf_event *hwc = &event->hw;
239 int counter = hwc->idx;
240 unsigned long value = 0;
241
242 if (ARMV6_CYCLE_COUNTER == counter)
243 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value));
244 else if (ARMV6_COUNTER0 == counter)
245 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value));
246 else if (ARMV6_COUNTER1 == counter)
247 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value));
248 else
249 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
250
251 return value;
252}
253
254static inline void armv6pmu_write_counter(struct perf_event *event, u64 value)
255{
256 struct hw_perf_event *hwc = &event->hw;
257 int counter = hwc->idx;
258
259 if (ARMV6_CYCLE_COUNTER == counter)
260 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
261 else if (ARMV6_COUNTER0 == counter)
262 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value));
263 else if (ARMV6_COUNTER1 == counter)
264 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value));
265 else
266 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
267}
268
269static void armv6pmu_enable_event(struct perf_event *event)
270{
271 unsigned long val, mask, evt, flags;
272 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
273 struct hw_perf_event *hwc = &event->hw;
274 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
275 int idx = hwc->idx;
276
277 if (ARMV6_CYCLE_COUNTER == idx) {
278 mask = 0;
279 evt = ARMV6_PMCR_CCOUNT_IEN;
280 } else if (ARMV6_COUNTER0 == idx) {
281 mask = ARMV6_PMCR_EVT_COUNT0_MASK;
282 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
283 ARMV6_PMCR_COUNT0_IEN;
284 } else if (ARMV6_COUNTER1 == idx) {
285 mask = ARMV6_PMCR_EVT_COUNT1_MASK;
286 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
287 ARMV6_PMCR_COUNT1_IEN;
288 } else {
289 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
290 return;
291 }
292
293 /*
294 * Mask out the current event and set the counter to count the event
295 * that we're interested in.
296 */
297 raw_spin_lock_irqsave(&events->pmu_lock, flags);
298 val = armv6_pmcr_read();
299 val &= ~mask;
300 val |= evt;
301 armv6_pmcr_write(val);
302 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
303}
304
305static irqreturn_t
306armv6pmu_handle_irq(struct arm_pmu *cpu_pmu)
307{
308 unsigned long pmcr = armv6_pmcr_read();
309 struct perf_sample_data data;
310 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
311 struct pt_regs *regs;
312 int idx;
313
314 if (!armv6_pmcr_has_overflowed(pmcr))
315 return IRQ_NONE;
316
317 regs = get_irq_regs();
318
319 /*
320 * The interrupts are cleared by writing the overflow flags back to
321 * the control register. All of the other bits don't have any effect
322 * if they are rewritten, so write the whole value back.
323 */
324 armv6_pmcr_write(pmcr);
325
326 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
327 struct perf_event *event = cpuc->events[idx];
328 struct hw_perf_event *hwc;
329
330 /* Ignore if we don't have an event. */
331 if (!event)
332 continue;
333
334 /*
335 * We have a single interrupt for all counters. Check that
336 * each counter has overflowed before we process it.
337 */
338 if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
339 continue;
340
341 hwc = &event->hw;
342 armpmu_event_update(event);
343 perf_sample_data_init(&data, 0, hwc->last_period);
344 if (!armpmu_event_set_period(event))
345 continue;
346
347 if (perf_event_overflow(event, &data, regs))
348 cpu_pmu->disable(event);
349 }
350
351 /*
352 * Handle the pending perf events.
353 *
354 * Note: this call *must* be run with interrupts disabled. For
355 * platforms that can have the PMU interrupts raised as an NMI, this
356 * will not work.
357 */
358 irq_work_run();
359
360 return IRQ_HANDLED;
361}
362
363static void armv6pmu_start(struct arm_pmu *cpu_pmu)
364{
365 unsigned long flags, val;
366 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
367
368 raw_spin_lock_irqsave(&events->pmu_lock, flags);
369 val = armv6_pmcr_read();
370 val |= ARMV6_PMCR_ENABLE;
371 armv6_pmcr_write(val);
372 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
373}
374
375static void armv6pmu_stop(struct arm_pmu *cpu_pmu)
376{
377 unsigned long flags, val;
378 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
379
380 raw_spin_lock_irqsave(&events->pmu_lock, flags);
381 val = armv6_pmcr_read();
382 val &= ~ARMV6_PMCR_ENABLE;
383 armv6_pmcr_write(val);
384 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
385}
386
387static int
388armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
389 struct perf_event *event)
390{
391 struct hw_perf_event *hwc = &event->hw;
392 /* Always place a cycle counter into the cycle counter. */
393 if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) {
394 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
395 return -EAGAIN;
396
397 return ARMV6_CYCLE_COUNTER;
398 } else {
399 /*
400 * For anything other than a cycle counter, try and use
401 * counter0 and counter1.
402 */
403 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask))
404 return ARMV6_COUNTER1;
405
406 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask))
407 return ARMV6_COUNTER0;
408
409 /* The counters are all in use. */
410 return -EAGAIN;
411 }
412}
413
414static void armv6pmu_clear_event_idx(struct pmu_hw_events *cpuc,
415 struct perf_event *event)
416{
417 clear_bit(event->hw.idx, cpuc->used_mask);
418}
419
420static void armv6pmu_disable_event(struct perf_event *event)
421{
422 unsigned long val, mask, evt, flags;
423 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
424 struct hw_perf_event *hwc = &event->hw;
425 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
426 int idx = hwc->idx;
427
428 if (ARMV6_CYCLE_COUNTER == idx) {
429 mask = ARMV6_PMCR_CCOUNT_IEN;
430 evt = 0;
431 } else if (ARMV6_COUNTER0 == idx) {
432 mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
433 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
434 } else if (ARMV6_COUNTER1 == idx) {
435 mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
436 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
437 } else {
438 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
439 return;
440 }
441
442 /*
443 * Mask out the current event and set the counter to count the number
444 * of ETM bus signal assertion cycles. The external reporting should
445 * be disabled and so this should never increment.
446 */
447 raw_spin_lock_irqsave(&events->pmu_lock, flags);
448 val = armv6_pmcr_read();
449 val &= ~mask;
450 val |= evt;
451 armv6_pmcr_write(val);
452 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
453}
454
455static void armv6mpcore_pmu_disable_event(struct perf_event *event)
456{
457 unsigned long val, mask, flags, evt = 0;
458 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
459 struct hw_perf_event *hwc = &event->hw;
460 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
461 int idx = hwc->idx;
462
463 if (ARMV6_CYCLE_COUNTER == idx) {
464 mask = ARMV6_PMCR_CCOUNT_IEN;
465 } else if (ARMV6_COUNTER0 == idx) {
466 mask = ARMV6_PMCR_COUNT0_IEN;
467 } else if (ARMV6_COUNTER1 == idx) {
468 mask = ARMV6_PMCR_COUNT1_IEN;
469 } else {
470 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
471 return;
472 }
473
474 /*
475 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
476 * simply disable the interrupt reporting.
477 */
478 raw_spin_lock_irqsave(&events->pmu_lock, flags);
479 val = armv6_pmcr_read();
480 val &= ~mask;
481 val |= evt;
482 armv6_pmcr_write(val);
483 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
484}
485
486static int armv6_map_event(struct perf_event *event)
487{
488 return armpmu_map_event(event, &armv6_perf_map,
489 &armv6_perf_cache_map, 0xFF);
490}
491
492static void armv6pmu_init(struct arm_pmu *cpu_pmu)
493{
494 cpu_pmu->handle_irq = armv6pmu_handle_irq;
495 cpu_pmu->enable = armv6pmu_enable_event;
496 cpu_pmu->disable = armv6pmu_disable_event;
497 cpu_pmu->read_counter = armv6pmu_read_counter;
498 cpu_pmu->write_counter = armv6pmu_write_counter;
499 cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
500 cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx;
501 cpu_pmu->start = armv6pmu_start;
502 cpu_pmu->stop = armv6pmu_stop;
503 cpu_pmu->map_event = armv6_map_event;
504 cpu_pmu->num_events = 3;
505}
506
507static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu)
508{
509 armv6pmu_init(cpu_pmu);
510 cpu_pmu->name = "armv6_1136";
511 return 0;
512}
513
514static int armv6_1156_pmu_init(struct arm_pmu *cpu_pmu)
515{
516 armv6pmu_init(cpu_pmu);
517 cpu_pmu->name = "armv6_1156";
518 return 0;
519}
520
521static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu)
522{
523 armv6pmu_init(cpu_pmu);
524 cpu_pmu->name = "armv6_1176";
525 return 0;
526}
527
528/*
529 * ARMv6mpcore is almost identical to single core ARMv6 with the exception
530 * that some of the events have different enumerations and that there is no
531 * *hack* to stop the programmable counters. To stop the counters we simply
532 * disable the interrupt reporting and update the event. When unthrottling we
533 * reset the period and enable the interrupt reporting.
534 */
535
536static int armv6mpcore_map_event(struct perf_event *event)
537{
538 return armpmu_map_event(event, &armv6mpcore_perf_map,
539 &armv6mpcore_perf_cache_map, 0xFF);
540}
541
542static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
543{
544 cpu_pmu->name = "armv6_11mpcore";
545 cpu_pmu->handle_irq = armv6pmu_handle_irq;
546 cpu_pmu->enable = armv6pmu_enable_event;
547 cpu_pmu->disable = armv6mpcore_pmu_disable_event;
548 cpu_pmu->read_counter = armv6pmu_read_counter;
549 cpu_pmu->write_counter = armv6pmu_write_counter;
550 cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
551 cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx;
552 cpu_pmu->start = armv6pmu_start;
553 cpu_pmu->stop = armv6pmu_stop;
554 cpu_pmu->map_event = armv6mpcore_map_event;
555 cpu_pmu->num_events = 3;
556
557 return 0;
558}
559
560static const struct of_device_id armv6_pmu_of_device_ids[] = {
561 {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
562 {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
563 {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
564 { /* sentinel value */ }
565};
566
567static const struct pmu_probe_info armv6_pmu_probe_table[] = {
568 ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init),
569 ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init),
570 ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init),
571 ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init),
572 { /* sentinel value */ }
573};
574
575static int armv6_pmu_device_probe(struct platform_device *pdev)
576{
577 return arm_pmu_device_probe(pdev, armv6_pmu_of_device_ids,
578 armv6_pmu_probe_table);
579}
580
581static struct platform_driver armv6_pmu_driver = {
582 .driver = {
583 .name = "armv6-pmu",
584 .of_match_table = armv6_pmu_of_device_ids,
585 },
586 .probe = armv6_pmu_device_probe,
587};
588
589builtin_platform_driver(armv6_pmu_driver);
590#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */