1config ARM
   2	bool
   3	default y
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   4	select ARCH_HAVE_CUSTOM_GPIO_H
   5	select HAVE_AOUT
   6	select HAVE_DMA_API_DEBUG
   7	select HAVE_IDE if PCI || ISA || PCMCIA
   8	select HAVE_DMA_ATTRS
   9	select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
  10	select HAVE_MEMBLOCK
  11	select RTC_LIB
  12	select SYS_SUPPORTS_APM_EMULATION
  13	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  15	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  16	select HAVE_ARCH_KGDB
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  17	select HAVE_ARCH_TRACEHOOK
  18	select HAVE_KPROBES if !XIP_KERNEL
  19	select HAVE_KRETPROBES if (HAVE_KPROBES)
  20	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  21	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  22	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  23	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  24	select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  25	select HAVE_GENERIC_DMA_COHERENT
 
 
 
 
 
 
 
 
 
 
 
 
  26	select HAVE_KERNEL_GZIP
  27	select HAVE_KERNEL_LZO
  28	select HAVE_KERNEL_LZMA
 
  29	select HAVE_KERNEL_XZ
  30	select HAVE_IRQ_WORK
 
 
 
 
 
  31	select HAVE_PERF_EVENTS
  32	select PERF_USE_VMALLOC
 
 
  33	select HAVE_REGS_AND_STACK_ACCESS_API
  34	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  35	select HAVE_C_RECORDMCOUNT
  36	select HAVE_GENERIC_HARDIRQS
  37	select HARDIRQS_SW_RESEND
  38	select GENERIC_IRQ_PROBE
  39	select GENERIC_IRQ_SHOW
  40	select GENERIC_IRQ_PROBE
  41	select HARDIRQS_SW_RESEND
  42	select CPU_PM if (SUSPEND || CPU_IDLE)
  43	select GENERIC_PCI_IOMAP
  44	select HAVE_BPF_JIT
  45	select GENERIC_SMP_IDLE_THREAD
  46	select KTIME_SCALAR
  47	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 
 
 
 
 
 
 
 
 
 
  48	help
  49	  The ARM series is a line of low-power-consumption RISC chip designs
  50	  licensed by ARM Ltd and targeted at embedded applications and
  51	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  52	  manufactured, but legacy ARM-based PC hardware remains popular in
  53	  Europe.  There is an ARM Linux project with a web page at
  54	  <http://www.arm.linux.org.uk/>.
  55
  56config ARM_HAS_SG_CHAIN
  57	bool
  58
  59config NEED_SG_DMA_LENGTH
  60	bool
 
 
 
 
 
  61
  62config ARM_DMA_USE_IOMMU
  63	select NEED_SG_DMA_LENGTH
  64	select ARM_HAS_SG_CHAIN
  65	bool
 
  66
  67config HAVE_PWM
  68	bool
  69
  70config MIGHT_HAVE_PCI
  71	bool
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  72
  73config SYS_SUPPORTS_APM_EMULATION
  74	bool
  75
  76config GENERIC_GPIO
  77	bool
  78
  79config HAVE_TCM
  80	bool
  81	select GENERIC_ALLOCATOR
  82
  83config HAVE_PROC_CPU
  84	bool
  85
  86config NO_IOPORT
  87	bool
  88
  89config EISA
  90	bool
  91	---help---
  92	  The Extended Industry Standard Architecture (EISA) bus was
  93	  developed as an open alternative to the IBM MicroChannel bus.
  94
  95	  The EISA bus provided some of the features of the IBM MicroChannel
  96	  bus while maintaining backward compatibility with cards made for
  97	  the older ISA bus.  The EISA bus saw limited use between 1988 and
  98	  1995 when it was made obsolete by the PCI bus.
  99
 100	  Say Y here if you are building a kernel for an EISA-based machine.
 101
 102	  Otherwise, say N.
 103
 104config SBUS
 105	bool
 106
 107config STACKTRACE_SUPPORT
 108	bool
 109	default y
 110
 111config HAVE_LATENCYTOP_SUPPORT
 112	bool
 113	depends on !SMP
 114	default y
 115
 116config LOCKDEP_SUPPORT
 117	bool
 118	default y
 119
 120config TRACE_IRQFLAGS_SUPPORT
 121	bool
 122	default y
 123
 124config GENERIC_LOCKBREAK
 125	bool
 126	default y
 127	depends on SMP && PREEMPT
 128
 129config RWSEM_GENERIC_SPINLOCK
 130	bool
 131	default y
 132
 133config RWSEM_XCHGADD_ALGORITHM
 134	bool
 135
 136config ARCH_HAS_ILOG2_U32
 137	bool
 138
 139config ARCH_HAS_ILOG2_U64
 140	bool
 141
 142config ARCH_HAS_CPUFREQ
 143	bool
 144	help
 145	  Internal node to signify that the ARCH has CPUFREQ support
 146	  and that the relevant menu configurations are displayed for
 147	  it.
 148
 149config GENERIC_HWEIGHT
 150	bool
 151	default y
 152
 153config GENERIC_CALIBRATE_DELAY
 154	bool
 155	default y
 156
 157config ARCH_MAY_HAVE_PC_FDC
 158	bool
 159
 160config ZONE_DMA
 161	bool
 162
 163config NEED_DMA_MAP_STATE
 164       def_bool y
 165
 166config ARCH_HAS_DMA_SET_COHERENT_MASK
 167	bool
 168
 169config GENERIC_ISA_DMA
 170	bool
 171
 172config FIQ
 173	bool
 174
 175config NEED_RET_TO_USER
 176	bool
 177
 178config ARCH_MTD_XIP
 179	bool
 180
 181config VECTORS_BASE
 182	hex
 183	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 184	default DRAM_BASE if REMAP_VECTORS_TO_RAM
 185	default 0x00000000
 186	help
 187	  The base address of exception vectors.
 188
 189config ARM_PATCH_PHYS_VIRT
 190	bool "Patch physical to virtual translations at runtime" if EMBEDDED
 191	default y
 192	depends on !XIP_KERNEL && MMU
 193	depends on !ARCH_REALVIEW || !SPARSEMEM
 194	help
 195	  Patch phys-to-virt and virt-to-phys translation functions at
 196	  boot and module load time according to the position of the
 197	  kernel in system memory.
 198
 199	  This can only be used with non-XIP MMU kernels where the base
 200	  of physical memory is at a 16MB boundary.
 201
 202	  Only disable this option if you know that you do not require
 203	  this feature (eg, building a kernel for a single machine) and
 204	  you need to shrink the kernel to the minimal size.
 205
 206config NEED_MACH_IO_H
 207	bool
 208	help
 209	  Select this when mach/io.h is required to provide special
 210	  definitions for this platform.  The need for mach/io.h should
 211	  be avoided when possible.
 212
 213config NEED_MACH_MEMORY_H
 214	bool
 215	help
 216	  Select this when mach/memory.h is required to provide special
 217	  definitions for this platform.  The need for mach/memory.h should
 218	  be avoided when possible.
 219
 220config PHYS_OFFSET
 221	hex "Physical address of main memory" if MMU
 222	depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 223	default DRAM_BASE if !MMU
 
 
 
 
 
 
 224	help
 225	  Please provide the physical address corresponding to the
 226	  location of main memory in your system.
 227
 228config GENERIC_BUG
 229	def_bool y
 230	depends on BUG
 231
 232source "init/Kconfig"
 233
 234source "kernel/Kconfig.freezer"
 
 235
 236menu "System Type"
 237
 238config MMU
 239	bool "MMU-based Paged Memory Management Support"
 240	default y
 241	help
 242	  Select if you want MMU-based virtualised addressing space
 243	  support by paged memory management. If unsure, say 'Y'.
 244
 245#
 246# The "ARM system type" choice list is ordered alphabetically by option
 247# text.  Please add new entries in the option alphabetic order.
 248#
 249choice
 250	prompt "ARM system type"
 251	default ARCH_VERSATILE
 252
 253config ARCH_INTEGRATOR
 254	bool "ARM Ltd. Integrator family"
 255	select ARM_AMBA
 256	select ARCH_HAS_CPUFREQ
 257	select CLKDEV_LOOKUP
 258	select HAVE_MACH_CLKDEV
 259	select HAVE_TCM
 260	select ICST
 261	select GENERIC_CLOCKEVENTS
 262	select PLAT_VERSATILE
 263	select PLAT_VERSATILE_FPGA_IRQ
 264	select NEED_MACH_IO_H
 265	select NEED_MACH_MEMORY_H
 266	select SPARSE_IRQ
 267	select MULTI_IRQ_HANDLER
 268	help
 269	  Support for ARM's Integrator platform.
 270
 271config ARCH_REALVIEW
 272	bool "ARM Ltd. RealView family"
 273	select ARM_AMBA
 274	select CLKDEV_LOOKUP
 275	select HAVE_MACH_CLKDEV
 276	select ICST
 277	select GENERIC_CLOCKEVENTS
 278	select ARCH_WANT_OPTIONAL_GPIOLIB
 279	select PLAT_VERSATILE
 280	select PLAT_VERSATILE_CLCD
 281	select ARM_TIMER_SP804
 282	select GPIO_PL061 if GPIOLIB
 283	select NEED_MACH_MEMORY_H
 284	help
 285	  This enables support for ARM Ltd RealView boards.
 286
 287config ARCH_VERSATILE
 288	bool "ARM Ltd. Versatile family"
 289	select ARM_AMBA
 290	select ARM_VIC
 291	select CLKDEV_LOOKUP
 292	select HAVE_MACH_CLKDEV
 293	select ICST
 294	select GENERIC_CLOCKEVENTS
 295	select ARCH_WANT_OPTIONAL_GPIOLIB
 296	select NEED_MACH_IO_H if PCI
 297	select PLAT_VERSATILE
 298	select PLAT_VERSATILE_CLCD
 299	select PLAT_VERSATILE_FPGA_IRQ
 300	select ARM_TIMER_SP804
 301	help
 302	  This enables support for ARM Ltd Versatile board.
 303
 304config ARCH_VEXPRESS
 305	bool "ARM Ltd. Versatile Express family"
 306	select ARCH_WANT_OPTIONAL_GPIOLIB
 307	select ARM_AMBA
 308	select ARM_TIMER_SP804
 309	select CLKDEV_LOOKUP
 310	select HAVE_MACH_CLKDEV
 311	select GENERIC_CLOCKEVENTS
 312	select HAVE_CLK
 313	select HAVE_PATA_PLATFORM
 314	select ICST
 315	select NO_IOPORT
 316	select PLAT_VERSATILE
 317	select PLAT_VERSATILE_CLCD
 318	help
 319	  This enables support for the ARM Ltd Versatile Express boards.
 320
 321config ARCH_AT91
 322	bool "Atmel AT91"
 323	select ARCH_REQUIRE_GPIOLIB
 324	select HAVE_CLK
 325	select CLKDEV_LOOKUP
 326	select IRQ_DOMAIN
 327	select NEED_MACH_IO_H if PCCARD
 328	help
 329	  This enables support for systems based on Atmel
 330	  AT91RM9200 and AT91SAM9* processors.
 331
 332config ARCH_BCMRING
 333	bool "Broadcom BCMRING"
 334	depends on MMU
 335	select CPU_V6
 336	select ARM_AMBA
 337	select ARM_TIMER_SP804
 338	select CLKDEV_LOOKUP
 339	select GENERIC_CLOCKEVENTS
 340	select ARCH_WANT_OPTIONAL_GPIOLIB
 341	help
 342	  Support for Broadcom's BCMRing platform.
 343
 344config ARCH_HIGHBANK
 345	bool "Calxeda Highbank-based"
 346	select ARCH_WANT_OPTIONAL_GPIOLIB
 347	select ARM_AMBA
 348	select ARM_GIC
 349	select ARM_TIMER_SP804
 350	select CACHE_L2X0
 351	select CLKDEV_LOOKUP
 352	select CPU_V7
 353	select GENERIC_CLOCKEVENTS
 354	select HAVE_ARM_SCU
 355	select HAVE_SMP
 356	select SPARSE_IRQ
 357	select USE_OF
 358	help
 359	  Support for the Calxeda Highbank SoC based boards.
 360
 361config ARCH_CLPS711X
 362	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 363	select CPU_ARM720T
 364	select ARCH_USES_GETTIMEOFFSET
 365	select NEED_MACH_MEMORY_H
 366	help
 367	  Support for Cirrus Logic 711x/721x/731x based boards.
 368
 369config ARCH_CNS3XXX
 370	bool "Cavium Networks CNS3XXX family"
 371	select CPU_V6K
 372	select GENERIC_CLOCKEVENTS
 373	select ARM_GIC
 374	select MIGHT_HAVE_CACHE_L2X0
 375	select MIGHT_HAVE_PCI
 376	select PCI_DOMAINS if PCI
 377	help
 378	  Support for Cavium Networks CNS3XXX platform.
 379
 380config ARCH_GEMINI
 381	bool "Cortina Systems Gemini"
 382	select CPU_FA526
 383	select ARCH_REQUIRE_GPIOLIB
 384	select ARCH_USES_GETTIMEOFFSET
 385	help
 386	  Support for the Cortina Systems Gemini family SoCs
 387
 388config ARCH_PRIMA2
 389	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 390	select CPU_V7
 391	select NO_IOPORT
 392	select GENERIC_CLOCKEVENTS
 393	select CLKDEV_LOOKUP
 394	select GENERIC_IRQ_CHIP
 395	select MIGHT_HAVE_CACHE_L2X0
 396	select PINCTRL
 397	select PINCTRL_SIRF
 398	select USE_OF
 399	select ZONE_DMA
 400	help
 401          Support for CSR SiRFSoC ARM Cortex A9 Platform
 402
 403config ARCH_EBSA110
 404	bool "EBSA-110"
 405	select CPU_SA110
 406	select ISA
 407	select NO_IOPORT
 408	select ARCH_USES_GETTIMEOFFSET
 409	select NEED_MACH_IO_H
 410	select NEED_MACH_MEMORY_H
 411	help
 412	  This is an evaluation board for the StrongARM processor available
 413	  from Digital. It has limited hardware on-board, including an
 414	  Ethernet interface, two PCMCIA sockets, two serial ports and a
 415	  parallel port.
 416
 417config ARCH_EP93XX
 418	bool "EP93xx-based"
 419	select CPU_ARM920T
 420	select ARM_AMBA
 421	select ARM_VIC
 422	select CLKDEV_LOOKUP
 423	select ARCH_REQUIRE_GPIOLIB
 424	select ARCH_HAS_HOLES_MEMORYMODEL
 425	select ARCH_USES_GETTIMEOFFSET
 426	select NEED_MACH_MEMORY_H
 427	help
 428	  This enables support for the Cirrus EP93xx series of CPUs.
 429
 430config ARCH_FOOTBRIDGE
 431	bool "FootBridge"
 432	select CPU_SA110
 433	select FOOTBRIDGE
 434	select GENERIC_CLOCKEVENTS
 435	select HAVE_IDE
 436	select NEED_MACH_IO_H
 437	select NEED_MACH_MEMORY_H
 438	help
 439	  Support for systems based on the DC21285 companion chip
 440	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 441
 442config ARCH_MXC
 443	bool "Freescale MXC/iMX-based"
 444	select GENERIC_CLOCKEVENTS
 445	select ARCH_REQUIRE_GPIOLIB
 446	select CLKDEV_LOOKUP
 447	select CLKSRC_MMIO
 448	select GENERIC_IRQ_CHIP
 449	select MULTI_IRQ_HANDLER
 450	help
 451	  Support for Freescale MXC/iMX-based family of processors
 452
 453config ARCH_MXS
 454	bool "Freescale MXS-based"
 455	select GENERIC_CLOCKEVENTS
 456	select ARCH_REQUIRE_GPIOLIB
 457	select CLKDEV_LOOKUP
 458	select CLKSRC_MMIO
 459	select COMMON_CLK
 460	select HAVE_CLK_PREPARE
 461	select PINCTRL
 462	select USE_OF
 463	help
 464	  Support for Freescale MXS-based family of processors
 465
 466config ARCH_NETX
 467	bool "Hilscher NetX based"
 468	select CLKSRC_MMIO
 469	select CPU_ARM926T
 470	select ARM_VIC
 471	select GENERIC_CLOCKEVENTS
 472	help
 473	  This enables support for systems based on the Hilscher NetX Soc
 474
 475config ARCH_H720X
 476	bool "Hynix HMS720x-based"
 477	select CPU_ARM720T
 478	select ISA_DMA_API
 479	select ARCH_USES_GETTIMEOFFSET
 480	help
 481	  This enables support for systems based on the Hynix HMS720x
 482
 483config ARCH_IOP13XX
 484	bool "IOP13xx-based"
 485	depends on MMU
 486	select CPU_XSC3
 487	select PLAT_IOP
 488	select PCI
 489	select ARCH_SUPPORTS_MSI
 490	select VMSPLIT_1G
 491	select NEED_MACH_IO_H
 492	select NEED_MACH_MEMORY_H
 493	select NEED_RET_TO_USER
 494	help
 495	  Support for Intel's IOP13XX (XScale) family of processors.
 496
 497config ARCH_IOP32X
 498	bool "IOP32x-based"
 499	depends on MMU
 500	select CPU_XSCALE
 501	select NEED_MACH_IO_H
 502	select NEED_RET_TO_USER
 503	select PLAT_IOP
 504	select PCI
 505	select ARCH_REQUIRE_GPIOLIB
 506	help
 507	  Support for Intel's 80219 and IOP32X (XScale) family of
 508	  processors.
 509
 510config ARCH_IOP33X
 511	bool "IOP33x-based"
 512	depends on MMU
 513	select CPU_XSCALE
 514	select NEED_MACH_IO_H
 515	select NEED_RET_TO_USER
 516	select PLAT_IOP
 517	select PCI
 518	select ARCH_REQUIRE_GPIOLIB
 519	help
 520	  Support for Intel's IOP33X (XScale) family of processors.
 521
 522config ARCH_IXP4XX
 523	bool "IXP4xx-based"
 524	depends on MMU
 525	select ARCH_HAS_DMA_SET_COHERENT_MASK
 526	select CLKSRC_MMIO
 527	select CPU_XSCALE
 528	select ARCH_REQUIRE_GPIOLIB
 529	select GENERIC_CLOCKEVENTS
 530	select MIGHT_HAVE_PCI
 531	select NEED_MACH_IO_H
 532	select DMABOUNCE if PCI
 533	help
 534	  Support for Intel's IXP4XX (XScale) family of processors.
 
 535
 536config ARCH_DOVE
 537	bool "Marvell Dove"
 538	select CPU_V7
 539	select PCI
 540	select ARCH_REQUIRE_GPIOLIB
 541	select GENERIC_CLOCKEVENTS
 542	select NEED_MACH_IO_H
 543	select PLAT_ORION
 544	help
 545	  Support for the Marvell Dove SoC 88AP510
 546
 547config ARCH_KIRKWOOD
 548	bool "Marvell Kirkwood"
 549	select CPU_FEROCEON
 550	select PCI
 551	select ARCH_REQUIRE_GPIOLIB
 552	select GENERIC_CLOCKEVENTS
 553	select NEED_MACH_IO_H
 554	select PLAT_ORION
 555	help
 556	  Support for the following Marvell Kirkwood series SoCs:
 557	  88F6180, 88F6192 and 88F6281.
 558
 559config ARCH_LPC32XX
 560	bool "NXP LPC32XX"
 561	select CLKSRC_MMIO
 562	select CPU_ARM926T
 563	select ARCH_REQUIRE_GPIOLIB
 564	select HAVE_IDE
 565	select ARM_AMBA
 566	select USB_ARCH_HAS_OHCI
 567	select CLKDEV_LOOKUP
 568	select GENERIC_CLOCKEVENTS
 569	select USE_OF
 570	help
 571	  Support for the NXP LPC32XX family of processors
 572
 573config ARCH_MV78XX0
 574	bool "Marvell MV78xx0"
 575	select CPU_FEROCEON
 576	select PCI
 577	select ARCH_REQUIRE_GPIOLIB
 578	select GENERIC_CLOCKEVENTS
 579	select NEED_MACH_IO_H
 580	select PLAT_ORION
 581	help
 582	  Support for the following Marvell MV78xx0 series SoCs:
 583	  MV781x0, MV782x0.
 584
 585config ARCH_ORION5X
 586	bool "Marvell Orion"
 587	depends on MMU
 588	select CPU_FEROCEON
 589	select PCI
 590	select ARCH_REQUIRE_GPIOLIB
 591	select GENERIC_CLOCKEVENTS
 592	select NEED_MACH_IO_H
 593	select PLAT_ORION
 594	help
 595	  Support for the following Marvell Orion 5x series SoCs:
 596	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 597	  Orion-2 (5281), Orion-1-90 (6183).
 598
 599config ARCH_MMP
 600	bool "Marvell PXA168/910/MMP2"
 601	depends on MMU
 602	select ARCH_REQUIRE_GPIOLIB
 603	select CLKDEV_LOOKUP
 604	select GENERIC_CLOCKEVENTS
 605	select GPIO_PXA
 606	select IRQ_DOMAIN
 607	select PLAT_PXA
 608	select SPARSE_IRQ
 609	select GENERIC_ALLOCATOR
 610	help
 611	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 612
 613config ARCH_KS8695
 614	bool "Micrel/Kendin KS8695"
 615	select CPU_ARM922T
 616	select ARCH_REQUIRE_GPIOLIB
 617	select ARCH_USES_GETTIMEOFFSET
 618	select NEED_MACH_MEMORY_H
 619	help
 620	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 621	  System-on-Chip devices.
 622
 623config ARCH_W90X900
 624	bool "Nuvoton W90X900 CPU"
 625	select CPU_ARM926T
 626	select ARCH_REQUIRE_GPIOLIB
 627	select CLKDEV_LOOKUP
 628	select CLKSRC_MMIO
 629	select GENERIC_CLOCKEVENTS
 630	help
 631	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 632	  At present, the w90x900 has been renamed nuc900, regarding
 633	  the ARM series product line, you can login the following
 634	  link address to know more.
 635
 636	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 637		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 638
 639config ARCH_TEGRA
 640	bool "NVIDIA Tegra"
 641	select CLKDEV_LOOKUP
 642	select CLKSRC_MMIO
 643	select GENERIC_CLOCKEVENTS
 644	select GENERIC_GPIO
 645	select HAVE_CLK
 646	select HAVE_SMP
 647	select MIGHT_HAVE_CACHE_L2X0
 648	select NEED_MACH_IO_H if PCI
 649	select ARCH_HAS_CPUFREQ
 650	help
 651	  This enables support for NVIDIA Tegra based systems (Tegra APX,
 652	  Tegra 6xx and Tegra 2 series).
 653
 654config ARCH_PICOXCELL
 655	bool "Picochip picoXcell"
 656	select ARCH_REQUIRE_GPIOLIB
 657	select ARM_PATCH_PHYS_VIRT
 658	select ARM_VIC
 659	select CPU_V6K
 660	select DW_APB_TIMER
 661	select GENERIC_CLOCKEVENTS
 662	select GENERIC_GPIO
 663	select HAVE_TCM
 664	select NO_IOPORT
 665	select SPARSE_IRQ
 666	select USE_OF
 667	help
 668	  This enables support for systems based on the Picochip picoXcell
 669	  family of Femtocell devices.  The picoxcell support requires device tree
 670	  for all boards.
 671
 672config ARCH_PNX4008
 673	bool "Philips Nexperia PNX4008 Mobile"
 674	select CPU_ARM926T
 675	select CLKDEV_LOOKUP
 676	select ARCH_USES_GETTIMEOFFSET
 677	help
 678	  This enables support for Philips PNX4008 mobile platform.
 679
 680config ARCH_PXA
 681	bool "PXA2xx/PXA3xx-based"
 682	depends on MMU
 683	select ARCH_MTD_XIP
 684	select ARCH_HAS_CPUFREQ
 685	select CLKDEV_LOOKUP
 686	select CLKSRC_MMIO
 687	select ARCH_REQUIRE_GPIOLIB
 688	select GENERIC_CLOCKEVENTS
 689	select GPIO_PXA
 690	select PLAT_PXA
 691	select SPARSE_IRQ
 692	select AUTO_ZRELADDR
 693	select MULTI_IRQ_HANDLER
 694	select ARM_CPU_SUSPEND if PM
 695	select HAVE_IDE
 696	help
 697	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 698
 699config ARCH_MSM
 700	bool "Qualcomm MSM"
 701	select HAVE_CLK
 702	select GENERIC_CLOCKEVENTS
 703	select ARCH_REQUIRE_GPIOLIB
 704	select CLKDEV_LOOKUP
 705	help
 706	  Support for Qualcomm MSM/QSD based systems.  This runs on the
 707	  apps processor of the MSM/QSD and depends on a shared memory
 708	  interface to the modem processor which runs the baseband
 709	  stack and controls some vital subsystems
 710	  (clock and power control, etc).
 711
 712config ARCH_SHMOBILE
 713	bool "Renesas SH-Mobile / R-Mobile"
 714	select HAVE_CLK
 715	select CLKDEV_LOOKUP
 716	select HAVE_MACH_CLKDEV
 717	select HAVE_SMP
 718	select GENERIC_CLOCKEVENTS
 719	select MIGHT_HAVE_CACHE_L2X0
 720	select NO_IOPORT
 721	select SPARSE_IRQ
 722	select MULTI_IRQ_HANDLER
 723	select PM_GENERIC_DOMAINS if PM
 724	select NEED_MACH_MEMORY_H
 725	help
 726	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 727
 728config ARCH_RPC
 729	bool "RiscPC"
 730	select ARCH_ACORN
 731	select FIQ
 732	select ARCH_MAY_HAVE_PC_FDC
 733	select HAVE_PATA_PLATFORM
 734	select ISA_DMA_API
 735	select NO_IOPORT
 736	select ARCH_SPARSEMEM_ENABLE
 737	select ARCH_USES_GETTIMEOFFSET
 738	select HAVE_IDE
 739	select NEED_MACH_IO_H
 740	select NEED_MACH_MEMORY_H
 741	help
 742	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
 743	  CD-ROM interface, serial and parallel port, and the floppy drive.
 744
 745config ARCH_SA1100
 746	bool "SA1100-based"
 747	select CLKSRC_MMIO
 748	select CPU_SA1100
 749	select ISA
 750	select ARCH_SPARSEMEM_ENABLE
 751	select ARCH_MTD_XIP
 752	select ARCH_HAS_CPUFREQ
 753	select CPU_FREQ
 754	select GENERIC_CLOCKEVENTS
 755	select CLKDEV_LOOKUP
 756	select ARCH_REQUIRE_GPIOLIB
 757	select HAVE_IDE
 758	select NEED_MACH_MEMORY_H
 759	select SPARSE_IRQ
 760	help
 761	  Support for StrongARM 11x0 based boards.
 762
 763config ARCH_S3C24XX
 764	bool "Samsung S3C24XX SoCs"
 765	select GENERIC_GPIO
 766	select ARCH_HAS_CPUFREQ
 767	select HAVE_CLK
 768	select CLKDEV_LOOKUP
 769	select ARCH_USES_GETTIMEOFFSET
 770	select HAVE_S3C2410_I2C if I2C
 771	select HAVE_S3C_RTC if RTC_CLASS
 772	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 773	select NEED_MACH_IO_H
 774	help
 775	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 776	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 777	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 778	  Samsung SMDK2410 development board (and derivatives).
 779
 780config ARCH_S3C64XX
 781	bool "Samsung S3C64XX"
 782	select PLAT_SAMSUNG
 783	select CPU_V6
 784	select ARM_VIC
 785	select HAVE_CLK
 786	select HAVE_TCM
 787	select CLKDEV_LOOKUP
 788	select NO_IOPORT
 789	select ARCH_USES_GETTIMEOFFSET
 790	select ARCH_HAS_CPUFREQ
 791	select ARCH_REQUIRE_GPIOLIB
 792	select SAMSUNG_CLKSRC
 793	select SAMSUNG_IRQ_VIC_TIMER
 794	select S3C_GPIO_TRACK
 795	select S3C_DEV_NAND
 796	select USB_ARCH_HAS_OHCI
 797	select SAMSUNG_GPIOLIB_4BIT
 798	select HAVE_S3C2410_I2C if I2C
 799	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 800	help
 801	  Samsung S3C64XX series based systems
 802
 803config ARCH_S5P64X0
 804	bool "Samsung S5P6440 S5P6450"
 805	select CPU_V6
 806	select GENERIC_GPIO
 807	select HAVE_CLK
 808	select CLKDEV_LOOKUP
 809	select CLKSRC_MMIO
 810	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 811	select GENERIC_CLOCKEVENTS
 812	select HAVE_S3C2410_I2C if I2C
 813	select HAVE_S3C_RTC if RTC_CLASS
 814	help
 815	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 816	  SMDK6450.
 817
 818config ARCH_S5PC100
 819	bool "Samsung S5PC100"
 820	select GENERIC_GPIO
 821	select HAVE_CLK
 822	select CLKDEV_LOOKUP
 823	select CPU_V7
 824	select ARCH_USES_GETTIMEOFFSET
 825	select HAVE_S3C2410_I2C if I2C
 826	select HAVE_S3C_RTC if RTC_CLASS
 827	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 828	help
 829	  Samsung S5PC100 series based systems
 830
 831config ARCH_S5PV210
 832	bool "Samsung S5PV210/S5PC110"
 833	select CPU_V7
 834	select ARCH_SPARSEMEM_ENABLE
 835	select ARCH_HAS_HOLES_MEMORYMODEL
 836	select GENERIC_GPIO
 837	select HAVE_CLK
 838	select CLKDEV_LOOKUP
 839	select CLKSRC_MMIO
 840	select ARCH_HAS_CPUFREQ
 841	select GENERIC_CLOCKEVENTS
 842	select HAVE_S3C2410_I2C if I2C
 843	select HAVE_S3C_RTC if RTC_CLASS
 844	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 845	select NEED_MACH_MEMORY_H
 846	help
 847	  Samsung S5PV210/S5PC110 series based systems
 848
 849config ARCH_EXYNOS
 850	bool "SAMSUNG EXYNOS"
 851	select CPU_V7
 852	select ARCH_SPARSEMEM_ENABLE
 853	select ARCH_HAS_HOLES_MEMORYMODEL
 854	select GENERIC_GPIO
 855	select HAVE_CLK
 856	select CLKDEV_LOOKUP
 857	select ARCH_HAS_CPUFREQ
 858	select GENERIC_CLOCKEVENTS
 859	select HAVE_S3C_RTC if RTC_CLASS
 860	select HAVE_S3C2410_I2C if I2C
 861	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 862	select NEED_MACH_MEMORY_H
 863	help
 864	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 865
 866config ARCH_SHARK
 867	bool "Shark"
 868	select CPU_SA110
 869	select ISA
 870	select ISA_DMA
 871	select ZONE_DMA
 872	select PCI
 873	select ARCH_USES_GETTIMEOFFSET
 874	select NEED_MACH_MEMORY_H
 875	select NEED_MACH_IO_H
 876	help
 877	  Support for the StrongARM based Digital DNARD machine, also known
 878	  as "Shark" (<http://www.shark-linux.de/shark.html>).
 879
 880config ARCH_U300
 881	bool "ST-Ericsson U300 Series"
 882	depends on MMU
 883	select CLKSRC_MMIO
 884	select CPU_ARM926T
 885	select HAVE_TCM
 886	select ARM_AMBA
 887	select ARM_PATCH_PHYS_VIRT
 888	select ARM_VIC
 889	select GENERIC_CLOCKEVENTS
 890	select CLKDEV_LOOKUP
 891	select HAVE_MACH_CLKDEV
 892	select GENERIC_GPIO
 893	select ARCH_REQUIRE_GPIOLIB
 894	help
 895	  Support for ST-Ericsson U300 series mobile platforms.
 896
 897config ARCH_U8500
 898	bool "ST-Ericsson U8500 Series"
 899	depends on MMU
 900	select CPU_V7
 901	select ARM_AMBA
 902	select GENERIC_CLOCKEVENTS
 903	select CLKDEV_LOOKUP
 904	select ARCH_REQUIRE_GPIOLIB
 905	select ARCH_HAS_CPUFREQ
 906	select HAVE_SMP
 907	select MIGHT_HAVE_CACHE_L2X0
 908	help
 909	  Support for ST-Ericsson's Ux500 architecture
 910
 911config ARCH_NOMADIK
 912	bool "STMicroelectronics Nomadik"
 913	select ARM_AMBA
 914	select ARM_VIC
 915	select CPU_ARM926T
 916	select CLKDEV_LOOKUP
 917	select GENERIC_CLOCKEVENTS
 918	select PINCTRL
 919	select MIGHT_HAVE_CACHE_L2X0
 920	select ARCH_REQUIRE_GPIOLIB
 921	help
 922	  Support for the Nomadik platform by ST-Ericsson
 923
 924config ARCH_DAVINCI
 925	bool "TI DaVinci"
 926	select GENERIC_CLOCKEVENTS
 927	select ARCH_REQUIRE_GPIOLIB
 928	select ZONE_DMA
 929	select HAVE_IDE
 930	select CLKDEV_LOOKUP
 931	select GENERIC_ALLOCATOR
 932	select GENERIC_IRQ_CHIP
 933	select ARCH_HAS_HOLES_MEMORYMODEL
 934	help
 935	  Support for TI's DaVinci platform.
 936
 937config ARCH_OMAP
 938	bool "TI OMAP"
 939	select HAVE_CLK
 940	select ARCH_REQUIRE_GPIOLIB
 941	select ARCH_HAS_CPUFREQ
 942	select CLKSRC_MMIO
 943	select GENERIC_CLOCKEVENTS
 944	select ARCH_HAS_HOLES_MEMORYMODEL
 945	help
 946	  Support for TI's OMAP platform (OMAP1/2/3/4).
 947
 948config PLAT_SPEAR
 949	bool "ST SPEAr"
 
 950	select ARM_AMBA
 951	select ARCH_REQUIRE_GPIOLIB
 952	select CLKDEV_LOOKUP
 953	select COMMON_CLK
 954	select CLKSRC_MMIO
 955	select GENERIC_CLOCKEVENTS
 956	select HAVE_CLK
 957	help
 958	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 959
 960config ARCH_VT8500
 961	bool "VIA/WonderMedia 85xx"
 962	select CPU_ARM926T
 963	select GENERIC_GPIO
 964	select ARCH_HAS_CPUFREQ
 965	select GENERIC_CLOCKEVENTS
 966	select ARCH_REQUIRE_GPIOLIB
 967	select HAVE_PWM
 968	help
 969	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 970
 971config ARCH_ZYNQ
 972	bool "Xilinx Zynq ARM Cortex A9 Platform"
 973	select CPU_V7
 974	select GENERIC_CLOCKEVENTS
 975	select CLKDEV_LOOKUP
 976	select ARM_GIC
 
 
 
 
 
 
 
 
 
 977	select ARM_AMBA
 978	select ICST
 979	select MIGHT_HAVE_CACHE_L2X0
 980	select USE_OF
 
 981	help
 982	  Support for Xilinx Zynq ARM Cortex A9 Platform
 983endchoice
 984
 985#
 986# This is sorted alphabetically by mach-* pathname.  However, plat-*
 987# Kconfigs may be included either alphabetically (according to the
 988# plat- suffix) or along side the corresponding mach-* source.
 989#
 
 
 
 
 
 
 
 
 
 
 990source "arch/arm/mach-at91/Kconfig"
 991
 992source "arch/arm/mach-bcmring/Kconfig"
 
 
 
 
 993
 994source "arch/arm/mach-clps711x/Kconfig"
 995
 996source "arch/arm/mach-cns3xxx/Kconfig"
 997
 998source "arch/arm/mach-davinci/Kconfig"
 999
 
 
1000source "arch/arm/mach-dove/Kconfig"
1001
1002source "arch/arm/mach-ep93xx/Kconfig"
1003
 
 
1004source "arch/arm/mach-footbridge/Kconfig"
1005
1006source "arch/arm/mach-gemini/Kconfig"
1007
1008source "arch/arm/mach-h720x/Kconfig"
1009
1010source "arch/arm/mach-integrator/Kconfig"
1011
1012source "arch/arm/mach-iop32x/Kconfig"
1013
1014source "arch/arm/mach-iop33x/Kconfig"
1015
1016source "arch/arm/mach-iop13xx/Kconfig"
1017
1018source "arch/arm/mach-ixp4xx/Kconfig"
1019
1020source "arch/arm/mach-kirkwood/Kconfig"
1021
1022source "arch/arm/mach-ks8695/Kconfig"
1023
1024source "arch/arm/mach-lpc32xx/Kconfig"
1025
1026source "arch/arm/mach-msm/Kconfig"
 
 
 
 
 
 
 
 
 
 
1027
1028source "arch/arm/mach-mv78xx0/Kconfig"
1029
1030source "arch/arm/plat-mxc/Kconfig"
1031
1032source "arch/arm/mach-mxs/Kconfig"
1033
1034source "arch/arm/mach-netx/Kconfig"
1035
1036source "arch/arm/mach-nomadik/Kconfig"
1037source "arch/arm/plat-nomadik/Kconfig"
1038
1039source "arch/arm/plat-omap/Kconfig"
 
 
1040
1041source "arch/arm/mach-omap1/Kconfig"
1042
1043source "arch/arm/mach-omap2/Kconfig"
1044
1045source "arch/arm/mach-orion5x/Kconfig"
1046
 
 
1047source "arch/arm/mach-pxa/Kconfig"
1048source "arch/arm/plat-pxa/Kconfig"
1049
1050source "arch/arm/mach-mmp/Kconfig"
1051
1052source "arch/arm/mach-realview/Kconfig"
1053
1054source "arch/arm/mach-sa1100/Kconfig"
1055
1056source "arch/arm/plat-samsung/Kconfig"
1057source "arch/arm/plat-s3c24xx/Kconfig"
1058
1059source "arch/arm/plat-spear/Kconfig"
1060
1061source "arch/arm/mach-s3c24xx/Kconfig"
1062if ARCH_S3C24XX
1063source "arch/arm/mach-s3c2412/Kconfig"
1064source "arch/arm/mach-s3c2440/Kconfig"
1065endif
1066
1067if ARCH_S3C64XX
1068source "arch/arm/mach-s3c64xx/Kconfig"
1069endif
1070
1071source "arch/arm/mach-s5p64x0/Kconfig"
1072
1073source "arch/arm/mach-s5pc100/Kconfig"
1074
1075source "arch/arm/mach-s5pv210/Kconfig"
1076
1077source "arch/arm/mach-exynos/Kconfig"
1078
1079source "arch/arm/mach-shmobile/Kconfig"
 
 
 
 
 
 
1080
1081source "arch/arm/mach-tegra/Kconfig"
1082
1083source "arch/arm/mach-u300/Kconfig"
1084
1085source "arch/arm/mach-ux500/Kconfig"
1086
1087source "arch/arm/mach-versatile/Kconfig"
1088
1089source "arch/arm/mach-vexpress/Kconfig"
1090source "arch/arm/plat-versatile/Kconfig"
1091
1092source "arch/arm/mach-vt8500/Kconfig"
1093
1094source "arch/arm/mach-w90x900/Kconfig"
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1095
1096# Definitions to make life easier
1097config ARCH_ACORN
1098	bool
1099
1100config PLAT_IOP
1101	bool
1102	select GENERIC_CLOCKEVENTS
1103
1104config PLAT_ORION
1105	bool
1106	select CLKSRC_MMIO
1107	select GENERIC_IRQ_CHIP
1108	select COMMON_CLK
1109
1110config PLAT_PXA
1111	bool
 
1112
1113config PLAT_VERSATILE
1114	bool
1115
1116config ARM_TIMER_SP804
1117	bool
1118	select CLKSRC_MMIO
1119	select HAVE_SCHED_CLOCK
1120
1121source arch/arm/mm/Kconfig
1122
1123config ARM_NR_BANKS
1124	int
1125	default 16 if ARCH_EP93XX
1126	default 8
1127
1128config IWMMXT
1129	bool "Enable iWMMXt support"
1130	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1131	default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1132	help
1133	  Enable support for iWMMXt context switching at run time if
1134	  running on a CPU that supports it.
1135
1136config XSCALE_PMU
1137	bool
1138	depends on CPU_XSCALE
1139	default y
1140
1141config CPU_HAS_PMU
1142	depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1143		   (!ARCH_OMAP3 || OMAP3_EMU)
1144	default y
1145	bool
1146
1147config MULTI_IRQ_HANDLER
1148	bool
1149	help
1150	  Allow each machine to specify it's own IRQ handler at run time.
1151
1152if !MMU
1153source "arch/arm/Kconfig-nommu"
1154endif
1155
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1156config ARM_ERRATA_326103
1157	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1158	depends on CPU_V6
1159	help
1160	  Executing a SWP instruction to read-only memory does not set bit 11
1161	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1162	  treat the access as a read, preventing a COW from occurring and
1163	  causing the faulting task to livelock.
1164
1165config ARM_ERRATA_411920
1166	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1167	depends on CPU_V6 || CPU_V6K
1168	help
1169	  Invalidation of the Instruction Cache operation can
1170	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1171	  It does not affect the MPCore. This option enables the ARM Ltd.
1172	  recommended workaround.
1173
1174config ARM_ERRATA_430973
1175	bool "ARM errata: Stale prediction on replaced interworking branch"
1176	depends on CPU_V7
1177	help
1178	  This option enables the workaround for the 430973 Cortex-A8
1179	  (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1180	  interworking branch is replaced with another code sequence at the
1181	  same virtual address, whether due to self-modifying code or virtual
1182	  to physical address re-mapping, Cortex-A8 does not recover from the
1183	  stale interworking branch prediction. This results in Cortex-A8
1184	  executing the new code sequence in the incorrect ARM or Thumb state.
1185	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1186	  and also flushes the branch target cache at every context switch.
1187	  Note that setting specific bits in the ACTLR register may not be
1188	  available in non-secure mode.
1189
1190config ARM_ERRATA_458693
1191	bool "ARM errata: Processor deadlock when a false hazard is created"
1192	depends on CPU_V7
 
1193	help
1194	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1195	  erratum. For very specific sequences of memory operations, it is
1196	  possible for a hazard condition intended for a cache line to instead
1197	  be incorrectly associated with a different cache line. This false
1198	  hazard might then cause a processor deadlock. The workaround enables
1199	  the L1 caching of the NEON accesses and disables the PLD instruction
1200	  in the ACTLR register. Note that setting specific bits in the ACTLR
1201	  register may not be available in non-secure mode.
1202
1203config ARM_ERRATA_460075
1204	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1205	depends on CPU_V7
 
1206	help
1207	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1208	  erratum. Any asynchronous access to the L2 cache may encounter a
1209	  situation in which recent store transactions to the L2 cache are lost
1210	  and overwritten with stale memory contents from external memory. The
1211	  workaround disables the write-allocate mode for the L2 cache via the
1212	  ACTLR register. Note that setting specific bits in the ACTLR register
1213	  may not be available in non-secure mode.
1214
1215config ARM_ERRATA_742230
1216	bool "ARM errata: DMB operation may be faulty"
1217	depends on CPU_V7 && SMP
 
1218	help
1219	  This option enables the workaround for the 742230 Cortex-A9
1220	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1221	  between two write operations may not ensure the correct visibility
1222	  ordering of the two writes. This workaround sets a specific bit in
1223	  the diagnostic register of the Cortex-A9 which causes the DMB
1224	  instruction to behave as a DSB, ensuring the correct behaviour of
1225	  the two writes.
1226
1227config ARM_ERRATA_742231
1228	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1229	depends on CPU_V7 && SMP
 
1230	help
1231	  This option enables the workaround for the 742231 Cortex-A9
1232	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1233	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1234	  accessing some data located in the same cache line, may get corrupted
1235	  data due to bad handling of the address hazard when the line gets
1236	  replaced from one of the CPUs at the same time as another CPU is
1237	  accessing it. This workaround sets specific bits in the diagnostic
1238	  register of the Cortex-A9 which reduces the linefill issuing
1239	  capabilities of the processor.
1240
1241config PL310_ERRATA_588369
1242	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1243	depends on CACHE_L2X0
1244	help
1245	   The PL310 L2 cache controller implements three types of Clean &
1246	   Invalidate maintenance operations: by Physical Address
1247	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1248	   They are architecturally defined to behave as the execution of a
1249	   clean operation followed immediately by an invalidate operation,
1250	   both performing to the same memory location. This functionality
1251	   is not correctly implemented in PL310 as clean lines are not
1252	   invalidated as a result of these operations.
1253
1254config ARM_ERRATA_720789
1255	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1256	depends on CPU_V7
1257	help
1258	  This option enables the workaround for the 720789 Cortex-A9 (prior to
1259	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1260	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1261	  As a consequence of this erratum, some TLB entries which should be
1262	  invalidated are not, resulting in an incoherency in the system page
1263	  tables. The workaround changes the TLB flushing routines to invalidate
1264	  entries regardless of the ASID.
1265
1266config PL310_ERRATA_727915
1267	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1268	depends on CACHE_L2X0
1269	help
1270	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1271	  operation (offset 0x7FC). This operation runs in background so that
1272	  PL310 can handle normal accesses while it is in progress. Under very
1273	  rare circumstances, due to this erratum, write data can be lost when
1274	  PL310 treats a cacheable write transaction during a Clean &
1275	  Invalidate by Way operation.
1276
1277config ARM_ERRATA_743622
1278	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1279	depends on CPU_V7
 
1280	help
1281	  This option enables the workaround for the 743622 Cortex-A9
1282	  (r2p*) erratum. Under very rare conditions, a faulty
1283	  optimisation in the Cortex-A9 Store Buffer may lead to data
1284	  corruption. This workaround sets a specific bit in the diagnostic
1285	  register of the Cortex-A9 which disables the Store Buffer
1286	  optimisation, preventing the defect from occurring. This has no
1287	  visible impact on the overall performance or power consumption of the
1288	  processor.
1289
1290config ARM_ERRATA_751472
1291	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1292	depends on CPU_V7
 
1293	help
1294	  This option enables the workaround for the 751472 Cortex-A9 (prior
1295	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1296	  completion of a following broadcasted operation if the second
1297	  operation is received by a CPU before the ICIALLUIS has completed,
1298	  potentially leading to corrupted entries in the cache or TLB.
1299
1300config PL310_ERRATA_753970
1301	bool "PL310 errata: cache sync operation may be faulty"
1302	depends on CACHE_PL310
1303	help
1304	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1305
1306	  Under some condition the effect of cache sync operation on
1307	  the store buffer still remains when the operation completes.
1308	  This means that the store buffer is always asked to drain and
1309	  this prevents it from merging any further writes. The workaround
1310	  is to replace the normal offset of cache sync operation (0x730)
1311	  by another offset targeting an unmapped PL310 register 0x740.
1312	  This has the same effect as the cache sync operation: store buffer
1313	  drain and waiting for all buffers empty.
1314
1315config ARM_ERRATA_754322
1316	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1317	depends on CPU_V7
1318	help
1319	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1320	  r3p*) erratum. A speculative memory access may cause a page table walk
1321	  which starts prior to an ASID switch but completes afterwards. This
1322	  can populate the micro-TLB with a stale entry which may be hit with
1323	  the new ASID. This workaround places two dsb instructions in the mm
1324	  switching code so that no page table walks can cross the ASID switch.
1325
1326config ARM_ERRATA_754327
1327	bool "ARM errata: no automatic Store Buffer drain"
1328	depends on CPU_V7 && SMP
1329	help
1330	  This option enables the workaround for the 754327 Cortex-A9 (prior to
1331	  r2p0) erratum. The Store Buffer does not have any automatic draining
1332	  mechanism and therefore a livelock may occur if an external agent
1333	  continuously polls a memory location waiting to observe an update.
1334	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
1335	  written polling loops from denying visibility of updates to memory.
1336
1337config ARM_ERRATA_364296
1338	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1339	depends on CPU_V6 && !SMP
1340	help
1341	  This options enables the workaround for the 364296 ARM1136
1342	  r0p2 erratum (possible cache data corruption with
1343	  hit-under-miss enabled). It sets the undocumented bit 31 in
1344	  the auxiliary control register and the FI bit in the control
1345	  register, thus disabling hit-under-miss without putting the
1346	  processor into full low interrupt latency mode. ARM11MPCore
1347	  is not affected.
1348
1349config ARM_ERRATA_764369
1350	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1351	depends on CPU_V7 && SMP
1352	help
1353	  This option enables the workaround for erratum 764369
1354	  affecting Cortex-A9 MPCore with two or more processors (all
1355	  current revisions). Under certain timing circumstances, a data
1356	  cache line maintenance operation by MVA targeting an Inner
1357	  Shareable memory region may fail to proceed up to either the
1358	  Point of Coherency or to the Point of Unification of the
1359	  system. This workaround adds a DSB instruction before the
1360	  relevant cache maintenance functions and sets a specific bit
1361	  in the diagnostic control register of the SCU.
1362
1363config PL310_ERRATA_769419
1364	bool "PL310 errata: no automatic Store Buffer drain"
1365	depends on CACHE_L2X0
1366	help
1367	  On revisions of the PL310 prior to r3p2, the Store Buffer does
1368	  not automatically drain. This can cause normal, non-cacheable
1369	  writes to be retained when the memory system is idle, leading
1370	  to suboptimal I/O performance for drivers using coherent DMA.
1371	  This option adds a write barrier to the cpu_idle loop so that,
1372	  on systems with an outer cache, the store buffer is drained
1373	  explicitly.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1374
1375endmenu
1376
1377source "arch/arm/common/Kconfig"
1378
1379menu "Bus support"
1380
1381config ARM_AMBA
1382	bool
1383
1384config ISA
1385	bool
1386	help
1387	  Find out whether you have ISA slots on your motherboard.  ISA is the
1388	  name of a bus system, i.e. the way the CPU talks to the other stuff
1389	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1390	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1391	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1392
1393# Select ISA DMA controller support
1394config ISA_DMA
1395	bool
1396	select ISA_DMA_API
1397
1398# Select ISA DMA interface
1399config ISA_DMA_API
1400	bool
1401
1402config PCI
1403	bool "PCI support" if MIGHT_HAVE_PCI
1404	help
1405	  Find out whether you have a PCI motherboard. PCI is the name of a
1406	  bus system, i.e. the way the CPU talks to the other stuff inside
1407	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1408	  VESA. If you have PCI, say Y, otherwise N.
1409
1410config PCI_DOMAINS
1411	bool
1412	depends on PCI
1413
1414config PCI_NANOENGINE
1415	bool "BSE nanoEngine PCI support"
1416	depends on SA1100_NANOENGINE
1417	help
1418	  Enable PCI on the BSE nanoEngine board.
1419
1420config PCI_SYSCALL
1421	def_bool PCI
1422
1423# Select the host bridge type
1424config PCI_HOST_VIA82C505
1425	bool
1426	depends on PCI && ARCH_SHARK
1427	default y
1428
1429config PCI_HOST_ITE8152
1430	bool
1431	depends on PCI && MACH_ARMCORE
1432	default y
1433	select DMABOUNCE
1434
1435source "drivers/pci/Kconfig"
1436
1437source "drivers/pcmcia/Kconfig"
1438
1439endmenu
1440
1441menu "Kernel Features"
1442
1443config HAVE_SMP
1444	bool
1445	help
1446	  This option should be selected by machines which have an SMP-
1447	  capable CPU.
1448
1449	  The only effect of this option is to make the SMP-related
1450	  options available to the user for configuration.
1451
1452config SMP
1453	bool "Symmetric Multi-Processing"
1454	depends on CPU_V6K || CPU_V7
1455	depends on GENERIC_CLOCKEVENTS
1456	depends on HAVE_SMP
1457	depends on MMU
1458	select USE_GENERIC_SMP_HELPERS
1459	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1460	help
1461	  This enables support for systems with more than one CPU. If you have
1462	  a system with only one CPU, like most personal computers, say N. If
1463	  you have a system with more than one CPU, say Y.
1464
1465	  If you say N here, the kernel will run on single and multiprocessor
1466	  machines, but will use only one CPU of a multiprocessor machine. If
1467	  you say Y here, the kernel will run on many, but not all, single
1468	  processor machines. On a single processor machine, the kernel will
1469	  run faster if you say N here.
1470
1471	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
1472	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1473	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1474
1475	  If you don't know what to do here, say N.
1476
1477config SMP_ON_UP
1478	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1479	depends on EXPERIMENTAL
1480	depends on SMP && !XIP_KERNEL
1481	default y
1482	help
1483	  SMP kernels contain instructions which fail on non-SMP processors.
1484	  Enabling this option allows the kernel to modify itself to make
1485	  these instructions safe.  Disabling it allows about 1K of space
1486	  savings.
1487
1488	  If you don't know what to do here, say Y.
1489
 
 
 
 
 
 
 
 
 
 
1490config ARM_CPU_TOPOLOGY
1491	bool "Support cpu topology definition"
1492	depends on SMP && CPU_V7
1493	default y
1494	help
1495	  Support ARM cpu topology definition. The MPIDR register defines
1496	  affinity between processors which is then used to describe the cpu
1497	  topology of an ARM System.
1498
1499config SCHED_MC
1500	bool "Multi-core scheduler support"
1501	depends on ARM_CPU_TOPOLOGY
1502	help
1503	  Multi-core scheduler support improves the CPU scheduler's decision
1504	  making when dealing with multi-core CPU chips at a cost of slightly
1505	  increased overhead in some places. If unsure say N here.
1506
1507config SCHED_SMT
1508	bool "SMT scheduler support"
1509	depends on ARM_CPU_TOPOLOGY
1510	help
1511	  Improves the CPU scheduler's decision making when dealing with
1512	  MultiThreading at a cost of slightly increased overhead in some
1513	  places. If unsure say N here.
1514
1515config HAVE_ARM_SCU
1516	bool
1517	help
1518	  This option enables support for the ARM system coherency unit
1519
1520config ARM_ARCH_TIMER
1521	bool "Architected timer support"
1522	depends on CPU_V7
 
1523	help
1524	  This option enables support for the ARM architected timer
1525
1526config HAVE_ARM_TWD
1527	bool
1528	depends on SMP
1529	help
1530	  This options enables support for the ARM timer and watchdog unit
1531
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1532choice
1533	prompt "Memory split"
 
1534	default VMSPLIT_3G
1535	help
1536	  Select the desired split between kernel and user memory.
1537
1538	  If you are not absolutely sure what you are doing, leave this
1539	  option alone!
1540
1541	config VMSPLIT_3G
1542		bool "3G/1G user/kernel split"
 
 
 
1543	config VMSPLIT_2G
1544		bool "2G/2G user/kernel split"
1545	config VMSPLIT_1G
1546		bool "1G/3G user/kernel split"
1547endchoice
1548
1549config PAGE_OFFSET
1550	hex
 
1551	default 0x40000000 if VMSPLIT_1G
1552	default 0x80000000 if VMSPLIT_2G
 
1553	default 0xC0000000
1554
 
 
 
 
 
 
 
 
 
1555config NR_CPUS
1556	int "Maximum number of CPUs (2-32)"
1557	range 2 32
 
1558	depends on SMP
1559	default "4"
 
 
 
 
 
1560
1561config HOTPLUG_CPU
1562	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1563	depends on SMP && HOTPLUG && EXPERIMENTAL
 
1564	help
1565	  Say Y here to experiment with turning CPUs off and on.  CPUs
1566	  can be controlled through /sys/devices/system/cpu.
1567
1568config LOCAL_TIMERS
1569	bool "Use local timer interrupts"
1570	depends on SMP
1571	default y
1572	select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1573	help
1574	  Enable support for local timers on SMP platforms, rather then the
1575	  legacy IPI broadcast method.  Local timers allows the system
1576	  accounting to be spread across the timer interval, preventing a
1577	  "thundering herd" at every timer tick.
1578
1579config ARCH_NR_GPIO
1580	int
1581	default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1582	default 355 if ARCH_U8500
1583	default 264 if MACH_H4700
1584	default 0
1585	help
1586	  Maximum number of GPIOs in the system.
1587
1588	  If unsure, leave the default value.
 
 
1589
1590source kernel/Kconfig.preempt
 
1591
1592config HZ
1593	int
1594	default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1595		ARCH_S5PV210 || ARCH_EXYNOS4
1596	default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1597	default AT91_TIMER_HZ if ARCH_AT91
1598	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1599	default 100
1600
1601config THUMB2_KERNEL
1602	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1603	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1604	select AEABI
1605	select ARM_ASM_UNIFIED
1606	select ARM_UNWIND
1607	help
1608	  By enabling this option, the kernel will be compiled in
1609	  Thumb-2 mode. A compiler/assembler that understand the unified
1610	  ARM-Thumb syntax is needed.
1611
1612	  If unsure, say N.
 
1613
1614config THUMB2_AVOID_R_ARM_THM_JUMP11
1615	bool "Work around buggy Thumb-2 short branch relocations in gas"
1616	depends on THUMB2_KERNEL && MODULES
1617	default y
1618	help
1619	  Various binutils versions can resolve Thumb-2 branches to
1620	  locally-defined, preemptible global symbols as short-range "b.n"
1621	  branch instructions.
1622
1623	  This is a problem, because there's no guarantee the final
1624	  destination of the symbol, or any candidate locations for a
1625	  trampoline, are within range of the branch.  For this reason, the
1626	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1627	  relocation in modules at all, and it makes little sense to add
1628	  support.
1629
1630	  The symptom is that the kernel fails with an "unsupported
1631	  relocation" error when loading some modules.
1632
1633	  Until fixed tools are available, passing
1634	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
1635	  code which hits this problem, at the cost of a bit of extra runtime
1636	  stack usage in some cases.
 
 
 
 
 
1637
1638	  The problem is described in more detail at:
1639	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
1640
1641	  Only Thumb-2 kernels are affected.
 
 
 
 
 
 
 
1642
1643	  Unless you are sure your tools don't have this problem, say Y.
1644
1645config ARM_ASM_UNIFIED
1646	bool
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1647
1648config AEABI
1649	bool "Use the ARM EABI to compile the kernel"
 
 
1650	help
1651	  This option allows for the kernel to be compiled using the latest
1652	  ARM ABI (aka EABI).  This is only useful if you are using a user
1653	  space environment that is also compiled with EABI.
1654
1655	  Since there are major incompatibilities between the legacy ABI and
1656	  EABI, especially with regard to structure member alignment, this
1657	  option also changes the kernel syscall calling convention to
1658	  disambiguate both ABIs and allow for backward compatibility support
1659	  (selected with CONFIG_OABI_COMPAT).
1660
1661	  To use this you need GCC version 4.0.0 or later.
1662
1663config OABI_COMPAT
1664	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1665	depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1666	default y
1667	help
1668	  This option preserves the old syscall interface along with the
1669	  new (ARM EABI) one. It also provides a compatibility layer to
1670	  intercept syscalls that have structure arguments which layout
1671	  in memory differs between the legacy ABI and the new ARM EABI
1672	  (only for non "thumb" binaries). This option adds a tiny
1673	  overhead to all syscalls and produces a slightly larger kernel.
 
 
 
 
 
1674	  If you know you'll be using only pure EABI user space then you
1675	  can say N here. If this option is not selected and you attempt
1676	  to execute a legacy ABI binary then the result will be
1677	  UNPREDICTABLE (in fact it can be predicted that it won't work
1678	  at all). If in doubt say Y.
1679
1680config ARCH_HAS_HOLES_MEMORYMODEL
1681	bool
1682
1683config ARCH_SPARSEMEM_ENABLE
1684	bool
1685
1686config ARCH_SPARSEMEM_DEFAULT
1687	def_bool ARCH_SPARSEMEM_ENABLE
1688
1689config ARCH_SELECT_MEMORY_MODEL
1690	def_bool ARCH_SPARSEMEM_ENABLE
1691
1692config HAVE_ARCH_PFN_VALID
1693	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 
 
 
 
1694
1695config HIGHMEM
1696	bool "High Memory Support"
1697	depends on MMU
 
 
1698	help
1699	  The address space of ARM processors is only 4 Gigabytes large
1700	  and it has to accommodate user address space, kernel address
1701	  space as well as some memory mapped IO. That means that, if you
1702	  have a large amount of physical memory and/or IO, not all of the
1703	  memory can be "permanently mapped" by the kernel. The physical
1704	  memory that is not permanently mapped is called "high memory".
1705
1706	  Depending on the selected kernel/user memory split, minimum
1707	  vmalloc space and actual amount of RAM, you may not need this
1708	  option which should result in a slightly faster kernel.
1709
1710	  If unsure, say n.
1711
1712config HIGHPTE
1713	bool "Allocate 2nd-level pagetables from highmem"
1714	depends on HIGHMEM
1715
1716config HW_PERF_EVENTS
1717	bool "Enable hardware performance counter support for perf events"
1718	depends on PERF_EVENTS && CPU_HAS_PMU
1719	default y
1720	help
1721	  Enable hardware performance counter support for perf events. If
1722	  disabled, perf events will use software events only.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1723
1724source "mm/Kconfig"
 
 
1725
1726config FORCE_MAX_ZONEORDER
1727	int "Maximum zone order" if ARCH_SHMOBILE
1728	range 11 64 if ARCH_SHMOBILE
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1729	default "9" if SA1111
1730	default "11"
1731	help
1732	  The kernel memory allocator divides physically contiguous memory
1733	  blocks into "zones", where each zone is a power of two number of
1734	  pages.  This option selects the largest power of two that the kernel
1735	  keeps in the memory allocator.  If you need to allocate very large
1736	  blocks of physically contiguous memory, then you may need to
1737	  increase this value.
1738
1739	  This config option is actually maximum order plus one. For example,
1740	  a value of 11 means that the largest free memory block is 2^10 pages.
1741
1742config LEDS
1743	bool "Timer and CPU usage LEDs"
1744	depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1745		   ARCH_EBSA285 || ARCH_INTEGRATOR || \
1746		   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1747		   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1748		   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1749		   ARCH_AT91 || ARCH_DAVINCI || \
1750		   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1751	help
1752	  If you say Y here, the LEDs on your machine will be used
1753	  to provide useful information about your current system status.
1754
1755	  If you are compiling a kernel for a NetWinder or EBSA-285, you will
1756	  be able to select which LEDs are active using the options below. If
1757	  you are compiling a kernel for the EBSA-110 or the LART however, the
1758	  red LED will simply flash regularly to indicate that the system is
1759	  still functional. It is safe to say Y here if you have a CATS
1760	  system, but the driver will do nothing.
1761
1762config LEDS_TIMER
1763	bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1764			    OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1765			    || MACH_OMAP_PERSEUS2
1766	depends on LEDS
1767	depends on !GENERIC_CLOCKEVENTS
1768	default y if ARCH_EBSA110
1769	help
1770	  If you say Y here, one of the system LEDs (the green one on the
1771	  NetWinder, the amber one on the EBSA285, or the red one on the LART)
1772	  will flash regularly to indicate that the system is still
1773	  operational. This is mainly useful to kernel hackers who are
1774	  debugging unstable kernels.
1775
1776	  The LART uses the same LED for both Timer LED and CPU usage LED
1777	  functions. You may choose to use both, but the Timer LED function
1778	  will overrule the CPU usage LED.
1779
1780config LEDS_CPU
1781	bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1782			!ARCH_OMAP) \
1783			|| OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1784			|| MACH_OMAP_PERSEUS2
1785	depends on LEDS
1786	help
1787	  If you say Y here, the red LED will be used to give a good real
1788	  time indication of CPU usage, by lighting whenever the idle task
1789	  is not currently executing.
1790
1791	  The LART uses the same LED for both Timer LED and CPU usage LED
1792	  functions. You may choose to use both, but the Timer LED function
1793	  will overrule the CPU usage LED.
1794
1795config ALIGNMENT_TRAP
1796	bool
1797	depends on CPU_CP15_MMU
1798	default y if !ARCH_EBSA110
1799	select HAVE_PROC_CPU if PROC_FS
1800	help
1801	  ARM processors cannot fetch/store information which is not
1802	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1803	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1804	  fetch/store instructions will be emulated in software if you say
1805	  here, which has a severe performance impact. This is necessary for
1806	  correct operation of some network protocols. With an IP-only
1807	  configuration it is safe to say N, otherwise say Y.
1808
1809config UACCESS_WITH_MEMCPY
1810	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1811	depends on MMU && EXPERIMENTAL
1812	default y if CPU_FEROCEON
1813	help
1814	  Implement faster copy_to_user and clear_user methods for CPU
1815	  cores where a 8-word STM instruction give significantly higher
1816	  memory write throughput than a sequence of individual 32bit stores.
1817
1818	  A possible side effect is a slight increase in scheduling latency
1819	  between threads sharing the same address space if they invoke
1820	  such copy operations with large buffers.
1821
1822	  However, if the CPU data cache is using a write-allocate mode,
1823	  this option is unlikely to provide any performance gain.
1824
1825config SECCOMP
1826	bool
1827	prompt "Enable seccomp to safely compute untrusted bytecode"
1828	---help---
1829	  This kernel feature is useful for number crunching applications
1830	  that may need to compute untrusted bytecode during their
1831	  execution. By using pipes or other transports made available to
1832	  the process as file descriptors supporting the read/write
1833	  syscalls, it's possible to isolate those applications in
1834	  their own address space using seccomp. Once seccomp is
1835	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1836	  and the task is only allowed to execute a few safe syscalls
1837	  defined by each seccomp mode.
1838
1839config CC_STACKPROTECTOR
1840	bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1841	depends on EXPERIMENTAL
1842	help
1843	  This option turns on the -fstack-protector GCC feature. This
1844	  feature puts, at the beginning of functions, a canary value on
1845	  the stack just before the return address, and validates
1846	  the value just before actually returning.  Stack based buffer
1847	  overflows (that need to overwrite this return address) now also
1848	  overwrite the canary, which gets detected and the attack is then
1849	  neutralized via a kernel panic.
1850	  This feature requires gcc version 4.2 or above.
1851
1852config DEPRECATED_PARAM_STRUCT
1853	bool "Provide old way to pass kernel parameters"
 
1854	help
1855	  This was deprecated in 2001 and announced to live on for 5 years.
1856	  Some old boot loaders still use this way.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1857
1858endmenu
1859
1860menu "Boot options"
1861
1862config USE_OF
1863	bool "Flattened Device Tree support"
1864	select OF
1865	select OF_EARLY_FLATTREE
1866	select IRQ_DOMAIN
 
1867	help
1868	  Include support for flattened device tree machine descriptions.
1869
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1870# Compressed boot loader in ROM.  Yes, we really want to ask about
1871# TEXT and BSS so we preserve their values in the config files.
1872config ZBOOT_ROM_TEXT
1873	hex "Compressed ROM boot loader base address"
1874	default "0"
1875	help
1876	  The physical address at which the ROM-able zImage is to be
1877	  placed in the target.  Platforms which normally make use of
1878	  ROM-able zImage formats normally set this to a suitable
1879	  value in their defconfig file.
1880
1881	  If ZBOOT_ROM is not enabled, this has no effect.
1882
1883config ZBOOT_ROM_BSS
1884	hex "Compressed ROM boot loader BSS address"
1885	default "0"
1886	help
1887	  The base address of an area of read/write memory in the target
1888	  for the ROM-able zImage which must be available while the
1889	  decompressor is running. It must be large enough to hold the
1890	  entire decompressed kernel plus an additional 128 KiB.
1891	  Platforms which normally make use of ROM-able zImage formats
1892	  normally set this to a suitable value in their defconfig file.
1893
1894	  If ZBOOT_ROM is not enabled, this has no effect.
1895
1896config ZBOOT_ROM
1897	bool "Compressed boot loader in ROM/flash"
1898	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
 
1899	help
1900	  Say Y here if you intend to execute your compressed kernel image
1901	  (zImage) directly from ROM or flash.  If unsure, say N.
1902
1903choice
1904	prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1905	depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1906	default ZBOOT_ROM_NONE
1907	help
1908	  Include experimental SD/MMC loading code in the ROM-able zImage.
1909	  With this enabled it is possible to write the ROM-able zImage
1910	  kernel image to an MMC or SD card and boot the kernel straight
1911	  from the reset vector. At reset the processor Mask ROM will load
1912	  the first part of the ROM-able zImage which in turn loads the
1913	  rest the kernel image to RAM.
1914
1915config ZBOOT_ROM_NONE
1916	bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1917	help
1918	  Do not load image from SD or MMC
1919
1920config ZBOOT_ROM_MMCIF
1921	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1922	help
1923	  Load image from MMCIF hardware block.
1924
1925config ZBOOT_ROM_SH_MOBILE_SDHI
1926	bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1927	help
1928	  Load image from SDHI hardware block
1929
1930endchoice
1931
1932config ARM_APPENDED_DTB
1933	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1934	depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1935	help
1936	  With this option, the boot code will look for a device tree binary
1937	  (DTB) appended to zImage
1938	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1939
1940	  This is meant as a backward compatibility convenience for those
1941	  systems with a bootloader that can't be upgraded to accommodate
1942	  the documented boot protocol using a device tree.
1943
1944	  Beware that there is very little in terms of protection against
1945	  this option being confused by leftover garbage in memory that might
1946	  look like a DTB header after a reboot if no actual DTB is appended
1947	  to zImage.  Do not leave this option active in a production kernel
1948	  if you don't intend to always append a DTB.  Proper passing of the
1949	  location into r2 of a bootloader provided DTB is always preferable
1950	  to this option.
1951
1952config ARM_ATAG_DTB_COMPAT
1953	bool "Supplement the appended DTB with traditional ATAG information"
1954	depends on ARM_APPENDED_DTB
1955	help
1956	  Some old bootloaders can't be updated to a DTB capable one, yet
1957	  they provide ATAGs with memory configuration, the ramdisk address,
1958	  the kernel cmdline string, etc.  Such information is dynamically
1959	  provided by the bootloader and can't always be stored in a static
1960	  DTB.  To allow a device tree enabled kernel to be used with such
1961	  bootloaders, this option allows zImage to extract the information
1962	  from the ATAG list and store it at run time into the appended DTB.
1963
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1964config CMDLINE
1965	string "Default kernel command string"
1966	default ""
1967	help
1968	  On some architectures (EBSA110 and CATS), there is currently no way
1969	  for the boot loader to pass arguments to the kernel. For these
1970	  architectures, you should supply some command-line options at build
1971	  time by entering them here. As a minimum, you should specify the
1972	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
1973
1974choice
1975	prompt "Kernel command line type" if CMDLINE != ""
1976	default CMDLINE_FROM_BOOTLOADER
1977
1978config CMDLINE_FROM_BOOTLOADER
1979	bool "Use bootloader kernel arguments if available"
1980	help
1981	  Uses the command-line options passed by the boot loader. If
1982	  the boot loader doesn't provide any, the default kernel command
1983	  string provided in CMDLINE will be used.
1984
1985config CMDLINE_EXTEND
1986	bool "Extend bootloader kernel arguments"
1987	help
1988	  The command-line arguments provided by the boot loader will be
1989	  appended to the default kernel command string.
1990
1991config CMDLINE_FORCE
1992	bool "Always use the default kernel command string"
1993	help
1994	  Always use the default kernel command string, even if the boot
1995	  loader passes other arguments to the kernel.
1996	  This is useful if you cannot or don't want to change the
1997	  command-line options your boot loader passes to the kernel.
1998endchoice
1999
2000config XIP_KERNEL
2001	bool "Kernel Execute-In-Place from ROM"
2002	depends on !ZBOOT_ROM && !ARM_LPAE
 
2003	help
2004	  Execute-In-Place allows the kernel to run from non-volatile storage
2005	  directly addressable by the CPU, such as NOR flash. This saves RAM
2006	  space since the text section of the kernel is not loaded from flash
2007	  to RAM.  Read-write sections, such as the data section and stack,
2008	  are still copied to RAM.  The XIP kernel is not compressed since
2009	  it has to run directly from flash, so it will take more space to
2010	  store it.  The flash address used to link the kernel object files,
2011	  and for storing it, is configuration dependent. Therefore, if you
2012	  say Y here, you must know the proper physical address where to
2013	  store the kernel image depending on your own flash memory usage.
2014
2015	  Also note that the make target becomes "make xipImage" rather than
2016	  "make zImage" or "make Image".  The final kernel binary to put in
2017	  ROM memory will be arch/arm/boot/xipImage.
2018
2019	  If unsure, say N.
2020
2021config XIP_PHYS_ADDR
2022	hex "XIP Kernel Physical Location"
2023	depends on XIP_KERNEL
2024	default "0x00080000"
2025	help
2026	  This is the physical address in your flash memory the kernel will
2027	  be linked for and stored to.  This address is dependent on your
2028	  own flash usage.
2029
 
 
 
 
 
 
 
 
 
 
 
2030config KEXEC
2031	bool "Kexec system call (EXPERIMENTAL)"
2032	depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
 
 
2033	help
2034	  kexec is a system call that implements the ability to shutdown your
2035	  current kernel, and to start another kernel.  It is like a reboot
2036	  but it is independent of the system firmware.   And like a reboot
2037	  you can start any kernel with it, not just Linux.
2038
2039	  It is an ongoing process to be certain the hardware in a machine
2040	  is properly shutdown, so do not be surprised if this code does not
2041	  initially work for you.  It may help to enable device hotplugging
2042	  support.
2043
2044config ATAGS_PROC
2045	bool "Export atags in procfs"
2046	depends on KEXEC
2047	default y
2048	help
2049	  Should the atags used to boot the kernel be exported in an "atags"
2050	  file in procfs. Useful with kexec.
2051
2052config CRASH_DUMP
2053	bool "Build kdump crash kernel (EXPERIMENTAL)"
2054	depends on EXPERIMENTAL
2055	help
2056	  Generate crash dump after being started by kexec. This should
2057	  be normally only set in special crash dump kernels which are
2058	  loaded in the main kernel with kexec-tools into a specially
2059	  reserved region and then later executed after a crash by
2060	  kdump/kexec. The crash dump kernel must be compiled to a
2061	  memory address not used by the main kernel
2062
2063	  For more details see Documentation/kdump/kdump.txt
2064
2065config AUTO_ZRELADDR
2066	bool "Auto calculation of the decompressed kernel image address"
2067	depends on !ZBOOT_ROM && !ARCH_U300
2068	help
2069	  ZRELADDR is the physical address where the decompressed kernel
2070	  image will be placed. If AUTO_ZRELADDR is selected, the address
2071	  will be determined at run-time by masking the current IP with
2072	  0xf8000000. This assumes the zImage being placed in the first 128MB
2073	  from start of memory.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2074
2075endmenu
2076
2077menu "CPU Power Management"
2078
2079if ARCH_HAS_CPUFREQ
2080
2081source "drivers/cpufreq/Kconfig"
2082
2083config CPU_FREQ_IMX
2084	tristate "CPUfreq driver for i.MX CPUs"
2085	depends on ARCH_MXC && CPU_FREQ
2086	select CPU_FREQ_TABLE
2087	help
2088	  This enables the CPUfreq driver for i.MX CPUs.
2089
2090config CPU_FREQ_SA1100
2091	bool
2092
2093config CPU_FREQ_SA1110
2094	bool
2095
2096config CPU_FREQ_INTEGRATOR
2097	tristate "CPUfreq driver for ARM Integrator CPUs"
2098	depends on ARCH_INTEGRATOR && CPU_FREQ
2099	default y
2100	help
2101	  This enables the CPUfreq driver for ARM Integrator CPUs.
2102
2103	  For details, take a look at <file:Documentation/cpu-freq>.
2104
2105	  If in doubt, say Y.
2106
2107config CPU_FREQ_PXA
2108	bool
2109	depends on CPU_FREQ && ARCH_PXA && PXA25x
2110	default y
2111	select CPU_FREQ_TABLE
2112	select CPU_FREQ_DEFAULT_GOV_USERSPACE
2113
2114config CPU_FREQ_S3C
2115	bool
2116	help
2117	  Internal configuration node for common cpufreq on Samsung SoC
2118
2119config CPU_FREQ_S3C24XX
2120	bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2121	depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2122	select CPU_FREQ_S3C
2123	help
2124	  This enables the CPUfreq driver for the Samsung S3C24XX family
2125	  of CPUs.
2126
2127	  For details, take a look at <file:Documentation/cpu-freq>.
2128
2129	  If in doubt, say N.
2130
2131config CPU_FREQ_S3C24XX_PLL
2132	bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2133	depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2134	help
2135	  Compile in support for changing the PLL frequency from the
2136	  S3C24XX series CPUfreq driver. The PLL takes time to settle
2137	  after a frequency change, so by default it is not enabled.
2138
2139	  This also means that the PLL tables for the selected CPU(s) will
2140	  be built which may increase the size of the kernel image.
2141
2142config CPU_FREQ_S3C24XX_DEBUG
2143	bool "Debug CPUfreq Samsung driver core"
2144	depends on CPU_FREQ_S3C24XX
2145	help
2146	  Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2147
2148config CPU_FREQ_S3C24XX_IODEBUG
2149	bool "Debug CPUfreq Samsung driver IO timing"
2150	depends on CPU_FREQ_S3C24XX
2151	help
2152	  Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2153
2154config CPU_FREQ_S3C24XX_DEBUGFS
2155	bool "Export debugfs for CPUFreq"
2156	depends on CPU_FREQ_S3C24XX && DEBUG_FS
2157	help
2158	  Export status information via debugfs.
2159
2160endif
2161
2162source "drivers/cpuidle/Kconfig"
2163
2164endmenu
2165
2166menu "Floating point emulation"
2167
2168comment "At least one emulation must be selected"
2169
2170config FPE_NWFPE
2171	bool "NWFPE math emulation"
2172	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2173	---help---
2174	  Say Y to include the NWFPE floating point emulator in the kernel.
2175	  This is necessary to run most binaries. Linux does not currently
2176	  support floating point hardware so you need to say Y here even if
2177	  your machine has an FPA or floating point co-processor podule.
2178
2179	  You may say N here if you are going to load the Acorn FPEmulator
2180	  early in the bootup.
2181
2182config FPE_NWFPE_XP
2183	bool "Support extended precision"
2184	depends on FPE_NWFPE
2185	help
2186	  Say Y to include 80-bit support in the kernel floating-point
2187	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2188	  Note that gcc does not generate 80-bit operations by default,
2189	  so in most cases this option only enlarges the size of the
2190	  floating point emulator without any good reason.
2191
2192	  You almost surely want to say N here.
2193
2194config FPE_FASTFPE
2195	bool "FastFPE math emulation (EXPERIMENTAL)"
2196	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2197	---help---
2198	  Say Y here to include the FAST floating point emulator in the kernel.
2199	  This is an experimental much faster emulator which now also has full
2200	  precision for the mantissa.  It does not support any exceptions.
2201	  It is very simple, and approximately 3-6 times faster than NWFPE.
2202
2203	  It should be sufficient for most programs.  It may be not suitable
2204	  for scientific calculations, but you have to check this for yourself.
2205	  If you do not feel you need a faster FP emulation you should better
2206	  choose NWFPE.
2207
2208config VFP
2209	bool "VFP-format floating point maths"
2210	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2211	help
2212	  Say Y to include VFP support code in the kernel. This is needed
2213	  if your hardware includes a VFP unit.
2214
2215	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
2216	  release notes and additional status information.
2217
2218	  Say N if your target does not have VFP hardware.
2219
2220config VFPv3
2221	bool
2222	depends on VFP
2223	default y if CPU_V7
2224
2225config NEON
2226	bool "Advanced SIMD (NEON) Extension support"
2227	depends on VFPv3 && CPU_V7
2228	help
2229	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2230	  Extension.
2231
2232endmenu
2233
2234menu "Userspace binary formats"
2235
2236source "fs/Kconfig.binfmt"
2237
2238config ARTHUR
2239	tristate "RISC OS personality"
2240	depends on !AEABI
2241	help
2242	  Say Y here to include the kernel code necessary if you want to run
2243	  Acorn RISC OS/Arthur binaries under Linux. This code is still very
2244	  experimental; if this sounds frightening, say N and sleep in peace.
2245	  You can also say M here to compile this support as a module (which
2246	  will be called arthur).
2247
2248endmenu
2249
2250menu "Power management options"
2251
2252source "kernel/power/Kconfig"
2253
2254config ARCH_SUSPEND_POSSIBLE
2255	depends on !ARCH_S5PC100 && !ARCH_TEGRA
2256	depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2257		CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2258	def_bool y
2259
2260config ARM_CPU_SUSPEND
2261	def_bool PM_SLEEP
2262
2263endmenu
2264
2265source "net/Kconfig"
2266
2267source "drivers/Kconfig"
2268
2269source "fs/Kconfig"
2270
2271source "arch/arm/Kconfig.debug"
2272
2273source "security/Kconfig"
2274
2275source "crypto/Kconfig"
2276
2277source "lib/Kconfig"