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1/*******************************************************************************
2 STMMAC Ethtool support
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/interrupt.h>
28#include <linux/mii.h>
29#include <linux/phy.h>
30#include <asm/io.h>
31
32#include "stmmac.h"
33#include "dwmac_dma.h"
34
35#define REG_SPACE_SIZE 0x1054
36#define MAC100_ETHTOOL_NAME "st_mac100"
37#define GMAC_ETHTOOL_NAME "st_gmac"
38
39struct stmmac_stats {
40 char stat_string[ETH_GSTRING_LEN];
41 int sizeof_stat;
42 int stat_offset;
43};
44
45#define STMMAC_STAT(m) \
46 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \
47 offsetof(struct stmmac_priv, xstats.m)}
48
49static const struct stmmac_stats stmmac_gstrings_stats[] = {
50 /* Transmit errors */
51 STMMAC_STAT(tx_underflow),
52 STMMAC_STAT(tx_carrier),
53 STMMAC_STAT(tx_losscarrier),
54 STMMAC_STAT(vlan_tag),
55 STMMAC_STAT(tx_deferred),
56 STMMAC_STAT(tx_vlan),
57 STMMAC_STAT(tx_jabber),
58 STMMAC_STAT(tx_frame_flushed),
59 STMMAC_STAT(tx_payload_error),
60 STMMAC_STAT(tx_ip_header_error),
61 /* Receive errors */
62 STMMAC_STAT(rx_desc),
63 STMMAC_STAT(sa_filter_fail),
64 STMMAC_STAT(overflow_error),
65 STMMAC_STAT(ipc_csum_error),
66 STMMAC_STAT(rx_collision),
67 STMMAC_STAT(rx_crc),
68 STMMAC_STAT(dribbling_bit),
69 STMMAC_STAT(rx_length),
70 STMMAC_STAT(rx_mii),
71 STMMAC_STAT(rx_multicast),
72 STMMAC_STAT(rx_gmac_overflow),
73 STMMAC_STAT(rx_watchdog),
74 STMMAC_STAT(da_rx_filter_fail),
75 STMMAC_STAT(sa_rx_filter_fail),
76 STMMAC_STAT(rx_missed_cntr),
77 STMMAC_STAT(rx_overflow_cntr),
78 STMMAC_STAT(rx_vlan),
79 /* Tx/Rx IRQ errors */
80 STMMAC_STAT(tx_undeflow_irq),
81 STMMAC_STAT(tx_process_stopped_irq),
82 STMMAC_STAT(tx_jabber_irq),
83 STMMAC_STAT(rx_overflow_irq),
84 STMMAC_STAT(rx_buf_unav_irq),
85 STMMAC_STAT(rx_process_stopped_irq),
86 STMMAC_STAT(rx_watchdog_irq),
87 STMMAC_STAT(tx_early_irq),
88 STMMAC_STAT(fatal_bus_error_irq),
89 /* Extra info */
90 STMMAC_STAT(threshold),
91 STMMAC_STAT(tx_pkt_n),
92 STMMAC_STAT(rx_pkt_n),
93 STMMAC_STAT(poll_n),
94 STMMAC_STAT(sched_timer_n),
95 STMMAC_STAT(normal_irq_n),
96};
97#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
98
99/* HW MAC Management counters (if supported) */
100#define STMMAC_MMC_STAT(m) \
101 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \
102 offsetof(struct stmmac_priv, mmc.m)}
103
104static const struct stmmac_stats stmmac_mmc[] = {
105 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
106 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
107 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
108 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
109 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
110 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
111 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
112 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
113 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
114 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
115 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
116 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
117 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
118 STMMAC_MMC_STAT(mmc_tx_underflow_error),
119 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
120 STMMAC_MMC_STAT(mmc_tx_multicol_g),
121 STMMAC_MMC_STAT(mmc_tx_deferred),
122 STMMAC_MMC_STAT(mmc_tx_latecol),
123 STMMAC_MMC_STAT(mmc_tx_exesscol),
124 STMMAC_MMC_STAT(mmc_tx_carrier_error),
125 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
126 STMMAC_MMC_STAT(mmc_tx_framecount_g),
127 STMMAC_MMC_STAT(mmc_tx_excessdef),
128 STMMAC_MMC_STAT(mmc_tx_pause_frame),
129 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
130 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
131 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
132 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
133 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
134 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
135 STMMAC_MMC_STAT(mmc_rx_crc_errror),
136 STMMAC_MMC_STAT(mmc_rx_align_error),
137 STMMAC_MMC_STAT(mmc_rx_run_error),
138 STMMAC_MMC_STAT(mmc_rx_jabber_error),
139 STMMAC_MMC_STAT(mmc_rx_undersize_g),
140 STMMAC_MMC_STAT(mmc_rx_oversize_g),
141 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
142 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
143 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
144 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
145 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
146 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
147 STMMAC_MMC_STAT(mmc_rx_unicast_g),
148 STMMAC_MMC_STAT(mmc_rx_length_error),
149 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
150 STMMAC_MMC_STAT(mmc_rx_pause_frames),
151 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
152 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
153 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
154 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
155 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
156 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
157 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
158 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
159 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
160 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
161 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
162 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
163 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
164 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
165 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
166 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
167 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
168 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
169 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
170 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
171 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
172 STMMAC_MMC_STAT(mmc_rx_udp_gd),
173 STMMAC_MMC_STAT(mmc_rx_udp_err),
174 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
175 STMMAC_MMC_STAT(mmc_rx_tcp_err),
176 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
177 STMMAC_MMC_STAT(mmc_rx_icmp_err),
178 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
179 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
180 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
181 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
182 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
183 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
184};
185#define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
186
187static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
188 struct ethtool_drvinfo *info)
189{
190 struct stmmac_priv *priv = netdev_priv(dev);
191
192 if (priv->plat->has_gmac)
193 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
194 else
195 strlcpy(info->driver, MAC100_ETHTOOL_NAME,
196 sizeof(info->driver));
197
198 strcpy(info->version, DRV_MODULE_VERSION);
199 info->fw_version[0] = '\0';
200}
201
202static int stmmac_ethtool_getsettings(struct net_device *dev,
203 struct ethtool_cmd *cmd)
204{
205 struct stmmac_priv *priv = netdev_priv(dev);
206 struct phy_device *phy = priv->phydev;
207 int rc;
208 if (phy == NULL) {
209 pr_err("%s: %s: PHY is not registered\n",
210 __func__, dev->name);
211 return -ENODEV;
212 }
213 if (!netif_running(dev)) {
214 pr_err("%s: interface is disabled: we cannot track "
215 "link speed / duplex setting\n", dev->name);
216 return -EBUSY;
217 }
218 cmd->transceiver = XCVR_INTERNAL;
219 spin_lock_irq(&priv->lock);
220 rc = phy_ethtool_gset(phy, cmd);
221 spin_unlock_irq(&priv->lock);
222 return rc;
223}
224
225static int stmmac_ethtool_setsettings(struct net_device *dev,
226 struct ethtool_cmd *cmd)
227{
228 struct stmmac_priv *priv = netdev_priv(dev);
229 struct phy_device *phy = priv->phydev;
230 int rc;
231
232 spin_lock(&priv->lock);
233 rc = phy_ethtool_sset(phy, cmd);
234 spin_unlock(&priv->lock);
235
236 return rc;
237}
238
239static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
240{
241 struct stmmac_priv *priv = netdev_priv(dev);
242 return priv->msg_enable;
243}
244
245static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
246{
247 struct stmmac_priv *priv = netdev_priv(dev);
248 priv->msg_enable = level;
249
250}
251
252static int stmmac_check_if_running(struct net_device *dev)
253{
254 if (!netif_running(dev))
255 return -EBUSY;
256 return 0;
257}
258
259static int stmmac_ethtool_get_regs_len(struct net_device *dev)
260{
261 return REG_SPACE_SIZE;
262}
263
264static void stmmac_ethtool_gregs(struct net_device *dev,
265 struct ethtool_regs *regs, void *space)
266{
267 int i;
268 u32 *reg_space = (u32 *) space;
269
270 struct stmmac_priv *priv = netdev_priv(dev);
271
272 memset(reg_space, 0x0, REG_SPACE_SIZE);
273
274 if (!priv->plat->has_gmac) {
275 /* MAC registers */
276 for (i = 0; i < 12; i++)
277 reg_space[i] = readl(priv->ioaddr + (i * 4));
278 /* DMA registers */
279 for (i = 0; i < 9; i++)
280 reg_space[i + 12] =
281 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
282 reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR);
283 reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR);
284 } else {
285 /* MAC registers */
286 for (i = 0; i < 55; i++)
287 reg_space[i] = readl(priv->ioaddr + (i * 4));
288 /* DMA registers */
289 for (i = 0; i < 22; i++)
290 reg_space[i + 55] =
291 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
292 }
293}
294
295static void
296stmmac_get_pauseparam(struct net_device *netdev,
297 struct ethtool_pauseparam *pause)
298{
299 struct stmmac_priv *priv = netdev_priv(netdev);
300
301 spin_lock(&priv->lock);
302
303 pause->rx_pause = 0;
304 pause->tx_pause = 0;
305 pause->autoneg = priv->phydev->autoneg;
306
307 if (priv->flow_ctrl & FLOW_RX)
308 pause->rx_pause = 1;
309 if (priv->flow_ctrl & FLOW_TX)
310 pause->tx_pause = 1;
311
312 spin_unlock(&priv->lock);
313}
314
315static int
316stmmac_set_pauseparam(struct net_device *netdev,
317 struct ethtool_pauseparam *pause)
318{
319 struct stmmac_priv *priv = netdev_priv(netdev);
320 struct phy_device *phy = priv->phydev;
321 int new_pause = FLOW_OFF;
322 int ret = 0;
323
324 spin_lock(&priv->lock);
325
326 if (pause->rx_pause)
327 new_pause |= FLOW_RX;
328 if (pause->tx_pause)
329 new_pause |= FLOW_TX;
330
331 priv->flow_ctrl = new_pause;
332 phy->autoneg = pause->autoneg;
333
334 if (phy->autoneg) {
335 if (netif_running(netdev))
336 ret = phy_start_aneg(phy);
337 } else
338 priv->hw->mac->flow_ctrl(priv->ioaddr, phy->duplex,
339 priv->flow_ctrl, priv->pause);
340 spin_unlock(&priv->lock);
341 return ret;
342}
343
344static void stmmac_get_ethtool_stats(struct net_device *dev,
345 struct ethtool_stats *dummy, u64 *data)
346{
347 struct stmmac_priv *priv = netdev_priv(dev);
348 int i, j = 0;
349
350 /* Update the DMA HW counters for dwmac10/100 */
351 if (!priv->plat->has_gmac)
352 priv->hw->dma->dma_diagnostic_fr(&dev->stats,
353 (void *) &priv->xstats,
354 priv->ioaddr);
355 else {
356 /* If supported, for new GMAC chips expose the MMC counters */
357 if (priv->dma_cap.rmon) {
358 dwmac_mmc_read(priv->ioaddr, &priv->mmc);
359
360 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
361 char *p;
362 p = (char *)priv + stmmac_mmc[i].stat_offset;
363
364 data[j++] = (stmmac_mmc[i].sizeof_stat ==
365 sizeof(u64)) ? (*(u64 *)p) :
366 (*(u32 *)p);
367 }
368 }
369 }
370 for (i = 0; i < STMMAC_STATS_LEN; i++) {
371 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
372 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
373 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
374 }
375}
376
377static int stmmac_get_sset_count(struct net_device *netdev, int sset)
378{
379 struct stmmac_priv *priv = netdev_priv(netdev);
380 int len;
381
382 switch (sset) {
383 case ETH_SS_STATS:
384 len = STMMAC_STATS_LEN;
385
386 if (priv->dma_cap.rmon)
387 len += STMMAC_MMC_STATS_LEN;
388
389 return len;
390 default:
391 return -EOPNOTSUPP;
392 }
393}
394
395static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
396{
397 int i;
398 u8 *p = data;
399 struct stmmac_priv *priv = netdev_priv(dev);
400
401 switch (stringset) {
402 case ETH_SS_STATS:
403 if (priv->dma_cap.rmon)
404 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
405 memcpy(p, stmmac_mmc[i].stat_string,
406 ETH_GSTRING_LEN);
407 p += ETH_GSTRING_LEN;
408 }
409 for (i = 0; i < STMMAC_STATS_LEN; i++) {
410 memcpy(p, stmmac_gstrings_stats[i].stat_string,
411 ETH_GSTRING_LEN);
412 p += ETH_GSTRING_LEN;
413 }
414 break;
415 default:
416 WARN_ON(1);
417 break;
418 }
419}
420
421/* Currently only support WOL through Magic packet. */
422static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
423{
424 struct stmmac_priv *priv = netdev_priv(dev);
425
426 spin_lock_irq(&priv->lock);
427 if (device_can_wakeup(priv->device)) {
428 wol->supported = WAKE_MAGIC | WAKE_UCAST;
429 wol->wolopts = priv->wolopts;
430 }
431 spin_unlock_irq(&priv->lock);
432}
433
434static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
435{
436 struct stmmac_priv *priv = netdev_priv(dev);
437 u32 support = WAKE_MAGIC | WAKE_UCAST;
438
439 /* By default almost all GMAC devices support the WoL via
440 * magic frame but we can disable it if the HW capability
441 * register shows no support for pmt_magic_frame. */
442 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
443 wol->wolopts &= ~WAKE_MAGIC;
444
445 if (!device_can_wakeup(priv->device))
446 return -EINVAL;
447
448 if (wol->wolopts & ~support)
449 return -EINVAL;
450
451 if (wol->wolopts) {
452 pr_info("stmmac: wakeup enable\n");
453 device_set_wakeup_enable(priv->device, 1);
454 enable_irq_wake(priv->wol_irq);
455 } else {
456 device_set_wakeup_enable(priv->device, 0);
457 disable_irq_wake(priv->wol_irq);
458 }
459
460 spin_lock_irq(&priv->lock);
461 priv->wolopts = wol->wolopts;
462 spin_unlock_irq(&priv->lock);
463
464 return 0;
465}
466
467static const struct ethtool_ops stmmac_ethtool_ops = {
468 .begin = stmmac_check_if_running,
469 .get_drvinfo = stmmac_ethtool_getdrvinfo,
470 .get_settings = stmmac_ethtool_getsettings,
471 .set_settings = stmmac_ethtool_setsettings,
472 .get_msglevel = stmmac_ethtool_getmsglevel,
473 .set_msglevel = stmmac_ethtool_setmsglevel,
474 .get_regs = stmmac_ethtool_gregs,
475 .get_regs_len = stmmac_ethtool_get_regs_len,
476 .get_link = ethtool_op_get_link,
477 .get_pauseparam = stmmac_get_pauseparam,
478 .set_pauseparam = stmmac_set_pauseparam,
479 .get_ethtool_stats = stmmac_get_ethtool_stats,
480 .get_strings = stmmac_get_strings,
481 .get_wol = stmmac_get_wol,
482 .set_wol = stmmac_set_wol,
483 .get_sset_count = stmmac_get_sset_count,
484 .get_ts_info = ethtool_op_get_ts_info,
485};
486
487void stmmac_set_ethtool_ops(struct net_device *netdev)
488{
489 SET_ETHTOOL_OPS(netdev, &stmmac_ethtool_ops);
490}
1// SPDX-License-Identifier: GPL-2.0-only
2/*******************************************************************************
3 STMMAC Ethtool support
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#include <linux/etherdevice.h>
12#include <linux/ethtool.h>
13#include <linux/interrupt.h>
14#include <linux/mii.h>
15#include <linux/phylink.h>
16#include <linux/net_tstamp.h>
17#include <asm/io.h>
18
19#include "stmmac.h"
20#include "dwmac_dma.h"
21#include "dwxgmac2.h"
22
23#define REG_SPACE_SIZE 0x1060
24#define GMAC4_REG_SPACE_SIZE 0x116C
25#define MAC100_ETHTOOL_NAME "st_mac100"
26#define GMAC_ETHTOOL_NAME "st_gmac"
27#define XGMAC_ETHTOOL_NAME "st_xgmac"
28
29/* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h
30 *
31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the
32 * same time due to the conflicting macro names.
33 */
34#define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100
35
36#define ETHTOOL_DMA_OFFSET 55
37
38struct stmmac_stats {
39 char stat_string[ETH_GSTRING_LEN];
40 int sizeof_stat;
41 int stat_offset;
42};
43
44#define STMMAC_STAT(m) \
45 { #m, sizeof_field(struct stmmac_extra_stats, m), \
46 offsetof(struct stmmac_priv, xstats.m)}
47
48static const struct stmmac_stats stmmac_gstrings_stats[] = {
49 /* Transmit errors */
50 STMMAC_STAT(tx_underflow),
51 STMMAC_STAT(tx_carrier),
52 STMMAC_STAT(tx_losscarrier),
53 STMMAC_STAT(vlan_tag),
54 STMMAC_STAT(tx_deferred),
55 STMMAC_STAT(tx_vlan),
56 STMMAC_STAT(tx_jabber),
57 STMMAC_STAT(tx_frame_flushed),
58 STMMAC_STAT(tx_payload_error),
59 STMMAC_STAT(tx_ip_header_error),
60 /* Receive errors */
61 STMMAC_STAT(rx_desc),
62 STMMAC_STAT(sa_filter_fail),
63 STMMAC_STAT(overflow_error),
64 STMMAC_STAT(ipc_csum_error),
65 STMMAC_STAT(rx_collision),
66 STMMAC_STAT(rx_crc_errors),
67 STMMAC_STAT(dribbling_bit),
68 STMMAC_STAT(rx_length),
69 STMMAC_STAT(rx_mii),
70 STMMAC_STAT(rx_multicast),
71 STMMAC_STAT(rx_gmac_overflow),
72 STMMAC_STAT(rx_watchdog),
73 STMMAC_STAT(da_rx_filter_fail),
74 STMMAC_STAT(sa_rx_filter_fail),
75 STMMAC_STAT(rx_missed_cntr),
76 STMMAC_STAT(rx_overflow_cntr),
77 STMMAC_STAT(rx_vlan),
78 STMMAC_STAT(rx_split_hdr_pkt_n),
79 /* Tx/Rx IRQ error info */
80 STMMAC_STAT(tx_undeflow_irq),
81 STMMAC_STAT(tx_process_stopped_irq),
82 STMMAC_STAT(tx_jabber_irq),
83 STMMAC_STAT(rx_overflow_irq),
84 STMMAC_STAT(rx_buf_unav_irq),
85 STMMAC_STAT(rx_process_stopped_irq),
86 STMMAC_STAT(rx_watchdog_irq),
87 STMMAC_STAT(tx_early_irq),
88 STMMAC_STAT(fatal_bus_error_irq),
89 /* Tx/Rx IRQ Events */
90 STMMAC_STAT(rx_early_irq),
91 STMMAC_STAT(threshold),
92 STMMAC_STAT(tx_pkt_n),
93 STMMAC_STAT(rx_pkt_n),
94 STMMAC_STAT(normal_irq_n),
95 STMMAC_STAT(rx_normal_irq_n),
96 STMMAC_STAT(napi_poll),
97 STMMAC_STAT(tx_normal_irq_n),
98 STMMAC_STAT(tx_clean),
99 STMMAC_STAT(tx_set_ic_bit),
100 STMMAC_STAT(irq_receive_pmt_irq_n),
101 /* MMC info */
102 STMMAC_STAT(mmc_tx_irq_n),
103 STMMAC_STAT(mmc_rx_irq_n),
104 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
105 /* EEE */
106 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
107 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
108 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
109 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
110 STMMAC_STAT(phy_eee_wakeup_error_n),
111 /* Extended RDES status */
112 STMMAC_STAT(ip_hdr_err),
113 STMMAC_STAT(ip_payload_err),
114 STMMAC_STAT(ip_csum_bypassed),
115 STMMAC_STAT(ipv4_pkt_rcvd),
116 STMMAC_STAT(ipv6_pkt_rcvd),
117 STMMAC_STAT(no_ptp_rx_msg_type_ext),
118 STMMAC_STAT(ptp_rx_msg_type_sync),
119 STMMAC_STAT(ptp_rx_msg_type_follow_up),
120 STMMAC_STAT(ptp_rx_msg_type_delay_req),
121 STMMAC_STAT(ptp_rx_msg_type_delay_resp),
122 STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
123 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
124 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
125 STMMAC_STAT(ptp_rx_msg_type_announce),
126 STMMAC_STAT(ptp_rx_msg_type_management),
127 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
128 STMMAC_STAT(ptp_frame_type),
129 STMMAC_STAT(ptp_ver),
130 STMMAC_STAT(timestamp_dropped),
131 STMMAC_STAT(av_pkt_rcvd),
132 STMMAC_STAT(av_tagged_pkt_rcvd),
133 STMMAC_STAT(vlan_tag_priority_val),
134 STMMAC_STAT(l3_filter_match),
135 STMMAC_STAT(l4_filter_match),
136 STMMAC_STAT(l3_l4_filter_no_match),
137 /* PCS */
138 STMMAC_STAT(irq_pcs_ane_n),
139 STMMAC_STAT(irq_pcs_link_n),
140 STMMAC_STAT(irq_rgmii_n),
141 /* DEBUG */
142 STMMAC_STAT(mtl_tx_status_fifo_full),
143 STMMAC_STAT(mtl_tx_fifo_not_empty),
144 STMMAC_STAT(mmtl_fifo_ctrl),
145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
147 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
148 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
149 STMMAC_STAT(mac_tx_in_pause),
150 STMMAC_STAT(mac_tx_frame_ctrl_xfer),
151 STMMAC_STAT(mac_tx_frame_ctrl_idle),
152 STMMAC_STAT(mac_tx_frame_ctrl_wait),
153 STMMAC_STAT(mac_tx_frame_ctrl_pause),
154 STMMAC_STAT(mac_gmii_tx_proto_engine),
155 STMMAC_STAT(mtl_rx_fifo_fill_level_full),
156 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
157 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
158 STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
161 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
162 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
163 STMMAC_STAT(mtl_rx_fifo_ctrl_active),
164 STMMAC_STAT(mac_rx_frame_ctrl_fifo),
165 STMMAC_STAT(mac_gmii_rx_proto_engine),
166 /* TSO */
167 STMMAC_STAT(tx_tso_frames),
168 STMMAC_STAT(tx_tso_nfrags),
169 /* EST */
170 STMMAC_STAT(mtl_est_cgce),
171 STMMAC_STAT(mtl_est_hlbs),
172 STMMAC_STAT(mtl_est_hlbf),
173 STMMAC_STAT(mtl_est_btre),
174 STMMAC_STAT(mtl_est_btrlm),
175};
176#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
177
178/* HW MAC Management counters (if supported) */
179#define STMMAC_MMC_STAT(m) \
180 { #m, sizeof_field(struct stmmac_counters, m), \
181 offsetof(struct stmmac_priv, mmc.m)}
182
183static const struct stmmac_stats stmmac_mmc[] = {
184 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
185 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
186 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
187 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
188 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
189 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
190 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
191 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
192 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
193 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
194 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
195 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
196 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
197 STMMAC_MMC_STAT(mmc_tx_underflow_error),
198 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
199 STMMAC_MMC_STAT(mmc_tx_multicol_g),
200 STMMAC_MMC_STAT(mmc_tx_deferred),
201 STMMAC_MMC_STAT(mmc_tx_latecol),
202 STMMAC_MMC_STAT(mmc_tx_exesscol),
203 STMMAC_MMC_STAT(mmc_tx_carrier_error),
204 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
205 STMMAC_MMC_STAT(mmc_tx_framecount_g),
206 STMMAC_MMC_STAT(mmc_tx_excessdef),
207 STMMAC_MMC_STAT(mmc_tx_pause_frame),
208 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
209 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
210 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
211 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
212 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
213 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
214 STMMAC_MMC_STAT(mmc_rx_crc_error),
215 STMMAC_MMC_STAT(mmc_rx_align_error),
216 STMMAC_MMC_STAT(mmc_rx_run_error),
217 STMMAC_MMC_STAT(mmc_rx_jabber_error),
218 STMMAC_MMC_STAT(mmc_rx_undersize_g),
219 STMMAC_MMC_STAT(mmc_rx_oversize_g),
220 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
221 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
222 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
223 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
224 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
225 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
226 STMMAC_MMC_STAT(mmc_rx_unicast_g),
227 STMMAC_MMC_STAT(mmc_rx_length_error),
228 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
229 STMMAC_MMC_STAT(mmc_rx_pause_frames),
230 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
231 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
232 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
233 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
234 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
235 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
236 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
237 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
238 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
239 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
240 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
241 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
242 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
243 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
244 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
245 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
246 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
247 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
248 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
249 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
250 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
251 STMMAC_MMC_STAT(mmc_rx_udp_gd),
252 STMMAC_MMC_STAT(mmc_rx_udp_err),
253 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
254 STMMAC_MMC_STAT(mmc_rx_tcp_err),
255 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
256 STMMAC_MMC_STAT(mmc_rx_icmp_err),
257 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
258 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
259 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
260 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
261 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
262 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
263 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
264 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
265 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
266 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
267 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
268 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
269};
270#define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
271
272static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = {
273 "tx_pkt_n",
274 "tx_irq_n",
275#define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string)
276};
277
278static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = {
279 "rx_pkt_n",
280 "rx_irq_n",
281#define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string)
282};
283
284static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
286{
287 struct stmmac_priv *priv = netdev_priv(dev);
288
289 if (priv->plat->has_gmac || priv->plat->has_gmac4)
290 strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
291 else if (priv->plat->has_xgmac)
292 strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver));
293 else
294 strscpy(info->driver, MAC100_ETHTOOL_NAME,
295 sizeof(info->driver));
296
297 if (priv->plat->pdev) {
298 strscpy(info->bus_info, pci_name(priv->plat->pdev),
299 sizeof(info->bus_info));
300 }
301}
302
303static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
304 struct ethtool_link_ksettings *cmd)
305{
306 struct stmmac_priv *priv = netdev_priv(dev);
307
308 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
309 priv->hw->pcs & STMMAC_PCS_SGMII) {
310 struct rgmii_adv adv;
311 u32 supported, advertising, lp_advertising;
312
313 if (!priv->xstats.pcs_link) {
314 cmd->base.speed = SPEED_UNKNOWN;
315 cmd->base.duplex = DUPLEX_UNKNOWN;
316 return 0;
317 }
318 cmd->base.duplex = priv->xstats.pcs_duplex;
319
320 cmd->base.speed = priv->xstats.pcs_speed;
321
322 /* Get and convert ADV/LP_ADV from the HW AN registers */
323 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
324 return -EOPNOTSUPP; /* should never happen indeed */
325
326 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
327
328 ethtool_convert_link_mode_to_legacy_u32(
329 &supported, cmd->link_modes.supported);
330 ethtool_convert_link_mode_to_legacy_u32(
331 &advertising, cmd->link_modes.advertising);
332 ethtool_convert_link_mode_to_legacy_u32(
333 &lp_advertising, cmd->link_modes.lp_advertising);
334
335 if (adv.pause & STMMAC_PCS_PAUSE)
336 advertising |= ADVERTISED_Pause;
337 if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
338 advertising |= ADVERTISED_Asym_Pause;
339 if (adv.lp_pause & STMMAC_PCS_PAUSE)
340 lp_advertising |= ADVERTISED_Pause;
341 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
342 lp_advertising |= ADVERTISED_Asym_Pause;
343
344 /* Reg49[3] always set because ANE is always supported */
345 cmd->base.autoneg = ADVERTISED_Autoneg;
346 supported |= SUPPORTED_Autoneg;
347 advertising |= ADVERTISED_Autoneg;
348 lp_advertising |= ADVERTISED_Autoneg;
349
350 if (adv.duplex) {
351 supported |= (SUPPORTED_1000baseT_Full |
352 SUPPORTED_100baseT_Full |
353 SUPPORTED_10baseT_Full);
354 advertising |= (ADVERTISED_1000baseT_Full |
355 ADVERTISED_100baseT_Full |
356 ADVERTISED_10baseT_Full);
357 } else {
358 supported |= (SUPPORTED_1000baseT_Half |
359 SUPPORTED_100baseT_Half |
360 SUPPORTED_10baseT_Half);
361 advertising |= (ADVERTISED_1000baseT_Half |
362 ADVERTISED_100baseT_Half |
363 ADVERTISED_10baseT_Half);
364 }
365 if (adv.lp_duplex)
366 lp_advertising |= (ADVERTISED_1000baseT_Full |
367 ADVERTISED_100baseT_Full |
368 ADVERTISED_10baseT_Full);
369 else
370 lp_advertising |= (ADVERTISED_1000baseT_Half |
371 ADVERTISED_100baseT_Half |
372 ADVERTISED_10baseT_Half);
373 cmd->base.port = PORT_OTHER;
374
375 ethtool_convert_legacy_u32_to_link_mode(
376 cmd->link_modes.supported, supported);
377 ethtool_convert_legacy_u32_to_link_mode(
378 cmd->link_modes.advertising, advertising);
379 ethtool_convert_legacy_u32_to_link_mode(
380 cmd->link_modes.lp_advertising, lp_advertising);
381
382 return 0;
383 }
384
385 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
386}
387
388static int
389stmmac_ethtool_set_link_ksettings(struct net_device *dev,
390 const struct ethtool_link_ksettings *cmd)
391{
392 struct stmmac_priv *priv = netdev_priv(dev);
393
394 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
395 priv->hw->pcs & STMMAC_PCS_SGMII) {
396 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause;
397
398 /* Only support ANE */
399 if (cmd->base.autoneg != AUTONEG_ENABLE)
400 return -EINVAL;
401
402 mask &= (ADVERTISED_1000baseT_Half |
403 ADVERTISED_1000baseT_Full |
404 ADVERTISED_100baseT_Half |
405 ADVERTISED_100baseT_Full |
406 ADVERTISED_10baseT_Half |
407 ADVERTISED_10baseT_Full);
408
409 mutex_lock(&priv->lock);
410 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
411 mutex_unlock(&priv->lock);
412
413 return 0;
414 }
415
416 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
417}
418
419static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
420{
421 struct stmmac_priv *priv = netdev_priv(dev);
422 return priv->msg_enable;
423}
424
425static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
426{
427 struct stmmac_priv *priv = netdev_priv(dev);
428 priv->msg_enable = level;
429
430}
431
432static int stmmac_check_if_running(struct net_device *dev)
433{
434 if (!netif_running(dev))
435 return -EBUSY;
436 return 0;
437}
438
439static int stmmac_ethtool_get_regs_len(struct net_device *dev)
440{
441 struct stmmac_priv *priv = netdev_priv(dev);
442
443 if (priv->plat->has_xgmac)
444 return XGMAC_REGSIZE * 4;
445 else if (priv->plat->has_gmac4)
446 return GMAC4_REG_SPACE_SIZE;
447 return REG_SPACE_SIZE;
448}
449
450static void stmmac_ethtool_gregs(struct net_device *dev,
451 struct ethtool_regs *regs, void *space)
452{
453 struct stmmac_priv *priv = netdev_priv(dev);
454 u32 *reg_space = (u32 *) space;
455
456 stmmac_dump_mac_regs(priv, priv->hw, reg_space);
457 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
458
459 /* Copy DMA registers to where ethtool expects them */
460 if (priv->plat->has_gmac4) {
461 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */
462 memcpy(®_space[ETHTOOL_DMA_OFFSET],
463 ®_space[GMAC4_DMA_CHAN_BASE_ADDR / 4],
464 NUM_DWMAC4_DMA_REGS * 4);
465 } else if (!priv->plat->has_xgmac) {
466 memcpy(®_space[ETHTOOL_DMA_OFFSET],
467 ®_space[DMA_BUS_MODE / 4],
468 NUM_DWMAC1000_DMA_REGS * 4);
469 }
470}
471
472static int stmmac_nway_reset(struct net_device *dev)
473{
474 struct stmmac_priv *priv = netdev_priv(dev);
475
476 return phylink_ethtool_nway_reset(priv->phylink);
477}
478
479static void stmmac_get_ringparam(struct net_device *netdev,
480 struct ethtool_ringparam *ring,
481 struct kernel_ethtool_ringparam *kernel_ring,
482 struct netlink_ext_ack *extack)
483{
484 struct stmmac_priv *priv = netdev_priv(netdev);
485
486 ring->rx_max_pending = DMA_MAX_RX_SIZE;
487 ring->tx_max_pending = DMA_MAX_TX_SIZE;
488 ring->rx_pending = priv->dma_conf.dma_rx_size;
489 ring->tx_pending = priv->dma_conf.dma_tx_size;
490}
491
492static int stmmac_set_ringparam(struct net_device *netdev,
493 struct ethtool_ringparam *ring,
494 struct kernel_ethtool_ringparam *kernel_ring,
495 struct netlink_ext_ack *extack)
496{
497 if (ring->rx_mini_pending || ring->rx_jumbo_pending ||
498 ring->rx_pending < DMA_MIN_RX_SIZE ||
499 ring->rx_pending > DMA_MAX_RX_SIZE ||
500 !is_power_of_2(ring->rx_pending) ||
501 ring->tx_pending < DMA_MIN_TX_SIZE ||
502 ring->tx_pending > DMA_MAX_TX_SIZE ||
503 !is_power_of_2(ring->tx_pending))
504 return -EINVAL;
505
506 return stmmac_reinit_ringparam(netdev, ring->rx_pending,
507 ring->tx_pending);
508}
509
510static void
511stmmac_get_pauseparam(struct net_device *netdev,
512 struct ethtool_pauseparam *pause)
513{
514 struct stmmac_priv *priv = netdev_priv(netdev);
515 struct rgmii_adv adv_lp;
516
517 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
518 pause->autoneg = 1;
519 if (!adv_lp.pause)
520 return;
521 } else {
522 phylink_ethtool_get_pauseparam(priv->phylink, pause);
523 }
524}
525
526static int
527stmmac_set_pauseparam(struct net_device *netdev,
528 struct ethtool_pauseparam *pause)
529{
530 struct stmmac_priv *priv = netdev_priv(netdev);
531 struct rgmii_adv adv_lp;
532
533 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
534 pause->autoneg = 1;
535 if (!adv_lp.pause)
536 return -EOPNOTSUPP;
537 return 0;
538 } else {
539 return phylink_ethtool_set_pauseparam(priv->phylink, pause);
540 }
541}
542
543static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)
544{
545 u32 tx_cnt = priv->plat->tx_queues_to_use;
546 u32 rx_cnt = priv->plat->rx_queues_to_use;
547 int q, stat;
548 char *p;
549
550 for (q = 0; q < tx_cnt; q++) {
551 p = (char *)priv + offsetof(struct stmmac_priv,
552 xstats.txq_stats[q].tx_pkt_n);
553 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
554 *data++ = (*(unsigned long *)p);
555 p += sizeof(unsigned long);
556 }
557 }
558 for (q = 0; q < rx_cnt; q++) {
559 p = (char *)priv + offsetof(struct stmmac_priv,
560 xstats.rxq_stats[q].rx_pkt_n);
561 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
562 *data++ = (*(unsigned long *)p);
563 p += sizeof(unsigned long);
564 }
565 }
566}
567
568static void stmmac_get_ethtool_stats(struct net_device *dev,
569 struct ethtool_stats *dummy, u64 *data)
570{
571 struct stmmac_priv *priv = netdev_priv(dev);
572 u32 rx_queues_count = priv->plat->rx_queues_to_use;
573 u32 tx_queues_count = priv->plat->tx_queues_to_use;
574 unsigned long count;
575 int i, j = 0, ret;
576
577 if (priv->dma_cap.asp) {
578 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
579 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
580 &count, NULL))
581 data[j++] = count;
582 }
583 }
584
585 /* Update the DMA HW counters for dwmac10/100 */
586 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats,
587 priv->ioaddr);
588 if (ret) {
589 /* If supported, for new GMAC chips expose the MMC counters */
590 if (priv->dma_cap.rmon) {
591 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
592
593 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
594 char *p;
595 p = (char *)priv + stmmac_mmc[i].stat_offset;
596
597 data[j++] = (stmmac_mmc[i].sizeof_stat ==
598 sizeof(u64)) ? (*(u64 *)p) :
599 (*(u32 *)p);
600 }
601 }
602 if (priv->eee_enabled) {
603 int val = phylink_get_eee_err(priv->phylink);
604 if (val)
605 priv->xstats.phy_eee_wakeup_error_n = val;
606 }
607
608 if (priv->synopsys_id >= DWMAC_CORE_3_50)
609 stmmac_mac_debug(priv, priv->ioaddr,
610 (void *)&priv->xstats,
611 rx_queues_count, tx_queues_count);
612 }
613 for (i = 0; i < STMMAC_STATS_LEN; i++) {
614 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
615 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
616 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
617 }
618 stmmac_get_per_qstats(priv, &data[j]);
619}
620
621static int stmmac_get_sset_count(struct net_device *netdev, int sset)
622{
623 struct stmmac_priv *priv = netdev_priv(netdev);
624 u32 tx_cnt = priv->plat->tx_queues_to_use;
625 u32 rx_cnt = priv->plat->rx_queues_to_use;
626 int i, len, safety_len = 0;
627
628 switch (sset) {
629 case ETH_SS_STATS:
630 len = STMMAC_STATS_LEN +
631 STMMAC_TXQ_STATS * tx_cnt +
632 STMMAC_RXQ_STATS * rx_cnt;
633
634 if (priv->dma_cap.rmon)
635 len += STMMAC_MMC_STATS_LEN;
636 if (priv->dma_cap.asp) {
637 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
638 if (!stmmac_safety_feat_dump(priv,
639 &priv->sstats, i,
640 NULL, NULL))
641 safety_len++;
642 }
643
644 len += safety_len;
645 }
646
647 return len;
648 case ETH_SS_TEST:
649 return stmmac_selftest_get_count(priv);
650 default:
651 return -EOPNOTSUPP;
652 }
653}
654
655static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data)
656{
657 u32 tx_cnt = priv->plat->tx_queues_to_use;
658 u32 rx_cnt = priv->plat->rx_queues_to_use;
659 int q, stat;
660
661 for (q = 0; q < tx_cnt; q++) {
662 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
663 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
664 stmmac_qstats_tx_string[stat]);
665 data += ETH_GSTRING_LEN;
666 }
667 }
668 for (q = 0; q < rx_cnt; q++) {
669 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
670 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
671 stmmac_qstats_rx_string[stat]);
672 data += ETH_GSTRING_LEN;
673 }
674 }
675}
676
677static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
678{
679 int i;
680 u8 *p = data;
681 struct stmmac_priv *priv = netdev_priv(dev);
682
683 switch (stringset) {
684 case ETH_SS_STATS:
685 if (priv->dma_cap.asp) {
686 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
687 const char *desc;
688 if (!stmmac_safety_feat_dump(priv,
689 &priv->sstats, i,
690 NULL, &desc)) {
691 memcpy(p, desc, ETH_GSTRING_LEN);
692 p += ETH_GSTRING_LEN;
693 }
694 }
695 }
696 if (priv->dma_cap.rmon)
697 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
698 memcpy(p, stmmac_mmc[i].stat_string,
699 ETH_GSTRING_LEN);
700 p += ETH_GSTRING_LEN;
701 }
702 for (i = 0; i < STMMAC_STATS_LEN; i++) {
703 memcpy(p, stmmac_gstrings_stats[i].stat_string,
704 ETH_GSTRING_LEN);
705 p += ETH_GSTRING_LEN;
706 }
707 stmmac_get_qstats_string(priv, p);
708 break;
709 case ETH_SS_TEST:
710 stmmac_selftest_get_strings(priv, p);
711 break;
712 default:
713 WARN_ON(1);
714 break;
715 }
716}
717
718/* Currently only support WOL through Magic packet. */
719static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
720{
721 struct stmmac_priv *priv = netdev_priv(dev);
722
723 if (!priv->plat->pmt)
724 return phylink_ethtool_get_wol(priv->phylink, wol);
725
726 mutex_lock(&priv->lock);
727 if (device_can_wakeup(priv->device)) {
728 wol->supported = WAKE_MAGIC | WAKE_UCAST;
729 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame)
730 wol->supported &= ~WAKE_MAGIC;
731 wol->wolopts = priv->wolopts;
732 }
733 mutex_unlock(&priv->lock);
734}
735
736static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
737{
738 struct stmmac_priv *priv = netdev_priv(dev);
739 u32 support = WAKE_MAGIC | WAKE_UCAST;
740
741 if (!device_can_wakeup(priv->device))
742 return -EOPNOTSUPP;
743
744 if (!priv->plat->pmt) {
745 int ret = phylink_ethtool_set_wol(priv->phylink, wol);
746
747 if (!ret)
748 device_set_wakeup_enable(priv->device, !!wol->wolopts);
749 return ret;
750 }
751
752 /* By default almost all GMAC devices support the WoL via
753 * magic frame but we can disable it if the HW capability
754 * register shows no support for pmt_magic_frame. */
755 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
756 wol->wolopts &= ~WAKE_MAGIC;
757
758 if (wol->wolopts & ~support)
759 return -EINVAL;
760
761 if (wol->wolopts) {
762 pr_info("stmmac: wakeup enable\n");
763 device_set_wakeup_enable(priv->device, 1);
764 enable_irq_wake(priv->wol_irq);
765 } else {
766 device_set_wakeup_enable(priv->device, 0);
767 disable_irq_wake(priv->wol_irq);
768 }
769
770 mutex_lock(&priv->lock);
771 priv->wolopts = wol->wolopts;
772 mutex_unlock(&priv->lock);
773
774 return 0;
775}
776
777static int stmmac_ethtool_op_get_eee(struct net_device *dev,
778 struct ethtool_eee *edata)
779{
780 struct stmmac_priv *priv = netdev_priv(dev);
781
782 if (!priv->dma_cap.eee)
783 return -EOPNOTSUPP;
784
785 edata->eee_enabled = priv->eee_enabled;
786 edata->eee_active = priv->eee_active;
787 edata->tx_lpi_timer = priv->tx_lpi_timer;
788 edata->tx_lpi_enabled = priv->tx_lpi_enabled;
789
790 return phylink_ethtool_get_eee(priv->phylink, edata);
791}
792
793static int stmmac_ethtool_op_set_eee(struct net_device *dev,
794 struct ethtool_eee *edata)
795{
796 struct stmmac_priv *priv = netdev_priv(dev);
797 int ret;
798
799 if (!priv->dma_cap.eee)
800 return -EOPNOTSUPP;
801
802 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled)
803 netdev_warn(priv->dev,
804 "Setting EEE tx-lpi is not supported\n");
805
806 if (!edata->eee_enabled)
807 stmmac_disable_eee_mode(priv);
808
809 ret = phylink_ethtool_set_eee(priv->phylink, edata);
810 if (ret)
811 return ret;
812
813 if (edata->eee_enabled &&
814 priv->tx_lpi_timer != edata->tx_lpi_timer) {
815 priv->tx_lpi_timer = edata->tx_lpi_timer;
816 stmmac_eee_init(priv);
817 }
818
819 return 0;
820}
821
822static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
823{
824 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
825
826 if (!clk) {
827 clk = priv->plat->clk_ref_rate;
828 if (!clk)
829 return 0;
830 }
831
832 return (usec * (clk / 1000000)) / 256;
833}
834
835static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
836{
837 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
838
839 if (!clk) {
840 clk = priv->plat->clk_ref_rate;
841 if (!clk)
842 return 0;
843 }
844
845 return (riwt * 256) / (clk / 1000000);
846}
847
848static int __stmmac_get_coalesce(struct net_device *dev,
849 struct ethtool_coalesce *ec,
850 int queue)
851{
852 struct stmmac_priv *priv = netdev_priv(dev);
853 u32 max_cnt;
854 u32 rx_cnt;
855 u32 tx_cnt;
856
857 rx_cnt = priv->plat->rx_queues_to_use;
858 tx_cnt = priv->plat->tx_queues_to_use;
859 max_cnt = max(rx_cnt, tx_cnt);
860
861 if (queue < 0)
862 queue = 0;
863 else if (queue >= max_cnt)
864 return -EINVAL;
865
866 if (queue < tx_cnt) {
867 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue];
868 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue];
869 } else {
870 ec->tx_coalesce_usecs = 0;
871 ec->tx_max_coalesced_frames = 0;
872 }
873
874 if (priv->use_riwt && queue < rx_cnt) {
875 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue];
876 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue],
877 priv);
878 } else {
879 ec->rx_max_coalesced_frames = 0;
880 ec->rx_coalesce_usecs = 0;
881 }
882
883 return 0;
884}
885
886static int stmmac_get_coalesce(struct net_device *dev,
887 struct ethtool_coalesce *ec,
888 struct kernel_ethtool_coalesce *kernel_coal,
889 struct netlink_ext_ack *extack)
890{
891 return __stmmac_get_coalesce(dev, ec, -1);
892}
893
894static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue,
895 struct ethtool_coalesce *ec)
896{
897 return __stmmac_get_coalesce(dev, ec, queue);
898}
899
900static int __stmmac_set_coalesce(struct net_device *dev,
901 struct ethtool_coalesce *ec,
902 int queue)
903{
904 struct stmmac_priv *priv = netdev_priv(dev);
905 bool all_queues = false;
906 unsigned int rx_riwt;
907 u32 max_cnt;
908 u32 rx_cnt;
909 u32 tx_cnt;
910
911 rx_cnt = priv->plat->rx_queues_to_use;
912 tx_cnt = priv->plat->tx_queues_to_use;
913 max_cnt = max(rx_cnt, tx_cnt);
914
915 if (queue < 0)
916 all_queues = true;
917 else if (queue >= max_cnt)
918 return -EINVAL;
919
920 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) {
921 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
922
923 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
924 return -EINVAL;
925
926 if (all_queues) {
927 int i;
928
929 for (i = 0; i < rx_cnt; i++) {
930 priv->rx_riwt[i] = rx_riwt;
931 stmmac_rx_watchdog(priv, priv->ioaddr,
932 rx_riwt, i);
933 priv->rx_coal_frames[i] =
934 ec->rx_max_coalesced_frames;
935 }
936 } else if (queue < rx_cnt) {
937 priv->rx_riwt[queue] = rx_riwt;
938 stmmac_rx_watchdog(priv, priv->ioaddr,
939 rx_riwt, queue);
940 priv->rx_coal_frames[queue] =
941 ec->rx_max_coalesced_frames;
942 }
943 }
944
945 if ((ec->tx_coalesce_usecs == 0) &&
946 (ec->tx_max_coalesced_frames == 0))
947 return -EINVAL;
948
949 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
950 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
951 return -EINVAL;
952
953 if (all_queues) {
954 int i;
955
956 for (i = 0; i < tx_cnt; i++) {
957 priv->tx_coal_frames[i] =
958 ec->tx_max_coalesced_frames;
959 priv->tx_coal_timer[i] =
960 ec->tx_coalesce_usecs;
961 }
962 } else if (queue < tx_cnt) {
963 priv->tx_coal_frames[queue] =
964 ec->tx_max_coalesced_frames;
965 priv->tx_coal_timer[queue] =
966 ec->tx_coalesce_usecs;
967 }
968
969 return 0;
970}
971
972static int stmmac_set_coalesce(struct net_device *dev,
973 struct ethtool_coalesce *ec,
974 struct kernel_ethtool_coalesce *kernel_coal,
975 struct netlink_ext_ack *extack)
976{
977 return __stmmac_set_coalesce(dev, ec, -1);
978}
979
980static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue,
981 struct ethtool_coalesce *ec)
982{
983 return __stmmac_set_coalesce(dev, ec, queue);
984}
985
986static int stmmac_get_rxnfc(struct net_device *dev,
987 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
988{
989 struct stmmac_priv *priv = netdev_priv(dev);
990
991 switch (rxnfc->cmd) {
992 case ETHTOOL_GRXRINGS:
993 rxnfc->data = priv->plat->rx_queues_to_use;
994 break;
995 default:
996 return -EOPNOTSUPP;
997 }
998
999 return 0;
1000}
1001
1002static u32 stmmac_get_rxfh_key_size(struct net_device *dev)
1003{
1004 struct stmmac_priv *priv = netdev_priv(dev);
1005
1006 return sizeof(priv->rss.key);
1007}
1008
1009static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)
1010{
1011 struct stmmac_priv *priv = netdev_priv(dev);
1012
1013 return ARRAY_SIZE(priv->rss.table);
1014}
1015
1016static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1017 u8 *hfunc)
1018{
1019 struct stmmac_priv *priv = netdev_priv(dev);
1020 int i;
1021
1022 if (indir) {
1023 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1024 indir[i] = priv->rss.table[i];
1025 }
1026
1027 if (key)
1028 memcpy(key, priv->rss.key, sizeof(priv->rss.key));
1029 if (hfunc)
1030 *hfunc = ETH_RSS_HASH_TOP;
1031
1032 return 0;
1033}
1034
1035static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir,
1036 const u8 *key, const u8 hfunc)
1037{
1038 struct stmmac_priv *priv = netdev_priv(dev);
1039 int i;
1040
1041 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP))
1042 return -EOPNOTSUPP;
1043
1044 if (indir) {
1045 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1046 priv->rss.table[i] = indir[i];
1047 }
1048
1049 if (key)
1050 memcpy(priv->rss.key, key, sizeof(priv->rss.key));
1051
1052 return stmmac_rss_configure(priv, priv->hw, &priv->rss,
1053 priv->plat->rx_queues_to_use);
1054}
1055
1056static void stmmac_get_channels(struct net_device *dev,
1057 struct ethtool_channels *chan)
1058{
1059 struct stmmac_priv *priv = netdev_priv(dev);
1060
1061 chan->rx_count = priv->plat->rx_queues_to_use;
1062 chan->tx_count = priv->plat->tx_queues_to_use;
1063 chan->max_rx = priv->dma_cap.number_rx_queues;
1064 chan->max_tx = priv->dma_cap.number_tx_queues;
1065}
1066
1067static int stmmac_set_channels(struct net_device *dev,
1068 struct ethtool_channels *chan)
1069{
1070 struct stmmac_priv *priv = netdev_priv(dev);
1071
1072 if (chan->rx_count > priv->dma_cap.number_rx_queues ||
1073 chan->tx_count > priv->dma_cap.number_tx_queues ||
1074 !chan->rx_count || !chan->tx_count)
1075 return -EINVAL;
1076
1077 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count);
1078}
1079
1080static int stmmac_get_ts_info(struct net_device *dev,
1081 struct ethtool_ts_info *info)
1082{
1083 struct stmmac_priv *priv = netdev_priv(dev);
1084
1085 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
1086
1087 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1088 SOF_TIMESTAMPING_TX_HARDWARE |
1089 SOF_TIMESTAMPING_RX_SOFTWARE |
1090 SOF_TIMESTAMPING_RX_HARDWARE |
1091 SOF_TIMESTAMPING_SOFTWARE |
1092 SOF_TIMESTAMPING_RAW_HARDWARE;
1093
1094 if (priv->ptp_clock)
1095 info->phc_index = ptp_clock_index(priv->ptp_clock);
1096
1097 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1098
1099 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
1100 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1101 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1102 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1103 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1104 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1105 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1106 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1107 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1108 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
1109 (1 << HWTSTAMP_FILTER_ALL));
1110 return 0;
1111 } else
1112 return ethtool_op_get_ts_info(dev, info);
1113}
1114
1115static int stmmac_get_tunable(struct net_device *dev,
1116 const struct ethtool_tunable *tuna, void *data)
1117{
1118 struct stmmac_priv *priv = netdev_priv(dev);
1119 int ret = 0;
1120
1121 switch (tuna->id) {
1122 case ETHTOOL_RX_COPYBREAK:
1123 *(u32 *)data = priv->rx_copybreak;
1124 break;
1125 default:
1126 ret = -EINVAL;
1127 break;
1128 }
1129
1130 return ret;
1131}
1132
1133static int stmmac_set_tunable(struct net_device *dev,
1134 const struct ethtool_tunable *tuna,
1135 const void *data)
1136{
1137 struct stmmac_priv *priv = netdev_priv(dev);
1138 int ret = 0;
1139
1140 switch (tuna->id) {
1141 case ETHTOOL_RX_COPYBREAK:
1142 priv->rx_copybreak = *(u32 *)data;
1143 break;
1144 default:
1145 ret = -EINVAL;
1146 break;
1147 }
1148
1149 return ret;
1150}
1151
1152static const struct ethtool_ops stmmac_ethtool_ops = {
1153 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1154 ETHTOOL_COALESCE_MAX_FRAMES,
1155 .begin = stmmac_check_if_running,
1156 .get_drvinfo = stmmac_ethtool_getdrvinfo,
1157 .get_msglevel = stmmac_ethtool_getmsglevel,
1158 .set_msglevel = stmmac_ethtool_setmsglevel,
1159 .get_regs = stmmac_ethtool_gregs,
1160 .get_regs_len = stmmac_ethtool_get_regs_len,
1161 .get_link = ethtool_op_get_link,
1162 .nway_reset = stmmac_nway_reset,
1163 .get_ringparam = stmmac_get_ringparam,
1164 .set_ringparam = stmmac_set_ringparam,
1165 .get_pauseparam = stmmac_get_pauseparam,
1166 .set_pauseparam = stmmac_set_pauseparam,
1167 .self_test = stmmac_selftest_run,
1168 .get_ethtool_stats = stmmac_get_ethtool_stats,
1169 .get_strings = stmmac_get_strings,
1170 .get_wol = stmmac_get_wol,
1171 .set_wol = stmmac_set_wol,
1172 .get_eee = stmmac_ethtool_op_get_eee,
1173 .set_eee = stmmac_ethtool_op_set_eee,
1174 .get_sset_count = stmmac_get_sset_count,
1175 .get_rxnfc = stmmac_get_rxnfc,
1176 .get_rxfh_key_size = stmmac_get_rxfh_key_size,
1177 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size,
1178 .get_rxfh = stmmac_get_rxfh,
1179 .set_rxfh = stmmac_set_rxfh,
1180 .get_ts_info = stmmac_get_ts_info,
1181 .get_coalesce = stmmac_get_coalesce,
1182 .set_coalesce = stmmac_set_coalesce,
1183 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce,
1184 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce,
1185 .get_channels = stmmac_get_channels,
1186 .set_channels = stmmac_set_channels,
1187 .get_tunable = stmmac_get_tunable,
1188 .set_tunable = stmmac_set_tunable,
1189 .get_link_ksettings = stmmac_ethtool_get_link_ksettings,
1190 .set_link_ksettings = stmmac_ethtool_set_link_ksettings,
1191};
1192
1193void stmmac_set_ethtool_ops(struct net_device *netdev)
1194{
1195 netdev->ethtool_ops = &stmmac_ethtool_ops;
1196}