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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 *
6 * Copyright (c) 2018 Baylibre, SAS.
7 * Author: Jerome Brunet <jbrunet@baylibre.com>
8 */
9
10/*
11 * In the most basic form, a Meson PLL is composed as follows:
12 *
13 * PLL
14 * +--------------------------------+
15 * | |
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
21 * | | | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
23 * | |
24 * +--------------------------------+
25 *
26 * out = in * (m + frac / frac_max) / n
27 */
28
29#include <linux/clk-provider.h>
30#include <linux/delay.h>
31#include <linux/err.h>
32#include <linux/io.h>
33#include <linux/math64.h>
34#include <linux/module.h>
35
36#include "clk-regmap.h"
37#include "clk-pll.h"
38
39static inline struct meson_clk_pll_data *
40meson_clk_pll_data(struct clk_regmap *clk)
41{
42 return (struct meson_clk_pll_data *)clk->data;
43}
44
45static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
46{
47 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
48 !MESON_PARM_APPLICABLE(&pll->frac))
49 return 1;
50
51 return 0;
52}
53
54static unsigned long __pll_params_to_rate(unsigned long parent_rate,
55 unsigned int m, unsigned int n,
56 unsigned int frac,
57 struct meson_clk_pll_data *pll)
58{
59 u64 rate = (u64)parent_rate * m;
60
61 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
62 u64 frac_rate = (u64)parent_rate * frac;
63
64 rate += DIV_ROUND_UP_ULL(frac_rate,
65 (1 << pll->frac.width));
66 }
67
68 return DIV_ROUND_UP_ULL(rate, n);
69}
70
71static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
72 unsigned long parent_rate)
73{
74 struct clk_regmap *clk = to_clk_regmap(hw);
75 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
76 unsigned int m, n, frac;
77
78 n = meson_parm_read(clk->map, &pll->n);
79
80 /*
81 * On some HW, N is set to zero on init. This value is invalid as
82 * it would result in a division by zero. The rate can't be
83 * calculated in this case
84 */
85 if (n == 0)
86 return 0;
87
88 m = meson_parm_read(clk->map, &pll->m);
89
90 frac = MESON_PARM_APPLICABLE(&pll->frac) ?
91 meson_parm_read(clk->map, &pll->frac) :
92 0;
93
94 return __pll_params_to_rate(parent_rate, m, n, frac, pll);
95}
96
97static unsigned int __pll_params_with_frac(unsigned long rate,
98 unsigned long parent_rate,
99 unsigned int m,
100 unsigned int n,
101 struct meson_clk_pll_data *pll)
102{
103 unsigned int frac_max = (1 << pll->frac.width);
104 u64 val = (u64)rate * n;
105
106 /* Bail out if we are already over the requested rate */
107 if (rate < parent_rate * m / n)
108 return 0;
109
110 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
111 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
112 else
113 val = div_u64(val * frac_max, parent_rate);
114
115 val -= m * frac_max;
116
117 return min((unsigned int)val, (frac_max - 1));
118}
119
120static bool meson_clk_pll_is_better(unsigned long rate,
121 unsigned long best,
122 unsigned long now,
123 struct meson_clk_pll_data *pll)
124{
125 if (__pll_round_closest_mult(pll)) {
126 /* Round Closest */
127 if (abs(now - rate) < abs(best - rate))
128 return true;
129 } else {
130 /* Round down */
131 if (now <= rate && best < now)
132 return true;
133 }
134
135 return false;
136}
137
138static int meson_clk_get_pll_table_index(unsigned int index,
139 unsigned int *m,
140 unsigned int *n,
141 struct meson_clk_pll_data *pll)
142{
143 if (!pll->table[index].n)
144 return -EINVAL;
145
146 *m = pll->table[index].m;
147 *n = pll->table[index].n;
148
149 return 0;
150}
151
152static unsigned int meson_clk_get_pll_range_m(unsigned long rate,
153 unsigned long parent_rate,
154 unsigned int n,
155 struct meson_clk_pll_data *pll)
156{
157 u64 val = (u64)rate * n;
158
159 if (__pll_round_closest_mult(pll))
160 return DIV_ROUND_CLOSEST_ULL(val, parent_rate);
161
162 return div_u64(val, parent_rate);
163}
164
165static int meson_clk_get_pll_range_index(unsigned long rate,
166 unsigned long parent_rate,
167 unsigned int index,
168 unsigned int *m,
169 unsigned int *n,
170 struct meson_clk_pll_data *pll)
171{
172 *n = index + 1;
173
174 /* Check the predivider range */
175 if (*n >= (1 << pll->n.width))
176 return -EINVAL;
177
178 if (*n == 1) {
179 /* Get the boundaries out the way */
180 if (rate <= pll->range->min * parent_rate) {
181 *m = pll->range->min;
182 return -ENODATA;
183 } else if (rate >= pll->range->max * parent_rate) {
184 *m = pll->range->max;
185 return -ENODATA;
186 }
187 }
188
189 *m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
190
191 /* the pre-divider gives a multiplier too big - stop */
192 if (*m >= (1 << pll->m.width))
193 return -EINVAL;
194
195 return 0;
196}
197
198static int meson_clk_get_pll_get_index(unsigned long rate,
199 unsigned long parent_rate,
200 unsigned int index,
201 unsigned int *m,
202 unsigned int *n,
203 struct meson_clk_pll_data *pll)
204{
205 if (pll->range)
206 return meson_clk_get_pll_range_index(rate, parent_rate,
207 index, m, n, pll);
208 else if (pll->table)
209 return meson_clk_get_pll_table_index(index, m, n, pll);
210
211 return -EINVAL;
212}
213
214static int meson_clk_get_pll_settings(unsigned long rate,
215 unsigned long parent_rate,
216 unsigned int *best_m,
217 unsigned int *best_n,
218 struct meson_clk_pll_data *pll)
219{
220 unsigned long best = 0, now = 0;
221 unsigned int i, m, n;
222 int ret;
223
224 for (i = 0, ret = 0; !ret; i++) {
225 ret = meson_clk_get_pll_get_index(rate, parent_rate,
226 i, &m, &n, pll);
227 if (ret == -EINVAL)
228 break;
229
230 now = __pll_params_to_rate(parent_rate, m, n, 0, pll);
231 if (meson_clk_pll_is_better(rate, best, now, pll)) {
232 best = now;
233 *best_m = m;
234 *best_n = n;
235
236 if (now == rate)
237 break;
238 }
239 }
240
241 return best ? 0 : -EINVAL;
242}
243
244static int meson_clk_pll_determine_rate(struct clk_hw *hw,
245 struct clk_rate_request *req)
246{
247 struct clk_regmap *clk = to_clk_regmap(hw);
248 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
249 unsigned int m, n, frac;
250 unsigned long round;
251 int ret;
252
253 ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,
254 &m, &n, pll);
255 if (ret)
256 return ret;
257
258 round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
259
260 if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {
261 req->rate = round;
262 return 0;
263 }
264
265 /*
266 * The rate provided by the setting is not an exact match, let's
267 * try to improve the result using the fractional parameter
268 */
269 frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
270 req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
271
272 return 0;
273}
274
275static int meson_clk_pll_wait_lock(struct clk_hw *hw)
276{
277 struct clk_regmap *clk = to_clk_regmap(hw);
278 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
279 int delay = 5000;
280
281 do {
282 /* Is the clock locked now ? Time out after 100ms. */
283 if (meson_parm_read(clk->map, &pll->l))
284 return 0;
285
286 udelay(20);
287 } while (--delay);
288
289 return -ETIMEDOUT;
290}
291
292static int meson_clk_pll_init(struct clk_hw *hw)
293{
294 struct clk_regmap *clk = to_clk_regmap(hw);
295 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
296
297 if (pll->init_count) {
298 meson_parm_write(clk->map, &pll->rst, 1);
299 regmap_multi_reg_write(clk->map, pll->init_regs,
300 pll->init_count);
301 meson_parm_write(clk->map, &pll->rst, 0);
302 }
303
304 return 0;
305}
306
307static int meson_clk_pll_is_enabled(struct clk_hw *hw)
308{
309 struct clk_regmap *clk = to_clk_regmap(hw);
310 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
311
312 if (meson_parm_read(clk->map, &pll->rst) ||
313 !meson_parm_read(clk->map, &pll->en) ||
314 !meson_parm_read(clk->map, &pll->l))
315 return 0;
316
317 return 1;
318}
319
320static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
321{
322 int retries = 10;
323
324 do {
325 meson_clk_pll_init(hw);
326 if (!meson_clk_pll_wait_lock(hw))
327 return 0;
328 pr_info("Retry enabling PCIe PLL clock\n");
329 } while (--retries);
330
331 return -EIO;
332}
333
334static int meson_clk_pll_enable(struct clk_hw *hw)
335{
336 struct clk_regmap *clk = to_clk_regmap(hw);
337 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
338
339 /* do nothing if the PLL is already enabled */
340 if (clk_hw_is_enabled(hw))
341 return 0;
342
343 /* Make sure the pll is in reset */
344 meson_parm_write(clk->map, &pll->rst, 1);
345
346 /* Enable the pll */
347 meson_parm_write(clk->map, &pll->en, 1);
348
349 /* Take the pll out reset */
350 meson_parm_write(clk->map, &pll->rst, 0);
351
352 if (meson_clk_pll_wait_lock(hw))
353 return -EIO;
354
355 return 0;
356}
357
358static void meson_clk_pll_disable(struct clk_hw *hw)
359{
360 struct clk_regmap *clk = to_clk_regmap(hw);
361 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
362
363 /* Put the pll is in reset */
364 meson_parm_write(clk->map, &pll->rst, 1);
365
366 /* Disable the pll */
367 meson_parm_write(clk->map, &pll->en, 0);
368}
369
370static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate)
372{
373 struct clk_regmap *clk = to_clk_regmap(hw);
374 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
375 unsigned int enabled, m, n, frac = 0;
376 unsigned long old_rate;
377 int ret;
378
379 if (parent_rate == 0 || rate == 0)
380 return -EINVAL;
381
382 old_rate = clk_hw_get_rate(hw);
383
384 ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
385 if (ret)
386 return ret;
387
388 enabled = meson_parm_read(clk->map, &pll->en);
389 if (enabled)
390 meson_clk_pll_disable(hw);
391
392 meson_parm_write(clk->map, &pll->n, n);
393 meson_parm_write(clk->map, &pll->m, m);
394
395 if (MESON_PARM_APPLICABLE(&pll->frac)) {
396 frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
397 meson_parm_write(clk->map, &pll->frac, frac);
398 }
399
400 /* If the pll is stopped, bail out now */
401 if (!enabled)
402 return 0;
403
404 ret = meson_clk_pll_enable(hw);
405 if (ret) {
406 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
407 __func__, old_rate);
408 /*
409 * FIXME: Do we really need/want this HACK ?
410 * It looks unsafe. what happens if the clock gets into a
411 * broken state and we can't lock back on the old_rate ? Looks
412 * like an infinite recursion is possible
413 */
414 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
415 }
416
417 return ret;
418}
419
420/*
421 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
422 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
423 * a strict register sequence to enable the PLL.
424 * To simplify, re-use the _init() op to enable the PLL and keep
425 * the other ops except set_rate since the rate is fixed.
426 */
427const struct clk_ops meson_clk_pcie_pll_ops = {
428 .recalc_rate = meson_clk_pll_recalc_rate,
429 .determine_rate = meson_clk_pll_determine_rate,
430 .is_enabled = meson_clk_pll_is_enabled,
431 .enable = meson_clk_pcie_pll_enable,
432 .disable = meson_clk_pll_disable
433};
434EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
435
436const struct clk_ops meson_clk_pll_ops = {
437 .init = meson_clk_pll_init,
438 .recalc_rate = meson_clk_pll_recalc_rate,
439 .determine_rate = meson_clk_pll_determine_rate,
440 .set_rate = meson_clk_pll_set_rate,
441 .is_enabled = meson_clk_pll_is_enabled,
442 .enable = meson_clk_pll_enable,
443 .disable = meson_clk_pll_disable
444};
445EXPORT_SYMBOL_GPL(meson_clk_pll_ops);
446
447const struct clk_ops meson_clk_pll_ro_ops = {
448 .recalc_rate = meson_clk_pll_recalc_rate,
449 .is_enabled = meson_clk_pll_is_enabled,
450};
451EXPORT_SYMBOL_GPL(meson_clk_pll_ro_ops);
452
453MODULE_DESCRIPTION("Amlogic PLL driver");
454MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
455MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
456MODULE_LICENSE("GPL v2");