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1/*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
7 *
8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
9 *
10 * This code is released under the GNU General Public License version 2 or
11 * later.
12 */
13
14#include <linux/init.h>
15
16#include <linux/mm.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/export.h>
20#include <linux/kernel_stat.h>
21#include <linux/mc146818rtc.h>
22#include <linux/cache.h>
23#include <linux/interrupt.h>
24#include <linux/cpu.h>
25#include <linux/gfp.h>
26
27#include <asm/mtrr.h>
28#include <asm/tlbflush.h>
29#include <asm/mmu_context.h>
30#include <asm/proto.h>
31#include <asm/apic.h>
32#include <asm/nmi.h>
33/*
34 * Some notes on x86 processor bugs affecting SMP operation:
35 *
36 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
37 * The Linux implications for SMP are handled as follows:
38 *
39 * Pentium III / [Xeon]
40 * None of the E1AP-E3AP errata are visible to the user.
41 *
42 * E1AP. see PII A1AP
43 * E2AP. see PII A2AP
44 * E3AP. see PII A3AP
45 *
46 * Pentium II / [Xeon]
47 * None of the A1AP-A3AP errata are visible to the user.
48 *
49 * A1AP. see PPro 1AP
50 * A2AP. see PPro 2AP
51 * A3AP. see PPro 7AP
52 *
53 * Pentium Pro
54 * None of 1AP-9AP errata are visible to the normal user,
55 * except occasional delivery of 'spurious interrupt' as trap #15.
56 * This is very rare and a non-problem.
57 *
58 * 1AP. Linux maps APIC as non-cacheable
59 * 2AP. worked around in hardware
60 * 3AP. fixed in C0 and above steppings microcode update.
61 * Linux does not use excessive STARTUP_IPIs.
62 * 4AP. worked around in hardware
63 * 5AP. symmetric IO mode (normal Linux operation) not affected.
64 * 'noapic' mode has vector 0xf filled out properly.
65 * 6AP. 'noapic' mode might be affected - fixed in later steppings
66 * 7AP. We do not assume writes to the LVT deassering IRQs
67 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
68 * 9AP. We do not use mixed mode
69 *
70 * Pentium
71 * There is a marginal case where REP MOVS on 100MHz SMP
72 * machines with B stepping processors can fail. XXX should provide
73 * an L1cache=Writethrough or L1cache=off option.
74 *
75 * B stepping CPUs may hang. There are hardware work arounds
76 * for this. We warn about it in case your board doesn't have the work
77 * arounds. Basically that's so I can tell anyone with a B stepping
78 * CPU and SMP problems "tough".
79 *
80 * Specific items [From Pentium Processor Specification Update]
81 *
82 * 1AP. Linux doesn't use remote read
83 * 2AP. Linux doesn't trust APIC errors
84 * 3AP. We work around this
85 * 4AP. Linux never generated 3 interrupts of the same priority
86 * to cause a lost local interrupt.
87 * 5AP. Remote read is never used
88 * 6AP. not affected - worked around in hardware
89 * 7AP. not affected - worked around in hardware
90 * 8AP. worked around in hardware - we get explicit CS errors if not
91 * 9AP. only 'noapic' mode affected. Might generate spurious
92 * interrupts, we log only the first one and count the
93 * rest silently.
94 * 10AP. not affected - worked around in hardware
95 * 11AP. Linux reads the APIC between writes to avoid this, as per
96 * the documentation. Make sure you preserve this as it affects
97 * the C stepping chips too.
98 * 12AP. not affected - worked around in hardware
99 * 13AP. not affected - worked around in hardware
100 * 14AP. we always deassert INIT during bootup
101 * 15AP. not affected - worked around in hardware
102 * 16AP. not affected - worked around in hardware
103 * 17AP. not affected - worked around in hardware
104 * 18AP. not affected - worked around in hardware
105 * 19AP. not affected - worked around in BIOS
106 *
107 * If this sounds worrying believe me these bugs are either ___RARE___,
108 * or are signal timing bugs worked around in hardware and there's
109 * about nothing of note with C stepping upwards.
110 */
111
112static atomic_t stopping_cpu = ATOMIC_INIT(-1);
113static bool smp_no_nmi_ipi = false;
114
115/*
116 * this function sends a 'reschedule' IPI to another CPU.
117 * it goes straight through and wastes no time serializing
118 * anything. Worst case is that we lose a reschedule ...
119 */
120static void native_smp_send_reschedule(int cpu)
121{
122 if (unlikely(cpu_is_offline(cpu))) {
123 WARN_ON(1);
124 return;
125 }
126 apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
127}
128
129void native_send_call_func_single_ipi(int cpu)
130{
131 apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
132}
133
134void native_send_call_func_ipi(const struct cpumask *mask)
135{
136 cpumask_var_t allbutself;
137
138 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
139 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
140 return;
141 }
142
143 cpumask_copy(allbutself, cpu_online_mask);
144 cpumask_clear_cpu(smp_processor_id(), allbutself);
145
146 if (cpumask_equal(mask, allbutself) &&
147 cpumask_equal(cpu_online_mask, cpu_callout_mask))
148 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
149 else
150 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
151
152 free_cpumask_var(allbutself);
153}
154
155static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
156{
157 /* We are registered on stopping cpu too, avoid spurious NMI */
158 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
159 return NMI_HANDLED;
160
161 stop_this_cpu(NULL);
162
163 return NMI_HANDLED;
164}
165
166/*
167 * this function calls the 'stop' function on all other CPUs in the system.
168 */
169
170asmlinkage void smp_reboot_interrupt(void)
171{
172 ack_APIC_irq();
173 irq_enter();
174 stop_this_cpu(NULL);
175 irq_exit();
176}
177
178static void native_stop_other_cpus(int wait)
179{
180 unsigned long flags;
181 unsigned long timeout;
182
183 if (reboot_force)
184 return;
185
186 /*
187 * Use an own vector here because smp_call_function
188 * does lots of things not suitable in a panic situation.
189 */
190
191 /*
192 * We start by using the REBOOT_VECTOR irq.
193 * The irq is treated as a sync point to allow critical
194 * regions of code on other cpus to release their spin locks
195 * and re-enable irqs. Jumping straight to an NMI might
196 * accidentally cause deadlocks with further shutdown/panic
197 * code. By syncing, we give the cpus up to one second to
198 * finish their work before we force them off with the NMI.
199 */
200 if (num_online_cpus() > 1) {
201 /* did someone beat us here? */
202 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
203 return;
204
205 /* sync above data before sending IRQ */
206 wmb();
207
208 apic->send_IPI_allbutself(REBOOT_VECTOR);
209
210 /*
211 * Don't wait longer than a second if the caller
212 * didn't ask us to wait.
213 */
214 timeout = USEC_PER_SEC;
215 while (num_online_cpus() > 1 && (wait || timeout--))
216 udelay(1);
217 }
218
219 /* if the REBOOT_VECTOR didn't work, try with the NMI */
220 if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi)) {
221 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
222 NMI_FLAG_FIRST, "smp_stop"))
223 /* Note: we ignore failures here */
224 /* Hope the REBOOT_IRQ is good enough */
225 goto finish;
226
227 /* sync above data before sending IRQ */
228 wmb();
229
230 pr_emerg("Shutting down cpus with NMI\n");
231
232 apic->send_IPI_allbutself(NMI_VECTOR);
233
234 /*
235 * Don't wait longer than a 10 ms if the caller
236 * didn't ask us to wait.
237 */
238 timeout = USEC_PER_MSEC * 10;
239 while (num_online_cpus() > 1 && (wait || timeout--))
240 udelay(1);
241 }
242
243finish:
244 local_irq_save(flags);
245 disable_local_APIC();
246 local_irq_restore(flags);
247}
248
249/*
250 * Reschedule call back.
251 */
252void smp_reschedule_interrupt(struct pt_regs *regs)
253{
254 ack_APIC_irq();
255 inc_irq_stat(irq_resched_count);
256 scheduler_ipi();
257 /*
258 * KVM uses this interrupt to force a cpu out of guest mode
259 */
260}
261
262void smp_call_function_interrupt(struct pt_regs *regs)
263{
264 ack_APIC_irq();
265 irq_enter();
266 generic_smp_call_function_interrupt();
267 inc_irq_stat(irq_call_count);
268 irq_exit();
269}
270
271void smp_call_function_single_interrupt(struct pt_regs *regs)
272{
273 ack_APIC_irq();
274 irq_enter();
275 generic_smp_call_function_single_interrupt();
276 inc_irq_stat(irq_call_count);
277 irq_exit();
278}
279
280static int __init nonmi_ipi_setup(char *str)
281{
282 smp_no_nmi_ipi = true;
283 return 1;
284}
285
286__setup("nonmi_ipi", nonmi_ipi_setup);
287
288struct smp_ops smp_ops = {
289 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
290 .smp_prepare_cpus = native_smp_prepare_cpus,
291 .smp_cpus_done = native_smp_cpus_done,
292
293 .stop_other_cpus = native_stop_other_cpus,
294 .smp_send_reschedule = native_smp_send_reschedule,
295
296 .cpu_up = native_cpu_up,
297 .cpu_die = native_cpu_die,
298 .cpu_disable = native_cpu_disable,
299 .play_dead = native_play_dead,
300
301 .send_call_func_ipi = native_send_call_func_ipi,
302 .send_call_func_single_ipi = native_send_call_func_single_ipi,
303};
304EXPORT_SYMBOL_GPL(smp_ops);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Intel SMP support routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * (c) 2002,2003 Andi Kleen, SuSE Labs.
8 *
9 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
10 */
11
12#include <linux/init.h>
13
14#include <linux/mm.h>
15#include <linux/delay.h>
16#include <linux/spinlock.h>
17#include <linux/export.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/cache.h>
21#include <linux/interrupt.h>
22#include <linux/cpu.h>
23#include <linux/gfp.h>
24
25#include <asm/mtrr.h>
26#include <asm/tlbflush.h>
27#include <asm/mmu_context.h>
28#include <asm/proto.h>
29#include <asm/apic.h>
30#include <asm/idtentry.h>
31#include <asm/nmi.h>
32#include <asm/mce.h>
33#include <asm/trace/irq_vectors.h>
34#include <asm/kexec.h>
35#include <asm/virtext.h>
36
37/*
38 * Some notes on x86 processor bugs affecting SMP operation:
39 *
40 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
41 * The Linux implications for SMP are handled as follows:
42 *
43 * Pentium III / [Xeon]
44 * None of the E1AP-E3AP errata are visible to the user.
45 *
46 * E1AP. see PII A1AP
47 * E2AP. see PII A2AP
48 * E3AP. see PII A3AP
49 *
50 * Pentium II / [Xeon]
51 * None of the A1AP-A3AP errata are visible to the user.
52 *
53 * A1AP. see PPro 1AP
54 * A2AP. see PPro 2AP
55 * A3AP. see PPro 7AP
56 *
57 * Pentium Pro
58 * None of 1AP-9AP errata are visible to the normal user,
59 * except occasional delivery of 'spurious interrupt' as trap #15.
60 * This is very rare and a non-problem.
61 *
62 * 1AP. Linux maps APIC as non-cacheable
63 * 2AP. worked around in hardware
64 * 3AP. fixed in C0 and above steppings microcode update.
65 * Linux does not use excessive STARTUP_IPIs.
66 * 4AP. worked around in hardware
67 * 5AP. symmetric IO mode (normal Linux operation) not affected.
68 * 'noapic' mode has vector 0xf filled out properly.
69 * 6AP. 'noapic' mode might be affected - fixed in later steppings
70 * 7AP. We do not assume writes to the LVT deasserting IRQs
71 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
72 * 9AP. We do not use mixed mode
73 *
74 * Pentium
75 * There is a marginal case where REP MOVS on 100MHz SMP
76 * machines with B stepping processors can fail. XXX should provide
77 * an L1cache=Writethrough or L1cache=off option.
78 *
79 * B stepping CPUs may hang. There are hardware work arounds
80 * for this. We warn about it in case your board doesn't have the work
81 * arounds. Basically that's so I can tell anyone with a B stepping
82 * CPU and SMP problems "tough".
83 *
84 * Specific items [From Pentium Processor Specification Update]
85 *
86 * 1AP. Linux doesn't use remote read
87 * 2AP. Linux doesn't trust APIC errors
88 * 3AP. We work around this
89 * 4AP. Linux never generated 3 interrupts of the same priority
90 * to cause a lost local interrupt.
91 * 5AP. Remote read is never used
92 * 6AP. not affected - worked around in hardware
93 * 7AP. not affected - worked around in hardware
94 * 8AP. worked around in hardware - we get explicit CS errors if not
95 * 9AP. only 'noapic' mode affected. Might generate spurious
96 * interrupts, we log only the first one and count the
97 * rest silently.
98 * 10AP. not affected - worked around in hardware
99 * 11AP. Linux reads the APIC between writes to avoid this, as per
100 * the documentation. Make sure you preserve this as it affects
101 * the C stepping chips too.
102 * 12AP. not affected - worked around in hardware
103 * 13AP. not affected - worked around in hardware
104 * 14AP. we always deassert INIT during bootup
105 * 15AP. not affected - worked around in hardware
106 * 16AP. not affected - worked around in hardware
107 * 17AP. not affected - worked around in hardware
108 * 18AP. not affected - worked around in hardware
109 * 19AP. not affected - worked around in BIOS
110 *
111 * If this sounds worrying believe me these bugs are either ___RARE___,
112 * or are signal timing bugs worked around in hardware and there's
113 * about nothing of note with C stepping upwards.
114 */
115
116static atomic_t stopping_cpu = ATOMIC_INIT(-1);
117static bool smp_no_nmi_ipi = false;
118
119static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
120{
121 /* We are registered on stopping cpu too, avoid spurious NMI */
122 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
123 return NMI_HANDLED;
124
125 cpu_emergency_vmxoff();
126 stop_this_cpu(NULL);
127
128 return NMI_HANDLED;
129}
130
131/*
132 * this function calls the 'stop' function on all other CPUs in the system.
133 */
134DEFINE_IDTENTRY_SYSVEC(sysvec_reboot)
135{
136 ack_APIC_irq();
137 cpu_emergency_vmxoff();
138 stop_this_cpu(NULL);
139}
140
141static int register_stop_handler(void)
142{
143 return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
144 NMI_FLAG_FIRST, "smp_stop");
145}
146
147static void native_stop_other_cpus(int wait)
148{
149 unsigned long flags;
150 unsigned long timeout;
151
152 if (reboot_force)
153 return;
154
155 /*
156 * Use an own vector here because smp_call_function
157 * does lots of things not suitable in a panic situation.
158 */
159
160 /*
161 * We start by using the REBOOT_VECTOR irq.
162 * The irq is treated as a sync point to allow critical
163 * regions of code on other cpus to release their spin locks
164 * and re-enable irqs. Jumping straight to an NMI might
165 * accidentally cause deadlocks with further shutdown/panic
166 * code. By syncing, we give the cpus up to one second to
167 * finish their work before we force them off with the NMI.
168 */
169 if (num_online_cpus() > 1) {
170 /* did someone beat us here? */
171 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
172 return;
173
174 /* sync above data before sending IRQ */
175 wmb();
176
177 apic_send_IPI_allbutself(REBOOT_VECTOR);
178
179 /*
180 * Don't wait longer than a second for IPI completion. The
181 * wait request is not checked here because that would
182 * prevent an NMI shutdown attempt in case that not all
183 * CPUs reach shutdown state.
184 */
185 timeout = USEC_PER_SEC;
186 while (num_online_cpus() > 1 && timeout--)
187 udelay(1);
188 }
189
190 /* if the REBOOT_VECTOR didn't work, try with the NMI */
191 if (num_online_cpus() > 1) {
192 /*
193 * If NMI IPI is enabled, try to register the stop handler
194 * and send the IPI. In any case try to wait for the other
195 * CPUs to stop.
196 */
197 if (!smp_no_nmi_ipi && !register_stop_handler()) {
198 /* Sync above data before sending IRQ */
199 wmb();
200
201 pr_emerg("Shutting down cpus with NMI\n");
202
203 apic_send_IPI_allbutself(NMI_VECTOR);
204 }
205 /*
206 * Don't wait longer than 10 ms if the caller didn't
207 * request it. If wait is true, the machine hangs here if
208 * one or more CPUs do not reach shutdown state.
209 */
210 timeout = USEC_PER_MSEC * 10;
211 while (num_online_cpus() > 1 && (wait || timeout--))
212 udelay(1);
213 }
214
215 local_irq_save(flags);
216 disable_local_APIC();
217 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
218 local_irq_restore(flags);
219}
220
221/*
222 * Reschedule call back. KVM uses this interrupt to force a cpu out of
223 * guest mode.
224 */
225DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi)
226{
227 ack_APIC_irq();
228 trace_reschedule_entry(RESCHEDULE_VECTOR);
229 inc_irq_stat(irq_resched_count);
230 scheduler_ipi();
231 trace_reschedule_exit(RESCHEDULE_VECTOR);
232}
233
234DEFINE_IDTENTRY_SYSVEC(sysvec_call_function)
235{
236 ack_APIC_irq();
237 trace_call_function_entry(CALL_FUNCTION_VECTOR);
238 inc_irq_stat(irq_call_count);
239 generic_smp_call_function_interrupt();
240 trace_call_function_exit(CALL_FUNCTION_VECTOR);
241}
242
243DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single)
244{
245 ack_APIC_irq();
246 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
247 inc_irq_stat(irq_call_count);
248 generic_smp_call_function_single_interrupt();
249 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
250}
251
252static int __init nonmi_ipi_setup(char *str)
253{
254 smp_no_nmi_ipi = true;
255 return 1;
256}
257
258__setup("nonmi_ipi", nonmi_ipi_setup);
259
260struct smp_ops smp_ops = {
261 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
262 .smp_prepare_cpus = native_smp_prepare_cpus,
263 .smp_cpus_done = native_smp_cpus_done,
264
265 .stop_other_cpus = native_stop_other_cpus,
266#if defined(CONFIG_KEXEC_CORE)
267 .crash_stop_other_cpus = kdump_nmi_shootdown_cpus,
268#endif
269 .smp_send_reschedule = native_smp_send_reschedule,
270
271 .cpu_up = native_cpu_up,
272 .cpu_die = native_cpu_die,
273 .cpu_disable = native_cpu_disable,
274 .play_dead = native_play_dead,
275
276 .send_call_func_ipi = native_send_call_func_ipi,
277 .send_call_func_single_ipi = native_send_call_func_single_ipi,
278};
279EXPORT_SYMBOL_GPL(smp_ops);