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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Arasan Secure Digital Host Controller Interface.
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 Wind River Systems, Inc.
6 * Copyright (C) 2013 Pengutronix e.K.
7 * Copyright (C) 2013 Xilinx Inc.
8 *
9 * Based on sdhci-of-esdhc.c
10 *
11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
12 * Copyright (c) 2009 MontaVista Software, Inc.
13 *
14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
15 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/mfd/syscon.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/phy/phy.h>
24#include <linux/regmap.h>
25#include <linux/reset.h>
26#include <linux/firmware/xlnx-zynqmp.h>
27
28#include "cqhci.h"
29#include "sdhci-cqhci.h"
30#include "sdhci-pltfm.h"
31
32#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
33
34#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
35#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
36
37#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
38#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
39
40#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
41#define VENDOR_ENHANCED_STROBE BIT(0)
42
43#define PHY_CLK_TOO_SLOW_HZ 400000
44#define MIN_PHY_CLK_HZ 50000000
45
46#define SDHCI_ITAPDLY_CHGWIN 0x200
47#define SDHCI_ITAPDLY_ENABLE 0x100
48#define SDHCI_OTAPDLY_ENABLE 0x40
49
50#define PHY_CTRL_REG1 0x270
51#define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0)
52#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)
53#define PHY_CTRL_ITAPDLY_SEL_SHIFT 1
54#define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6)
55#define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
56#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12)
57#define PHY_CTRL_OTAPDLY_SEL_SHIFT 12
58#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16)
59#define PHY_CTRL_STRB_SEL_SHIFT 16
60#define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24)
61
62#define PHY_CTRL_REG2 0x274
63#define PHY_CTRL_EN_DLL_MASK BIT(0)
64#define PHY_CTRL_DLL_RDY_MASK BIT(1)
65#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4)
66#define PHY_CTRL_FREQ_SEL_SHIFT 4
67#define PHY_CTRL_SEL_DLY_TX_MASK BIT(16)
68#define PHY_CTRL_SEL_DLY_RX_MASK BIT(17)
69#define FREQSEL_200M_170M 0x0
70#define FREQSEL_170M_140M 0x1
71#define FREQSEL_140M_110M 0x2
72#define FREQSEL_110M_80M 0x3
73#define FREQSEL_80M_50M 0x4
74#define FREQSEL_275M_250M 0x5
75#define FREQSEL_250M_225M 0x6
76#define FREQSEL_225M_200M 0x7
77#define PHY_DLL_TIMEOUT_MS 100
78
79#define SDHCI_HW_RST_EN BIT(4)
80
81/* Default settings for ZynqMP Clock Phases */
82#define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
83#define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
84
85#define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
86#define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
87
88#define VERSAL_NET_EMMC_ICLK_PHASE {0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 0}
89#define VERSAL_NET_EMMC_OCLK_PHASE {0, 113, 0, 0, 0, 0, 0, 0, 113, 79, 45}
90
91#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77
92
93/*
94 * On some SoCs the syscon area has a feature where the upper 16-bits of
95 * each 32-bit register act as a write mask for the lower 16-bits. This allows
96 * atomic updates of the register without locking. This macro is used on SoCs
97 * that have that feature.
98 */
99#define HIWORD_UPDATE(val, mask, shift) \
100 ((val) << (shift) | (mask) << ((shift) + 16))
101
102/**
103 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
104 *
105 * @reg: Offset within the syscon of the register containing this field
106 * @width: Number of bits for this field
107 * @shift: Bit offset within @reg of this field (or -1 if not avail)
108 */
109struct sdhci_arasan_soc_ctl_field {
110 u32 reg;
111 u16 width;
112 s16 shift;
113};
114
115/**
116 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
117 *
118 * @baseclkfreq: Where to find corecfg_baseclkfreq
119 * @clockmultiplier: Where to find corecfg_clockmultiplier
120 * @support64b: Where to find SUPPORT64B bit
121 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
122 *
123 * It's up to the licensee of the Arsan IP block to make these available
124 * somewhere if needed. Presumably these will be scattered somewhere that's
125 * accessible via the syscon API.
126 */
127struct sdhci_arasan_soc_ctl_map {
128 struct sdhci_arasan_soc_ctl_field baseclkfreq;
129 struct sdhci_arasan_soc_ctl_field clockmultiplier;
130 struct sdhci_arasan_soc_ctl_field support64b;
131 bool hiword_update;
132};
133
134/**
135 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
136 *
137 * @sdcardclk_ops: The output clock related operations
138 * @sampleclk_ops: The sample clock related operations
139 */
140struct sdhci_arasan_clk_ops {
141 const struct clk_ops *sdcardclk_ops;
142 const struct clk_ops *sampleclk_ops;
143};
144
145/**
146 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
147 *
148 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
149 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
150 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
151 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
152 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
153 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
154 * @set_clk_delays: Function pointer for setting Clock Delays
155 * @clk_of_data: Platform specific runtime clock data storage pointer
156 */
157struct sdhci_arasan_clk_data {
158 struct clk_hw sdcardclk_hw;
159 struct clk *sdcardclk;
160 struct clk_hw sampleclk_hw;
161 struct clk *sampleclk;
162 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
163 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
164 void (*set_clk_delays)(struct sdhci_host *host);
165 void *clk_of_data;
166};
167
168/**
169 * struct sdhci_arasan_data - Arasan Controller Data
170 *
171 * @host: Pointer to the main SDHCI host structure.
172 * @clk_ahb: Pointer to the AHB clock
173 * @phy: Pointer to the generic phy
174 * @is_phy_on: True if the PHY is on; false if not.
175 * @internal_phy_reg: True if the PHY is within the Host controller.
176 * @has_cqe: True if controller has command queuing engine.
177 * @clk_data: Struct for the Arasan Controller Clock Data.
178 * @clk_ops: Struct for the Arasan Controller Clock Operations.
179 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
180 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
181 * @quirks: Arasan deviations from spec.
182 */
183struct sdhci_arasan_data {
184 struct sdhci_host *host;
185 struct clk *clk_ahb;
186 struct phy *phy;
187 bool is_phy_on;
188 bool internal_phy_reg;
189
190 bool has_cqe;
191 struct sdhci_arasan_clk_data clk_data;
192 const struct sdhci_arasan_clk_ops *clk_ops;
193
194 struct regmap *soc_ctl_base;
195 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
196 unsigned int quirks;
197
198/* Controller does not have CD wired and will not function normally without */
199#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
200/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
201 * internal clock even when the clock isn't stable */
202#define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
203/*
204 * Some of the Arasan variations might not have timing requirements
205 * met at 25MHz for Default Speed mode, those controllers work at
206 * 19MHz instead
207 */
208#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
209};
210
211struct sdhci_arasan_of_data {
212 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
213 const struct sdhci_pltfm_data *pdata;
214 const struct sdhci_arasan_clk_ops *clk_ops;
215};
216
217static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
218 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
219 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
220 .hiword_update = true,
221};
222
223static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
224 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
225 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
226 .hiword_update = false,
227};
228
229static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
230 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
231 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
232 .hiword_update = false,
233};
234
235static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
236 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
237 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
238 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
239 .hiword_update = false,
240};
241
242static void sdhci_arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
243{
244 u32 reg;
245
246 reg = readl(host->ioaddr + PHY_CTRL_REG2);
247 if (enable)
248 reg |= (PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
249 else
250 reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
251
252 writel(reg, host->ioaddr + PHY_CTRL_REG2);
253}
254
255static int sdhci_arasan_phy_set_dll(struct sdhci_host *host, bool enable)
256{
257 u32 reg;
258
259 reg = readl(host->ioaddr + PHY_CTRL_REG2);
260 if (enable)
261 reg |= PHY_CTRL_EN_DLL_MASK;
262 else
263 reg &= ~PHY_CTRL_EN_DLL_MASK;
264
265 writel(reg, host->ioaddr + PHY_CTRL_REG2);
266
267 if (!enable)
268 return 0;
269
270 return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
271 (reg & PHY_CTRL_DLL_RDY_MASK), 10,
272 1000 * PHY_DLL_TIMEOUT_MS);
273}
274
275static void sdhci_arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
276{
277 u32 reg, freq_sel, freq;
278
279 freq = DIV_ROUND_CLOSEST(clock, 1000000);
280 if (freq <= 200 && freq > 170)
281 freq_sel = FREQSEL_200M_170M;
282 else if (freq <= 170 && freq > 140)
283 freq_sel = FREQSEL_170M_140M;
284 else if (freq <= 140 && freq > 110)
285 freq_sel = FREQSEL_140M_110M;
286 else if (freq <= 110 && freq > 80)
287 freq_sel = FREQSEL_110M_80M;
288 else
289 freq_sel = FREQSEL_80M_50M;
290
291 reg = readl(host->ioaddr + PHY_CTRL_REG2);
292 reg &= ~PHY_CTRL_FREQ_SEL_MASK;
293 reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT);
294 writel(reg, host->ioaddr + PHY_CTRL_REG2);
295}
296
297/**
298 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
299 *
300 * @host: The sdhci_host
301 * @fld: The field to write to
302 * @val: The value to write
303 *
304 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
305 * Note that if a field is specified as not available (shift < 0) then
306 * this function will silently return an error code. It will be noisy
307 * and print errors for any other (unexpected) errors.
308 *
309 * Return: 0 on success and error value on error
310 */
311static int sdhci_arasan_syscon_write(struct sdhci_host *host,
312 const struct sdhci_arasan_soc_ctl_field *fld,
313 u32 val)
314{
315 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
316 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
317 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
318 u32 reg = fld->reg;
319 u16 width = fld->width;
320 s16 shift = fld->shift;
321 int ret;
322
323 /*
324 * Silently return errors for shift < 0 so caller doesn't have
325 * to check for fields which are optional. For fields that
326 * are required then caller needs to do something special
327 * anyway.
328 */
329 if (shift < 0)
330 return -EINVAL;
331
332 if (sdhci_arasan->soc_ctl_map->hiword_update)
333 ret = regmap_write(soc_ctl_base, reg,
334 HIWORD_UPDATE(val, GENMASK(width, 0),
335 shift));
336 else
337 ret = regmap_update_bits(soc_ctl_base, reg,
338 GENMASK(shift + width, shift),
339 val << shift);
340
341 /* Yell about (unexpected) regmap errors */
342 if (ret)
343 pr_warn("%s: Regmap write fail: %d\n",
344 mmc_hostname(host->mmc), ret);
345
346 return ret;
347}
348
349static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
350{
351 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
353 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
354 bool ctrl_phy = false;
355
356 if (!IS_ERR(sdhci_arasan->phy)) {
357 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
358 /*
359 * If PHY off, set clock to max speed and power PHY on.
360 *
361 * Although PHY docs apparently suggest power cycling
362 * when changing the clock the PHY doesn't like to be
363 * powered on while at low speeds like those used in ID
364 * mode. Even worse is powering the PHY on while the
365 * clock is off.
366 *
367 * To workaround the PHY limitations, the best we can
368 * do is to power it on at a faster speed and then slam
369 * through low speeds without power cycling.
370 */
371 sdhci_set_clock(host, host->max_clk);
372 if (phy_power_on(sdhci_arasan->phy)) {
373 pr_err("%s: Cannot power on phy.\n",
374 mmc_hostname(host->mmc));
375 return;
376 }
377
378 sdhci_arasan->is_phy_on = true;
379
380 /*
381 * We'll now fall through to the below case with
382 * ctrl_phy = false (so we won't turn off/on). The
383 * sdhci_set_clock() will set the real clock.
384 */
385 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
386 /*
387 * At higher clock speeds the PHY is fine being power
388 * cycled and docs say you _should_ power cycle when
389 * changing clock speeds.
390 */
391 ctrl_phy = true;
392 }
393 }
394
395 if (ctrl_phy && sdhci_arasan->is_phy_on) {
396 phy_power_off(sdhci_arasan->phy);
397 sdhci_arasan->is_phy_on = false;
398 }
399
400 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
401 /*
402 * Some of the Arasan variations might not have timing
403 * requirements met at 25MHz for Default Speed mode,
404 * those controllers work at 19MHz instead.
405 */
406 if (clock == DEFAULT_SPEED_MAX_DTR)
407 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
408 }
409
410 /* Set the Input and Output Clock Phase Delays */
411 if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ)
412 clk_data->set_clk_delays(host);
413
414 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
415 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
416 sdhci_arasan_phy_set_dll(host, 0);
417 sdhci_arasan_phy_set_delaychain(host, 0);
418 sdhci_arasan_phy_dll_set_freq(host, clock);
419 } else if (sdhci_arasan->internal_phy_reg) {
420 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
421 sdhci_arasan_phy_set_delaychain(host, 1);
422 }
423
424 sdhci_set_clock(host, clock);
425
426 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ)
427 sdhci_arasan_phy_set_dll(host, 1);
428
429 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
430 /*
431 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
432 * after enabling the clock even though the clock is not
433 * stable. Trying to use a clock without waiting here results
434 * in EILSEQ while detecting some older/slower cards. The
435 * chosen delay is the maximum delay from sdhci_set_clock.
436 */
437 msleep(20);
438
439 if (ctrl_phy) {
440 if (phy_power_on(sdhci_arasan->phy)) {
441 pr_err("%s: Cannot power on phy.\n",
442 mmc_hostname(host->mmc));
443 return;
444 }
445
446 sdhci_arasan->is_phy_on = true;
447 }
448}
449
450static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
451 struct mmc_ios *ios)
452{
453 u32 vendor;
454 struct sdhci_host *host = mmc_priv(mmc);
455
456 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
457 if (ios->enhanced_strobe)
458 vendor |= VENDOR_ENHANCED_STROBE;
459 else
460 vendor &= ~VENDOR_ENHANCED_STROBE;
461
462 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
463}
464
465static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
466{
467 u8 ctrl;
468 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
469 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
470
471 sdhci_and_cqhci_reset(host, mask);
472
473 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
474 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
475 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
476 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
477 }
478}
479
480static void sdhci_arasan_hw_reset(struct sdhci_host *host)
481{
482 u8 reg;
483
484 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
485 reg |= SDHCI_HW_RST_EN;
486 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
487 /* As per eMMC spec, minimum 1us is required but give it 2us for good measure */
488 usleep_range(2, 5);
489 reg &= ~SDHCI_HW_RST_EN;
490 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
491 /* As per eMMC spec, minimum 200us is required but give it 300us for good measure */
492 usleep_range(300, 500);
493}
494
495static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
496 struct mmc_ios *ios)
497{
498 switch (ios->signal_voltage) {
499 case MMC_SIGNAL_VOLTAGE_180:
500 /*
501 * Plese don't switch to 1V8 as arasan,5.1 doesn't
502 * actually refer to this setting to indicate the
503 * signal voltage and the state machine will be broken
504 * actually if we force to enable 1V8. That's something
505 * like broken quirk but we could work around here.
506 */
507 return 0;
508 case MMC_SIGNAL_VOLTAGE_330:
509 case MMC_SIGNAL_VOLTAGE_120:
510 /* We don't support 3V3 and 1V2 */
511 break;
512 }
513
514 return -EINVAL;
515}
516
517static const struct sdhci_ops sdhci_arasan_ops = {
518 .set_clock = sdhci_arasan_set_clock,
519 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
520 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
521 .set_bus_width = sdhci_set_bus_width,
522 .reset = sdhci_arasan_reset,
523 .set_uhs_signaling = sdhci_set_uhs_signaling,
524 .set_power = sdhci_set_power_and_bus_voltage,
525 .hw_reset = sdhci_arasan_hw_reset,
526};
527
528static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
529{
530 int cmd_error = 0;
531 int data_error = 0;
532
533 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
534 return intmask;
535
536 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
537
538 return 0;
539}
540
541static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
542{
543 sdhci_dumpregs(mmc_priv(mmc));
544}
545
546static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
547{
548 struct sdhci_host *host = mmc_priv(mmc);
549 u32 reg;
550
551 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
552 while (reg & SDHCI_DATA_AVAILABLE) {
553 sdhci_readl(host, SDHCI_BUFFER);
554 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
555 }
556
557 sdhci_cqe_enable(mmc);
558}
559
560static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
561 .enable = sdhci_arasan_cqe_enable,
562 .disable = sdhci_cqe_disable,
563 .dumpregs = sdhci_arasan_dumpregs,
564};
565
566static const struct sdhci_ops sdhci_arasan_cqe_ops = {
567 .set_clock = sdhci_arasan_set_clock,
568 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
569 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
570 .set_bus_width = sdhci_set_bus_width,
571 .reset = sdhci_arasan_reset,
572 .set_uhs_signaling = sdhci_set_uhs_signaling,
573 .set_power = sdhci_set_power_and_bus_voltage,
574 .irq = sdhci_arasan_cqhci_irq,
575};
576
577static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
578 .ops = &sdhci_arasan_cqe_ops,
579 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
580 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
581 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
582};
583
584#ifdef CONFIG_PM_SLEEP
585/**
586 * sdhci_arasan_suspend - Suspend method for the driver
587 * @dev: Address of the device structure
588 *
589 * Put the device in a low power state.
590 *
591 * Return: 0 on success and error value on error
592 */
593static int sdhci_arasan_suspend(struct device *dev)
594{
595 struct sdhci_host *host = dev_get_drvdata(dev);
596 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
597 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
598 int ret;
599
600 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
601 mmc_retune_needed(host->mmc);
602
603 if (sdhci_arasan->has_cqe) {
604 ret = cqhci_suspend(host->mmc);
605 if (ret)
606 return ret;
607 }
608
609 ret = sdhci_suspend_host(host);
610 if (ret)
611 return ret;
612
613 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
614 ret = phy_power_off(sdhci_arasan->phy);
615 if (ret) {
616 dev_err(dev, "Cannot power off phy.\n");
617 if (sdhci_resume_host(host))
618 dev_err(dev, "Cannot resume host.\n");
619
620 return ret;
621 }
622 sdhci_arasan->is_phy_on = false;
623 }
624
625 clk_disable(pltfm_host->clk);
626 clk_disable(sdhci_arasan->clk_ahb);
627
628 return 0;
629}
630
631/**
632 * sdhci_arasan_resume - Resume method for the driver
633 * @dev: Address of the device structure
634 *
635 * Resume operation after suspend
636 *
637 * Return: 0 on success and error value on error
638 */
639static int sdhci_arasan_resume(struct device *dev)
640{
641 struct sdhci_host *host = dev_get_drvdata(dev);
642 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
643 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
644 int ret;
645
646 ret = clk_enable(sdhci_arasan->clk_ahb);
647 if (ret) {
648 dev_err(dev, "Cannot enable AHB clock.\n");
649 return ret;
650 }
651
652 ret = clk_enable(pltfm_host->clk);
653 if (ret) {
654 dev_err(dev, "Cannot enable SD clock.\n");
655 return ret;
656 }
657
658 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
659 ret = phy_power_on(sdhci_arasan->phy);
660 if (ret) {
661 dev_err(dev, "Cannot power on phy.\n");
662 return ret;
663 }
664 sdhci_arasan->is_phy_on = true;
665 }
666
667 ret = sdhci_resume_host(host);
668 if (ret) {
669 dev_err(dev, "Cannot resume host.\n");
670 return ret;
671 }
672
673 if (sdhci_arasan->has_cqe)
674 return cqhci_resume(host->mmc);
675
676 return 0;
677}
678#endif /* ! CONFIG_PM_SLEEP */
679
680static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
681 sdhci_arasan_resume);
682
683/**
684 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
685 *
686 * @hw: Pointer to the hardware clock structure.
687 * @parent_rate: The parent rate (should be rate of clk_xin).
688 *
689 * Return the current actual rate of the SD card clock. This can be used
690 * to communicate with out PHY.
691 *
692 * Return: The card clock rate.
693 */
694static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
695 unsigned long parent_rate)
696{
697 struct sdhci_arasan_clk_data *clk_data =
698 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
699 struct sdhci_arasan_data *sdhci_arasan =
700 container_of(clk_data, struct sdhci_arasan_data, clk_data);
701 struct sdhci_host *host = sdhci_arasan->host;
702
703 return host->mmc->actual_clock;
704}
705
706static const struct clk_ops arasan_sdcardclk_ops = {
707 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
708};
709
710/**
711 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
712 *
713 * @hw: Pointer to the hardware clock structure.
714 * @parent_rate: The parent rate (should be rate of clk_xin).
715 *
716 * Return the current actual rate of the sampling clock. This can be used
717 * to communicate with out PHY.
718 *
719 * Return: The sample clock rate.
720 */
721static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
722 unsigned long parent_rate)
723{
724 struct sdhci_arasan_clk_data *clk_data =
725 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
726 struct sdhci_arasan_data *sdhci_arasan =
727 container_of(clk_data, struct sdhci_arasan_data, clk_data);
728 struct sdhci_host *host = sdhci_arasan->host;
729
730 return host->mmc->actual_clock;
731}
732
733static const struct clk_ops arasan_sampleclk_ops = {
734 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
735};
736
737/**
738 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
739 *
740 * @hw: Pointer to the hardware clock structure.
741 * @degrees: The clock phase shift between 0 - 359.
742 *
743 * Set the SD Output Clock Tap Delays for Output path
744 *
745 * Return: 0 on success and error value on error
746 */
747static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
748{
749 struct sdhci_arasan_clk_data *clk_data =
750 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
751 struct sdhci_arasan_data *sdhci_arasan =
752 container_of(clk_data, struct sdhci_arasan_data, clk_data);
753 struct sdhci_host *host = sdhci_arasan->host;
754 const char *clk_name = clk_hw_get_name(hw);
755 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
756 u8 tap_delay, tap_max = 0;
757 int ret;
758
759 /* This is applicable for SDHCI_SPEC_300 and above */
760 if (host->version < SDHCI_SPEC_300)
761 return 0;
762
763 switch (host->timing) {
764 case MMC_TIMING_MMC_HS:
765 case MMC_TIMING_SD_HS:
766 case MMC_TIMING_UHS_SDR25:
767 case MMC_TIMING_UHS_DDR50:
768 case MMC_TIMING_MMC_DDR52:
769 /* For 50MHz clock, 30 Taps are available */
770 tap_max = 30;
771 break;
772 case MMC_TIMING_UHS_SDR50:
773 /* For 100MHz clock, 15 Taps are available */
774 tap_max = 15;
775 break;
776 case MMC_TIMING_UHS_SDR104:
777 case MMC_TIMING_MMC_HS200:
778 /* For 200MHz clock, 8 Taps are available */
779 tap_max = 8;
780 break;
781 default:
782 break;
783 }
784
785 tap_delay = (degrees * tap_max) / 360;
786
787 /* Set the Clock Phase */
788 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
789 if (ret)
790 pr_err("Error setting Output Tap Delay\n");
791
792 /* Release DLL Reset */
793 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
794
795 return ret;
796}
797
798static const struct clk_ops zynqmp_sdcardclk_ops = {
799 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
800 .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
801};
802
803/**
804 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
805 *
806 * @hw: Pointer to the hardware clock structure.
807 * @degrees: The clock phase shift between 0 - 359.
808 *
809 * Set the SD Input Clock Tap Delays for Input path
810 *
811 * Return: 0 on success and error value on error
812 */
813static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
814{
815 struct sdhci_arasan_clk_data *clk_data =
816 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
817 struct sdhci_arasan_data *sdhci_arasan =
818 container_of(clk_data, struct sdhci_arasan_data, clk_data);
819 struct sdhci_host *host = sdhci_arasan->host;
820 const char *clk_name = clk_hw_get_name(hw);
821 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
822 u8 tap_delay, tap_max = 0;
823 int ret;
824
825 /* This is applicable for SDHCI_SPEC_300 and above */
826 if (host->version < SDHCI_SPEC_300)
827 return 0;
828
829 /* Assert DLL Reset */
830 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
831
832 switch (host->timing) {
833 case MMC_TIMING_MMC_HS:
834 case MMC_TIMING_SD_HS:
835 case MMC_TIMING_UHS_SDR25:
836 case MMC_TIMING_UHS_DDR50:
837 case MMC_TIMING_MMC_DDR52:
838 /* For 50MHz clock, 120 Taps are available */
839 tap_max = 120;
840 break;
841 case MMC_TIMING_UHS_SDR50:
842 /* For 100MHz clock, 60 Taps are available */
843 tap_max = 60;
844 break;
845 case MMC_TIMING_UHS_SDR104:
846 case MMC_TIMING_MMC_HS200:
847 /* For 200MHz clock, 30 Taps are available */
848 tap_max = 30;
849 break;
850 default:
851 break;
852 }
853
854 tap_delay = (degrees * tap_max) / 360;
855
856 /* Set the Clock Phase */
857 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
858 if (ret)
859 pr_err("Error setting Input Tap Delay\n");
860
861 return ret;
862}
863
864static const struct clk_ops zynqmp_sampleclk_ops = {
865 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
866 .set_phase = sdhci_zynqmp_sampleclk_set_phase,
867};
868
869/**
870 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
871 *
872 * @hw: Pointer to the hardware clock structure.
873 * @degrees: The clock phase shift between 0 - 359.
874 *
875 * Set the SD Output Clock Tap Delays for Output path
876 *
877 * Return: 0 on success and error value on error
878 */
879static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
880{
881 struct sdhci_arasan_clk_data *clk_data =
882 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
883 struct sdhci_arasan_data *sdhci_arasan =
884 container_of(clk_data, struct sdhci_arasan_data, clk_data);
885 struct sdhci_host *host = sdhci_arasan->host;
886 u8 tap_delay, tap_max = 0;
887
888 /* This is applicable for SDHCI_SPEC_300 and above */
889 if (host->version < SDHCI_SPEC_300)
890 return 0;
891
892 switch (host->timing) {
893 case MMC_TIMING_MMC_HS:
894 case MMC_TIMING_SD_HS:
895 case MMC_TIMING_UHS_SDR25:
896 case MMC_TIMING_UHS_DDR50:
897 case MMC_TIMING_MMC_DDR52:
898 /* For 50MHz clock, 30 Taps are available */
899 tap_max = 30;
900 break;
901 case MMC_TIMING_UHS_SDR50:
902 /* For 100MHz clock, 15 Taps are available */
903 tap_max = 15;
904 break;
905 case MMC_TIMING_UHS_SDR104:
906 case MMC_TIMING_MMC_HS200:
907 /* For 200MHz clock, 8 Taps are available */
908 tap_max = 8;
909 break;
910 default:
911 break;
912 }
913
914 tap_delay = (degrees * tap_max) / 360;
915
916 /* Set the Clock Phase */
917 if (tap_delay) {
918 u32 regval;
919
920 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
921 regval |= SDHCI_OTAPDLY_ENABLE;
922 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
923 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
924 regval |= tap_delay;
925 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
926 }
927
928 return 0;
929}
930
931static const struct clk_ops versal_sdcardclk_ops = {
932 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
933 .set_phase = sdhci_versal_sdcardclk_set_phase,
934};
935
936/**
937 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
938 *
939 * @hw: Pointer to the hardware clock structure.
940 * @degrees: The clock phase shift between 0 - 359.
941 *
942 * Set the SD Input Clock Tap Delays for Input path
943 *
944 * Return: 0 on success and error value on error
945 */
946static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
947{
948 struct sdhci_arasan_clk_data *clk_data =
949 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
950 struct sdhci_arasan_data *sdhci_arasan =
951 container_of(clk_data, struct sdhci_arasan_data, clk_data);
952 struct sdhci_host *host = sdhci_arasan->host;
953 u8 tap_delay, tap_max = 0;
954
955 /* This is applicable for SDHCI_SPEC_300 and above */
956 if (host->version < SDHCI_SPEC_300)
957 return 0;
958
959 switch (host->timing) {
960 case MMC_TIMING_MMC_HS:
961 case MMC_TIMING_SD_HS:
962 case MMC_TIMING_UHS_SDR25:
963 case MMC_TIMING_UHS_DDR50:
964 case MMC_TIMING_MMC_DDR52:
965 /* For 50MHz clock, 120 Taps are available */
966 tap_max = 120;
967 break;
968 case MMC_TIMING_UHS_SDR50:
969 /* For 100MHz clock, 60 Taps are available */
970 tap_max = 60;
971 break;
972 case MMC_TIMING_UHS_SDR104:
973 case MMC_TIMING_MMC_HS200:
974 /* For 200MHz clock, 30 Taps are available */
975 tap_max = 30;
976 break;
977 default:
978 break;
979 }
980
981 tap_delay = (degrees * tap_max) / 360;
982
983 /* Set the Clock Phase */
984 if (tap_delay) {
985 u32 regval;
986
987 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
988 regval |= SDHCI_ITAPDLY_CHGWIN;
989 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
990 regval |= SDHCI_ITAPDLY_ENABLE;
991 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
992 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
993 regval |= tap_delay;
994 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
995 regval &= ~SDHCI_ITAPDLY_CHGWIN;
996 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
997 }
998
999 return 0;
1000}
1001
1002static const struct clk_ops versal_sampleclk_ops = {
1003 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
1004 .set_phase = sdhci_versal_sampleclk_set_phase,
1005};
1006
1007static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
1008{
1009 struct sdhci_arasan_clk_data *clk_data =
1010 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
1011 struct sdhci_arasan_data *sdhci_arasan =
1012 container_of(clk_data, struct sdhci_arasan_data, clk_data);
1013 struct sdhci_host *host = sdhci_arasan->host;
1014 u8 tap_delay, tap_max = 0;
1015
1016 switch (host->timing) {
1017 case MMC_TIMING_MMC_HS:
1018 case MMC_TIMING_MMC_DDR52:
1019 tap_max = 16;
1020 break;
1021 case MMC_TIMING_MMC_HS200:
1022 case MMC_TIMING_MMC_HS400:
1023 /* For 200MHz clock, 32 Taps are available */
1024 tap_max = 32;
1025 break;
1026 default:
1027 break;
1028 }
1029
1030 tap_delay = (degrees * tap_max) / 360;
1031
1032 /* Set the Clock Phase */
1033 if (tap_delay) {
1034 u32 regval;
1035
1036 regval = sdhci_readl(host, PHY_CTRL_REG1);
1037 regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
1038 sdhci_writel(host, regval, PHY_CTRL_REG1);
1039 regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
1040 regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
1041 sdhci_writel(host, regval, PHY_CTRL_REG1);
1042 }
1043
1044 return 0;
1045}
1046
1047static const struct clk_ops versal_net_sdcardclk_ops = {
1048 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
1049 .set_phase = sdhci_versal_net_emmc_sdcardclk_set_phase,
1050};
1051
1052static int sdhci_versal_net_emmc_sampleclk_set_phase(struct clk_hw *hw, int degrees)
1053{
1054 struct sdhci_arasan_clk_data *clk_data =
1055 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
1056 struct sdhci_arasan_data *sdhci_arasan =
1057 container_of(clk_data, struct sdhci_arasan_data, clk_data);
1058 struct sdhci_host *host = sdhci_arasan->host;
1059 u8 tap_delay, tap_max = 0;
1060 u32 regval;
1061
1062 switch (host->timing) {
1063 case MMC_TIMING_MMC_HS:
1064 case MMC_TIMING_MMC_DDR52:
1065 tap_max = 32;
1066 break;
1067 case MMC_TIMING_MMC_HS400:
1068 /* Strobe select tap point for strb90 and strb180 */
1069 regval = sdhci_readl(host, PHY_CTRL_REG1);
1070 regval &= ~PHY_CTRL_STRB_SEL_MASK;
1071 regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
1072 sdhci_writel(host, regval, PHY_CTRL_REG1);
1073 break;
1074 default:
1075 break;
1076 }
1077
1078 tap_delay = (degrees * tap_max) / 360;
1079
1080 /* Set the Clock Phase */
1081 if (tap_delay) {
1082 regval = sdhci_readl(host, PHY_CTRL_REG1);
1083 regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
1084 sdhci_writel(host, regval, PHY_CTRL_REG1);
1085 regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
1086 sdhci_writel(host, regval, PHY_CTRL_REG1);
1087 regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
1088 regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
1089 sdhci_writel(host, regval, PHY_CTRL_REG1);
1090 regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
1091 sdhci_writel(host, regval, PHY_CTRL_REG1);
1092 }
1093
1094 return 0;
1095}
1096
1097static const struct clk_ops versal_net_sampleclk_ops = {
1098 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
1099 .set_phase = sdhci_versal_net_emmc_sampleclk_set_phase,
1100};
1101
1102static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
1103{
1104 u16 clk;
1105
1106 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1107 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
1108 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1109
1110 /* Issue DLL Reset */
1111 zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
1112
1113 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1114
1115 sdhci_enable_clk(host, clk);
1116}
1117
1118static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
1119{
1120 struct sdhci_host *host = mmc_priv(mmc);
1121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1122 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1123 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
1124 const char *clk_name = clk_hw_get_name(hw);
1125 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
1126 NODE_SD_1;
1127 int err;
1128
1129 /* ZynqMP SD controller does not perform auto tuning in DDR50 mode */
1130 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1131 return 0;
1132
1133 arasan_zynqmp_dll_reset(host, device_id);
1134
1135 err = sdhci_execute_tuning(mmc, opcode);
1136 if (err)
1137 return err;
1138
1139 arasan_zynqmp_dll_reset(host, device_id);
1140
1141 return 0;
1142}
1143
1144/**
1145 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
1146 *
1147 * @host: The sdhci_host
1148 * @value: The value to write
1149 *
1150 * The corecfg_clockmultiplier is supposed to contain clock multiplier
1151 * value of programmable clock generator.
1152 *
1153 * NOTES:
1154 * - Many existing devices don't seem to do this and work fine. To keep
1155 * compatibility for old hardware where the device tree doesn't provide a
1156 * register map, this function is a noop if a soc_ctl_map hasn't been provided
1157 * for this platform.
1158 * - The value of corecfg_clockmultiplier should sync with that of corresponding
1159 * value reading from sdhci_capability_register. So this function is called
1160 * once at probe time and never called again.
1161 */
1162static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
1163 u32 value)
1164{
1165 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1166 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1167 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1168 sdhci_arasan->soc_ctl_map;
1169
1170 /* Having a map is optional */
1171 if (!soc_ctl_map)
1172 return;
1173
1174 /* If we have a map, we expect to have a syscon */
1175 if (!sdhci_arasan->soc_ctl_base) {
1176 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1177 mmc_hostname(host->mmc));
1178 return;
1179 }
1180
1181 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
1182}
1183
1184/**
1185 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
1186 *
1187 * @host: The sdhci_host
1188 *
1189 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
1190 * function can be used to make that happen.
1191 *
1192 * NOTES:
1193 * - Many existing devices don't seem to do this and work fine. To keep
1194 * compatibility for old hardware where the device tree doesn't provide a
1195 * register map, this function is a noop if a soc_ctl_map hasn't been provided
1196 * for this platform.
1197 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1198 * to achieve lower clock rates. That means that this function is called once
1199 * at probe time and never called again.
1200 */
1201static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
1202{
1203 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1204 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1205 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
1206 sdhci_arasan->soc_ctl_map;
1207 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1208
1209 /* Having a map is optional */
1210 if (!soc_ctl_map)
1211 return;
1212
1213 /* If we have a map, we expect to have a syscon */
1214 if (!sdhci_arasan->soc_ctl_base) {
1215 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1216 mmc_hostname(host->mmc));
1217 return;
1218 }
1219
1220 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
1221}
1222
1223static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
1224{
1225 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1226 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1227 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1228
1229 clk_set_phase(clk_data->sampleclk,
1230 clk_data->clk_phase_in[host->timing]);
1231 clk_set_phase(clk_data->sdcardclk,
1232 clk_data->clk_phase_out[host->timing]);
1233}
1234
1235static void arasan_dt_read_clk_phase(struct device *dev,
1236 struct sdhci_arasan_clk_data *clk_data,
1237 unsigned int timing, const char *prop)
1238{
1239 struct device_node *np = dev->of_node;
1240
1241 u32 clk_phase[2] = {0};
1242 int ret;
1243
1244 /*
1245 * Read Tap Delay values from DT, if the DT does not contain the
1246 * Tap Values then use the pre-defined values.
1247 */
1248 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1249 2, 0);
1250 if (ret < 0) {
1251 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1252 prop, clk_data->clk_phase_in[timing],
1253 clk_data->clk_phase_out[timing]);
1254 return;
1255 }
1256
1257 /* The values read are Input and Output Clock Delays in order */
1258 clk_data->clk_phase_in[timing] = clk_phase[0];
1259 clk_data->clk_phase_out[timing] = clk_phase[1];
1260}
1261
1262/**
1263 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1264 *
1265 * @dev: Pointer to our struct device.
1266 * @clk_data: Pointer to the Clock Data structure
1267 *
1268 * Called at initialization to parse the values of Clock Delays.
1269 */
1270static void arasan_dt_parse_clk_phases(struct device *dev,
1271 struct sdhci_arasan_clk_data *clk_data)
1272{
1273 u32 mio_bank = 0;
1274 int i;
1275
1276 /*
1277 * This has been kept as a pointer and is assigned a function here.
1278 * So that different controller variants can assign their own handling
1279 * function.
1280 */
1281 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1282
1283 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1284 u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1285 ZYNQMP_ICLK_PHASE;
1286 u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1287 ZYNQMP_OCLK_PHASE;
1288
1289 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1290 if (mio_bank == 2) {
1291 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1292 zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1293 }
1294
1295 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1296 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1297 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1298 }
1299 }
1300
1301 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1302 u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1303 VERSAL_ICLK_PHASE;
1304 u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1305 VERSAL_OCLK_PHASE;
1306
1307 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1308 clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1309 clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1310 }
1311 }
1312 if (of_device_is_compatible(dev->of_node, "xlnx,versal-net-emmc")) {
1313 u32 versal_net_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1314 VERSAL_NET_EMMC_ICLK_PHASE;
1315 u32 versal_net_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1316 VERSAL_NET_EMMC_OCLK_PHASE;
1317
1318 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1319 clk_data->clk_phase_in[i] = versal_net_iclk_phase[i];
1320 clk_data->clk_phase_out[i] = versal_net_oclk_phase[i];
1321 }
1322 }
1323 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1324 "clk-phase-legacy");
1325 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1326 "clk-phase-mmc-hs");
1327 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1328 "clk-phase-sd-hs");
1329 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1330 "clk-phase-uhs-sdr12");
1331 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1332 "clk-phase-uhs-sdr25");
1333 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1334 "clk-phase-uhs-sdr50");
1335 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1336 "clk-phase-uhs-sdr104");
1337 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1338 "clk-phase-uhs-ddr50");
1339 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1340 "clk-phase-mmc-ddr52");
1341 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1342 "clk-phase-mmc-hs200");
1343 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1344 "clk-phase-mmc-hs400");
1345}
1346
1347static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1348 .ops = &sdhci_arasan_ops,
1349 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1350 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1351 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1352 SDHCI_QUIRK2_STOP_WITH_TC,
1353};
1354
1355static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1356 .sdcardclk_ops = &arasan_sdcardclk_ops,
1357 .sampleclk_ops = &arasan_sampleclk_ops,
1358};
1359
1360static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1361 .pdata = &sdhci_arasan_pdata,
1362 .clk_ops = &arasan_clk_ops,
1363};
1364
1365static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1366 .ops = &sdhci_arasan_cqe_ops,
1367 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1368 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1369 SDHCI_QUIRK_NO_LED |
1370 SDHCI_QUIRK_32BIT_DMA_ADDR |
1371 SDHCI_QUIRK_32BIT_DMA_SIZE |
1372 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1373 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1374 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1375 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1376 SDHCI_QUIRK2_STOP_WITH_TC |
1377 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1378};
1379
1380static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1381 .ops = &sdhci_arasan_ops,
1382 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1383 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1384 SDHCI_QUIRK_NO_LED |
1385 SDHCI_QUIRK_32BIT_DMA_ADDR |
1386 SDHCI_QUIRK_32BIT_DMA_SIZE |
1387 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1388 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1389 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1390 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1391 SDHCI_QUIRK2_STOP_WITH_TC |
1392 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1393};
1394
1395static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1396 .ops = &sdhci_arasan_ops,
1397 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1398 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1399 SDHCI_QUIRK_NO_LED |
1400 SDHCI_QUIRK_32BIT_DMA_ADDR |
1401 SDHCI_QUIRK_32BIT_DMA_SIZE |
1402 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1403 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1404 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1405 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1406 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1407};
1408
1409static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1410 .soc_ctl_map = &rk3399_soc_ctl_map,
1411 .pdata = &sdhci_arasan_cqe_pdata,
1412 .clk_ops = &arasan_clk_ops,
1413};
1414
1415static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1416 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1417 .pdata = &sdhci_arasan_cqe_pdata,
1418 .clk_ops = &arasan_clk_ops,
1419};
1420
1421static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1422 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1423 .pdata = &sdhci_arasan_cqe_pdata,
1424 .clk_ops = &arasan_clk_ops,
1425};
1426
1427static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1428 .ops = &sdhci_arasan_ops,
1429 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1430 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1431 SDHCI_QUIRK2_STOP_WITH_TC,
1432};
1433
1434static const struct sdhci_pltfm_data sdhci_arasan_versal_net_pdata = {
1435 .ops = &sdhci_arasan_ops,
1436 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1437 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1438 SDHCI_QUIRK2_STOP_WITH_TC |
1439 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
1440};
1441
1442static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1443 .sdcardclk_ops = &zynqmp_sdcardclk_ops,
1444 .sampleclk_ops = &zynqmp_sampleclk_ops,
1445};
1446
1447static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1448 .pdata = &sdhci_arasan_zynqmp_pdata,
1449 .clk_ops = &zynqmp_clk_ops,
1450};
1451
1452static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1453 .sdcardclk_ops = &versal_sdcardclk_ops,
1454 .sampleclk_ops = &versal_sampleclk_ops,
1455};
1456
1457static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1458 .pdata = &sdhci_arasan_zynqmp_pdata,
1459 .clk_ops = &versal_clk_ops,
1460};
1461
1462static const struct sdhci_arasan_clk_ops versal_net_clk_ops = {
1463 .sdcardclk_ops = &versal_net_sdcardclk_ops,
1464 .sampleclk_ops = &versal_net_sampleclk_ops,
1465};
1466
1467static struct sdhci_arasan_of_data sdhci_arasan_versal_net_data = {
1468 .pdata = &sdhci_arasan_versal_net_pdata,
1469 .clk_ops = &versal_net_clk_ops,
1470};
1471
1472static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1473 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1474 .pdata = &sdhci_keembay_emmc_pdata,
1475 .clk_ops = &arasan_clk_ops,
1476};
1477
1478static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1479 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1480 .pdata = &sdhci_keembay_sd_pdata,
1481 .clk_ops = &arasan_clk_ops,
1482};
1483
1484static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1485 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1486 .pdata = &sdhci_keembay_sdio_pdata,
1487 .clk_ops = &arasan_clk_ops,
1488};
1489
1490static const struct of_device_id sdhci_arasan_of_match[] = {
1491 /* SoC-specific compatible strings w/ soc_ctl_map */
1492 {
1493 .compatible = "rockchip,rk3399-sdhci-5.1",
1494 .data = &sdhci_arasan_rk3399_data,
1495 },
1496 {
1497 .compatible = "intel,lgm-sdhci-5.1-emmc",
1498 .data = &intel_lgm_emmc_data,
1499 },
1500 {
1501 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1502 .data = &intel_lgm_sdxc_data,
1503 },
1504 {
1505 .compatible = "intel,keembay-sdhci-5.1-emmc",
1506 .data = &intel_keembay_emmc_data,
1507 },
1508 {
1509 .compatible = "intel,keembay-sdhci-5.1-sd",
1510 .data = &intel_keembay_sd_data,
1511 },
1512 {
1513 .compatible = "intel,keembay-sdhci-5.1-sdio",
1514 .data = &intel_keembay_sdio_data,
1515 },
1516 /* Generic compatible below here */
1517 {
1518 .compatible = "arasan,sdhci-8.9a",
1519 .data = &sdhci_arasan_generic_data,
1520 },
1521 {
1522 .compatible = "arasan,sdhci-5.1",
1523 .data = &sdhci_arasan_generic_data,
1524 },
1525 {
1526 .compatible = "arasan,sdhci-4.9a",
1527 .data = &sdhci_arasan_generic_data,
1528 },
1529 {
1530 .compatible = "xlnx,zynqmp-8.9a",
1531 .data = &sdhci_arasan_zynqmp_data,
1532 },
1533 {
1534 .compatible = "xlnx,versal-8.9a",
1535 .data = &sdhci_arasan_versal_data,
1536 },
1537 {
1538 .compatible = "xlnx,versal-net-emmc",
1539 .data = &sdhci_arasan_versal_net_data,
1540 },
1541 { /* sentinel */ }
1542};
1543MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1544
1545/**
1546 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1547 *
1548 * @sdhci_arasan: Our private data structure.
1549 * @clk_xin: Pointer to the functional clock
1550 * @dev: Pointer to our struct device.
1551 *
1552 * Some PHY devices need to know what the actual card clock is. In order for
1553 * them to find out, we'll provide a clock through the common clock framework
1554 * for them to query.
1555 *
1556 * Return: 0 on success and error value on error
1557 */
1558static int
1559sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1560 struct clk *clk_xin,
1561 struct device *dev)
1562{
1563 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1564 struct device_node *np = dev->of_node;
1565 struct clk_init_data sdcardclk_init;
1566 const char *parent_clk_name;
1567 int ret;
1568
1569 ret = of_property_read_string_index(np, "clock-output-names", 0,
1570 &sdcardclk_init.name);
1571 if (ret) {
1572 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1573 return ret;
1574 }
1575
1576 parent_clk_name = __clk_get_name(clk_xin);
1577 sdcardclk_init.parent_names = &parent_clk_name;
1578 sdcardclk_init.num_parents = 1;
1579 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1580 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1581
1582 clk_data->sdcardclk_hw.init = &sdcardclk_init;
1583 clk_data->sdcardclk =
1584 devm_clk_register(dev, &clk_data->sdcardclk_hw);
1585 if (IS_ERR(clk_data->sdcardclk))
1586 return PTR_ERR(clk_data->sdcardclk);
1587 clk_data->sdcardclk_hw.init = NULL;
1588
1589 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1590 clk_data->sdcardclk);
1591 if (ret)
1592 dev_err(dev, "Failed to add sdcard clock provider\n");
1593
1594 return ret;
1595}
1596
1597/**
1598 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1599 *
1600 * @sdhci_arasan: Our private data structure.
1601 * @clk_xin: Pointer to the functional clock
1602 * @dev: Pointer to our struct device.
1603 *
1604 * Some PHY devices need to know what the actual card clock is. In order for
1605 * them to find out, we'll provide a clock through the common clock framework
1606 * for them to query.
1607 *
1608 * Return: 0 on success and error value on error
1609 */
1610static int
1611sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1612 struct clk *clk_xin,
1613 struct device *dev)
1614{
1615 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1616 struct device_node *np = dev->of_node;
1617 struct clk_init_data sampleclk_init;
1618 const char *parent_clk_name;
1619 int ret;
1620
1621 ret = of_property_read_string_index(np, "clock-output-names", 1,
1622 &sampleclk_init.name);
1623 if (ret) {
1624 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1625 return ret;
1626 }
1627
1628 parent_clk_name = __clk_get_name(clk_xin);
1629 sampleclk_init.parent_names = &parent_clk_name;
1630 sampleclk_init.num_parents = 1;
1631 sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1632 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1633
1634 clk_data->sampleclk_hw.init = &sampleclk_init;
1635 clk_data->sampleclk =
1636 devm_clk_register(dev, &clk_data->sampleclk_hw);
1637 if (IS_ERR(clk_data->sampleclk))
1638 return PTR_ERR(clk_data->sampleclk);
1639 clk_data->sampleclk_hw.init = NULL;
1640
1641 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1642 clk_data->sampleclk);
1643 if (ret)
1644 dev_err(dev, "Failed to add sample clock provider\n");
1645
1646 return ret;
1647}
1648
1649/**
1650 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1651 *
1652 * @dev: Pointer to our struct device.
1653 *
1654 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1655 * returned success.
1656 */
1657static void sdhci_arasan_unregister_sdclk(struct device *dev)
1658{
1659 struct device_node *np = dev->of_node;
1660
1661 if (!of_property_present(np, "#clock-cells"))
1662 return;
1663
1664 of_clk_del_provider(dev->of_node);
1665}
1666
1667/**
1668 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1669 * @host: The sdhci_host
1670 * @value: The value to write
1671 *
1672 * This should be set based on the System Address Bus.
1673 * 0: the Core supports only 32-bit System Address Bus.
1674 * 1: the Core supports 64-bit System Address Bus.
1675 *
1676 * NOTE:
1677 * For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1678 * Keem Bay does not support 64-bit access.
1679 */
1680static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1681{
1682 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1683 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1684 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
1685
1686 /* Having a map is optional */
1687 soc_ctl_map = sdhci_arasan->soc_ctl_map;
1688 if (!soc_ctl_map)
1689 return;
1690
1691 /* If we have a map, we expect to have a syscon */
1692 if (!sdhci_arasan->soc_ctl_base) {
1693 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1694 mmc_hostname(host->mmc));
1695 return;
1696 }
1697
1698 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1699}
1700
1701/**
1702 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1703 *
1704 * @sdhci_arasan: Our private data structure.
1705 * @clk_xin: Pointer to the functional clock
1706 * @dev: Pointer to our struct device.
1707 *
1708 * Some PHY devices need to know what the actual card clock is. In order for
1709 * them to find out, we'll provide a clock through the common clock framework
1710 * for them to query.
1711 *
1712 * Note: without seriously re-architecting SDHCI's clock code and testing on
1713 * all platforms, there's no way to create a totally beautiful clock here
1714 * with all clock ops implemented. Instead, we'll just create a clock that can
1715 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1716 * framework that we're doing things behind its back. This should be sufficient
1717 * to create nice clean device tree bindings and later (if needed) we can try
1718 * re-architecting SDHCI if we see some benefit to it.
1719 *
1720 * Return: 0 on success and error value on error
1721 */
1722static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1723 struct clk *clk_xin,
1724 struct device *dev)
1725{
1726 struct device_node *np = dev->of_node;
1727 u32 num_clks = 0;
1728 int ret;
1729
1730 /* Providing a clock to the PHY is optional; no error if missing */
1731 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1732 return 0;
1733
1734 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1735 if (ret)
1736 return ret;
1737
1738 if (num_clks) {
1739 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1740 dev);
1741 if (ret) {
1742 sdhci_arasan_unregister_sdclk(dev);
1743 return ret;
1744 }
1745 }
1746
1747 return 0;
1748}
1749
1750static int sdhci_zynqmp_set_dynamic_config(struct device *dev,
1751 struct sdhci_arasan_data *sdhci_arasan)
1752{
1753 struct sdhci_host *host = sdhci_arasan->host;
1754 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
1755 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1756 const char *clk_name = clk_hw_get_name(hw);
1757 u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
1758 struct reset_control *rstc;
1759 int ret;
1760
1761 /* Obtain SDHC reset control */
1762 rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
1763 if (IS_ERR(rstc)) {
1764 dev_err(dev, "Cannot get SDHC reset.\n");
1765 return PTR_ERR(rstc);
1766 }
1767
1768 ret = reset_control_assert(rstc);
1769 if (ret)
1770 return ret;
1771
1772 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0);
1773 if (ret)
1774 return ret;
1775
1776 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL,
1777 !!(host->mmc->caps & MMC_CAP_NONREMOVABLE));
1778 if (ret)
1779 return ret;
1780
1781 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1782 if (mhz > 100 && mhz <= 200)
1783 mhz = 200;
1784 else if (mhz > 50 && mhz <= 100)
1785 mhz = 100;
1786 else if (mhz > 25 && mhz <= 50)
1787 mhz = 50;
1788 else
1789 mhz = 25;
1790
1791 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
1792 if (ret)
1793 return ret;
1794
1795 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT,
1796 !!(host->mmc->caps & MMC_CAP_8_BIT_DATA));
1797 if (ret)
1798 return ret;
1799
1800 ret = reset_control_deassert(rstc);
1801 if (ret)
1802 return ret;
1803
1804 usleep_range(1000, 1500);
1805
1806 return 0;
1807}
1808
1809static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1810{
1811 struct sdhci_host *host = sdhci_arasan->host;
1812 struct cqhci_host *cq_host;
1813 bool dma64;
1814 int ret;
1815
1816 if (!sdhci_arasan->has_cqe)
1817 return sdhci_add_host(host);
1818
1819 ret = sdhci_setup_host(host);
1820 if (ret)
1821 return ret;
1822
1823 cq_host = devm_kzalloc(host->mmc->parent,
1824 sizeof(*cq_host), GFP_KERNEL);
1825 if (!cq_host) {
1826 ret = -ENOMEM;
1827 goto cleanup;
1828 }
1829
1830 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1831 cq_host->ops = &sdhci_arasan_cqhci_ops;
1832
1833 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1834 if (dma64)
1835 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1836
1837 ret = cqhci_init(cq_host, host->mmc, dma64);
1838 if (ret)
1839 goto cleanup;
1840
1841 ret = __sdhci_add_host(host);
1842 if (ret)
1843 goto cleanup;
1844
1845 return 0;
1846
1847cleanup:
1848 sdhci_cleanup_host(host);
1849 return ret;
1850}
1851
1852static int sdhci_arasan_probe(struct platform_device *pdev)
1853{
1854 int ret;
1855 struct device_node *node;
1856 struct clk *clk_xin;
1857 struct clk *clk_dll;
1858 struct sdhci_host *host;
1859 struct sdhci_pltfm_host *pltfm_host;
1860 struct device *dev = &pdev->dev;
1861 struct device_node *np = dev->of_node;
1862 struct sdhci_arasan_data *sdhci_arasan;
1863 const struct sdhci_arasan_of_data *data;
1864
1865 data = of_device_get_match_data(dev);
1866 if (!data)
1867 return -EINVAL;
1868
1869 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1870
1871 if (IS_ERR(host))
1872 return PTR_ERR(host);
1873
1874 pltfm_host = sdhci_priv(host);
1875 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1876 sdhci_arasan->host = host;
1877
1878 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1879 sdhci_arasan->clk_ops = data->clk_ops;
1880
1881 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);
1882 if (node) {
1883 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1884 of_node_put(node);
1885
1886 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1887 ret = dev_err_probe(dev,
1888 PTR_ERR(sdhci_arasan->soc_ctl_base),
1889 "Can't get syscon\n");
1890 goto err_pltfm_free;
1891 }
1892 }
1893
1894 sdhci_get_of_property(pdev);
1895
1896 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
1897 if (IS_ERR(sdhci_arasan->clk_ahb)) {
1898 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
1899 "clk_ahb clock not found.\n");
1900 goto err_pltfm_free;
1901 }
1902
1903 clk_xin = devm_clk_get(dev, "clk_xin");
1904 if (IS_ERR(clk_xin)) {
1905 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1906 goto err_pltfm_free;
1907 }
1908
1909 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1910 if (ret) {
1911 dev_err(dev, "Unable to enable AHB clock.\n");
1912 goto err_pltfm_free;
1913 }
1914
1915 /* If clock-frequency property is set, use the provided value */
1916 if (pltfm_host->clock &&
1917 pltfm_host->clock != clk_get_rate(clk_xin)) {
1918 ret = clk_set_rate(clk_xin, pltfm_host->clock);
1919 if (ret) {
1920 dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1921 goto clk_dis_ahb;
1922 }
1923 }
1924
1925 ret = clk_prepare_enable(clk_xin);
1926 if (ret) {
1927 dev_err(dev, "Unable to enable SD clock.\n");
1928 goto clk_dis_ahb;
1929 }
1930
1931 clk_dll = devm_clk_get_optional_enabled(dev, "gate");
1932 if (IS_ERR(clk_dll)) {
1933 ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n");
1934 goto clk_disable_all;
1935 }
1936
1937 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1938 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1939
1940 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1941 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1942
1943 pltfm_host->clk = clk_xin;
1944
1945 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1946 sdhci_arasan_update_clockmultiplier(host, 0x0);
1947
1948 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1949 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1950 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1951 sdhci_arasan_update_clockmultiplier(host, 0x0);
1952 sdhci_arasan_update_support64b(host, 0x0);
1953
1954 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1955 }
1956
1957 sdhci_arasan_update_baseclkfreq(host);
1958
1959 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
1960 if (ret)
1961 goto clk_disable_all;
1962
1963 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1964 host->mmc_host_ops.execute_tuning =
1965 arasan_zynqmp_execute_tuning;
1966
1967 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
1968 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
1969 }
1970
1971 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);
1972
1973 ret = mmc_of_parse(host->mmc);
1974 if (ret) {
1975 ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
1976 goto unreg_clk;
1977 }
1978
1979 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1980 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG);
1981 if (!ret) {
1982 ret = sdhci_zynqmp_set_dynamic_config(dev, sdhci_arasan);
1983 if (ret)
1984 goto unreg_clk;
1985 }
1986 }
1987
1988 sdhci_arasan->phy = ERR_PTR(-ENODEV);
1989 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {
1990 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");
1991 if (IS_ERR(sdhci_arasan->phy)) {
1992 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),
1993 "No phy for arasan,sdhci-5.1.\n");
1994 goto unreg_clk;
1995 }
1996
1997 ret = phy_init(sdhci_arasan->phy);
1998 if (ret < 0) {
1999 dev_err(dev, "phy_init err.\n");
2000 goto unreg_clk;
2001 }
2002
2003 host->mmc_host_ops.hs400_enhanced_strobe =
2004 sdhci_arasan_hs400_enhanced_strobe;
2005 host->mmc_host_ops.start_signal_voltage_switch =
2006 sdhci_arasan_voltage_switch;
2007 sdhci_arasan->has_cqe = true;
2008 host->mmc->caps2 |= MMC_CAP2_CQE;
2009
2010 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
2011 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
2012 }
2013
2014 if (of_device_is_compatible(np, "xlnx,versal-net-emmc"))
2015 sdhci_arasan->internal_phy_reg = true;
2016
2017 ret = sdhci_arasan_add_host(sdhci_arasan);
2018 if (ret)
2019 goto err_add_host;
2020
2021 return 0;
2022
2023err_add_host:
2024 if (!IS_ERR(sdhci_arasan->phy))
2025 phy_exit(sdhci_arasan->phy);
2026unreg_clk:
2027 sdhci_arasan_unregister_sdclk(dev);
2028clk_disable_all:
2029 clk_disable_unprepare(clk_xin);
2030clk_dis_ahb:
2031 clk_disable_unprepare(sdhci_arasan->clk_ahb);
2032err_pltfm_free:
2033 sdhci_pltfm_free(pdev);
2034 return ret;
2035}
2036
2037static void sdhci_arasan_remove(struct platform_device *pdev)
2038{
2039 struct sdhci_host *host = platform_get_drvdata(pdev);
2040 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2041 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
2042 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
2043 struct clk *clk_xin = pltfm_host->clk;
2044
2045 if (!IS_ERR(sdhci_arasan->phy)) {
2046 if (sdhci_arasan->is_phy_on)
2047 phy_power_off(sdhci_arasan->phy);
2048 phy_exit(sdhci_arasan->phy);
2049 }
2050
2051 sdhci_arasan_unregister_sdclk(&pdev->dev);
2052
2053 sdhci_pltfm_remove(pdev);
2054
2055 clk_disable_unprepare(clk_xin);
2056 clk_disable_unprepare(clk_ahb);
2057}
2058
2059static struct platform_driver sdhci_arasan_driver = {
2060 .driver = {
2061 .name = "sdhci-arasan",
2062 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2063 .of_match_table = sdhci_arasan_of_match,
2064 .pm = &sdhci_arasan_dev_pm_ops,
2065 },
2066 .probe = sdhci_arasan_probe,
2067 .remove = sdhci_arasan_remove,
2068};
2069
2070module_platform_driver(sdhci_arasan_driver);
2071
2072MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
2073MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
2074MODULE_LICENSE("GPL");