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1/*
2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
3 *
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
5 *
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
11
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
17 *
18
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24/* Why don't we use the SD controllers' carddetect feature?
25 *
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
33 */
34
35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/platform_device.h>
38#include <linux/mm.h>
39#include <linux/interrupt.h>
40#include <linux/dma-mapping.h>
41#include <linux/scatterlist.h>
42#include <linux/leds.h>
43#include <linux/mmc/host.h>
44#include <linux/slab.h>
45
46#include <asm/io.h>
47#include <asm/mach-au1x00/au1000.h>
48#include <asm/mach-au1x00/au1xxx_dbdma.h>
49#include <asm/mach-au1x00/au1100_mmc.h>
50
51#define DRIVER_NAME "au1xxx-mmc"
52
53/* Set this to enable special debugging macros */
54/* #define DEBUG */
55
56#ifdef DEBUG
57#define DBG(fmt, idx, args...) \
58 pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
59#else
60#define DBG(fmt, idx, args...) do {} while (0)
61#endif
62
63/* Hardware definitions */
64#define AU1XMMC_DESCRIPTOR_COUNT 1
65
66/* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
67#define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
68#define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
69
70#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
71 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
72 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
73
74/* This gives us a hard value for the stop command that we can write directly
75 * to the command register.
76 */
77#define STOP_CMD \
78 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
79
80/* This is the set of interrupts that we configure by default. */
81#define AU1XMMC_INTERRUPTS \
82 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
83 SD_CONFIG_CR | SD_CONFIG_I)
84
85/* The poll event (looking for insert/remove events runs twice a second. */
86#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
87
88struct au1xmmc_host {
89 struct mmc_host *mmc;
90 struct mmc_request *mrq;
91
92 u32 flags;
93 u32 iobase;
94 u32 clock;
95 u32 bus_width;
96 u32 power_mode;
97
98 int status;
99
100 struct {
101 int len;
102 int dir;
103 } dma;
104
105 struct {
106 int index;
107 int offset;
108 int len;
109 } pio;
110
111 u32 tx_chan;
112 u32 rx_chan;
113
114 int irq;
115
116 struct tasklet_struct finish_task;
117 struct tasklet_struct data_task;
118 struct au1xmmc_platform_data *platdata;
119 struct platform_device *pdev;
120 struct resource *ioarea;
121};
122
123/* Status flags used by the host structure */
124#define HOST_F_XMIT 0x0001
125#define HOST_F_RECV 0x0002
126#define HOST_F_DMA 0x0010
127#define HOST_F_DBDMA 0x0020
128#define HOST_F_ACTIVE 0x0100
129#define HOST_F_STOP 0x1000
130
131#define HOST_S_IDLE 0x0001
132#define HOST_S_CMD 0x0002
133#define HOST_S_DATA 0x0003
134#define HOST_S_STOP 0x0004
135
136/* Easy access macros */
137#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
138#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
139#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
140#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
141#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
142#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
143#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
144#define HOST_CMD(h) ((h)->iobase + SD_CMD)
145#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
146#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
147#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
148
149#define DMA_CHANNEL(h) \
150 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
151
152static inline int has_dbdma(void)
153{
154 switch (alchemy_get_cputype()) {
155 case ALCHEMY_CPU_AU1200:
156 case ALCHEMY_CPU_AU1300:
157 return 1;
158 default:
159 return 0;
160 }
161}
162
163static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
164{
165 u32 val = au_readl(HOST_CONFIG(host));
166 val |= mask;
167 au_writel(val, HOST_CONFIG(host));
168 au_sync();
169}
170
171static inline void FLUSH_FIFO(struct au1xmmc_host *host)
172{
173 u32 val = au_readl(HOST_CONFIG2(host));
174
175 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
176 au_sync_delay(1);
177
178 /* SEND_STOP will turn off clock control - this re-enables it */
179 val &= ~SD_CONFIG2_DF;
180
181 au_writel(val, HOST_CONFIG2(host));
182 au_sync();
183}
184
185static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
186{
187 u32 val = au_readl(HOST_CONFIG(host));
188 val &= ~mask;
189 au_writel(val, HOST_CONFIG(host));
190 au_sync();
191}
192
193static inline void SEND_STOP(struct au1xmmc_host *host)
194{
195 u32 config2;
196
197 WARN_ON(host->status != HOST_S_DATA);
198 host->status = HOST_S_STOP;
199
200 config2 = au_readl(HOST_CONFIG2(host));
201 au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
202 au_sync();
203
204 /* Send the stop command */
205 au_writel(STOP_CMD, HOST_CMD(host));
206}
207
208static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
209{
210 if (host->platdata && host->platdata->set_power)
211 host->platdata->set_power(host->mmc, state);
212}
213
214static int au1xmmc_card_inserted(struct mmc_host *mmc)
215{
216 struct au1xmmc_host *host = mmc_priv(mmc);
217
218 if (host->platdata && host->platdata->card_inserted)
219 return !!host->platdata->card_inserted(host->mmc);
220
221 return -ENOSYS;
222}
223
224static int au1xmmc_card_readonly(struct mmc_host *mmc)
225{
226 struct au1xmmc_host *host = mmc_priv(mmc);
227
228 if (host->platdata && host->platdata->card_readonly)
229 return !!host->platdata->card_readonly(mmc);
230
231 return -ENOSYS;
232}
233
234static void au1xmmc_finish_request(struct au1xmmc_host *host)
235{
236 struct mmc_request *mrq = host->mrq;
237
238 host->mrq = NULL;
239 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
240
241 host->dma.len = 0;
242 host->dma.dir = 0;
243
244 host->pio.index = 0;
245 host->pio.offset = 0;
246 host->pio.len = 0;
247
248 host->status = HOST_S_IDLE;
249
250 mmc_request_done(host->mmc, mrq);
251}
252
253static void au1xmmc_tasklet_finish(unsigned long param)
254{
255 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
256 au1xmmc_finish_request(host);
257}
258
259static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
260 struct mmc_command *cmd, struct mmc_data *data)
261{
262 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
263
264 switch (mmc_resp_type(cmd)) {
265 case MMC_RSP_NONE:
266 break;
267 case MMC_RSP_R1:
268 mmccmd |= SD_CMD_RT_1;
269 break;
270 case MMC_RSP_R1B:
271 mmccmd |= SD_CMD_RT_1B;
272 break;
273 case MMC_RSP_R2:
274 mmccmd |= SD_CMD_RT_2;
275 break;
276 case MMC_RSP_R3:
277 mmccmd |= SD_CMD_RT_3;
278 break;
279 default:
280 pr_info("au1xmmc: unhandled response type %02x\n",
281 mmc_resp_type(cmd));
282 return -EINVAL;
283 }
284
285 if (data) {
286 if (data->flags & MMC_DATA_READ) {
287 if (data->blocks > 1)
288 mmccmd |= SD_CMD_CT_4;
289 else
290 mmccmd |= SD_CMD_CT_2;
291 } else if (data->flags & MMC_DATA_WRITE) {
292 if (data->blocks > 1)
293 mmccmd |= SD_CMD_CT_3;
294 else
295 mmccmd |= SD_CMD_CT_1;
296 }
297 }
298
299 au_writel(cmd->arg, HOST_CMDARG(host));
300 au_sync();
301
302 if (wait)
303 IRQ_OFF(host, SD_CONFIG_CR);
304
305 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
306 au_sync();
307
308 /* Wait for the command to go on the line */
309 while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
310 /* nop */;
311
312 /* Wait for the command to come back */
313 if (wait) {
314 u32 status = au_readl(HOST_STATUS(host));
315
316 while (!(status & SD_STATUS_CR))
317 status = au_readl(HOST_STATUS(host));
318
319 /* Clear the CR status */
320 au_writel(SD_STATUS_CR, HOST_STATUS(host));
321
322 IRQ_ON(host, SD_CONFIG_CR);
323 }
324
325 return 0;
326}
327
328static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
329{
330 struct mmc_request *mrq = host->mrq;
331 struct mmc_data *data;
332 u32 crc;
333
334 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
335
336 if (host->mrq == NULL)
337 return;
338
339 data = mrq->cmd->data;
340
341 if (status == 0)
342 status = au_readl(HOST_STATUS(host));
343
344 /* The transaction is really over when the SD_STATUS_DB bit is clear */
345 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
346 status = au_readl(HOST_STATUS(host));
347
348 data->error = 0;
349 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
350
351 /* Process any errors */
352 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
353 if (host->flags & HOST_F_XMIT)
354 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
355
356 if (crc)
357 data->error = -EILSEQ;
358
359 /* Clear the CRC bits */
360 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
361
362 data->bytes_xfered = 0;
363
364 if (!data->error) {
365 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
366 u32 chan = DMA_CHANNEL(host);
367
368 chan_tab_t *c = *((chan_tab_t **)chan);
369 au1x_dma_chan_t *cp = c->chan_ptr;
370 data->bytes_xfered = cp->ddma_bytecnt;
371 } else
372 data->bytes_xfered =
373 (data->blocks * data->blksz) - host->pio.len;
374 }
375
376 au1xmmc_finish_request(host);
377}
378
379static void au1xmmc_tasklet_data(unsigned long param)
380{
381 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
382
383 u32 status = au_readl(HOST_STATUS(host));
384 au1xmmc_data_complete(host, status);
385}
386
387#define AU1XMMC_MAX_TRANSFER 8
388
389static void au1xmmc_send_pio(struct au1xmmc_host *host)
390{
391 struct mmc_data *data;
392 int sg_len, max, count;
393 unsigned char *sg_ptr, val;
394 u32 status;
395 struct scatterlist *sg;
396
397 data = host->mrq->data;
398
399 if (!(host->flags & HOST_F_XMIT))
400 return;
401
402 /* This is the pointer to the data buffer */
403 sg = &data->sg[host->pio.index];
404 sg_ptr = sg_virt(sg) + host->pio.offset;
405
406 /* This is the space left inside the buffer */
407 sg_len = data->sg[host->pio.index].length - host->pio.offset;
408
409 /* Check if we need less than the size of the sg_buffer */
410 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
411 if (max > AU1XMMC_MAX_TRANSFER)
412 max = AU1XMMC_MAX_TRANSFER;
413
414 for (count = 0; count < max; count++) {
415 status = au_readl(HOST_STATUS(host));
416
417 if (!(status & SD_STATUS_TH))
418 break;
419
420 val = *sg_ptr++;
421
422 au_writel((unsigned long)val, HOST_TXPORT(host));
423 au_sync();
424 }
425
426 host->pio.len -= count;
427 host->pio.offset += count;
428
429 if (count == sg_len) {
430 host->pio.index++;
431 host->pio.offset = 0;
432 }
433
434 if (host->pio.len == 0) {
435 IRQ_OFF(host, SD_CONFIG_TH);
436
437 if (host->flags & HOST_F_STOP)
438 SEND_STOP(host);
439
440 tasklet_schedule(&host->data_task);
441 }
442}
443
444static void au1xmmc_receive_pio(struct au1xmmc_host *host)
445{
446 struct mmc_data *data;
447 int max, count, sg_len = 0;
448 unsigned char *sg_ptr = NULL;
449 u32 status, val;
450 struct scatterlist *sg;
451
452 data = host->mrq->data;
453
454 if (!(host->flags & HOST_F_RECV))
455 return;
456
457 max = host->pio.len;
458
459 if (host->pio.index < host->dma.len) {
460 sg = &data->sg[host->pio.index];
461 sg_ptr = sg_virt(sg) + host->pio.offset;
462
463 /* This is the space left inside the buffer */
464 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
465
466 /* Check if we need less than the size of the sg_buffer */
467 if (sg_len < max)
468 max = sg_len;
469 }
470
471 if (max > AU1XMMC_MAX_TRANSFER)
472 max = AU1XMMC_MAX_TRANSFER;
473
474 for (count = 0; count < max; count++) {
475 status = au_readl(HOST_STATUS(host));
476
477 if (!(status & SD_STATUS_NE))
478 break;
479
480 if (status & SD_STATUS_RC) {
481 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
482 host->pio.len, count);
483 break;
484 }
485
486 if (status & SD_STATUS_RO) {
487 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
488 host->pio.len, count);
489 break;
490 }
491 else if (status & SD_STATUS_RU) {
492 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
493 host->pio.len, count);
494 break;
495 }
496
497 val = au_readl(HOST_RXPORT(host));
498
499 if (sg_ptr)
500 *sg_ptr++ = (unsigned char)(val & 0xFF);
501 }
502
503 host->pio.len -= count;
504 host->pio.offset += count;
505
506 if (sg_len && count == sg_len) {
507 host->pio.index++;
508 host->pio.offset = 0;
509 }
510
511 if (host->pio.len == 0) {
512 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
513 IRQ_OFF(host, SD_CONFIG_NE);
514
515 if (host->flags & HOST_F_STOP)
516 SEND_STOP(host);
517
518 tasklet_schedule(&host->data_task);
519 }
520}
521
522/* This is called when a command has been completed - grab the response
523 * and check for errors. Then start the data transfer if it is indicated.
524 */
525static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
526{
527 struct mmc_request *mrq = host->mrq;
528 struct mmc_command *cmd;
529 u32 r[4];
530 int i, trans;
531
532 if (!host->mrq)
533 return;
534
535 cmd = mrq->cmd;
536 cmd->error = 0;
537
538 if (cmd->flags & MMC_RSP_PRESENT) {
539 if (cmd->flags & MMC_RSP_136) {
540 r[0] = au_readl(host->iobase + SD_RESP3);
541 r[1] = au_readl(host->iobase + SD_RESP2);
542 r[2] = au_readl(host->iobase + SD_RESP1);
543 r[3] = au_readl(host->iobase + SD_RESP0);
544
545 /* The CRC is omitted from the response, so really
546 * we only got 120 bytes, but the engine expects
547 * 128 bits, so we have to shift things up.
548 */
549 for (i = 0; i < 4; i++) {
550 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
551 if (i != 3)
552 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
553 }
554 } else {
555 /* Techincally, we should be getting all 48 bits of
556 * the response (SD_RESP1 + SD_RESP2), but because
557 * our response omits the CRC, our data ends up
558 * being shifted 8 bits to the right. In this case,
559 * that means that the OSR data starts at bit 31,
560 * so we can just read RESP0 and return that.
561 */
562 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
563 }
564 }
565
566 /* Figure out errors */
567 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
568 cmd->error = -EILSEQ;
569
570 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
571
572 if (!trans || cmd->error) {
573 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
574 tasklet_schedule(&host->finish_task);
575 return;
576 }
577
578 host->status = HOST_S_DATA;
579
580 if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
581 u32 channel = DMA_CHANNEL(host);
582
583 /* Start the DBDMA as soon as the buffer gets something in it */
584
585 if (host->flags & HOST_F_RECV) {
586 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
587
588 while((status & mask) != mask)
589 status = au_readl(HOST_STATUS(host));
590 }
591
592 au1xxx_dbdma_start(channel);
593 }
594}
595
596static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
597{
598 unsigned int pbus = get_au1x00_speed();
599 unsigned int divisor;
600 u32 config;
601
602 /* From databook:
603 * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
604 */
605 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
606 pbus /= 2;
607 divisor = ((pbus / rate) / 2) - 1;
608
609 config = au_readl(HOST_CONFIG(host));
610
611 config &= ~(SD_CONFIG_DIV);
612 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
613
614 au_writel(config, HOST_CONFIG(host));
615 au_sync();
616}
617
618static int au1xmmc_prepare_data(struct au1xmmc_host *host,
619 struct mmc_data *data)
620{
621 int datalen = data->blocks * data->blksz;
622
623 if (data->flags & MMC_DATA_READ)
624 host->flags |= HOST_F_RECV;
625 else
626 host->flags |= HOST_F_XMIT;
627
628 if (host->mrq->stop)
629 host->flags |= HOST_F_STOP;
630
631 host->dma.dir = DMA_BIDIRECTIONAL;
632
633 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
634 data->sg_len, host->dma.dir);
635
636 if (host->dma.len == 0)
637 return -ETIMEDOUT;
638
639 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
640
641 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
642 int i;
643 u32 channel = DMA_CHANNEL(host);
644
645 au1xxx_dbdma_stop(channel);
646
647 for (i = 0; i < host->dma.len; i++) {
648 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
649 struct scatterlist *sg = &data->sg[i];
650 int sg_len = sg->length;
651
652 int len = (datalen > sg_len) ? sg_len : datalen;
653
654 if (i == host->dma.len - 1)
655 flags = DDMA_FLAGS_IE;
656
657 if (host->flags & HOST_F_XMIT) {
658 ret = au1xxx_dbdma_put_source(channel,
659 sg_phys(sg), len, flags);
660 } else {
661 ret = au1xxx_dbdma_put_dest(channel,
662 sg_phys(sg), len, flags);
663 }
664
665 if (!ret)
666 goto dataerr;
667
668 datalen -= len;
669 }
670 } else {
671 host->pio.index = 0;
672 host->pio.offset = 0;
673 host->pio.len = datalen;
674
675 if (host->flags & HOST_F_XMIT)
676 IRQ_ON(host, SD_CONFIG_TH);
677 else
678 IRQ_ON(host, SD_CONFIG_NE);
679 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
680 }
681
682 return 0;
683
684dataerr:
685 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
686 host->dma.dir);
687 return -ETIMEDOUT;
688}
689
690/* This actually starts a command or data transaction */
691static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
692{
693 struct au1xmmc_host *host = mmc_priv(mmc);
694 int ret = 0;
695
696 WARN_ON(irqs_disabled());
697 WARN_ON(host->status != HOST_S_IDLE);
698
699 host->mrq = mrq;
700 host->status = HOST_S_CMD;
701
702 /* fail request immediately if no card is present */
703 if (0 == au1xmmc_card_inserted(mmc)) {
704 mrq->cmd->error = -ENOMEDIUM;
705 au1xmmc_finish_request(host);
706 return;
707 }
708
709 if (mrq->data) {
710 FLUSH_FIFO(host);
711 ret = au1xmmc_prepare_data(host, mrq->data);
712 }
713
714 if (!ret)
715 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
716
717 if (ret) {
718 mrq->cmd->error = ret;
719 au1xmmc_finish_request(host);
720 }
721}
722
723static void au1xmmc_reset_controller(struct au1xmmc_host *host)
724{
725 /* Apply the clock */
726 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
727 au_sync_delay(1);
728
729 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
730 au_sync_delay(5);
731
732 au_writel(~0, HOST_STATUS(host));
733 au_sync();
734
735 au_writel(0, HOST_BLKSIZE(host));
736 au_writel(0x001fffff, HOST_TIMEOUT(host));
737 au_sync();
738
739 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
740 au_sync();
741
742 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
743 au_sync_delay(1);
744
745 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
746 au_sync();
747
748 /* Configure interrupts */
749 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
750 au_sync();
751}
752
753
754static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
755{
756 struct au1xmmc_host *host = mmc_priv(mmc);
757 u32 config2;
758
759 if (ios->power_mode == MMC_POWER_OFF)
760 au1xmmc_set_power(host, 0);
761 else if (ios->power_mode == MMC_POWER_ON) {
762 au1xmmc_set_power(host, 1);
763 }
764
765 if (ios->clock && ios->clock != host->clock) {
766 au1xmmc_set_clock(host, ios->clock);
767 host->clock = ios->clock;
768 }
769
770 config2 = au_readl(HOST_CONFIG2(host));
771 switch (ios->bus_width) {
772 case MMC_BUS_WIDTH_8:
773 config2 |= SD_CONFIG2_BB;
774 break;
775 case MMC_BUS_WIDTH_4:
776 config2 &= ~SD_CONFIG2_BB;
777 config2 |= SD_CONFIG2_WB;
778 break;
779 case MMC_BUS_WIDTH_1:
780 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
781 break;
782 }
783 au_writel(config2, HOST_CONFIG2(host));
784 au_sync();
785}
786
787#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
788#define STATUS_DATA_IN (SD_STATUS_NE)
789#define STATUS_DATA_OUT (SD_STATUS_TH)
790
791static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
792{
793 struct au1xmmc_host *host = dev_id;
794 u32 status;
795
796 status = au_readl(HOST_STATUS(host));
797
798 if (!(status & SD_STATUS_I))
799 return IRQ_NONE; /* not ours */
800
801 if (status & SD_STATUS_SI) /* SDIO */
802 mmc_signal_sdio_irq(host->mmc);
803
804 if (host->mrq && (status & STATUS_TIMEOUT)) {
805 if (status & SD_STATUS_RAT)
806 host->mrq->cmd->error = -ETIMEDOUT;
807 else if (status & SD_STATUS_DT)
808 host->mrq->data->error = -ETIMEDOUT;
809
810 /* In PIO mode, interrupts might still be enabled */
811 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
812
813 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
814 tasklet_schedule(&host->finish_task);
815 }
816#if 0
817 else if (status & SD_STATUS_DD) {
818 /* Sometimes we get a DD before a NE in PIO mode */
819 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
820 au1xmmc_receive_pio(host);
821 else {
822 au1xmmc_data_complete(host, status);
823 /* tasklet_schedule(&host->data_task); */
824 }
825 }
826#endif
827 else if (status & SD_STATUS_CR) {
828 if (host->status == HOST_S_CMD)
829 au1xmmc_cmd_complete(host, status);
830
831 } else if (!(host->flags & HOST_F_DMA)) {
832 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
833 au1xmmc_send_pio(host);
834 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
835 au1xmmc_receive_pio(host);
836
837 } else if (status & 0x203F3C70) {
838 DBG("Unhandled status %8.8x\n", host->pdev->id,
839 status);
840 }
841
842 au_writel(status, HOST_STATUS(host));
843 au_sync();
844
845 return IRQ_HANDLED;
846}
847
848/* 8bit memory DMA device */
849static dbdev_tab_t au1xmmc_mem_dbdev = {
850 .dev_id = DSCR_CMD0_ALWAYS,
851 .dev_flags = DEV_FLAGS_ANYUSE,
852 .dev_tsize = 0,
853 .dev_devwidth = 8,
854 .dev_physaddr = 0x00000000,
855 .dev_intlevel = 0,
856 .dev_intpolarity = 0,
857};
858static int memid;
859
860static void au1xmmc_dbdma_callback(int irq, void *dev_id)
861{
862 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
863
864 /* Avoid spurious interrupts */
865 if (!host->mrq)
866 return;
867
868 if (host->flags & HOST_F_STOP)
869 SEND_STOP(host);
870
871 tasklet_schedule(&host->data_task);
872}
873
874static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
875{
876 struct resource *res;
877 int txid, rxid;
878
879 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
880 if (!res)
881 return -ENODEV;
882 txid = res->start;
883
884 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
885 if (!res)
886 return -ENODEV;
887 rxid = res->start;
888
889 if (!memid)
890 return -ENODEV;
891
892 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
893 au1xmmc_dbdma_callback, (void *)host);
894 if (!host->tx_chan) {
895 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
896 return -ENODEV;
897 }
898
899 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
900 au1xmmc_dbdma_callback, (void *)host);
901 if (!host->rx_chan) {
902 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
903 au1xxx_dbdma_chan_free(host->tx_chan);
904 return -ENODEV;
905 }
906
907 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
908 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
909
910 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
911 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
912
913 /* DBDMA is good to go */
914 host->flags |= HOST_F_DMA | HOST_F_DBDMA;
915
916 return 0;
917}
918
919static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
920{
921 if (host->flags & HOST_F_DMA) {
922 host->flags &= ~HOST_F_DMA;
923 au1xxx_dbdma_chan_free(host->tx_chan);
924 au1xxx_dbdma_chan_free(host->rx_chan);
925 }
926}
927
928static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
929{
930 struct au1xmmc_host *host = mmc_priv(mmc);
931
932 if (en)
933 IRQ_ON(host, SD_CONFIG_SI);
934 else
935 IRQ_OFF(host, SD_CONFIG_SI);
936}
937
938static const struct mmc_host_ops au1xmmc_ops = {
939 .request = au1xmmc_request,
940 .set_ios = au1xmmc_set_ios,
941 .get_ro = au1xmmc_card_readonly,
942 .get_cd = au1xmmc_card_inserted,
943 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
944};
945
946static int __devinit au1xmmc_probe(struct platform_device *pdev)
947{
948 struct mmc_host *mmc;
949 struct au1xmmc_host *host;
950 struct resource *r;
951 int ret, iflag;
952
953 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
954 if (!mmc) {
955 dev_err(&pdev->dev, "no memory for mmc_host\n");
956 ret = -ENOMEM;
957 goto out0;
958 }
959
960 host = mmc_priv(mmc);
961 host->mmc = mmc;
962 host->platdata = pdev->dev.platform_data;
963 host->pdev = pdev;
964
965 ret = -ENODEV;
966 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
967 if (!r) {
968 dev_err(&pdev->dev, "no mmio defined\n");
969 goto out1;
970 }
971
972 host->ioarea = request_mem_region(r->start, resource_size(r),
973 pdev->name);
974 if (!host->ioarea) {
975 dev_err(&pdev->dev, "mmio already in use\n");
976 goto out1;
977 }
978
979 host->iobase = (unsigned long)ioremap(r->start, 0x3c);
980 if (!host->iobase) {
981 dev_err(&pdev->dev, "cannot remap mmio\n");
982 goto out2;
983 }
984
985 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
986 if (!r) {
987 dev_err(&pdev->dev, "no IRQ defined\n");
988 goto out3;
989 }
990 host->irq = r->start;
991
992 mmc->ops = &au1xmmc_ops;
993
994 mmc->f_min = 450000;
995 mmc->f_max = 24000000;
996
997 mmc->max_blk_size = 2048;
998 mmc->max_blk_count = 512;
999
1000 mmc->ocr_avail = AU1XMMC_OCR;
1001 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1002 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1003
1004 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
1005
1006 switch (alchemy_get_cputype()) {
1007 case ALCHEMY_CPU_AU1100:
1008 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1009 break;
1010 case ALCHEMY_CPU_AU1200:
1011 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1012 break;
1013 case ALCHEMY_CPU_AU1300:
1014 iflag = 0; /* nothing is shared */
1015 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1016 mmc->f_max = 52000000;
1017 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1018 mmc->caps |= MMC_CAP_8_BIT_DATA;
1019 break;
1020 }
1021
1022 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1023 if (ret) {
1024 dev_err(&pdev->dev, "cannot grab IRQ\n");
1025 goto out3;
1026 }
1027
1028 host->status = HOST_S_IDLE;
1029
1030 /* board-specific carddetect setup, if any */
1031 if (host->platdata && host->platdata->cd_setup) {
1032 ret = host->platdata->cd_setup(mmc, 1);
1033 if (ret) {
1034 dev_warn(&pdev->dev, "board CD setup failed\n");
1035 mmc->caps |= MMC_CAP_NEEDS_POLL;
1036 }
1037 } else
1038 mmc->caps |= MMC_CAP_NEEDS_POLL;
1039
1040 /* platform may not be able to use all advertised caps */
1041 if (host->platdata)
1042 mmc->caps &= ~(host->platdata->mask_host_caps);
1043
1044 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1045 (unsigned long)host);
1046
1047 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1048 (unsigned long)host);
1049
1050 if (has_dbdma()) {
1051 ret = au1xmmc_dbdma_init(host);
1052 if (ret)
1053 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1054 }
1055
1056#ifdef CONFIG_LEDS_CLASS
1057 if (host->platdata && host->platdata->led) {
1058 struct led_classdev *led = host->platdata->led;
1059 led->name = mmc_hostname(mmc);
1060 led->brightness = LED_OFF;
1061 led->default_trigger = mmc_hostname(mmc);
1062 ret = led_classdev_register(mmc_dev(mmc), led);
1063 if (ret)
1064 goto out5;
1065 }
1066#endif
1067
1068 au1xmmc_reset_controller(host);
1069
1070 ret = mmc_add_host(mmc);
1071 if (ret) {
1072 dev_err(&pdev->dev, "cannot add mmc host\n");
1073 goto out6;
1074 }
1075
1076 platform_set_drvdata(pdev, host);
1077
1078 pr_info(DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1079 " (mode=%s)\n", pdev->id, host->iobase,
1080 host->flags & HOST_F_DMA ? "dma" : "pio");
1081
1082 return 0; /* all ok */
1083
1084out6:
1085#ifdef CONFIG_LEDS_CLASS
1086 if (host->platdata && host->platdata->led)
1087 led_classdev_unregister(host->platdata->led);
1088out5:
1089#endif
1090 au_writel(0, HOST_ENABLE(host));
1091 au_writel(0, HOST_CONFIG(host));
1092 au_writel(0, HOST_CONFIG2(host));
1093 au_sync();
1094
1095 if (host->flags & HOST_F_DBDMA)
1096 au1xmmc_dbdma_shutdown(host);
1097
1098 tasklet_kill(&host->data_task);
1099 tasklet_kill(&host->finish_task);
1100
1101 if (host->platdata && host->platdata->cd_setup &&
1102 !(mmc->caps & MMC_CAP_NEEDS_POLL))
1103 host->platdata->cd_setup(mmc, 0);
1104
1105 free_irq(host->irq, host);
1106out3:
1107 iounmap((void *)host->iobase);
1108out2:
1109 release_resource(host->ioarea);
1110 kfree(host->ioarea);
1111out1:
1112 mmc_free_host(mmc);
1113out0:
1114 return ret;
1115}
1116
1117static int __devexit au1xmmc_remove(struct platform_device *pdev)
1118{
1119 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1120
1121 if (host) {
1122 mmc_remove_host(host->mmc);
1123
1124#ifdef CONFIG_LEDS_CLASS
1125 if (host->platdata && host->platdata->led)
1126 led_classdev_unregister(host->platdata->led);
1127#endif
1128
1129 if (host->platdata && host->platdata->cd_setup &&
1130 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1131 host->platdata->cd_setup(host->mmc, 0);
1132
1133 au_writel(0, HOST_ENABLE(host));
1134 au_writel(0, HOST_CONFIG(host));
1135 au_writel(0, HOST_CONFIG2(host));
1136 au_sync();
1137
1138 tasklet_kill(&host->data_task);
1139 tasklet_kill(&host->finish_task);
1140
1141 if (host->flags & HOST_F_DBDMA)
1142 au1xmmc_dbdma_shutdown(host);
1143
1144 au1xmmc_set_power(host, 0);
1145
1146 free_irq(host->irq, host);
1147 iounmap((void *)host->iobase);
1148 release_resource(host->ioarea);
1149 kfree(host->ioarea);
1150
1151 mmc_free_host(host->mmc);
1152 platform_set_drvdata(pdev, NULL);
1153 }
1154 return 0;
1155}
1156
1157#ifdef CONFIG_PM
1158static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1159{
1160 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1161 int ret;
1162
1163 ret = mmc_suspend_host(host->mmc);
1164 if (ret)
1165 return ret;
1166
1167 au_writel(0, HOST_CONFIG2(host));
1168 au_writel(0, HOST_CONFIG(host));
1169 au_writel(0xffffffff, HOST_STATUS(host));
1170 au_writel(0, HOST_ENABLE(host));
1171 au_sync();
1172
1173 return 0;
1174}
1175
1176static int au1xmmc_resume(struct platform_device *pdev)
1177{
1178 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1179
1180 au1xmmc_reset_controller(host);
1181
1182 return mmc_resume_host(host->mmc);
1183}
1184#else
1185#define au1xmmc_suspend NULL
1186#define au1xmmc_resume NULL
1187#endif
1188
1189static struct platform_driver au1xmmc_driver = {
1190 .probe = au1xmmc_probe,
1191 .remove = au1xmmc_remove,
1192 .suspend = au1xmmc_suspend,
1193 .resume = au1xmmc_resume,
1194 .driver = {
1195 .name = DRIVER_NAME,
1196 .owner = THIS_MODULE,
1197 },
1198};
1199
1200static int __init au1xmmc_init(void)
1201{
1202 if (has_dbdma()) {
1203 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1204 * of 8 bits. And since devices are shared, we need to create
1205 * our own to avoid freaking out other devices.
1206 */
1207 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1208 if (!memid)
1209 pr_err("au1xmmc: cannot add memory dbdma\n");
1210 }
1211 return platform_driver_register(&au1xmmc_driver);
1212}
1213
1214static void __exit au1xmmc_exit(void)
1215{
1216 if (has_dbdma() && memid)
1217 au1xxx_ddma_del_device(memid);
1218
1219 platform_driver_unregister(&au1xmmc_driver);
1220}
1221
1222module_init(au1xmmc_init);
1223module_exit(au1xmmc_exit);
1224
1225MODULE_AUTHOR("Advanced Micro Devices, Inc");
1226MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1227MODULE_LICENSE("GPL");
1228MODULE_ALIAS("platform:au1xxx-mmc");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
4 *
5 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 *
7 * Developed with help from the 2.4.30 MMC AU1XXX controller including
8 * the following copyright notices:
9 * Copyright (c) 2003-2004 Embedded Edge, LLC.
10 * Portions Copyright (C) 2002 Embedix, Inc
11 * Copyright 2002 Hewlett-Packard Company
12
13 * 2.6 version of this driver inspired by:
14 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
15 * All Rights Reserved.
16 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
17 * All Rights Reserved.
18 *
19
20 */
21
22/* Why don't we use the SD controllers' carddetect feature?
23 *
24 * From the AU1100 MMC application guide:
25 * If the Au1100-based design is intended to support both MultiMediaCards
26 * and 1- or 4-data bit SecureDigital cards, then the solution is to
27 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
28 * In doing so, a MMC card never enters SPI-mode communications,
29 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
30 * (the low to high transition will not occur).
31 */
32
33#include <linux/clk.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/platform_device.h>
37#include <linux/mm.h>
38#include <linux/interrupt.h>
39#include <linux/dma-mapping.h>
40#include <linux/scatterlist.h>
41#include <linux/highmem.h>
42#include <linux/leds.h>
43#include <linux/mmc/host.h>
44#include <linux/slab.h>
45#include <linux/workqueue.h>
46
47#include <asm/io.h>
48#include <asm/mach-au1x00/au1000.h>
49#include <asm/mach-au1x00/au1xxx_dbdma.h>
50#include <asm/mach-au1x00/au1100_mmc.h>
51
52#define DRIVER_NAME "au1xxx-mmc"
53
54/* Set this to enable special debugging macros */
55/* #define DEBUG */
56
57#ifdef DEBUG
58#define DBG(fmt, idx, args...) \
59 pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
60#else
61#define DBG(fmt, idx, args...) do {} while (0)
62#endif
63
64/* Hardware definitions */
65#define AU1XMMC_DESCRIPTOR_COUNT 1
66
67/* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
68#define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
69#define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
70
71#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
72 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
73 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
74
75/* This gives us a hard value for the stop command that we can write directly
76 * to the command register.
77 */
78#define STOP_CMD \
79 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
80
81/* This is the set of interrupts that we configure by default. */
82#define AU1XMMC_INTERRUPTS \
83 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
84 SD_CONFIG_CR | SD_CONFIG_I)
85
86/* The poll event (looking for insert/remove events runs twice a second. */
87#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
88
89struct au1xmmc_host {
90 struct mmc_host *mmc;
91 struct mmc_request *mrq;
92
93 u32 flags;
94 void __iomem *iobase;
95 u32 clock;
96 u32 bus_width;
97 u32 power_mode;
98
99 int status;
100
101 struct {
102 int len;
103 int dir;
104 } dma;
105
106 struct {
107 int index;
108 int offset;
109 int len;
110 } pio;
111
112 u32 tx_chan;
113 u32 rx_chan;
114
115 int irq;
116
117 struct work_struct finish_bh_work;
118 struct work_struct data_bh_work;
119 struct au1xmmc_platform_data *platdata;
120 struct platform_device *pdev;
121 struct resource *ioarea;
122 struct clk *clk;
123};
124
125/* Status flags used by the host structure */
126#define HOST_F_XMIT 0x0001
127#define HOST_F_RECV 0x0002
128#define HOST_F_DMA 0x0010
129#define HOST_F_DBDMA 0x0020
130#define HOST_F_ACTIVE 0x0100
131#define HOST_F_STOP 0x1000
132
133#define HOST_S_IDLE 0x0001
134#define HOST_S_CMD 0x0002
135#define HOST_S_DATA 0x0003
136#define HOST_S_STOP 0x0004
137
138/* Easy access macros */
139#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
140#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
141#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
142#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
143#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
144#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
145#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
146#define HOST_CMD(h) ((h)->iobase + SD_CMD)
147#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
148#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
149#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
150
151#define DMA_CHANNEL(h) \
152 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
153
154static inline int has_dbdma(void)
155{
156 switch (alchemy_get_cputype()) {
157 case ALCHEMY_CPU_AU1200:
158 case ALCHEMY_CPU_AU1300:
159 return 1;
160 default:
161 return 0;
162 }
163}
164
165static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
166{
167 u32 val = __raw_readl(HOST_CONFIG(host));
168 val |= mask;
169 __raw_writel(val, HOST_CONFIG(host));
170 wmb(); /* drain writebuffer */
171}
172
173static inline void FLUSH_FIFO(struct au1xmmc_host *host)
174{
175 u32 val = __raw_readl(HOST_CONFIG2(host));
176
177 __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
178 wmb(); /* drain writebuffer */
179 mdelay(1);
180
181 /* SEND_STOP will turn off clock control - this re-enables it */
182 val &= ~SD_CONFIG2_DF;
183
184 __raw_writel(val, HOST_CONFIG2(host));
185 wmb(); /* drain writebuffer */
186}
187
188static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
189{
190 u32 val = __raw_readl(HOST_CONFIG(host));
191 val &= ~mask;
192 __raw_writel(val, HOST_CONFIG(host));
193 wmb(); /* drain writebuffer */
194}
195
196static inline void SEND_STOP(struct au1xmmc_host *host)
197{
198 u32 config2;
199
200 WARN_ON(host->status != HOST_S_DATA);
201 host->status = HOST_S_STOP;
202
203 config2 = __raw_readl(HOST_CONFIG2(host));
204 __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
205 wmb(); /* drain writebuffer */
206
207 /* Send the stop command */
208 __raw_writel(STOP_CMD, HOST_CMD(host));
209 wmb(); /* drain writebuffer */
210}
211
212static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
213{
214 if (host->platdata && host->platdata->set_power)
215 host->platdata->set_power(host->mmc, state);
216}
217
218static int au1xmmc_card_inserted(struct mmc_host *mmc)
219{
220 struct au1xmmc_host *host = mmc_priv(mmc);
221
222 if (host->platdata && host->platdata->card_inserted)
223 return !!host->platdata->card_inserted(host->mmc);
224
225 return -ENOSYS;
226}
227
228static int au1xmmc_card_readonly(struct mmc_host *mmc)
229{
230 struct au1xmmc_host *host = mmc_priv(mmc);
231
232 if (host->platdata && host->platdata->card_readonly)
233 return !!host->platdata->card_readonly(mmc);
234
235 return -ENOSYS;
236}
237
238static void au1xmmc_finish_request(struct au1xmmc_host *host)
239{
240 struct mmc_request *mrq = host->mrq;
241
242 host->mrq = NULL;
243 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
244
245 host->dma.len = 0;
246 host->dma.dir = 0;
247
248 host->pio.index = 0;
249 host->pio.offset = 0;
250 host->pio.len = 0;
251
252 host->status = HOST_S_IDLE;
253
254 mmc_request_done(host->mmc, mrq);
255}
256
257static void au1xmmc_finish_bh_work(struct work_struct *t)
258{
259 struct au1xmmc_host *host = from_work(host, t, finish_bh_work);
260 au1xmmc_finish_request(host);
261}
262
263static int au1xmmc_send_command(struct au1xmmc_host *host,
264 struct mmc_command *cmd, struct mmc_data *data)
265{
266 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
267
268 switch (mmc_resp_type(cmd)) {
269 case MMC_RSP_NONE:
270 break;
271 case MMC_RSP_R1:
272 mmccmd |= SD_CMD_RT_1;
273 break;
274 case MMC_RSP_R1B:
275 mmccmd |= SD_CMD_RT_1B;
276 break;
277 case MMC_RSP_R2:
278 mmccmd |= SD_CMD_RT_2;
279 break;
280 case MMC_RSP_R3:
281 mmccmd |= SD_CMD_RT_3;
282 break;
283 default:
284 pr_info("au1xmmc: unhandled response type %02x\n",
285 mmc_resp_type(cmd));
286 return -EINVAL;
287 }
288
289 if (data) {
290 if (data->flags & MMC_DATA_READ) {
291 if (data->blocks > 1)
292 mmccmd |= SD_CMD_CT_4;
293 else
294 mmccmd |= SD_CMD_CT_2;
295 } else if (data->flags & MMC_DATA_WRITE) {
296 if (data->blocks > 1)
297 mmccmd |= SD_CMD_CT_3;
298 else
299 mmccmd |= SD_CMD_CT_1;
300 }
301 }
302
303 __raw_writel(cmd->arg, HOST_CMDARG(host));
304 wmb(); /* drain writebuffer */
305
306 __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
307 wmb(); /* drain writebuffer */
308
309 /* Wait for the command to go on the line */
310 while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
311 /* nop */;
312
313 return 0;
314}
315
316static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
317{
318 struct mmc_request *mrq = host->mrq;
319 struct mmc_data *data;
320 u32 crc;
321
322 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
323
324 if (host->mrq == NULL)
325 return;
326
327 data = mrq->cmd->data;
328
329 if (status == 0)
330 status = __raw_readl(HOST_STATUS(host));
331
332 /* The transaction is really over when the SD_STATUS_DB bit is clear */
333 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
334 status = __raw_readl(HOST_STATUS(host));
335
336 data->error = 0;
337 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
338
339 /* Process any errors */
340 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
341 if (host->flags & HOST_F_XMIT)
342 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
343
344 if (crc)
345 data->error = -EILSEQ;
346
347 /* Clear the CRC bits */
348 __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
349
350 data->bytes_xfered = 0;
351
352 if (!data->error) {
353 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
354 u32 chan = DMA_CHANNEL(host);
355
356 chan_tab_t *c = *((chan_tab_t **)chan);
357 au1x_dma_chan_t *cp = c->chan_ptr;
358 data->bytes_xfered = cp->ddma_bytecnt;
359 } else
360 data->bytes_xfered =
361 (data->blocks * data->blksz) - host->pio.len;
362 }
363
364 au1xmmc_finish_request(host);
365}
366
367static void au1xmmc_data_bh_work(struct work_struct *t)
368{
369 struct au1xmmc_host *host = from_work(host, t, data_bh_work);
370
371 u32 status = __raw_readl(HOST_STATUS(host));
372 au1xmmc_data_complete(host, status);
373}
374
375#define AU1XMMC_MAX_TRANSFER 8
376
377static void au1xmmc_send_pio(struct au1xmmc_host *host)
378{
379 struct mmc_data *data;
380 int sg_len, max, count;
381 unsigned char *sg_ptr, val;
382 u32 status;
383 struct scatterlist *sg;
384
385 data = host->mrq->data;
386
387 if (!(host->flags & HOST_F_XMIT))
388 return;
389
390 /* This is the pointer to the data buffer */
391 sg = &data->sg[host->pio.index];
392 sg_ptr = kmap_local_page(sg_page(sg)) + sg->offset + host->pio.offset;
393
394 /* This is the space left inside the buffer */
395 sg_len = data->sg[host->pio.index].length - host->pio.offset;
396
397 /* Check if we need less than the size of the sg_buffer */
398 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
399 if (max > AU1XMMC_MAX_TRANSFER)
400 max = AU1XMMC_MAX_TRANSFER;
401
402 for (count = 0; count < max; count++) {
403 status = __raw_readl(HOST_STATUS(host));
404
405 if (!(status & SD_STATUS_TH))
406 break;
407
408 val = sg_ptr[count];
409
410 __raw_writel((unsigned long)val, HOST_TXPORT(host));
411 wmb(); /* drain writebuffer */
412 }
413 kunmap_local(sg_ptr);
414
415 host->pio.len -= count;
416 host->pio.offset += count;
417
418 if (count == sg_len) {
419 host->pio.index++;
420 host->pio.offset = 0;
421 }
422
423 if (host->pio.len == 0) {
424 IRQ_OFF(host, SD_CONFIG_TH);
425
426 if (host->flags & HOST_F_STOP)
427 SEND_STOP(host);
428
429 queue_work(system_bh_wq, &host->data_bh_work);
430 }
431}
432
433static void au1xmmc_receive_pio(struct au1xmmc_host *host)
434{
435 struct mmc_data *data;
436 int max, count, sg_len = 0;
437 unsigned char *sg_ptr = NULL;
438 u32 status, val;
439 struct scatterlist *sg;
440
441 data = host->mrq->data;
442
443 if (!(host->flags & HOST_F_RECV))
444 return;
445
446 max = host->pio.len;
447
448 if (host->pio.index < host->dma.len) {
449 sg = &data->sg[host->pio.index];
450 sg_ptr = kmap_local_page(sg_page(sg)) + sg->offset + host->pio.offset;
451
452 /* This is the space left inside the buffer */
453 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
454
455 /* Check if we need less than the size of the sg_buffer */
456 if (sg_len < max)
457 max = sg_len;
458 }
459
460 if (max > AU1XMMC_MAX_TRANSFER)
461 max = AU1XMMC_MAX_TRANSFER;
462
463 for (count = 0; count < max; count++) {
464 status = __raw_readl(HOST_STATUS(host));
465
466 if (!(status & SD_STATUS_NE))
467 break;
468
469 if (status & SD_STATUS_RC) {
470 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
471 host->pio.len, count);
472 break;
473 }
474
475 if (status & SD_STATUS_RO) {
476 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
477 host->pio.len, count);
478 break;
479 }
480 else if (status & SD_STATUS_RU) {
481 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
482 host->pio.len, count);
483 break;
484 }
485
486 val = __raw_readl(HOST_RXPORT(host));
487
488 if (sg_ptr)
489 sg_ptr[count] = (unsigned char)(val & 0xFF);
490 }
491 if (sg_ptr)
492 kunmap_local(sg_ptr);
493
494 host->pio.len -= count;
495 host->pio.offset += count;
496
497 if (sg_len && count == sg_len) {
498 host->pio.index++;
499 host->pio.offset = 0;
500 }
501
502 if (host->pio.len == 0) {
503 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
504 IRQ_OFF(host, SD_CONFIG_NE);
505
506 if (host->flags & HOST_F_STOP)
507 SEND_STOP(host);
508
509 queue_work(system_bh_wq, &host->data_bh_work);
510 }
511}
512
513/* This is called when a command has been completed - grab the response
514 * and check for errors. Then start the data transfer if it is indicated.
515 */
516static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
517{
518 struct mmc_request *mrq = host->mrq;
519 struct mmc_command *cmd;
520 u32 r[4];
521 int i, trans;
522
523 if (!host->mrq)
524 return;
525
526 cmd = mrq->cmd;
527 cmd->error = 0;
528
529 if (cmd->flags & MMC_RSP_PRESENT) {
530 if (cmd->flags & MMC_RSP_136) {
531 r[0] = __raw_readl(host->iobase + SD_RESP3);
532 r[1] = __raw_readl(host->iobase + SD_RESP2);
533 r[2] = __raw_readl(host->iobase + SD_RESP1);
534 r[3] = __raw_readl(host->iobase + SD_RESP0);
535
536 /* The CRC is omitted from the response, so really
537 * we only got 120 bytes, but the engine expects
538 * 128 bits, so we have to shift things up.
539 */
540 for (i = 0; i < 4; i++) {
541 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
542 if (i != 3)
543 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
544 }
545 } else {
546 /* Technically, we should be getting all 48 bits of
547 * the response (SD_RESP1 + SD_RESP2), but because
548 * our response omits the CRC, our data ends up
549 * being shifted 8 bits to the right. In this case,
550 * that means that the OSR data starts at bit 31,
551 * so we can just read RESP0 and return that.
552 */
553 cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
554 }
555 }
556
557 /* Figure out errors */
558 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
559 cmd->error = -EILSEQ;
560
561 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
562
563 if (!trans || cmd->error) {
564 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
565 queue_work(system_bh_wq, &host->finish_bh_work);
566 return;
567 }
568
569 host->status = HOST_S_DATA;
570
571 if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
572 u32 channel = DMA_CHANNEL(host);
573
574 /* Start the DBDMA as soon as the buffer gets something in it */
575
576 if (host->flags & HOST_F_RECV) {
577 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
578
579 while((status & mask) != mask)
580 status = __raw_readl(HOST_STATUS(host));
581 }
582
583 au1xxx_dbdma_start(channel);
584 }
585}
586
587static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
588{
589 unsigned int pbus = clk_get_rate(host->clk);
590 unsigned int divisor = ((pbus / rate) / 2) - 1;
591 u32 config;
592
593 config = __raw_readl(HOST_CONFIG(host));
594
595 config &= ~(SD_CONFIG_DIV);
596 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
597
598 __raw_writel(config, HOST_CONFIG(host));
599 wmb(); /* drain writebuffer */
600}
601
602static int au1xmmc_prepare_data(struct au1xmmc_host *host,
603 struct mmc_data *data)
604{
605 int datalen = data->blocks * data->blksz;
606
607 if (data->flags & MMC_DATA_READ)
608 host->flags |= HOST_F_RECV;
609 else
610 host->flags |= HOST_F_XMIT;
611
612 if (host->mrq->stop)
613 host->flags |= HOST_F_STOP;
614
615 host->dma.dir = DMA_BIDIRECTIONAL;
616
617 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
618 data->sg_len, host->dma.dir);
619
620 if (host->dma.len == 0)
621 return -ETIMEDOUT;
622
623 __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
624
625 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
626 int i;
627 u32 channel = DMA_CHANNEL(host);
628
629 au1xxx_dbdma_stop(channel);
630
631 for (i = 0; i < host->dma.len; i++) {
632 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
633 struct scatterlist *sg = &data->sg[i];
634 int sg_len = sg->length;
635
636 int len = (datalen > sg_len) ? sg_len : datalen;
637
638 if (i == host->dma.len - 1)
639 flags = DDMA_FLAGS_IE;
640
641 if (host->flags & HOST_F_XMIT) {
642 ret = au1xxx_dbdma_put_source(channel,
643 sg_phys(sg), len, flags);
644 } else {
645 ret = au1xxx_dbdma_put_dest(channel,
646 sg_phys(sg), len, flags);
647 }
648
649 if (!ret)
650 goto dataerr;
651
652 datalen -= len;
653 }
654 } else {
655 host->pio.index = 0;
656 host->pio.offset = 0;
657 host->pio.len = datalen;
658
659 if (host->flags & HOST_F_XMIT)
660 IRQ_ON(host, SD_CONFIG_TH);
661 else
662 IRQ_ON(host, SD_CONFIG_NE);
663 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
664 }
665
666 return 0;
667
668dataerr:
669 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
670 host->dma.dir);
671 return -ETIMEDOUT;
672}
673
674/* This actually starts a command or data transaction */
675static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
676{
677 struct au1xmmc_host *host = mmc_priv(mmc);
678 int ret = 0;
679
680 WARN_ON(irqs_disabled());
681 WARN_ON(host->status != HOST_S_IDLE);
682
683 host->mrq = mrq;
684 host->status = HOST_S_CMD;
685
686 /* fail request immediately if no card is present */
687 if (0 == au1xmmc_card_inserted(mmc)) {
688 mrq->cmd->error = -ENOMEDIUM;
689 au1xmmc_finish_request(host);
690 return;
691 }
692
693 if (mrq->data) {
694 FLUSH_FIFO(host);
695 ret = au1xmmc_prepare_data(host, mrq->data);
696 }
697
698 if (!ret)
699 ret = au1xmmc_send_command(host, mrq->cmd, mrq->data);
700
701 if (ret) {
702 mrq->cmd->error = ret;
703 au1xmmc_finish_request(host);
704 }
705}
706
707static void au1xmmc_reset_controller(struct au1xmmc_host *host)
708{
709 /* Apply the clock */
710 __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
711 wmb(); /* drain writebuffer */
712 mdelay(1);
713
714 __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
715 wmb(); /* drain writebuffer */
716 mdelay(5);
717
718 __raw_writel(~0, HOST_STATUS(host));
719 wmb(); /* drain writebuffer */
720
721 __raw_writel(0, HOST_BLKSIZE(host));
722 __raw_writel(0x001fffff, HOST_TIMEOUT(host));
723 wmb(); /* drain writebuffer */
724
725 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
726 wmb(); /* drain writebuffer */
727
728 __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
729 wmb(); /* drain writebuffer */
730 mdelay(1);
731
732 __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
733 wmb(); /* drain writebuffer */
734
735 /* Configure interrupts */
736 __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
737 wmb(); /* drain writebuffer */
738}
739
740
741static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
742{
743 struct au1xmmc_host *host = mmc_priv(mmc);
744 u32 config2;
745
746 if (ios->power_mode == MMC_POWER_OFF)
747 au1xmmc_set_power(host, 0);
748 else if (ios->power_mode == MMC_POWER_ON) {
749 au1xmmc_set_power(host, 1);
750 }
751
752 if (ios->clock && ios->clock != host->clock) {
753 au1xmmc_set_clock(host, ios->clock);
754 host->clock = ios->clock;
755 }
756
757 config2 = __raw_readl(HOST_CONFIG2(host));
758 switch (ios->bus_width) {
759 case MMC_BUS_WIDTH_8:
760 config2 |= SD_CONFIG2_BB;
761 break;
762 case MMC_BUS_WIDTH_4:
763 config2 &= ~SD_CONFIG2_BB;
764 config2 |= SD_CONFIG2_WB;
765 break;
766 case MMC_BUS_WIDTH_1:
767 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
768 break;
769 }
770 __raw_writel(config2, HOST_CONFIG2(host));
771 wmb(); /* drain writebuffer */
772}
773
774#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
775#define STATUS_DATA_IN (SD_STATUS_NE)
776#define STATUS_DATA_OUT (SD_STATUS_TH)
777
778static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
779{
780 struct au1xmmc_host *host = dev_id;
781 u32 status;
782
783 status = __raw_readl(HOST_STATUS(host));
784
785 if (!(status & SD_STATUS_I))
786 return IRQ_NONE; /* not ours */
787
788 if (status & SD_STATUS_SI) /* SDIO */
789 mmc_signal_sdio_irq(host->mmc);
790
791 if (host->mrq && (status & STATUS_TIMEOUT)) {
792 if (status & SD_STATUS_RAT)
793 host->mrq->cmd->error = -ETIMEDOUT;
794 else if (status & SD_STATUS_DT)
795 host->mrq->data->error = -ETIMEDOUT;
796
797 /* In PIO mode, interrupts might still be enabled */
798 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
799
800 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
801 queue_work(system_bh_wq, &host->finish_bh_work);
802 }
803#if 0
804 else if (status & SD_STATUS_DD) {
805 /* Sometimes we get a DD before a NE in PIO mode */
806 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
807 au1xmmc_receive_pio(host);
808 else {
809 au1xmmc_data_complete(host, status);
810 /* queue_work(system_bh_wq, &host->data_bh_work); */
811 }
812 }
813#endif
814 else if (status & SD_STATUS_CR) {
815 if (host->status == HOST_S_CMD)
816 au1xmmc_cmd_complete(host, status);
817
818 } else if (!(host->flags & HOST_F_DMA)) {
819 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
820 au1xmmc_send_pio(host);
821 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
822 au1xmmc_receive_pio(host);
823
824 } else if (status & 0x203F3C70) {
825 DBG("Unhandled status %8.8x\n", host->pdev->id,
826 status);
827 }
828
829 __raw_writel(status, HOST_STATUS(host));
830 wmb(); /* drain writebuffer */
831
832 return IRQ_HANDLED;
833}
834
835/* 8bit memory DMA device */
836static dbdev_tab_t au1xmmc_mem_dbdev = {
837 .dev_id = DSCR_CMD0_ALWAYS,
838 .dev_flags = DEV_FLAGS_ANYUSE,
839 .dev_tsize = 0,
840 .dev_devwidth = 8,
841 .dev_physaddr = 0x00000000,
842 .dev_intlevel = 0,
843 .dev_intpolarity = 0,
844};
845static int memid;
846
847static void au1xmmc_dbdma_callback(int irq, void *dev_id)
848{
849 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
850
851 /* Avoid spurious interrupts */
852 if (!host->mrq)
853 return;
854
855 if (host->flags & HOST_F_STOP)
856 SEND_STOP(host);
857
858 queue_work(system_bh_wq, &host->data_bh_work);
859}
860
861static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
862{
863 struct resource *res;
864 int txid, rxid;
865
866 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
867 if (!res)
868 return -ENODEV;
869 txid = res->start;
870
871 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
872 if (!res)
873 return -ENODEV;
874 rxid = res->start;
875
876 if (!memid)
877 return -ENODEV;
878
879 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
880 au1xmmc_dbdma_callback, (void *)host);
881 if (!host->tx_chan) {
882 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
883 return -ENODEV;
884 }
885
886 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
887 au1xmmc_dbdma_callback, (void *)host);
888 if (!host->rx_chan) {
889 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
890 au1xxx_dbdma_chan_free(host->tx_chan);
891 return -ENODEV;
892 }
893
894 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
895 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
896
897 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
898 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
899
900 /* DBDMA is good to go */
901 host->flags |= HOST_F_DMA | HOST_F_DBDMA;
902
903 return 0;
904}
905
906static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
907{
908 if (host->flags & HOST_F_DMA) {
909 host->flags &= ~HOST_F_DMA;
910 au1xxx_dbdma_chan_free(host->tx_chan);
911 au1xxx_dbdma_chan_free(host->rx_chan);
912 }
913}
914
915static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
916{
917 struct au1xmmc_host *host = mmc_priv(mmc);
918
919 if (en)
920 IRQ_ON(host, SD_CONFIG_SI);
921 else
922 IRQ_OFF(host, SD_CONFIG_SI);
923}
924
925static const struct mmc_host_ops au1xmmc_ops = {
926 .request = au1xmmc_request,
927 .set_ios = au1xmmc_set_ios,
928 .get_ro = au1xmmc_card_readonly,
929 .get_cd = au1xmmc_card_inserted,
930 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
931};
932
933static int au1xmmc_probe(struct platform_device *pdev)
934{
935 struct mmc_host *mmc;
936 struct au1xmmc_host *host;
937 struct resource *r;
938 int ret, iflag;
939
940 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
941 if (!mmc) {
942 dev_err(&pdev->dev, "no memory for mmc_host\n");
943 ret = -ENOMEM;
944 goto out0;
945 }
946
947 host = mmc_priv(mmc);
948 host->mmc = mmc;
949 host->platdata = pdev->dev.platform_data;
950 host->pdev = pdev;
951
952 ret = -ENODEV;
953 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
954 if (!r) {
955 dev_err(&pdev->dev, "no mmio defined\n");
956 goto out1;
957 }
958
959 host->ioarea = request_mem_region(r->start, resource_size(r),
960 pdev->name);
961 if (!host->ioarea) {
962 dev_err(&pdev->dev, "mmio already in use\n");
963 goto out1;
964 }
965
966 host->iobase = ioremap(r->start, 0x3c);
967 if (!host->iobase) {
968 dev_err(&pdev->dev, "cannot remap mmio\n");
969 goto out2;
970 }
971
972 host->irq = platform_get_irq(pdev, 0);
973 if (host->irq < 0) {
974 ret = host->irq;
975 goto out3;
976 }
977
978 mmc->ops = &au1xmmc_ops;
979
980 mmc->f_min = 450000;
981 mmc->f_max = 24000000;
982
983 mmc->max_blk_size = 2048;
984 mmc->max_blk_count = 512;
985
986 mmc->ocr_avail = AU1XMMC_OCR;
987 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
988 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
989
990 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
991
992 switch (alchemy_get_cputype()) {
993 case ALCHEMY_CPU_AU1100:
994 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
995 break;
996 case ALCHEMY_CPU_AU1200:
997 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
998 break;
999 case ALCHEMY_CPU_AU1300:
1000 iflag = 0; /* nothing is shared */
1001 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1002 mmc->f_max = 52000000;
1003 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1004 mmc->caps |= MMC_CAP_8_BIT_DATA;
1005 break;
1006 }
1007
1008 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1009 if (ret) {
1010 dev_err(&pdev->dev, "cannot grab IRQ\n");
1011 goto out3;
1012 }
1013
1014 host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
1015 if (IS_ERR(host->clk)) {
1016 dev_err(&pdev->dev, "cannot find clock\n");
1017 ret = PTR_ERR(host->clk);
1018 goto out_irq;
1019 }
1020
1021 ret = clk_prepare_enable(host->clk);
1022 if (ret) {
1023 dev_err(&pdev->dev, "cannot enable clock\n");
1024 goto out_clk;
1025 }
1026
1027 host->status = HOST_S_IDLE;
1028
1029 /* board-specific carddetect setup, if any */
1030 if (host->platdata && host->platdata->cd_setup) {
1031 ret = host->platdata->cd_setup(mmc, 1);
1032 if (ret) {
1033 dev_warn(&pdev->dev, "board CD setup failed\n");
1034 mmc->caps |= MMC_CAP_NEEDS_POLL;
1035 }
1036 } else
1037 mmc->caps |= MMC_CAP_NEEDS_POLL;
1038
1039 /* platform may not be able to use all advertised caps */
1040 if (host->platdata)
1041 mmc->caps &= ~(host->platdata->mask_host_caps);
1042
1043 INIT_WORK(&host->data_bh_work, au1xmmc_data_bh_work);
1044
1045 INIT_WORK(&host->finish_bh_work, au1xmmc_finish_bh_work);
1046
1047 if (has_dbdma()) {
1048 ret = au1xmmc_dbdma_init(host);
1049 if (ret)
1050 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1051 }
1052
1053#ifdef CONFIG_LEDS_CLASS
1054 if (host->platdata && host->platdata->led) {
1055 struct led_classdev *led = host->platdata->led;
1056 led->name = mmc_hostname(mmc);
1057 led->brightness = LED_OFF;
1058 led->default_trigger = mmc_hostname(mmc);
1059 ret = led_classdev_register(mmc_dev(mmc), led);
1060 if (ret)
1061 goto out5;
1062 }
1063#endif
1064
1065 au1xmmc_reset_controller(host);
1066
1067 ret = mmc_add_host(mmc);
1068 if (ret) {
1069 dev_err(&pdev->dev, "cannot add mmc host\n");
1070 goto out6;
1071 }
1072
1073 platform_set_drvdata(pdev, host);
1074
1075 pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
1076 " (mode=%s)\n", pdev->id, host->iobase,
1077 host->flags & HOST_F_DMA ? "dma" : "pio");
1078
1079 return 0; /* all ok */
1080
1081out6:
1082#ifdef CONFIG_LEDS_CLASS
1083 if (host->platdata && host->platdata->led)
1084 led_classdev_unregister(host->platdata->led);
1085out5:
1086#endif
1087 __raw_writel(0, HOST_ENABLE(host));
1088 __raw_writel(0, HOST_CONFIG(host));
1089 __raw_writel(0, HOST_CONFIG2(host));
1090 wmb(); /* drain writebuffer */
1091
1092 if (host->flags & HOST_F_DBDMA)
1093 au1xmmc_dbdma_shutdown(host);
1094
1095 cancel_work_sync(&host->data_bh_work);
1096 cancel_work_sync(&host->finish_bh_work);
1097
1098 if (host->platdata && host->platdata->cd_setup &&
1099 !(mmc->caps & MMC_CAP_NEEDS_POLL))
1100 host->platdata->cd_setup(mmc, 0);
1101
1102 clk_disable_unprepare(host->clk);
1103out_clk:
1104 clk_put(host->clk);
1105out_irq:
1106 free_irq(host->irq, host);
1107out3:
1108 iounmap((void *)host->iobase);
1109out2:
1110 release_resource(host->ioarea);
1111 kfree(host->ioarea);
1112out1:
1113 mmc_free_host(mmc);
1114out0:
1115 return ret;
1116}
1117
1118static void au1xmmc_remove(struct platform_device *pdev)
1119{
1120 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1121
1122 if (host) {
1123 mmc_remove_host(host->mmc);
1124
1125#ifdef CONFIG_LEDS_CLASS
1126 if (host->platdata && host->platdata->led)
1127 led_classdev_unregister(host->platdata->led);
1128#endif
1129
1130 if (host->platdata && host->platdata->cd_setup &&
1131 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1132 host->platdata->cd_setup(host->mmc, 0);
1133
1134 __raw_writel(0, HOST_ENABLE(host));
1135 __raw_writel(0, HOST_CONFIG(host));
1136 __raw_writel(0, HOST_CONFIG2(host));
1137 wmb(); /* drain writebuffer */
1138
1139 cancel_work_sync(&host->data_bh_work);
1140 cancel_work_sync(&host->finish_bh_work);
1141
1142 if (host->flags & HOST_F_DBDMA)
1143 au1xmmc_dbdma_shutdown(host);
1144
1145 au1xmmc_set_power(host, 0);
1146
1147 clk_disable_unprepare(host->clk);
1148 clk_put(host->clk);
1149
1150 free_irq(host->irq, host);
1151 iounmap((void *)host->iobase);
1152 release_resource(host->ioarea);
1153 kfree(host->ioarea);
1154
1155 mmc_free_host(host->mmc);
1156 }
1157}
1158
1159#ifdef CONFIG_PM
1160static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1161{
1162 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1163
1164 __raw_writel(0, HOST_CONFIG2(host));
1165 __raw_writel(0, HOST_CONFIG(host));
1166 __raw_writel(0xffffffff, HOST_STATUS(host));
1167 __raw_writel(0, HOST_ENABLE(host));
1168 wmb(); /* drain writebuffer */
1169
1170 return 0;
1171}
1172
1173static int au1xmmc_resume(struct platform_device *pdev)
1174{
1175 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1176
1177 au1xmmc_reset_controller(host);
1178
1179 return 0;
1180}
1181#else
1182#define au1xmmc_suspend NULL
1183#define au1xmmc_resume NULL
1184#endif
1185
1186static struct platform_driver au1xmmc_driver = {
1187 .probe = au1xmmc_probe,
1188 .remove = au1xmmc_remove,
1189 .suspend = au1xmmc_suspend,
1190 .resume = au1xmmc_resume,
1191 .driver = {
1192 .name = DRIVER_NAME,
1193 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1194 },
1195};
1196
1197static int __init au1xmmc_init(void)
1198{
1199 if (has_dbdma()) {
1200 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1201 * of 8 bits. And since devices are shared, we need to create
1202 * our own to avoid freaking out other devices.
1203 */
1204 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1205 if (!memid)
1206 pr_err("au1xmmc: cannot add memory dbdma\n");
1207 }
1208 return platform_driver_register(&au1xmmc_driver);
1209}
1210
1211static void __exit au1xmmc_exit(void)
1212{
1213 if (has_dbdma() && memid)
1214 au1xxx_ddma_del_device(memid);
1215
1216 platform_driver_unregister(&au1xmmc_driver);
1217}
1218
1219module_init(au1xmmc_init);
1220module_exit(au1xmmc_exit);
1221
1222MODULE_AUTHOR("Advanced Micro Devices, Inc");
1223MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1224MODULE_LICENSE("GPL");
1225MODULE_ALIAS("platform:au1xxx-mmc");