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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10
11#include "ccu_common.h"
12#include "ccu_reset.h"
13
14#include "ccu_div.h"
15#include "ccu_gate.h"
16#include "ccu_mp.h"
17#include "ccu_nm.h"
18
19#include "ccu-sun50i-h6-r.h"
20
21/*
22 * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
23 * clock definitions in the BSP source code.
24 */
25
26static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
27 "iosc", "pll-periph0" };
28static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
29 { .index = 3, .shift = 0, .width = 5 },
30};
31
32static struct ccu_div ar100_clk = {
33 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
34
35 .mux = {
36 .shift = 24,
37 .width = 2,
38
39 .var_predivs = ar100_r_apb2_predivs,
40 .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
41 },
42
43 .common = {
44 .reg = 0x000,
45 .features = CCU_FEATURE_VARIABLE_PREDIV,
46 .hw.init = CLK_HW_INIT_PARENTS("ar100",
47 ar100_r_apb2_parents,
48 &ccu_div_ops,
49 0),
50 },
51};
52
53static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54
55static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
56
57static struct ccu_div r_apb2_clk = {
58 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
59
60 .mux = {
61 .shift = 24,
62 .width = 2,
63
64 .var_predivs = ar100_r_apb2_predivs,
65 .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
66 },
67
68 .common = {
69 .reg = 0x010,
70 .features = CCU_FEATURE_VARIABLE_PREDIV,
71 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
72 ar100_r_apb2_parents,
73 &ccu_div_ops,
74 0),
75 },
76};
77
78/*
79 * Information about the gate/resets are gathered from the clock header file
80 * in the BSP source code, although most of them are unused. The existence
81 * of the hardware block is verified with "3.1 Memory Mapping" chapter in
82 * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
83 * with "3.3.2.1 System Bus Tree" chapter inthe same document.
84 */
85static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
86 0x11c, BIT(0), 0);
87static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
88 0x12c, BIT(0), 0);
89static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
90 0x13c, BIT(0), 0);
91static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
92 0x18c, BIT(0), 0);
93static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
94 0x19c, BIT(0), 0);
95static SUNXI_CCU_GATE(r_apb2_rsb_clk, "r-apb2-rsb", "r-apb2",
96 0x1bc, BIT(0), 0);
97static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
98 0x1cc, BIT(0), 0);
99static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
100 0x1ec, BIT(0), 0);
101static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1",
102 0x20c, BIT(0), CLK_IGNORE_UNUSED);
103
104/* Information of IR(RX) mod clock is gathered from BSP source code */
105static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
106static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
107 r_mod0_default_parents, 0x1c0,
108 0, 5, /* M */
109 8, 2, /* P */
110 24, 1, /* mux */
111 BIT(31), /* gate */
112 0);
113
114/*
115 * BSP didn't use the 1-wire function at all now, and the information about
116 * this mod clock is guessed from the IR mod clock above. The existence of
117 * this mod clock is proven by BSP clock header, and the dividers are verified
118 * by contents in the 1-wire related chapter of the User Manual.
119 */
120
121static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
122 r_mod0_default_parents, 0x1e0,
123 0, 5, /* M */
124 8, 2, /* P */
125 24, 1, /* mux */
126 BIT(31), /* gate */
127 0);
128
129static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
130 &ar100_clk.common,
131 &r_apb1_clk.common,
132 &r_apb2_clk.common,
133 &r_apb1_timer_clk.common,
134 &r_apb1_twd_clk.common,
135 &r_apb1_pwm_clk.common,
136 &r_apb2_uart_clk.common,
137 &r_apb2_i2c_clk.common,
138 &r_apb2_rsb_clk.common,
139 &r_apb1_ir_clk.common,
140 &r_apb1_w1_clk.common,
141 &r_apb1_rtc_clk.common,
142 &ir_clk.common,
143 &w1_clk.common,
144};
145
146static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
147 .hws = {
148 [CLK_AR100] = &ar100_clk.common.hw,
149 [CLK_R_AHB] = &r_ahb_clk.hw,
150 [CLK_R_APB1] = &r_apb1_clk.common.hw,
151 [CLK_R_APB2] = &r_apb2_clk.common.hw,
152 [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
153 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
154 [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
155 [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
156 [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
157 [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
158 [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
159 [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
160 [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
161 [CLK_IR] = &ir_clk.common.hw,
162 [CLK_W1] = &w1_clk.common.hw,
163 },
164 .num = CLK_NUMBER,
165};
166
167static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
168 .hws = {
169 [CLK_R_AHB] = &r_ahb_clk.hw,
170 [CLK_R_APB1] = &r_apb1_clk.common.hw,
171 [CLK_R_APB2] = &r_apb2_clk.common.hw,
172 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
173 [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
174 [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
175 [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
176 [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
177 [CLK_IR] = &ir_clk.common.hw,
178 },
179 .num = CLK_NUMBER,
180};
181
182static const struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
183 [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
184 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
185 [RST_R_APB1_PWM] = { 0x13c, BIT(16) },
186 [RST_R_APB2_UART] = { 0x18c, BIT(16) },
187 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
188 [RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
189 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
190 [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
191};
192
193static const struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
194 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
195 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
196 [RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
197 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
198};
199
200static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
201 .ccu_clks = sun50i_h6_r_ccu_clks,
202 .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
203
204 .hw_clks = &sun50i_h6_r_hw_clks,
205
206 .resets = sun50i_h6_r_ccu_resets,
207 .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
208};
209
210static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
211 .ccu_clks = sun50i_h6_r_ccu_clks,
212 .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
213
214 .hw_clks = &sun50i_h616_r_hw_clks,
215
216 .resets = sun50i_h616_r_ccu_resets,
217 .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
218};
219
220static int sun50i_h6_r_ccu_probe(struct platform_device *pdev)
221{
222 const struct sunxi_ccu_desc *desc;
223 void __iomem *reg;
224
225 desc = of_device_get_match_data(&pdev->dev);
226 if (!desc)
227 return -EINVAL;
228
229 reg = devm_platform_ioremap_resource(pdev, 0);
230 if (IS_ERR(reg))
231 return PTR_ERR(reg);
232
233 return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
234}
235
236static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
237 {
238 .compatible = "allwinner,sun50i-h6-r-ccu",
239 .data = &sun50i_h6_r_ccu_desc,
240 },
241 {
242 .compatible = "allwinner,sun50i-h616-r-ccu",
243 .data = &sun50i_h616_r_ccu_desc,
244 },
245 { }
246};
247MODULE_DEVICE_TABLE(of, sun50i_h6_r_ccu_ids);
248
249static struct platform_driver sun50i_h6_r_ccu_driver = {
250 .probe = sun50i_h6_r_ccu_probe,
251 .driver = {
252 .name = "sun50i-h6-r-ccu",
253 .suppress_bind_attrs = true,
254 .of_match_table = sun50i_h6_r_ccu_ids,
255 },
256};
257module_platform_driver(sun50i_h6_r_ccu_driver);
258
259MODULE_IMPORT_NS("SUNXI_CCU");
260MODULE_DESCRIPTION("Support for the Allwinner H6 and H616 PRCM CCU");
261MODULE_LICENSE("GPL");