1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4 */
  5
  6#include <linux/clk-provider.h>
  7#include <linux/module.h>
  8#include <linux/platform_device.h>
  9#include <linux/regmap.h>
 10
 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 12
 13#include "common.h"
 14#include "clk-alpha-pll.h"
 15#include "clk-branch.h"
 16#include "clk-pll.h"
 17#include "clk-rcg.h"
 18#include "clk-regmap.h"
 19#include "gdsc.h"
 20
 21#define CX_GMU_CBCR_SLEEP_MASK		0xf
 22#define CX_GMU_CBCR_SLEEP_SHIFT		4
 23#define CX_GMU_CBCR_WAKE_MASK		0xf
 24#define CX_GMU_CBCR_WAKE_SHIFT		8
 25
 26enum {
 27	P_BI_TCXO,
 28	P_GPLL0_OUT_MAIN,
 29	P_GPLL0_OUT_MAIN_DIV,
 30	P_GPU_CC_PLL1_OUT_MAIN,
 31};
 32
 33static const struct alpha_pll_config gpu_cc_pll1_config = {
 34	.l = 0x1a,
 35	.alpha = 0xaab,
 36};
 37
 38static struct clk_alpha_pll gpu_cc_pll1 = {
 39	.offset = 0x100,
 40	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 41	.clkr = {
 42		.hw.init = &(struct clk_init_data){
 43			.name = "gpu_cc_pll1",
 44			.parent_data = &(const struct clk_parent_data){
 45				.fw_name = "bi_tcxo", .name = "bi_tcxo",
 46			},
 47			.num_parents = 1,
 48			.ops = &clk_alpha_pll_fabia_ops,
 49		},
 50	},
 51};
 52
 53static const struct parent_map gpu_cc_parent_map_0[] = {
 54	{ P_BI_TCXO, 0 },
 55	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
 56	{ P_GPLL0_OUT_MAIN, 5 },
 57	{ P_GPLL0_OUT_MAIN_DIV, 6 },
 58};
 59
 60static const struct clk_parent_data gpu_cc_parent_data_0[] = {
 61	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 62	{ .hw = &gpu_cc_pll1.clkr.hw },
 63	{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
 64	{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
 65};
 66
 67static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
 68	F(19200000, P_BI_TCXO, 1, 0, 0),
 69	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
 70	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
 71	{ }
 72};
 73
 74static struct clk_rcg2 gpu_cc_gmu_clk_src = {
 75	.cmd_rcgr = 0x1120,
 76	.mnd_width = 0,
 77	.hid_width = 5,
 78	.parent_map = gpu_cc_parent_map_0,
 79	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
 80	.clkr.hw.init = &(struct clk_init_data){
 81		.name = "gpu_cc_gmu_clk_src",
 82		.parent_data = gpu_cc_parent_data_0,
 83		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
 84		.ops = &clk_rcg2_shared_ops,
 85	},
 86};
 87
 88static struct clk_branch gpu_cc_cx_gmu_clk = {
 89	.halt_reg = 0x1098,
 90	.halt_check = BRANCH_HALT,
 91	.clkr = {
 92		.enable_reg = 0x1098,
 93		.enable_mask = BIT(0),
 94		.hw.init = &(struct clk_init_data){
 95			.name = "gpu_cc_cx_gmu_clk",
 96			.parent_hws = (const struct clk_hw*[]){
 97				&gpu_cc_gmu_clk_src.clkr.hw,
 98			},
 99			.num_parents = 1,
100			.flags = CLK_SET_RATE_PARENT,
101			.ops = &clk_branch2_ops,
102		},
103	},
104};
105
106static struct clk_branch gpu_cc_cxo_clk = {
107	.halt_reg = 0x109c,
108	.halt_check = BRANCH_HALT,
109	.clkr = {
110		.enable_reg = 0x109c,
111		.enable_mask = BIT(0),
112		.hw.init = &(struct clk_init_data){
113			.name = "gpu_cc_cxo_clk",
114			.ops = &clk_branch2_ops,
115		},
116	},
117};
118
119static struct gdsc gpu_cx_gdsc = {
120	.gdscr = 0x106c,
121	.gds_hw_ctrl = 0x1540,
122	.clk_dis_wait_val = 0x8,
123	.pd = {
124		.name = "gpu_cx_gdsc",
125	},
126	.pwrsts = PWRSTS_OFF_ON,
127	.flags = VOTABLE,
128};
129
130static struct gdsc gpu_gx_gdsc = {
131	.gdscr = 0x100c,
132	.clamp_io_ctrl = 0x1508,
133	.pd = {
134		.name = "gpu_gx_gdsc",
135		.power_on = gdsc_gx_do_nothing_enable,
136	},
137	.pwrsts = PWRSTS_OFF_ON,
138	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
139};
140
141static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
142	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
143	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
144	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
145	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
146};
147
148static struct gdsc *gpu_cc_sdm845_gdscs[] = {
149	[GPU_CX_GDSC] = &gpu_cx_gdsc,
150	[GPU_GX_GDSC] = &gpu_gx_gdsc,
151};
152
153static const struct regmap_config gpu_cc_sdm845_regmap_config = {
154	.reg_bits	= 32,
155	.reg_stride	= 4,
156	.val_bits	= 32,
157	.max_register	= 0x8008,
158	.fast_io	= true,
159};
160
161static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
162	.config = &gpu_cc_sdm845_regmap_config,
163	.clks = gpu_cc_sdm845_clocks,
164	.num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
165	.gdscs = gpu_cc_sdm845_gdscs,
166	.num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
167};
168
169static const struct of_device_id gpu_cc_sdm845_match_table[] = {
170	{ .compatible = "qcom,sdm845-gpucc" },
171	{ }
172};
173MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
174
175static int gpu_cc_sdm845_probe(struct platform_device *pdev)
176{
177	struct regmap *regmap;
178	unsigned int value, mask;
179
180	regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
181	if (IS_ERR(regmap))
182		return PTR_ERR(regmap);
183
184	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
185
186	/*
187	 * Configure gpu_cc_cx_gmu_clk with recommended
188	 * wakeup/sleep settings
189	 */
190	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
191	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
192	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
193	regmap_update_bits(regmap, 0x1098, mask, value);
194
195	return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap);
196}
197
198static struct platform_driver gpu_cc_sdm845_driver = {
199	.probe = gpu_cc_sdm845_probe,
200	.driver = {
201		.name = "sdm845-gpucc",
202		.of_match_table = gpu_cc_sdm845_match_table,
203	},
204};
205
206module_platform_driver(gpu_cc_sdm845_driver);
207
208MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
209MODULE_LICENSE("GPL v2");