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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13
14#include <dt-bindings/clock/qcom,gcc-sc7280.h>
15
16#include "clk-alpha-pll.h"
17#include "clk-branch.h"
18#include "clk-rcg.h"
19#include "clk-regmap-divider.h"
20#include "clk-regmap-mux.h"
21#include "clk-regmap-phy-mux.h"
22#include "common.h"
23#include "gdsc.h"
24#include "reset.h"
25
26enum {
27 P_BI_TCXO,
28 P_GCC_GPLL0_OUT_EVEN,
29 P_GCC_GPLL0_OUT_MAIN,
30 P_GCC_GPLL0_OUT_ODD,
31 P_GCC_GPLL10_OUT_MAIN,
32 P_GCC_GPLL4_OUT_MAIN,
33 P_GCC_GPLL9_OUT_MAIN,
34 P_PCIE_0_PIPE_CLK,
35 P_PCIE_1_PIPE_CLK,
36 P_SLEEP_CLK,
37 P_UFS_PHY_RX_SYMBOL_0_CLK,
38 P_UFS_PHY_RX_SYMBOL_1_CLK,
39 P_UFS_PHY_TX_SYMBOL_0_CLK,
40 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
41 P_GCC_MSS_GPLL0_MAIN_DIV_CLK,
42};
43
44static struct clk_alpha_pll gcc_gpll0 = {
45 .offset = 0x0,
46 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
47 .clkr = {
48 .enable_reg = 0x52010,
49 .enable_mask = BIT(0),
50 .hw.init = &(struct clk_init_data){
51 .name = "gcc_gpll0",
52 .parent_data = &(const struct clk_parent_data){
53 .fw_name = "bi_tcxo",
54 },
55 .num_parents = 1,
56 .ops = &clk_alpha_pll_fixed_lucid_ops,
57 },
58 },
59};
60
61static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
62 { 0x1, 2 },
63 { }
64};
65
66static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
67 .offset = 0x0,
68 .post_div_shift = 8,
69 .post_div_table = post_div_table_gcc_gpll0_out_even,
70 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
71 .width = 4,
72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
73 .clkr.hw.init = &(struct clk_init_data){
74 .name = "gcc_gpll0_out_even",
75 .parent_hws = (const struct clk_hw*[]){
76 &gcc_gpll0.clkr.hw,
77 },
78 .num_parents = 1,
79 .ops = &clk_alpha_pll_postdiv_lucid_ops,
80 },
81};
82
83static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
84 { 0x3, 3 },
85 { }
86};
87
88static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
89 .offset = 0x0,
90 .post_div_shift = 12,
91 .post_div_table = post_div_table_gcc_gpll0_out_odd,
92 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
93 .width = 4,
94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
95 .clkr.hw.init = &(struct clk_init_data){
96 .name = "gcc_gpll0_out_odd",
97 .parent_hws = (const struct clk_hw*[]){
98 &gcc_gpll0.clkr.hw,
99 },
100 .num_parents = 1,
101 .ops = &clk_alpha_pll_postdiv_lucid_ops,
102 },
103};
104
105static struct clk_alpha_pll gcc_gpll1 = {
106 .offset = 0x1000,
107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
108 .clkr = {
109 .enable_reg = 0x52010,
110 .enable_mask = BIT(1),
111 .hw.init = &(struct clk_init_data){
112 .name = "gcc_gpll1",
113 .parent_data = &(const struct clk_parent_data){
114 .fw_name = "bi_tcxo",
115 },
116 .num_parents = 1,
117 .ops = &clk_alpha_pll_fixed_lucid_ops,
118 },
119 },
120};
121
122static struct clk_alpha_pll gcc_gpll10 = {
123 .offset = 0x1e000,
124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
125 .clkr = {
126 .enable_reg = 0x52010,
127 .enable_mask = BIT(9),
128 .hw.init = &(struct clk_init_data){
129 .name = "gcc_gpll10",
130 .parent_data = &(const struct clk_parent_data){
131 .fw_name = "bi_tcxo",
132 },
133 .num_parents = 1,
134 .ops = &clk_alpha_pll_fixed_lucid_ops,
135 },
136 },
137};
138
139static struct clk_alpha_pll gcc_gpll4 = {
140 .offset = 0x76000,
141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
142 .clkr = {
143 .enable_reg = 0x52010,
144 .enable_mask = BIT(4),
145 .hw.init = &(struct clk_init_data){
146 .name = "gcc_gpll4",
147 .parent_data = &(const struct clk_parent_data){
148 .fw_name = "bi_tcxo",
149 },
150 .num_parents = 1,
151 .ops = &clk_alpha_pll_fixed_lucid_ops,
152 },
153 },
154};
155
156static struct clk_alpha_pll gcc_gpll9 = {
157 .offset = 0x1c000,
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
159 .clkr = {
160 .enable_reg = 0x52010,
161 .enable_mask = BIT(8),
162 .hw.init = &(struct clk_init_data){
163 .name = "gcc_gpll9",
164 .parent_data = &(const struct clk_parent_data){
165 .fw_name = "bi_tcxo",
166 },
167 .num_parents = 1,
168 .ops = &clk_alpha_pll_fixed_lucid_ops,
169 },
170 },
171};
172
173static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
174 .halt_check = BRANCH_HALT_DELAY,
175 .clkr = {
176 .enable_reg = 0x52000,
177 .enable_mask = BIT(17),
178 .hw.init = &(struct clk_init_data){
179 .name = "gcc_mss_gpll0_main_div_clk_src",
180 .parent_hws = (const struct clk_hw*[]){
181 &gcc_gpll0_out_even.clkr.hw,
182 },
183 .num_parents = 1,
184 .flags = CLK_SET_RATE_PARENT,
185 .ops = &clk_branch2_ops,
186 },
187 },
188};
189
190static const struct parent_map gcc_parent_map_0[] = {
191 { P_BI_TCXO, 0 },
192 { P_GCC_GPLL0_OUT_MAIN, 1 },
193 { P_GCC_GPLL0_OUT_EVEN, 6 },
194};
195
196static const struct clk_parent_data gcc_parent_data_0[] = {
197 { .fw_name = "bi_tcxo" },
198 { .hw = &gcc_gpll0.clkr.hw },
199 { .hw = &gcc_gpll0_out_even.clkr.hw },
200};
201
202static const struct parent_map gcc_parent_map_1[] = {
203 { P_BI_TCXO, 0 },
204 { P_GCC_GPLL0_OUT_MAIN, 1 },
205 { P_GCC_GPLL0_OUT_ODD, 3 },
206 { P_GCC_GPLL0_OUT_EVEN, 6 },
207};
208
209static const struct clk_parent_data gcc_parent_data_1[] = {
210 { .fw_name = "bi_tcxo" },
211 { .hw = &gcc_gpll0.clkr.hw },
212 { .hw = &gcc_gpll0_out_odd.clkr.hw },
213 { .hw = &gcc_gpll0_out_even.clkr.hw },
214};
215
216static const struct parent_map gcc_parent_map_2[] = {
217 { P_BI_TCXO, 0 },
218 { P_SLEEP_CLK, 5 },
219};
220
221static const struct clk_parent_data gcc_parent_data_2[] = {
222 { .fw_name = "bi_tcxo" },
223 { .fw_name = "sleep_clk" },
224};
225
226static const struct parent_map gcc_parent_map_3[] = {
227 { P_BI_TCXO, 0 },
228};
229
230static const struct clk_parent_data gcc_parent_data_3[] = {
231 { .fw_name = "bi_tcxo" },
232};
233
234static const struct parent_map gcc_parent_map_4[] = {
235 { P_BI_TCXO, 0 },
236 { P_GCC_GPLL0_OUT_MAIN, 1 },
237 { P_GCC_GPLL0_OUT_ODD, 3 },
238 { P_SLEEP_CLK, 5 },
239 { P_GCC_GPLL0_OUT_EVEN, 6 },
240};
241
242static const struct clk_parent_data gcc_parent_data_4[] = {
243 { .fw_name = "bi_tcxo" },
244 { .hw = &gcc_gpll0.clkr.hw },
245 { .hw = &gcc_gpll0_out_odd.clkr.hw },
246 { .fw_name = "sleep_clk" },
247 { .hw = &gcc_gpll0_out_even.clkr.hw },
248};
249
250static const struct parent_map gcc_parent_map_5[] = {
251 { P_BI_TCXO, 0 },
252 { P_GCC_GPLL0_OUT_EVEN, 6 },
253};
254
255static const struct clk_parent_data gcc_parent_data_5[] = {
256 { .fw_name = "bi_tcxo" },
257 { .hw = &gcc_gpll0_out_even.clkr.hw },
258};
259
260static const struct parent_map gcc_parent_map_8[] = {
261 { P_BI_TCXO, 0 },
262 { P_GCC_GPLL0_OUT_MAIN, 1 },
263 { P_GCC_GPLL0_OUT_ODD, 3 },
264 { P_GCC_GPLL10_OUT_MAIN, 5 },
265 { P_GCC_GPLL0_OUT_EVEN, 6 },
266};
267
268static const struct clk_parent_data gcc_parent_data_8[] = {
269 { .fw_name = "bi_tcxo" },
270 { .hw = &gcc_gpll0.clkr.hw },
271 { .hw = &gcc_gpll0_out_odd.clkr.hw },
272 { .hw = &gcc_gpll10.clkr.hw },
273 { .hw = &gcc_gpll0_out_even.clkr.hw },
274};
275
276static const struct parent_map gcc_parent_map_9[] = {
277 { P_BI_TCXO, 0 },
278 { P_GCC_GPLL0_OUT_MAIN, 1 },
279 { P_GCC_GPLL9_OUT_MAIN, 2 },
280 { P_GCC_GPLL0_OUT_ODD, 3 },
281 { P_GCC_GPLL4_OUT_MAIN, 5 },
282 { P_GCC_GPLL0_OUT_EVEN, 6 },
283};
284
285static const struct clk_parent_data gcc_parent_data_9[] = {
286 { .fw_name = "bi_tcxo" },
287 { .hw = &gcc_gpll0.clkr.hw },
288 { .hw = &gcc_gpll9.clkr.hw },
289 { .hw = &gcc_gpll0_out_odd.clkr.hw },
290 { .hw = &gcc_gpll4.clkr.hw },
291 { .hw = &gcc_gpll0_out_even.clkr.hw },
292};
293
294static const struct parent_map gcc_parent_map_10[] = {
295 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
296 { P_BI_TCXO, 2 },
297};
298
299static const struct clk_parent_data gcc_parent_data_10[] = {
300 { .fw_name = "ufs_phy_rx_symbol_0_clk" },
301 { .fw_name = "bi_tcxo" },
302};
303
304static const struct parent_map gcc_parent_map_11[] = {
305 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
306 { P_BI_TCXO, 2 },
307};
308
309static const struct clk_parent_data gcc_parent_data_11[] = {
310 { .fw_name = "ufs_phy_rx_symbol_1_clk" },
311 { .fw_name = "bi_tcxo" },
312};
313
314static const struct parent_map gcc_parent_map_12[] = {
315 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
316 { P_BI_TCXO, 2 },
317};
318
319static const struct clk_parent_data gcc_parent_data_12[] = {
320 { .fw_name = "ufs_phy_tx_symbol_0_clk" },
321 { .fw_name = "bi_tcxo" },
322};
323
324static const struct parent_map gcc_parent_map_13[] = {
325 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
326 { P_BI_TCXO, 2 },
327};
328
329static const struct clk_parent_data gcc_parent_data_13[] = {
330 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
331 { .fw_name = "bi_tcxo" },
332};
333
334static const struct parent_map gcc_parent_map_14[] = {
335 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
336 { P_BI_TCXO, 2 },
337};
338
339static const struct clk_parent_data gcc_parent_data_14[] = {
340 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
341 { .fw_name = "bi_tcxo" },
342};
343
344static const struct parent_map gcc_parent_map_15[] = {
345 { P_BI_TCXO, 0 },
346 { P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 },
347};
348
349static const struct clk_parent_data gcc_parent_data_15[] = {
350 { .fw_name = "bi_tcxo" },
351 { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
352};
353
354static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
355 .reg = 0x6b054,
356 .clkr = {
357 .hw.init = &(struct clk_init_data){
358 .name = "gcc_pcie_0_pipe_clk_src",
359 .parent_data = &(const struct clk_parent_data){
360 .fw_name = "pcie_0_pipe_clk",
361 .name = "pcie_0_pipe_clk",
362 },
363 .num_parents = 1,
364 .ops = &clk_regmap_phy_mux_ops,
365 },
366 },
367};
368
369static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
370 .reg = 0x8d054,
371 .clkr = {
372 .hw.init = &(struct clk_init_data){
373 .name = "gcc_pcie_1_pipe_clk_src",
374 .parent_data = &(const struct clk_parent_data){
375 .fw_name = "pcie_1_pipe_clk",
376 .name = "pcie_1_pipe_clk",
377 },
378 .num_parents = 1,
379 .ops = &clk_regmap_phy_mux_ops,
380 },
381 },
382};
383
384static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
385 .reg = 0x77058,
386 .shift = 0,
387 .width = 2,
388 .parent_map = gcc_parent_map_10,
389 .clkr = {
390 .hw.init = &(struct clk_init_data){
391 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
392 .parent_data = gcc_parent_data_10,
393 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
394 .ops = &clk_regmap_mux_closest_ops,
395 },
396 },
397};
398
399static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
400 .reg = 0x770c8,
401 .shift = 0,
402 .width = 2,
403 .parent_map = gcc_parent_map_11,
404 .clkr = {
405 .hw.init = &(struct clk_init_data){
406 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
407 .parent_data = gcc_parent_data_11,
408 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
409 .ops = &clk_regmap_mux_closest_ops,
410 },
411 },
412};
413
414static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
415 .reg = 0x77048,
416 .shift = 0,
417 .width = 2,
418 .parent_map = gcc_parent_map_12,
419 .clkr = {
420 .hw.init = &(struct clk_init_data){
421 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
422 .parent_data = gcc_parent_data_12,
423 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
424 .ops = &clk_regmap_mux_closest_ops,
425 },
426 },
427};
428
429static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
430 .reg = 0xf060,
431 .shift = 0,
432 .width = 2,
433 .parent_map = gcc_parent_map_13,
434 .clkr = {
435 .hw.init = &(struct clk_init_data){
436 .name = "gcc_usb3_prim_phy_pipe_clk_src",
437 .parent_data = gcc_parent_data_13,
438 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
439 .ops = &clk_regmap_mux_closest_ops,
440 },
441 },
442};
443
444static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
445 .reg = 0x9e060,
446 .shift = 0,
447 .width = 2,
448 .parent_map = gcc_parent_map_14,
449 .clkr = {
450 .hw.init = &(struct clk_init_data){
451 .name = "gcc_usb3_sec_phy_pipe_clk_src",
452 .parent_data = gcc_parent_data_14,
453 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
454 .ops = &clk_regmap_mux_closest_ops,
455 },
456 },
457};
458
459static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
460 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
461 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
462 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
463 { }
464};
465
466static struct clk_rcg2 gcc_gp1_clk_src = {
467 .cmd_rcgr = 0x64004,
468 .mnd_width = 16,
469 .hid_width = 5,
470 .parent_map = gcc_parent_map_4,
471 .freq_tbl = ftbl_gcc_gp1_clk_src,
472 .clkr.hw.init = &(struct clk_init_data){
473 .name = "gcc_gp1_clk_src",
474 .parent_data = gcc_parent_data_4,
475 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
476 .ops = &clk_rcg2_ops,
477 },
478};
479
480static struct clk_rcg2 gcc_gp2_clk_src = {
481 .cmd_rcgr = 0x65004,
482 .mnd_width = 16,
483 .hid_width = 5,
484 .parent_map = gcc_parent_map_4,
485 .freq_tbl = ftbl_gcc_gp1_clk_src,
486 .clkr.hw.init = &(struct clk_init_data){
487 .name = "gcc_gp2_clk_src",
488 .parent_data = gcc_parent_data_4,
489 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
490 .ops = &clk_rcg2_ops,
491 },
492};
493
494static struct clk_rcg2 gcc_gp3_clk_src = {
495 .cmd_rcgr = 0x66004,
496 .mnd_width = 16,
497 .hid_width = 5,
498 .parent_map = gcc_parent_map_4,
499 .freq_tbl = ftbl_gcc_gp1_clk_src,
500 .clkr.hw.init = &(struct clk_init_data){
501 .name = "gcc_gp3_clk_src",
502 .parent_data = gcc_parent_data_4,
503 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
504 .ops = &clk_rcg2_ops,
505 },
506};
507
508static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
509 F(9600000, P_BI_TCXO, 2, 0, 0),
510 F(19200000, P_BI_TCXO, 1, 0, 0),
511 { }
512};
513
514static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
515 .cmd_rcgr = 0x6b058,
516 .mnd_width = 16,
517 .hid_width = 5,
518 .parent_map = gcc_parent_map_2,
519 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "gcc_pcie_0_aux_clk_src",
522 .parent_data = gcc_parent_data_2,
523 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
524 .ops = &clk_rcg2_ops,
525 },
526};
527
528static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
529 F(19200000, P_BI_TCXO, 1, 0, 0),
530 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
531 { }
532};
533
534static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
535 .cmd_rcgr = 0x6b03c,
536 .mnd_width = 0,
537 .hid_width = 5,
538 .parent_map = gcc_parent_map_0,
539 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
540 .clkr.hw.init = &(struct clk_init_data){
541 .name = "gcc_pcie_0_phy_rchng_clk_src",
542 .parent_data = gcc_parent_data_0,
543 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
544 .ops = &clk_rcg2_ops,
545 },
546};
547
548static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
549 .cmd_rcgr = 0x8d058,
550 .mnd_width = 16,
551 .hid_width = 5,
552 .parent_map = gcc_parent_map_2,
553 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
554 .clkr.hw.init = &(struct clk_init_data){
555 .name = "gcc_pcie_1_aux_clk_src",
556 .parent_data = gcc_parent_data_2,
557 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
558 .ops = &clk_rcg2_ops,
559 },
560};
561
562static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
563 .cmd_rcgr = 0x8d03c,
564 .mnd_width = 0,
565 .hid_width = 5,
566 .parent_map = gcc_parent_map_0,
567 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
568 .clkr.hw.init = &(struct clk_init_data){
569 .name = "gcc_pcie_1_phy_rchng_clk_src",
570 .parent_data = gcc_parent_data_0,
571 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
572 .flags = CLK_SET_RATE_PARENT,
573 .ops = &clk_rcg2_ops,
574 },
575};
576
577static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
578 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
579 { }
580};
581
582static struct clk_rcg2 gcc_pdm2_clk_src = {
583 .cmd_rcgr = 0x33010,
584 .mnd_width = 0,
585 .hid_width = 5,
586 .parent_map = gcc_parent_map_0,
587 .freq_tbl = ftbl_gcc_pdm2_clk_src,
588 .clkr.hw.init = &(struct clk_init_data){
589 .name = "gcc_pdm2_clk_src",
590 .parent_data = gcc_parent_data_0,
591 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
592 .flags = CLK_SET_RATE_PARENT,
593 .ops = &clk_rcg2_ops,
594 },
595};
596
597static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
598 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
599 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
600 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
601 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
602 { }
603};
604
605static struct clk_rcg2 gcc_qspi_core_clk_src = {
606 .cmd_rcgr = 0x4b00c,
607 .mnd_width = 0,
608 .hid_width = 5,
609 .parent_map = gcc_parent_map_0,
610 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "gcc_qspi_core_clk_src",
613 .parent_data = gcc_parent_data_0,
614 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
615 .ops = &clk_rcg2_floor_ops,
616 },
617};
618
619static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
620 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
621 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
622 F(19200000, P_BI_TCXO, 1, 0, 0),
623 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
624 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
625 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
626 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
627 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
628 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
629 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
630 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
631 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
632 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
633 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
634 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
635 { }
636};
637
638static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
639 .name = "gcc_qupv3_wrap0_s0_clk_src",
640 .parent_data = gcc_parent_data_0,
641 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
642 .ops = &clk_rcg2_ops,
643};
644
645static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
646 .cmd_rcgr = 0x17010,
647 .mnd_width = 16,
648 .hid_width = 5,
649 .parent_map = gcc_parent_map_0,
650 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
651 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
652};
653
654static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
655 .name = "gcc_qupv3_wrap0_s1_clk_src",
656 .parent_data = gcc_parent_data_0,
657 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
658 .ops = &clk_rcg2_ops,
659};
660
661static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
662 .cmd_rcgr = 0x17140,
663 .mnd_width = 16,
664 .hid_width = 5,
665 .parent_map = gcc_parent_map_0,
666 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
667 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
668};
669
670static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
671 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
672 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
673 F(19200000, P_BI_TCXO, 1, 0, 0),
674 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
675 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
676 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
677 F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23),
678 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
679 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
680 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
681 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
682 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
683 { }
684};
685
686static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
687 .name = "gcc_qupv3_wrap0_s2_clk_src",
688 .parent_data = gcc_parent_data_0,
689 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
690 .ops = &clk_rcg2_ops,
691};
692
693static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
694 .cmd_rcgr = 0x17270,
695 .mnd_width = 16,
696 .hid_width = 5,
697 .parent_map = gcc_parent_map_0,
698 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
699 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
700};
701
702static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
703 .name = "gcc_qupv3_wrap0_s3_clk_src",
704 .parent_data = gcc_parent_data_0,
705 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
706 .ops = &clk_rcg2_ops,
707};
708
709static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
710 .cmd_rcgr = 0x173a0,
711 .mnd_width = 16,
712 .hid_width = 5,
713 .parent_map = gcc_parent_map_0,
714 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
715 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
716};
717
718static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
719 .name = "gcc_qupv3_wrap0_s4_clk_src",
720 .parent_data = gcc_parent_data_0,
721 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
722 .ops = &clk_rcg2_ops,
723};
724
725static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
726 .cmd_rcgr = 0x174d0,
727 .mnd_width = 16,
728 .hid_width = 5,
729 .parent_map = gcc_parent_map_0,
730 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
731 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
732};
733
734static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
735 .name = "gcc_qupv3_wrap0_s5_clk_src",
736 .parent_data = gcc_parent_data_0,
737 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
738 .ops = &clk_rcg2_ops,
739};
740
741static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
742 .cmd_rcgr = 0x17600,
743 .mnd_width = 16,
744 .hid_width = 5,
745 .parent_map = gcc_parent_map_0,
746 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
747 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
748};
749
750static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
751 .name = "gcc_qupv3_wrap0_s6_clk_src",
752 .parent_data = gcc_parent_data_0,
753 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
754 .ops = &clk_rcg2_ops,
755};
756
757static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
758 .cmd_rcgr = 0x17730,
759 .mnd_width = 16,
760 .hid_width = 5,
761 .parent_map = gcc_parent_map_0,
762 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
763 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
764};
765
766static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
767 .name = "gcc_qupv3_wrap0_s7_clk_src",
768 .parent_data = gcc_parent_data_0,
769 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
770 .ops = &clk_rcg2_ops,
771};
772
773static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
774 .cmd_rcgr = 0x17860,
775 .mnd_width = 16,
776 .hid_width = 5,
777 .parent_map = gcc_parent_map_0,
778 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
779 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
780};
781
782static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
783 .name = "gcc_qupv3_wrap1_s0_clk_src",
784 .parent_data = gcc_parent_data_0,
785 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
786 .ops = &clk_rcg2_ops,
787};
788
789static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
790 .cmd_rcgr = 0x18010,
791 .mnd_width = 16,
792 .hid_width = 5,
793 .parent_map = gcc_parent_map_0,
794 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
795 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
796};
797
798static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
799 .name = "gcc_qupv3_wrap1_s1_clk_src",
800 .parent_data = gcc_parent_data_0,
801 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
802 .ops = &clk_rcg2_ops,
803};
804
805static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
806 .cmd_rcgr = 0x18140,
807 .mnd_width = 16,
808 .hid_width = 5,
809 .parent_map = gcc_parent_map_0,
810 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
811 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
812};
813
814static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
815 .name = "gcc_qupv3_wrap1_s2_clk_src",
816 .parent_data = gcc_parent_data_0,
817 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
818 .ops = &clk_rcg2_ops,
819};
820
821static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
822 .cmd_rcgr = 0x18270,
823 .mnd_width = 16,
824 .hid_width = 5,
825 .parent_map = gcc_parent_map_0,
826 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
827 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
828};
829
830static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
831 .name = "gcc_qupv3_wrap1_s3_clk_src",
832 .parent_data = gcc_parent_data_0,
833 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
834 .ops = &clk_rcg2_ops,
835};
836
837static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
838 .cmd_rcgr = 0x183a0,
839 .mnd_width = 16,
840 .hid_width = 5,
841 .parent_map = gcc_parent_map_0,
842 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
843 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
844};
845
846static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
847 .name = "gcc_qupv3_wrap1_s4_clk_src",
848 .parent_data = gcc_parent_data_0,
849 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
850 .ops = &clk_rcg2_ops,
851};
852
853static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
854 .cmd_rcgr = 0x184d0,
855 .mnd_width = 16,
856 .hid_width = 5,
857 .parent_map = gcc_parent_map_0,
858 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
859 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
860};
861
862static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
863 .name = "gcc_qupv3_wrap1_s5_clk_src",
864 .parent_data = gcc_parent_data_0,
865 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
866 .ops = &clk_rcg2_ops,
867};
868
869static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
870 .cmd_rcgr = 0x18600,
871 .mnd_width = 16,
872 .hid_width = 5,
873 .parent_map = gcc_parent_map_0,
874 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
875 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
876};
877
878static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
879 .name = "gcc_qupv3_wrap1_s6_clk_src",
880 .parent_data = gcc_parent_data_0,
881 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
882 .ops = &clk_rcg2_ops,
883};
884
885static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
886 .cmd_rcgr = 0x18730,
887 .mnd_width = 16,
888 .hid_width = 5,
889 .parent_map = gcc_parent_map_0,
890 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
891 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
892};
893
894static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
895 .name = "gcc_qupv3_wrap1_s7_clk_src",
896 .parent_data = gcc_parent_data_0,
897 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
898 .ops = &clk_rcg2_ops,
899};
900
901static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
902 .cmd_rcgr = 0x18860,
903 .mnd_width = 16,
904 .hid_width = 5,
905 .parent_map = gcc_parent_map_0,
906 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
907 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
908};
909
910static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
911 F(144000, P_BI_TCXO, 16, 3, 25),
912 F(400000, P_BI_TCXO, 12, 1, 4),
913 F(19200000, P_BI_TCXO, 1, 0, 0),
914 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
915 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
916 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
917 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
918 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
919 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
920 { }
921};
922
923static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
924 .cmd_rcgr = 0x7500c,
925 .mnd_width = 8,
926 .hid_width = 5,
927 .parent_map = gcc_parent_map_8,
928 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
929 .clkr.hw.init = &(struct clk_init_data){
930 .name = "gcc_sdcc1_apps_clk_src",
931 .parent_data = gcc_parent_data_8,
932 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
933 .ops = &clk_rcg2_floor_ops,
934 },
935};
936
937static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
938 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
939 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
940 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
941 { }
942};
943
944static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
945 .cmd_rcgr = 0x7502c,
946 .mnd_width = 0,
947 .hid_width = 5,
948 .parent_map = gcc_parent_map_1,
949 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
950 .clkr.hw.init = &(struct clk_init_data){
951 .name = "gcc_sdcc1_ice_core_clk_src",
952 .parent_data = gcc_parent_data_1,
953 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
954 .ops = &clk_rcg2_floor_ops,
955 },
956};
957
958static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
959 F(400000, P_BI_TCXO, 12, 1, 4),
960 F(19200000, P_BI_TCXO, 1, 0, 0),
961 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
962 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
963 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
964 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
965 { }
966};
967
968static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
969 .cmd_rcgr = 0x1400c,
970 .mnd_width = 8,
971 .hid_width = 5,
972 .parent_map = gcc_parent_map_9,
973 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_sdcc2_apps_clk_src",
976 .parent_data = gcc_parent_data_9,
977 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
978 .flags = CLK_OPS_PARENT_ENABLE,
979 .ops = &clk_rcg2_floor_ops,
980 },
981};
982
983static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
984 F(400000, P_BI_TCXO, 12, 1, 4),
985 F(19200000, P_BI_TCXO, 1, 0, 0),
986 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
987 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
988 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
989 { }
990};
991
992static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
993 .cmd_rcgr = 0x1600c,
994 .mnd_width = 8,
995 .hid_width = 5,
996 .parent_map = gcc_parent_map_1,
997 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
998 .clkr.hw.init = &(struct clk_init_data){
999 .name = "gcc_sdcc4_apps_clk_src",
1000 .parent_data = gcc_parent_data_1,
1001 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1002 .ops = &clk_rcg2_floor_ops,
1003 },
1004};
1005
1006static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1007 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1008 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1009 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1010 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1011 { }
1012};
1013
1014static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1015 .cmd_rcgr = 0x77024,
1016 .mnd_width = 8,
1017 .hid_width = 5,
1018 .parent_map = gcc_parent_map_0,
1019 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "gcc_ufs_phy_axi_clk_src",
1022 .parent_data = gcc_parent_data_0,
1023 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1024 .ops = &clk_rcg2_ops,
1025 },
1026};
1027
1028static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1029 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1030 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1031 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1032 { }
1033};
1034
1035static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1036 .cmd_rcgr = 0x7706c,
1037 .mnd_width = 0,
1038 .hid_width = 5,
1039 .parent_map = gcc_parent_map_0,
1040 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "gcc_ufs_phy_ice_core_clk_src",
1043 .parent_data = gcc_parent_data_0,
1044 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1045 .ops = &clk_rcg2_ops,
1046 },
1047};
1048
1049static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1050 .cmd_rcgr = 0x770a0,
1051 .mnd_width = 0,
1052 .hid_width = 5,
1053 .parent_map = gcc_parent_map_3,
1054 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1055 .clkr.hw.init = &(struct clk_init_data){
1056 .name = "gcc_ufs_phy_phy_aux_clk_src",
1057 .parent_data = gcc_parent_data_3,
1058 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1059 .ops = &clk_rcg2_ops,
1060 },
1061};
1062
1063static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1064 .cmd_rcgr = 0x77084,
1065 .mnd_width = 0,
1066 .hid_width = 5,
1067 .parent_map = gcc_parent_map_0,
1068 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1069 .clkr.hw.init = &(struct clk_init_data){
1070 .name = "gcc_ufs_phy_unipro_core_clk_src",
1071 .parent_data = gcc_parent_data_0,
1072 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1073 .ops = &clk_rcg2_ops,
1074 },
1075};
1076
1077static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1078 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1079 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1080 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1081 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1082 { }
1083};
1084
1085static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1086 .cmd_rcgr = 0xf020,
1087 .mnd_width = 8,
1088 .hid_width = 5,
1089 .parent_map = gcc_parent_map_1,
1090 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1091 .clkr.hw.init = &(struct clk_init_data){
1092 .name = "gcc_usb30_prim_master_clk_src",
1093 .parent_data = gcc_parent_data_1,
1094 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1095 .ops = &clk_rcg2_ops,
1096 },
1097};
1098
1099static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1100 F(19200000, P_BI_TCXO, 1, 0, 0),
1101 { }
1102};
1103
1104static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1105 .cmd_rcgr = 0xf038,
1106 .mnd_width = 0,
1107 .hid_width = 5,
1108 .parent_map = gcc_parent_map_3,
1109 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1112 .parent_data = gcc_parent_data_3,
1113 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1114 .ops = &clk_rcg2_ops,
1115 },
1116};
1117
1118static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
1119 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1120 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1121 { }
1122};
1123
1124static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1125 .cmd_rcgr = 0x9e020,
1126 .mnd_width = 8,
1127 .hid_width = 5,
1128 .parent_map = gcc_parent_map_5,
1129 .freq_tbl = ftbl_gcc_usb30_sec_master_clk_src,
1130 .clkr.hw.init = &(struct clk_init_data){
1131 .name = "gcc_usb30_sec_master_clk_src",
1132 .parent_data = gcc_parent_data_5,
1133 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1134 .ops = &clk_rcg2_ops,
1135 },
1136};
1137
1138static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1139 .cmd_rcgr = 0x9e038,
1140 .mnd_width = 0,
1141 .hid_width = 5,
1142 .parent_map = gcc_parent_map_3,
1143 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1144 .clkr.hw.init = &(struct clk_init_data){
1145 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1146 .parent_data = gcc_parent_data_3,
1147 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1148 .ops = &clk_rcg2_ops,
1149 },
1150};
1151
1152static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1153 .cmd_rcgr = 0xf064,
1154 .mnd_width = 0,
1155 .hid_width = 5,
1156 .parent_map = gcc_parent_map_2,
1157 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1158 .clkr.hw.init = &(struct clk_init_data){
1159 .name = "gcc_usb3_prim_phy_aux_clk_src",
1160 .parent_data = gcc_parent_data_2,
1161 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1162 .ops = &clk_rcg2_ops,
1163 },
1164};
1165
1166static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1167 .cmd_rcgr = 0x9e064,
1168 .mnd_width = 0,
1169 .hid_width = 5,
1170 .parent_map = gcc_parent_map_2,
1171 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1172 .clkr.hw.init = &(struct clk_init_data){
1173 .name = "gcc_usb3_sec_phy_aux_clk_src",
1174 .parent_data = gcc_parent_data_2,
1175 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1176 .ops = &clk_rcg2_ops,
1177 },
1178};
1179
1180static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
1181 F(4800000, P_BI_TCXO, 4, 0, 0),
1182 F(19200000, P_BI_TCXO, 1, 0, 0),
1183 { }
1184};
1185
1186static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
1187 .cmd_rcgr = 0x3d02c,
1188 .mnd_width = 0,
1189 .hid_width = 5,
1190 .parent_map = gcc_parent_map_3,
1191 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
1192 .clkr.hw.init = &(struct clk_init_data){
1193 .name = "gcc_sec_ctrl_clk_src",
1194 .parent_data = gcc_parent_data_3,
1195 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1196 .ops = &clk_rcg2_ops,
1197 },
1198};
1199
1200static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1201 .reg = 0xf050,
1202 .shift = 0,
1203 .width = 4,
1204 .clkr.hw.init = &(struct clk_init_data) {
1205 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1206 .parent_hws = (const struct clk_hw*[]){
1207 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1208 },
1209 .num_parents = 1,
1210 .flags = CLK_SET_RATE_PARENT,
1211 .ops = &clk_regmap_div_ro_ops,
1212 },
1213};
1214
1215static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1216 .reg = 0x9e050,
1217 .shift = 0,
1218 .width = 4,
1219 .clkr.hw.init = &(struct clk_init_data) {
1220 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1221 .parent_hws = (const struct clk_hw*[]){
1222 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1223 },
1224 .num_parents = 1,
1225 .flags = CLK_SET_RATE_PARENT,
1226 .ops = &clk_regmap_div_ro_ops,
1227 },
1228};
1229
1230static struct clk_branch gcc_pcie_clkref_en = {
1231 .halt_reg = 0x8c004,
1232 .halt_check = BRANCH_HALT,
1233 .clkr = {
1234 .enable_reg = 0x8c004,
1235 .enable_mask = BIT(0),
1236 .hw.init = &(struct clk_init_data){
1237 .name = "gcc_pcie_clkref_en",
1238 .ops = &clk_branch2_ops,
1239 },
1240 },
1241};
1242
1243static struct clk_branch gcc_edp_clkref_en = {
1244 .halt_reg = 0x8c008,
1245 .halt_check = BRANCH_HALT,
1246 .clkr = {
1247 .enable_reg = 0x8c008,
1248 .enable_mask = BIT(0),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "gcc_edp_clkref_en",
1251 .ops = &clk_branch2_ops,
1252 },
1253 },
1254};
1255
1256static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1257 .halt_reg = 0x6b080,
1258 .halt_check = BRANCH_HALT_SKIP,
1259 .hwcg_reg = 0x6b080,
1260 .hwcg_bit = 1,
1261 .clkr = {
1262 .enable_reg = 0x52000,
1263 .enable_mask = BIT(12),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "gcc_aggre_noc_pcie_0_axi_clk",
1266 .ops = &clk_branch2_ops,
1267 },
1268 },
1269};
1270
1271static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1272 .halt_reg = 0x8d084,
1273 .halt_check = BRANCH_HALT_SKIP,
1274 .hwcg_reg = 0x8d084,
1275 .hwcg_bit = 1,
1276 .clkr = {
1277 .enable_reg = 0x52000,
1278 .enable_mask = BIT(11),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_aggre_noc_pcie_1_axi_clk",
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284};
1285
1286static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1287 .halt_reg = 0x90010,
1288 .halt_check = BRANCH_HALT_VOTED,
1289 .hwcg_reg = 0x90010,
1290 .hwcg_bit = 1,
1291 .clkr = {
1292 .enable_reg = 0x52000,
1293 .enable_mask = BIT(18),
1294 .hw.init = &(struct clk_init_data){
1295 .name = "gcc_aggre_noc_pcie_tbu_clk",
1296 .ops = &clk_branch2_ops,
1297 },
1298 },
1299};
1300
1301static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = {
1302 .halt_reg = 0x8d088,
1303 .halt_check = BRANCH_HALT_VOTED,
1304 .hwcg_reg = 0x8d088,
1305 .hwcg_bit = 1,
1306 .clkr = {
1307 .enable_reg = 0x52008,
1308 .enable_mask = BIT(28),
1309 .hw.init = &(struct clk_init_data){
1310 .name = "gcc_aggre_noc_pcie_center_sf_axi_clk",
1311 .ops = &clk_branch2_ops,
1312 },
1313 },
1314};
1315
1316static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1317 .halt_reg = 0x770cc,
1318 .halt_check = BRANCH_HALT_VOTED,
1319 .hwcg_reg = 0x770cc,
1320 .hwcg_bit = 1,
1321 .clkr = {
1322 .enable_reg = 0x770cc,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_aggre_ufs_phy_axi_clk",
1326 .parent_hws = (const struct clk_hw*[]){
1327 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1328 },
1329 .num_parents = 1,
1330 .flags = CLK_SET_RATE_PARENT,
1331 .ops = &clk_branch2_ops,
1332 },
1333 },
1334};
1335
1336static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1337 .halt_reg = 0xf080,
1338 .halt_check = BRANCH_HALT_VOTED,
1339 .hwcg_reg = 0xf080,
1340 .hwcg_bit = 1,
1341 .clkr = {
1342 .enable_reg = 0xf080,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "gcc_aggre_usb3_prim_axi_clk",
1346 .parent_hws = (const struct clk_hw*[]){
1347 &gcc_usb30_prim_master_clk_src.clkr.hw,
1348 },
1349 .num_parents = 1,
1350 .flags = CLK_SET_RATE_PARENT,
1351 .ops = &clk_branch2_ops,
1352 },
1353 },
1354};
1355
1356static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1357 .halt_reg = 0x9e080,
1358 .halt_check = BRANCH_HALT_VOTED,
1359 .hwcg_reg = 0x9e080,
1360 .hwcg_bit = 1,
1361 .clkr = {
1362 .enable_reg = 0x9e080,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_aggre_usb3_sec_axi_clk",
1366 .parent_hws = (const struct clk_hw*[]){
1367 &gcc_usb30_sec_master_clk_src.clkr.hw,
1368 },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374};
1375
1376static struct clk_branch gcc_camera_hf_axi_clk = {
1377 .halt_reg = 0x26010,
1378 .halt_check = BRANCH_HALT_SKIP,
1379 .hwcg_reg = 0x26010,
1380 .hwcg_bit = 1,
1381 .clkr = {
1382 .enable_reg = 0x26010,
1383 .enable_mask = BIT(0),
1384 .hw.init = &(struct clk_init_data){
1385 .name = "gcc_camera_hf_axi_clk",
1386 .ops = &clk_branch2_ops,
1387 },
1388 },
1389};
1390
1391static struct clk_branch gcc_camera_sf_axi_clk = {
1392 .halt_reg = 0x2601c,
1393 .halt_check = BRANCH_HALT_SKIP,
1394 .hwcg_reg = 0x2601c,
1395 .hwcg_bit = 1,
1396 .clkr = {
1397 .enable_reg = 0x2601c,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "gcc_camera_sf_axi_clk",
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404};
1405
1406static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1407 .halt_reg = 0xf07c,
1408 .halt_check = BRANCH_HALT_VOTED,
1409 .hwcg_reg = 0xf07c,
1410 .hwcg_bit = 1,
1411 .clkr = {
1412 .enable_reg = 0xf07c,
1413 .enable_mask = BIT(0),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1416 .parent_hws = (const struct clk_hw*[]){
1417 &gcc_usb30_prim_master_clk_src.clkr.hw,
1418 },
1419 .num_parents = 1,
1420 .flags = CLK_SET_RATE_PARENT,
1421 .ops = &clk_branch2_ops,
1422 },
1423 },
1424};
1425
1426static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1427 .halt_reg = 0x9e07c,
1428 .halt_check = BRANCH_HALT_VOTED,
1429 .hwcg_reg = 0x9e07c,
1430 .hwcg_bit = 1,
1431 .clkr = {
1432 .enable_reg = 0x9e07c,
1433 .enable_mask = BIT(0),
1434 .hw.init = &(struct clk_init_data){
1435 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1436 .parent_hws = (const struct clk_hw*[]){
1437 &gcc_usb30_sec_master_clk_src.clkr.hw,
1438 },
1439 .num_parents = 1,
1440 .flags = CLK_SET_RATE_PARENT,
1441 .ops = &clk_branch2_ops,
1442 },
1443 },
1444};
1445
1446static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1447 .halt_reg = 0x71154,
1448 .halt_check = BRANCH_HALT_SKIP,
1449 .hwcg_reg = 0x71154,
1450 .hwcg_bit = 1,
1451 .clkr = {
1452 .enable_reg = 0x71154,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_ddrss_gpu_axi_clk",
1456 .ops = &clk_branch2_aon_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_ddrss_pcie_sf_clk = {
1462 .halt_reg = 0x8d080,
1463 .halt_check = BRANCH_HALT_SKIP,
1464 .hwcg_reg = 0x8d080,
1465 .hwcg_bit = 1,
1466 .clkr = {
1467 .enable_reg = 0x52000,
1468 .enable_mask = BIT(19),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "gcc_ddrss_pcie_sf_clk",
1471 .ops = &clk_branch2_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch gcc_disp_gpll0_clk_src = {
1477 .halt_check = BRANCH_HALT_DELAY,
1478 .clkr = {
1479 .enable_reg = 0x52000,
1480 .enable_mask = BIT(7),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "gcc_disp_gpll0_clk_src",
1483 .parent_hws = (const struct clk_hw*[]){
1484 &gcc_gpll0.clkr.hw,
1485 },
1486 .num_parents = 1,
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1489 },
1490 },
1491};
1492
1493static struct clk_branch gcc_disp_hf_axi_clk = {
1494 .halt_reg = 0x2700c,
1495 .halt_check = BRANCH_HALT_SKIP,
1496 .hwcg_reg = 0x2700c,
1497 .hwcg_bit = 1,
1498 .clkr = {
1499 .enable_reg = 0x2700c,
1500 .enable_mask = BIT(0),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "gcc_disp_hf_axi_clk",
1503 .ops = &clk_branch2_ops,
1504 },
1505 },
1506};
1507
1508static struct clk_branch gcc_disp_sf_axi_clk = {
1509 .halt_reg = 0x27014,
1510 .halt_check = BRANCH_HALT_SKIP,
1511 .hwcg_reg = 0x27014,
1512 .hwcg_bit = 1,
1513 .clkr = {
1514 .enable_reg = 0x27014,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_disp_sf_axi_clk",
1518 .ops = &clk_branch2_ops,
1519 },
1520 },
1521};
1522
1523static struct clk_branch gcc_gp1_clk = {
1524 .halt_reg = 0x64000,
1525 .halt_check = BRANCH_HALT,
1526 .clkr = {
1527 .enable_reg = 0x64000,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_gp1_clk",
1531 .parent_hws = (const struct clk_hw*[]){
1532 &gcc_gp1_clk_src.clkr.hw,
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539};
1540
1541static struct clk_branch gcc_gp2_clk = {
1542 .halt_reg = 0x65000,
1543 .halt_check = BRANCH_HALT,
1544 .clkr = {
1545 .enable_reg = 0x65000,
1546 .enable_mask = BIT(0),
1547 .hw.init = &(struct clk_init_data){
1548 .name = "gcc_gp2_clk",
1549 .parent_hws = (const struct clk_hw*[]){
1550 &gcc_gp2_clk_src.clkr.hw,
1551 },
1552 .num_parents = 1,
1553 .flags = CLK_SET_RATE_PARENT,
1554 .ops = &clk_branch2_ops,
1555 },
1556 },
1557};
1558
1559static struct clk_branch gcc_gp3_clk = {
1560 .halt_reg = 0x66000,
1561 .halt_check = BRANCH_HALT,
1562 .clkr = {
1563 .enable_reg = 0x66000,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "gcc_gp3_clk",
1567 .parent_hws = (const struct clk_hw*[]){
1568 &gcc_gp3_clk_src.clkr.hw,
1569 },
1570 .num_parents = 1,
1571 .flags = CLK_SET_RATE_PARENT,
1572 .ops = &clk_branch2_ops,
1573 },
1574 },
1575};
1576
1577static struct clk_branch gcc_gpu_gpll0_clk_src = {
1578 .halt_check = BRANCH_HALT_DELAY,
1579 .clkr = {
1580 .enable_reg = 0x52000,
1581 .enable_mask = BIT(15),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "gcc_gpu_gpll0_clk_src",
1584 .parent_hws = (const struct clk_hw*[]){
1585 &gcc_gpll0.clkr.hw,
1586 },
1587 .num_parents = 1,
1588 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_branch2_ops,
1590 },
1591 },
1592};
1593
1594static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1595 .halt_check = BRANCH_HALT_DELAY,
1596 .clkr = {
1597 .enable_reg = 0x52000,
1598 .enable_mask = BIT(16),
1599 .hw.init = &(struct clk_init_data){
1600 .name = "gcc_gpu_gpll0_div_clk_src",
1601 .parent_hws = (const struct clk_hw*[]){
1602 &gcc_gpll0_out_even.clkr.hw,
1603 },
1604 .num_parents = 1,
1605 .flags = CLK_SET_RATE_PARENT,
1606 .ops = &clk_branch2_ops,
1607 },
1608 },
1609};
1610
1611static struct clk_branch gcc_gpu_iref_en = {
1612 .halt_reg = 0x8c014,
1613 .halt_check = BRANCH_HALT,
1614 .clkr = {
1615 .enable_reg = 0x8c014,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "gcc_gpu_iref_en",
1619 .ops = &clk_branch2_ops,
1620 },
1621 },
1622};
1623
1624static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1625 .halt_reg = 0x7100c,
1626 .halt_check = BRANCH_HALT_VOTED,
1627 .hwcg_reg = 0x7100c,
1628 .hwcg_bit = 1,
1629 .clkr = {
1630 .enable_reg = 0x7100c,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "gcc_gpu_memnoc_gfx_clk",
1634 .ops = &clk_branch2_aon_ops,
1635 },
1636 },
1637};
1638
1639static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1640 .halt_reg = 0x71018,
1641 .halt_check = BRANCH_HALT,
1642 .clkr = {
1643 .enable_reg = 0x71018,
1644 .enable_mask = BIT(0),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1647 .ops = &clk_branch2_aon_ops,
1648 },
1649 },
1650};
1651
1652static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1653 .halt_reg = 0x6b038,
1654 .halt_check = BRANCH_HALT_VOTED,
1655 .clkr = {
1656 .enable_reg = 0x52000,
1657 .enable_mask = BIT(22),
1658 .hw.init = &(struct clk_init_data){
1659 .name = "gcc_pcie0_phy_rchng_clk",
1660 .parent_hws = (const struct clk_hw*[]){
1661 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1662 },
1663 .num_parents = 1,
1664 .flags = CLK_SET_RATE_PARENT,
1665 .ops = &clk_branch2_ops,
1666 },
1667 },
1668};
1669
1670static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1671 .halt_reg = 0x8d038,
1672 .halt_check = BRANCH_HALT_VOTED,
1673 .clkr = {
1674 .enable_reg = 0x52000,
1675 .enable_mask = BIT(23),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "gcc_pcie1_phy_rchng_clk",
1678 .parent_hws = (const struct clk_hw*[]){
1679 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1680 },
1681 .num_parents = 1,
1682 .flags = CLK_SET_RATE_PARENT,
1683 .ops = &clk_branch2_ops,
1684 },
1685 },
1686};
1687
1688static struct clk_branch gcc_pcie_0_aux_clk = {
1689 .halt_reg = 0x6b028,
1690 .halt_check = BRANCH_HALT_VOTED,
1691 .clkr = {
1692 .enable_reg = 0x52008,
1693 .enable_mask = BIT(3),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "gcc_pcie_0_aux_clk",
1696 .parent_hws = (const struct clk_hw*[]){
1697 &gcc_pcie_0_aux_clk_src.clkr.hw,
1698 },
1699 .num_parents = 1,
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1702 },
1703 },
1704};
1705
1706static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1707 .halt_reg = 0x6b024,
1708 .halt_check = BRANCH_HALT_VOTED,
1709 .hwcg_reg = 0x6b024,
1710 .hwcg_bit = 1,
1711 .clkr = {
1712 .enable_reg = 0x52008,
1713 .enable_mask = BIT(2),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "gcc_pcie_0_cfg_ahb_clk",
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719};
1720
1721static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1722 .halt_reg = 0x6b01c,
1723 .halt_check = BRANCH_HALT_SKIP,
1724 .clkr = {
1725 .enable_reg = 0x52008,
1726 .enable_mask = BIT(1),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gcc_pcie_0_mstr_axi_clk",
1729 .ops = &clk_branch2_ops,
1730 },
1731 },
1732};
1733
1734static struct clk_branch gcc_pcie_0_pipe_clk = {
1735 .halt_reg = 0x6b030,
1736 .halt_check = BRANCH_HALT_SKIP,
1737 .clkr = {
1738 .enable_reg = 0x52008,
1739 .enable_mask = BIT(4),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gcc_pcie_0_pipe_clk",
1742 .parent_hws = (const struct clk_hw*[]){
1743 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1744 },
1745 .num_parents = 1,
1746 .flags = CLK_SET_RATE_PARENT,
1747 .ops = &clk_branch2_ops,
1748 },
1749 },
1750};
1751
1752static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1753 .halt_reg = 0x6b014,
1754 .halt_check = BRANCH_HALT_VOTED,
1755 .clkr = {
1756 .enable_reg = 0x52008,
1757 .enable_mask = BIT(0),
1758 .hw.init = &(struct clk_init_data){
1759 .name = "gcc_pcie_0_slv_axi_clk",
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763};
1764
1765static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1766 .halt_reg = 0x6b010,
1767 .halt_check = BRANCH_HALT_VOTED,
1768 .clkr = {
1769 .enable_reg = 0x52008,
1770 .enable_mask = BIT(5),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776};
1777
1778static struct clk_branch gcc_pcie_1_aux_clk = {
1779 .halt_reg = 0x8d028,
1780 .halt_check = BRANCH_HALT_VOTED,
1781 .clkr = {
1782 .enable_reg = 0x52000,
1783 .enable_mask = BIT(29),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "gcc_pcie_1_aux_clk",
1786 .parent_hws = (const struct clk_hw*[]){
1787 &gcc_pcie_1_aux_clk_src.clkr.hw,
1788 },
1789 .num_parents = 1,
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794};
1795
1796static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1797 .halt_reg = 0x8d024,
1798 .halt_check = BRANCH_HALT_VOTED,
1799 .hwcg_reg = 0x8d024,
1800 .hwcg_bit = 1,
1801 .clkr = {
1802 .enable_reg = 0x52000,
1803 .enable_mask = BIT(28),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "gcc_pcie_1_cfg_ahb_clk",
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809};
1810
1811static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1812 .halt_reg = 0x8d01c,
1813 .halt_check = BRANCH_HALT_SKIP,
1814 .clkr = {
1815 .enable_reg = 0x52000,
1816 .enable_mask = BIT(27),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_pcie_1_mstr_axi_clk",
1819 .ops = &clk_branch2_ops,
1820 },
1821 },
1822};
1823
1824static struct clk_branch gcc_pcie_1_pipe_clk = {
1825 .halt_reg = 0x8d030,
1826 .halt_check = BRANCH_HALT_SKIP,
1827 .clkr = {
1828 .enable_reg = 0x52000,
1829 .enable_mask = BIT(30),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "gcc_pcie_1_pipe_clk",
1832 .parent_hws = (const struct clk_hw*[]){
1833 &gcc_pcie_1_pipe_clk_src.clkr.hw,
1834 },
1835 .num_parents = 1,
1836 .flags = CLK_SET_RATE_PARENT,
1837 .ops = &clk_branch2_ops,
1838 },
1839 },
1840};
1841
1842static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1843 .halt_reg = 0x8d014,
1844 .halt_check = BRANCH_HALT_VOTED,
1845 .clkr = {
1846 .enable_reg = 0x52000,
1847 .enable_mask = BIT(26),
1848 .hw.init = &(struct clk_init_data){
1849 .name = "gcc_pcie_1_slv_axi_clk",
1850 .ops = &clk_branch2_ops,
1851 },
1852 },
1853};
1854
1855static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1856 .halt_reg = 0x8d010,
1857 .halt_check = BRANCH_HALT_VOTED,
1858 .clkr = {
1859 .enable_reg = 0x52000,
1860 .enable_mask = BIT(25),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1863 .ops = &clk_branch2_ops,
1864 },
1865 },
1866};
1867
1868static struct clk_branch gcc_pcie_throttle_core_clk = {
1869 .halt_reg = 0x90018,
1870 .halt_check = BRANCH_HALT_SKIP,
1871 .hwcg_reg = 0x90018,
1872 .hwcg_bit = 1,
1873 .clkr = {
1874 .enable_reg = 0x52000,
1875 .enable_mask = BIT(20),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "gcc_pcie_throttle_core_clk",
1878 .ops = &clk_branch2_ops,
1879 },
1880 },
1881};
1882
1883static struct clk_branch gcc_pdm2_clk = {
1884 .halt_reg = 0x3300c,
1885 .halt_check = BRANCH_HALT,
1886 .clkr = {
1887 .enable_reg = 0x3300c,
1888 .enable_mask = BIT(0),
1889 .hw.init = &(struct clk_init_data){
1890 .name = "gcc_pdm2_clk",
1891 .parent_hws = (const struct clk_hw*[]){
1892 &gcc_pdm2_clk_src.clkr.hw,
1893 },
1894 .num_parents = 1,
1895 .flags = CLK_SET_RATE_PARENT,
1896 .ops = &clk_branch2_ops,
1897 },
1898 },
1899};
1900
1901static struct clk_branch gcc_pdm_ahb_clk = {
1902 .halt_reg = 0x33004,
1903 .halt_check = BRANCH_HALT_VOTED,
1904 .hwcg_reg = 0x33004,
1905 .hwcg_bit = 1,
1906 .clkr = {
1907 .enable_reg = 0x33004,
1908 .enable_mask = BIT(0),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "gcc_pdm_ahb_clk",
1911 .ops = &clk_branch2_ops,
1912 },
1913 },
1914};
1915
1916static struct clk_branch gcc_pdm_xo4_clk = {
1917 .halt_reg = 0x33008,
1918 .halt_check = BRANCH_HALT,
1919 .clkr = {
1920 .enable_reg = 0x33008,
1921 .enable_mask = BIT(0),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "gcc_pdm_xo4_clk",
1924 .ops = &clk_branch2_ops,
1925 },
1926 },
1927};
1928
1929static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1930 .halt_reg = 0x26008,
1931 .halt_check = BRANCH_HALT_VOTED,
1932 .hwcg_reg = 0x26008,
1933 .hwcg_bit = 1,
1934 .clkr = {
1935 .enable_reg = 0x26008,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "gcc_qmip_camera_nrt_ahb_clk",
1939 .ops = &clk_branch2_ops,
1940 },
1941 },
1942};
1943
1944static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1945 .halt_reg = 0x2600c,
1946 .halt_check = BRANCH_HALT_VOTED,
1947 .hwcg_reg = 0x2600c,
1948 .hwcg_bit = 1,
1949 .clkr = {
1950 .enable_reg = 0x2600c,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "gcc_qmip_camera_rt_ahb_clk",
1954 .ops = &clk_branch2_ops,
1955 },
1956 },
1957};
1958
1959static struct clk_branch gcc_qmip_disp_ahb_clk = {
1960 .halt_reg = 0x27008,
1961 .halt_check = BRANCH_HALT_VOTED,
1962 .clkr = {
1963 .enable_reg = 0x27008,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_qmip_disp_ahb_clk",
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970};
1971
1972static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1973 .halt_reg = 0x28008,
1974 .halt_check = BRANCH_HALT_VOTED,
1975 .hwcg_reg = 0x28008,
1976 .hwcg_bit = 1,
1977 .clkr = {
1978 .enable_reg = 0x28008,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "gcc_qmip_video_vcodec_ahb_clk",
1982 .ops = &clk_branch2_ops,
1983 },
1984 },
1985};
1986
1987static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1988 .halt_reg = 0x4b004,
1989 .halt_check = BRANCH_HALT,
1990 .hwcg_reg = 0x4b004,
1991 .hwcg_bit = 1,
1992 .clkr = {
1993 .enable_reg = 0x4b004,
1994 .enable_mask = BIT(0),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1997 .ops = &clk_branch2_ops,
1998 },
1999 },
2000};
2001
2002static struct clk_branch gcc_qspi_core_clk = {
2003 .halt_reg = 0x4b008,
2004 .halt_check = BRANCH_HALT,
2005 .clkr = {
2006 .enable_reg = 0x4b008,
2007 .enable_mask = BIT(0),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "gcc_qspi_core_clk",
2010 .parent_hws = (const struct clk_hw*[]){
2011 &gcc_qspi_core_clk_src.clkr.hw,
2012 },
2013 .num_parents = 1,
2014 .flags = CLK_SET_RATE_PARENT,
2015 .ops = &clk_branch2_ops,
2016 },
2017 },
2018};
2019
2020static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2021 .halt_reg = 0x23008,
2022 .halt_check = BRANCH_HALT_VOTED,
2023 .clkr = {
2024 .enable_reg = 0x52008,
2025 .enable_mask = BIT(9),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gcc_qupv3_wrap0_core_2x_clk",
2028 .ops = &clk_branch2_ops,
2029 },
2030 },
2031};
2032
2033static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2034 .halt_reg = 0x23000,
2035 .halt_check = BRANCH_HALT_VOTED,
2036 .clkr = {
2037 .enable_reg = 0x52008,
2038 .enable_mask = BIT(8),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gcc_qupv3_wrap0_core_clk",
2041 .ops = &clk_branch2_ops,
2042 },
2043 },
2044};
2045
2046static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2047 .halt_reg = 0x1700c,
2048 .halt_check = BRANCH_HALT_VOTED,
2049 .clkr = {
2050 .enable_reg = 0x52008,
2051 .enable_mask = BIT(10),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gcc_qupv3_wrap0_s0_clk",
2054 .parent_hws = (const struct clk_hw*[]){
2055 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2056 },
2057 .num_parents = 1,
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2065 .halt_reg = 0x1713c,
2066 .halt_check = BRANCH_HALT_VOTED,
2067 .clkr = {
2068 .enable_reg = 0x52008,
2069 .enable_mask = BIT(11),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "gcc_qupv3_wrap0_s1_clk",
2072 .parent_hws = (const struct clk_hw*[]){
2073 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2074 },
2075 .num_parents = 1,
2076 .flags = CLK_SET_RATE_PARENT,
2077 .ops = &clk_branch2_ops,
2078 },
2079 },
2080};
2081
2082static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2083 .halt_reg = 0x1726c,
2084 .halt_check = BRANCH_HALT_VOTED,
2085 .clkr = {
2086 .enable_reg = 0x52008,
2087 .enable_mask = BIT(12),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "gcc_qupv3_wrap0_s2_clk",
2090 .parent_hws = (const struct clk_hw*[]){
2091 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2092 },
2093 .num_parents = 1,
2094 .flags = CLK_SET_RATE_PARENT,
2095 .ops = &clk_branch2_ops,
2096 },
2097 },
2098};
2099
2100static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2101 .halt_reg = 0x1739c,
2102 .halt_check = BRANCH_HALT_VOTED,
2103 .clkr = {
2104 .enable_reg = 0x52008,
2105 .enable_mask = BIT(13),
2106 .hw.init = &(struct clk_init_data){
2107 .name = "gcc_qupv3_wrap0_s3_clk",
2108 .parent_hws = (const struct clk_hw*[]){
2109 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2110 },
2111 .num_parents = 1,
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2114 },
2115 },
2116};
2117
2118static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2119 .halt_reg = 0x174cc,
2120 .halt_check = BRANCH_HALT_VOTED,
2121 .clkr = {
2122 .enable_reg = 0x52008,
2123 .enable_mask = BIT(14),
2124 .hw.init = &(struct clk_init_data){
2125 .name = "gcc_qupv3_wrap0_s4_clk",
2126 .parent_hws = (const struct clk_hw*[]){
2127 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2128 },
2129 .num_parents = 1,
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2132 },
2133 },
2134};
2135
2136static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2137 .halt_reg = 0x175fc,
2138 .halt_check = BRANCH_HALT_VOTED,
2139 .clkr = {
2140 .enable_reg = 0x52008,
2141 .enable_mask = BIT(15),
2142 .hw.init = &(struct clk_init_data){
2143 .name = "gcc_qupv3_wrap0_s5_clk",
2144 .parent_hws = (const struct clk_hw*[]){
2145 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2146 },
2147 .num_parents = 1,
2148 .flags = CLK_SET_RATE_PARENT,
2149 .ops = &clk_branch2_ops,
2150 },
2151 },
2152};
2153
2154static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2155 .halt_reg = 0x1772c,
2156 .halt_check = BRANCH_HALT_VOTED,
2157 .clkr = {
2158 .enable_reg = 0x52008,
2159 .enable_mask = BIT(16),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "gcc_qupv3_wrap0_s6_clk",
2162 .parent_hws = (const struct clk_hw*[]){
2163 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2164 },
2165 .num_parents = 1,
2166 .flags = CLK_SET_RATE_PARENT,
2167 .ops = &clk_branch2_ops,
2168 },
2169 },
2170};
2171
2172static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2173 .halt_reg = 0x1785c,
2174 .halt_check = BRANCH_HALT_VOTED,
2175 .clkr = {
2176 .enable_reg = 0x52008,
2177 .enable_mask = BIT(17),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_qupv3_wrap0_s7_clk",
2180 .parent_hws = (const struct clk_hw*[]){
2181 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2182 },
2183 .num_parents = 1,
2184 .flags = CLK_SET_RATE_PARENT,
2185 .ops = &clk_branch2_ops,
2186 },
2187 },
2188};
2189
2190static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2191 .halt_reg = 0x23140,
2192 .halt_check = BRANCH_HALT_VOTED,
2193 .clkr = {
2194 .enable_reg = 0x52008,
2195 .enable_mask = BIT(18),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "gcc_qupv3_wrap1_core_2x_clk",
2198 .ops = &clk_branch2_ops,
2199 },
2200 },
2201};
2202
2203static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2204 .halt_reg = 0x23138,
2205 .halt_check = BRANCH_HALT_VOTED,
2206 .clkr = {
2207 .enable_reg = 0x52008,
2208 .enable_mask = BIT(19),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_qupv3_wrap1_core_clk",
2211 .ops = &clk_branch2_ops,
2212 },
2213 },
2214};
2215
2216static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2217 .halt_reg = 0x1800c,
2218 .halt_check = BRANCH_HALT_VOTED,
2219 .clkr = {
2220 .enable_reg = 0x52008,
2221 .enable_mask = BIT(22),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "gcc_qupv3_wrap1_s0_clk",
2224 .parent_hws = (const struct clk_hw*[]){
2225 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2226 },
2227 .num_parents = 1,
2228 .flags = CLK_SET_RATE_PARENT,
2229 .ops = &clk_branch2_ops,
2230 },
2231 },
2232};
2233
2234static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2235 .halt_reg = 0x1813c,
2236 .halt_check = BRANCH_HALT_VOTED,
2237 .clkr = {
2238 .enable_reg = 0x52008,
2239 .enable_mask = BIT(23),
2240 .hw.init = &(struct clk_init_data){
2241 .name = "gcc_qupv3_wrap1_s1_clk",
2242 .parent_hws = (const struct clk_hw*[]){
2243 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2244 },
2245 .num_parents = 1,
2246 .flags = CLK_SET_RATE_PARENT,
2247 .ops = &clk_branch2_ops,
2248 },
2249 },
2250};
2251
2252static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2253 .halt_reg = 0x1826c,
2254 .halt_check = BRANCH_HALT_VOTED,
2255 .clkr = {
2256 .enable_reg = 0x52008,
2257 .enable_mask = BIT(24),
2258 .hw.init = &(struct clk_init_data){
2259 .name = "gcc_qupv3_wrap1_s2_clk",
2260 .parent_hws = (const struct clk_hw*[]){
2261 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2262 },
2263 .num_parents = 1,
2264 .flags = CLK_SET_RATE_PARENT,
2265 .ops = &clk_branch2_ops,
2266 },
2267 },
2268};
2269
2270static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2271 .halt_reg = 0x1839c,
2272 .halt_check = BRANCH_HALT_VOTED,
2273 .clkr = {
2274 .enable_reg = 0x52008,
2275 .enable_mask = BIT(25),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "gcc_qupv3_wrap1_s3_clk",
2278 .parent_hws = (const struct clk_hw*[]){
2279 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2280 },
2281 .num_parents = 1,
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286};
2287
2288static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2289 .halt_reg = 0x184cc,
2290 .halt_check = BRANCH_HALT_VOTED,
2291 .clkr = {
2292 .enable_reg = 0x52008,
2293 .enable_mask = BIT(26),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_qupv3_wrap1_s4_clk",
2296 .parent_hws = (const struct clk_hw*[]){
2297 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2298 },
2299 .num_parents = 1,
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2302 },
2303 },
2304};
2305
2306static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2307 .halt_reg = 0x185fc,
2308 .halt_check = BRANCH_HALT_VOTED,
2309 .clkr = {
2310 .enable_reg = 0x52008,
2311 .enable_mask = BIT(27),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "gcc_qupv3_wrap1_s5_clk",
2314 .parent_hws = (const struct clk_hw*[]){
2315 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2316 },
2317 .num_parents = 1,
2318 .flags = CLK_SET_RATE_PARENT,
2319 .ops = &clk_branch2_ops,
2320 },
2321 },
2322};
2323
2324static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2325 .halt_reg = 0x1872c,
2326 .halt_check = BRANCH_HALT_VOTED,
2327 .clkr = {
2328 .enable_reg = 0x52000,
2329 .enable_mask = BIT(13),
2330 .hw.init = &(struct clk_init_data){
2331 .name = "gcc_qupv3_wrap1_s6_clk",
2332 .parent_hws = (const struct clk_hw*[]){
2333 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2334 },
2335 .num_parents = 1,
2336 .flags = CLK_SET_RATE_PARENT,
2337 .ops = &clk_branch2_ops,
2338 },
2339 },
2340};
2341
2342static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2343 .halt_reg = 0x1885c,
2344 .halt_check = BRANCH_HALT_VOTED,
2345 .clkr = {
2346 .enable_reg = 0x52000,
2347 .enable_mask = BIT(14),
2348 .hw.init = &(struct clk_init_data){
2349 .name = "gcc_qupv3_wrap1_s7_clk",
2350 .parent_hws = (const struct clk_hw*[]){
2351 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2352 },
2353 .num_parents = 1,
2354 .flags = CLK_SET_RATE_PARENT,
2355 .ops = &clk_branch2_ops,
2356 },
2357 },
2358};
2359
2360static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2361 .halt_reg = 0x17004,
2362 .halt_check = BRANCH_HALT_VOTED,
2363 .hwcg_reg = 0x17004,
2364 .hwcg_bit = 1,
2365 .clkr = {
2366 .enable_reg = 0x52008,
2367 .enable_mask = BIT(6),
2368 .hw.init = &(struct clk_init_data){
2369 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2370 .ops = &clk_branch2_ops,
2371 },
2372 },
2373};
2374
2375static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2376 .halt_reg = 0x17008,
2377 .halt_check = BRANCH_HALT_VOTED,
2378 .hwcg_reg = 0x17008,
2379 .hwcg_bit = 1,
2380 .clkr = {
2381 .enable_reg = 0x52008,
2382 .enable_mask = BIT(7),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2385 .ops = &clk_branch2_ops,
2386 },
2387 },
2388};
2389
2390static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2391 .halt_reg = 0x18004,
2392 .halt_check = BRANCH_HALT_VOTED,
2393 .hwcg_reg = 0x18004,
2394 .hwcg_bit = 1,
2395 .clkr = {
2396 .enable_reg = 0x52008,
2397 .enable_mask = BIT(20),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2400 .ops = &clk_branch2_ops,
2401 },
2402 },
2403};
2404
2405static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2406 .halt_reg = 0x18008,
2407 .halt_check = BRANCH_HALT_VOTED,
2408 .hwcg_reg = 0x18008,
2409 .hwcg_bit = 1,
2410 .clkr = {
2411 .enable_reg = 0x52008,
2412 .enable_mask = BIT(21),
2413 .hw.init = &(struct clk_init_data){
2414 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2415 .ops = &clk_branch2_ops,
2416 },
2417 },
2418};
2419
2420static struct clk_branch gcc_sdcc1_ahb_clk = {
2421 .halt_reg = 0x75004,
2422 .halt_check = BRANCH_HALT,
2423 .clkr = {
2424 .enable_reg = 0x75004,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_sdcc1_ahb_clk",
2428 .ops = &clk_branch2_ops,
2429 },
2430 },
2431};
2432
2433static struct clk_branch gcc_sdcc1_apps_clk = {
2434 .halt_reg = 0x75008,
2435 .halt_check = BRANCH_HALT,
2436 .clkr = {
2437 .enable_reg = 0x75008,
2438 .enable_mask = BIT(0),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "gcc_sdcc1_apps_clk",
2441 .parent_hws = (const struct clk_hw*[]){
2442 &gcc_sdcc1_apps_clk_src.clkr.hw,
2443 },
2444 .num_parents = 1,
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2447 },
2448 },
2449};
2450
2451static struct clk_branch gcc_sdcc1_ice_core_clk = {
2452 .halt_reg = 0x75024,
2453 .halt_check = BRANCH_HALT_VOTED,
2454 .hwcg_reg = 0x75024,
2455 .hwcg_bit = 1,
2456 .clkr = {
2457 .enable_reg = 0x75024,
2458 .enable_mask = BIT(0),
2459 .hw.init = &(struct clk_init_data){
2460 .name = "gcc_sdcc1_ice_core_clk",
2461 .parent_hws = (const struct clk_hw*[]){
2462 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2463 },
2464 .num_parents = 1,
2465 .flags = CLK_SET_RATE_PARENT,
2466 .ops = &clk_branch2_ops,
2467 },
2468 },
2469};
2470
2471static struct clk_branch gcc_sdcc2_ahb_clk = {
2472 .halt_reg = 0x14008,
2473 .halt_check = BRANCH_HALT,
2474 .clkr = {
2475 .enable_reg = 0x14008,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_sdcc2_ahb_clk",
2479 .ops = &clk_branch2_ops,
2480 },
2481 },
2482};
2483
2484static struct clk_branch gcc_sdcc2_apps_clk = {
2485 .halt_reg = 0x14004,
2486 .halt_check = BRANCH_HALT,
2487 .clkr = {
2488 .enable_reg = 0x14004,
2489 .enable_mask = BIT(0),
2490 .hw.init = &(struct clk_init_data){
2491 .name = "gcc_sdcc2_apps_clk",
2492 .parent_hws = (const struct clk_hw*[]){
2493 &gcc_sdcc2_apps_clk_src.clkr.hw,
2494 },
2495 .num_parents = 1,
2496 .flags = CLK_SET_RATE_PARENT,
2497 .ops = &clk_branch2_ops,
2498 },
2499 },
2500};
2501
2502static struct clk_branch gcc_sdcc4_ahb_clk = {
2503 .halt_reg = 0x16008,
2504 .halt_check = BRANCH_HALT,
2505 .clkr = {
2506 .enable_reg = 0x16008,
2507 .enable_mask = BIT(0),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "gcc_sdcc4_ahb_clk",
2510 .ops = &clk_branch2_ops,
2511 },
2512 },
2513};
2514
2515static struct clk_branch gcc_sdcc4_apps_clk = {
2516 .halt_reg = 0x16004,
2517 .halt_check = BRANCH_HALT,
2518 .clkr = {
2519 .enable_reg = 0x16004,
2520 .enable_mask = BIT(0),
2521 .hw.init = &(struct clk_init_data){
2522 .name = "gcc_sdcc4_apps_clk",
2523 .parent_hws = (const struct clk_hw*[]){
2524 &gcc_sdcc4_apps_clk_src.clkr.hw,
2525 },
2526 .num_parents = 1,
2527 .flags = CLK_SET_RATE_PARENT,
2528 .ops = &clk_branch2_ops,
2529 },
2530 },
2531};
2532
2533static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2534 .halt_reg = 0x9001c,
2535 .halt_check = BRANCH_HALT,
2536 .clkr = {
2537 .enable_reg = 0x9001c,
2538 .enable_mask = BIT(0),
2539 .hw.init = &(struct clk_init_data){
2540 .name = "gcc_throttle_pcie_ahb_clk",
2541 .ops = &clk_branch2_ops,
2542 },
2543 },
2544};
2545
2546static struct clk_branch gcc_titan_nrt_throttle_core_clk = {
2547 .halt_reg = 0x26024,
2548 .halt_check = BRANCH_HALT_SKIP,
2549 .hwcg_reg = 0x26024,
2550 .hwcg_bit = 1,
2551 .clkr = {
2552 .enable_reg = 0x26024,
2553 .enable_mask = BIT(0),
2554 .hw.init = &(struct clk_init_data){
2555 .name = "gcc_titan_nrt_throttle_core_clk",
2556 .ops = &clk_branch2_ops,
2557 },
2558 },
2559};
2560
2561static struct clk_branch gcc_titan_rt_throttle_core_clk = {
2562 .halt_reg = 0x26018,
2563 .halt_check = BRANCH_HALT_SKIP,
2564 .hwcg_reg = 0x26018,
2565 .hwcg_bit = 1,
2566 .clkr = {
2567 .enable_reg = 0x26018,
2568 .enable_mask = BIT(0),
2569 .hw.init = &(struct clk_init_data){
2570 .name = "gcc_titan_rt_throttle_core_clk",
2571 .ops = &clk_branch2_ops,
2572 },
2573 },
2574};
2575
2576static struct clk_branch gcc_ufs_1_clkref_en = {
2577 .halt_reg = 0x8c000,
2578 .halt_check = BRANCH_HALT,
2579 .clkr = {
2580 .enable_reg = 0x8c000,
2581 .enable_mask = BIT(0),
2582 .hw.init = &(struct clk_init_data){
2583 .name = "gcc_ufs_1_clkref_en",
2584 .ops = &clk_branch2_ops,
2585 },
2586 },
2587};
2588
2589static struct clk_branch gcc_ufs_phy_ahb_clk = {
2590 .halt_reg = 0x77018,
2591 .halt_check = BRANCH_HALT_VOTED,
2592 .hwcg_reg = 0x77018,
2593 .hwcg_bit = 1,
2594 .clkr = {
2595 .enable_reg = 0x77018,
2596 .enable_mask = BIT(0),
2597 .hw.init = &(struct clk_init_data){
2598 .name = "gcc_ufs_phy_ahb_clk",
2599 .ops = &clk_branch2_ops,
2600 },
2601 },
2602};
2603
2604static struct clk_branch gcc_ufs_phy_axi_clk = {
2605 .halt_reg = 0x77010,
2606 .halt_check = BRANCH_HALT_VOTED,
2607 .hwcg_reg = 0x77010,
2608 .hwcg_bit = 1,
2609 .clkr = {
2610 .enable_reg = 0x77010,
2611 .enable_mask = BIT(0),
2612 .hw.init = &(struct clk_init_data){
2613 .name = "gcc_ufs_phy_axi_clk",
2614 .parent_hws = (const struct clk_hw*[]){
2615 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2616 },
2617 .num_parents = 1,
2618 .flags = CLK_SET_RATE_PARENT,
2619 .ops = &clk_branch2_ops,
2620 },
2621 },
2622};
2623
2624static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2625 .halt_reg = 0x77064,
2626 .halt_check = BRANCH_HALT_VOTED,
2627 .hwcg_reg = 0x77064,
2628 .hwcg_bit = 1,
2629 .clkr = {
2630 .enable_reg = 0x77064,
2631 .enable_mask = BIT(0),
2632 .hw.init = &(struct clk_init_data){
2633 .name = "gcc_ufs_phy_ice_core_clk",
2634 .parent_hws = (const struct clk_hw*[]){
2635 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2636 },
2637 .num_parents = 1,
2638 .flags = CLK_SET_RATE_PARENT,
2639 .ops = &clk_branch2_ops,
2640 },
2641 },
2642};
2643
2644static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2645 .halt_reg = 0x7709c,
2646 .halt_check = BRANCH_HALT_VOTED,
2647 .hwcg_reg = 0x7709c,
2648 .hwcg_bit = 1,
2649 .clkr = {
2650 .enable_reg = 0x7709c,
2651 .enable_mask = BIT(0),
2652 .hw.init = &(struct clk_init_data){
2653 .name = "gcc_ufs_phy_phy_aux_clk",
2654 .parent_hws = (const struct clk_hw*[]){
2655 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2656 },
2657 .num_parents = 1,
2658 .flags = CLK_SET_RATE_PARENT,
2659 .ops = &clk_branch2_ops,
2660 },
2661 },
2662};
2663
2664static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2665 .halt_reg = 0x77020,
2666 .halt_check = BRANCH_HALT_DELAY,
2667 .clkr = {
2668 .enable_reg = 0x77020,
2669 .enable_mask = BIT(0),
2670 .hw.init = &(struct clk_init_data){
2671 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2672 .parent_hws = (const struct clk_hw*[]){
2673 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2674 },
2675 .num_parents = 1,
2676 .flags = CLK_SET_RATE_PARENT,
2677 .ops = &clk_branch2_ops,
2678 },
2679 },
2680};
2681
2682static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2683 .halt_reg = 0x770b8,
2684 .halt_check = BRANCH_HALT_DELAY,
2685 .clkr = {
2686 .enable_reg = 0x770b8,
2687 .enable_mask = BIT(0),
2688 .hw.init = &(struct clk_init_data){
2689 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2690 .parent_hws = (const struct clk_hw*[]){
2691 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2692 },
2693 .num_parents = 1,
2694 .flags = CLK_SET_RATE_PARENT,
2695 .ops = &clk_branch2_ops,
2696 },
2697 },
2698};
2699
2700static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2701 .halt_reg = 0x7701c,
2702 .halt_check = BRANCH_HALT_DELAY,
2703 .clkr = {
2704 .enable_reg = 0x7701c,
2705 .enable_mask = BIT(0),
2706 .hw.init = &(struct clk_init_data){
2707 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2708 .parent_hws = (const struct clk_hw*[]){
2709 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2710 },
2711 .num_parents = 1,
2712 .flags = CLK_SET_RATE_PARENT,
2713 .ops = &clk_branch2_ops,
2714 },
2715 },
2716};
2717
2718static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2719 .halt_reg = 0x7705c,
2720 .halt_check = BRANCH_HALT_VOTED,
2721 .hwcg_reg = 0x7705c,
2722 .hwcg_bit = 1,
2723 .clkr = {
2724 .enable_reg = 0x7705c,
2725 .enable_mask = BIT(0),
2726 .hw.init = &(struct clk_init_data){
2727 .name = "gcc_ufs_phy_unipro_core_clk",
2728 .parent_hws = (const struct clk_hw*[]){
2729 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2730 },
2731 .num_parents = 1,
2732 .flags = CLK_SET_RATE_PARENT,
2733 .ops = &clk_branch2_ops,
2734 },
2735 },
2736};
2737
2738static struct clk_branch gcc_usb30_prim_master_clk = {
2739 .halt_reg = 0xf010,
2740 .halt_check = BRANCH_HALT,
2741 .clkr = {
2742 .enable_reg = 0xf010,
2743 .enable_mask = BIT(0),
2744 .hw.init = &(struct clk_init_data){
2745 .name = "gcc_usb30_prim_master_clk",
2746 .parent_hws = (const struct clk_hw*[]){
2747 &gcc_usb30_prim_master_clk_src.clkr.hw,
2748 },
2749 .num_parents = 1,
2750 .flags = CLK_SET_RATE_PARENT,
2751 .ops = &clk_branch2_ops,
2752 },
2753 },
2754};
2755
2756static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2757 .halt_reg = 0xf01c,
2758 .halt_check = BRANCH_HALT,
2759 .clkr = {
2760 .enable_reg = 0xf01c,
2761 .enable_mask = BIT(0),
2762 .hw.init = &(struct clk_init_data){
2763 .name = "gcc_usb30_prim_mock_utmi_clk",
2764 .parent_hws = (const struct clk_hw*[]) {
2765 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2766 },
2767 .num_parents = 1,
2768 .flags = CLK_SET_RATE_PARENT,
2769 .ops = &clk_branch2_ops,
2770 },
2771 },
2772};
2773
2774static struct clk_branch gcc_usb30_prim_sleep_clk = {
2775 .halt_reg = 0xf018,
2776 .halt_check = BRANCH_HALT,
2777 .clkr = {
2778 .enable_reg = 0xf018,
2779 .enable_mask = BIT(0),
2780 .hw.init = &(struct clk_init_data){
2781 .name = "gcc_usb30_prim_sleep_clk",
2782 .ops = &clk_branch2_ops,
2783 },
2784 },
2785};
2786
2787static struct clk_branch gcc_usb30_sec_master_clk = {
2788 .halt_reg = 0x9e010,
2789 .halt_check = BRANCH_HALT,
2790 .clkr = {
2791 .enable_reg = 0x9e010,
2792 .enable_mask = BIT(0),
2793 .hw.init = &(struct clk_init_data){
2794 .name = "gcc_usb30_sec_master_clk",
2795 .parent_hws = (const struct clk_hw*[]){
2796 &gcc_usb30_sec_master_clk_src.clkr.hw,
2797 },
2798 .num_parents = 1,
2799 .flags = CLK_SET_RATE_PARENT,
2800 .ops = &clk_branch2_ops,
2801 },
2802 },
2803};
2804
2805static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2806 .halt_reg = 0x9e01c,
2807 .halt_check = BRANCH_HALT,
2808 .clkr = {
2809 .enable_reg = 0x9e01c,
2810 .enable_mask = BIT(0),
2811 .hw.init = &(struct clk_init_data){
2812 .name = "gcc_usb30_sec_mock_utmi_clk",
2813 .parent_hws = (const struct clk_hw*[]) {
2814 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
2815 },
2816 .num_parents = 1,
2817 .flags = CLK_SET_RATE_PARENT,
2818 .ops = &clk_branch2_ops,
2819 },
2820 },
2821};
2822
2823static struct clk_branch gcc_usb30_sec_sleep_clk = {
2824 .halt_reg = 0x9e018,
2825 .halt_check = BRANCH_HALT,
2826 .clkr = {
2827 .enable_reg = 0x9e018,
2828 .enable_mask = BIT(0),
2829 .hw.init = &(struct clk_init_data){
2830 .name = "gcc_usb30_sec_sleep_clk",
2831 .ops = &clk_branch2_ops,
2832 },
2833 },
2834};
2835
2836static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2837 .halt_reg = 0xf054,
2838 .halt_check = BRANCH_HALT,
2839 .clkr = {
2840 .enable_reg = 0xf054,
2841 .enable_mask = BIT(0),
2842 .hw.init = &(struct clk_init_data){
2843 .name = "gcc_usb3_prim_phy_aux_clk",
2844 .parent_hws = (const struct clk_hw*[]){
2845 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2846 },
2847 .num_parents = 1,
2848 .flags = CLK_SET_RATE_PARENT,
2849 .ops = &clk_branch2_ops,
2850 },
2851 },
2852};
2853
2854static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2855 .halt_reg = 0xf058,
2856 .halt_check = BRANCH_HALT,
2857 .clkr = {
2858 .enable_reg = 0xf058,
2859 .enable_mask = BIT(0),
2860 .hw.init = &(struct clk_init_data){
2861 .name = "gcc_usb3_prim_phy_com_aux_clk",
2862 .parent_hws = (const struct clk_hw*[]){
2863 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2864 },
2865 .num_parents = 1,
2866 .flags = CLK_SET_RATE_PARENT,
2867 .ops = &clk_branch2_ops,
2868 },
2869 },
2870};
2871
2872static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2873 .halt_reg = 0xf05c,
2874 .halt_check = BRANCH_HALT_DELAY,
2875 .hwcg_reg = 0xf05c,
2876 .hwcg_bit = 1,
2877 .clkr = {
2878 .enable_reg = 0xf05c,
2879 .enable_mask = BIT(0),
2880 .hw.init = &(struct clk_init_data){
2881 .name = "gcc_usb3_prim_phy_pipe_clk",
2882 .parent_hws = (const struct clk_hw*[]){
2883 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2884 },
2885 .num_parents = 1,
2886 .flags = CLK_SET_RATE_PARENT,
2887 .ops = &clk_branch2_ops,
2888 },
2889 },
2890};
2891
2892static struct clk_branch gcc_cfg_noc_lpass_clk = {
2893 .halt_reg = 0x47020,
2894 .halt_check = BRANCH_HALT,
2895 .clkr = {
2896 .enable_reg = 0x47020,
2897 .enable_mask = BIT(0),
2898 .hw.init = &(struct clk_init_data){
2899 .name = "gcc_cfg_noc_lpass_clk",
2900 .ops = &clk_branch2_aon_ops,
2901 },
2902 },
2903};
2904static struct clk_branch gcc_mss_cfg_ahb_clk = {
2905 .halt_reg = 0x8a000,
2906 .halt_check = BRANCH_HALT,
2907 .clkr = {
2908 .enable_reg = 0x8a000,
2909 .enable_mask = BIT(0),
2910 .hw.init = &(struct clk_init_data){
2911 .name = "gcc_mss_cfg_ahb_clk",
2912 .ops = &clk_branch2_ops,
2913 },
2914 },
2915};
2916
2917static struct clk_branch gcc_mss_offline_axi_clk = {
2918 .halt_reg = 0x8a004,
2919 .halt_check = BRANCH_HALT_DELAY,
2920 .clkr = {
2921 .enable_reg = 0x8a004,
2922 .enable_mask = BIT(0),
2923 .hw.init = &(struct clk_init_data){
2924 .name = "gcc_mss_offline_axi_clk",
2925 .ops = &clk_branch2_ops,
2926 },
2927 },
2928};
2929
2930static struct clk_branch gcc_mss_snoc_axi_clk = {
2931 .halt_reg = 0x8a154,
2932 .halt_check = BRANCH_HALT_DELAY,
2933 .clkr = {
2934 .enable_reg = 0x8a154,
2935 .enable_mask = BIT(0),
2936 .hw.init = &(struct clk_init_data){
2937 .name = "gcc_mss_snoc_axi_clk",
2938 .ops = &clk_branch2_ops,
2939 },
2940 },
2941};
2942
2943static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2944 .halt_reg = 0x8a158,
2945 .halt_check = BRANCH_HALT,
2946 .clkr = {
2947 .enable_reg = 0x8a158,
2948 .enable_mask = BIT(0),
2949 .hw.init = &(struct clk_init_data){
2950 .name = "gcc_mss_q6_memnoc_axi_clk",
2951 .ops = &clk_branch2_ops,
2952 },
2953 },
2954};
2955
2956static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = {
2957 .reg = 0x8a2a4,
2958 .shift = 0,
2959 .width = 1,
2960 .parent_map = gcc_parent_map_15,
2961 .clkr = {
2962 .hw.init = &(struct clk_init_data){
2963 .name = "gcc_mss_q6ss_boot_clk_src",
2964 .parent_data = gcc_parent_data_15,
2965 .num_parents = ARRAY_SIZE(gcc_parent_data_15),
2966 .ops = &clk_regmap_mux_closest_ops,
2967 },
2968 },
2969};
2970
2971static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2972 .halt_reg = 0x9e054,
2973 .halt_check = BRANCH_HALT,
2974 .clkr = {
2975 .enable_reg = 0x9e054,
2976 .enable_mask = BIT(0),
2977 .hw.init = &(struct clk_init_data){
2978 .name = "gcc_usb3_sec_phy_aux_clk",
2979 .parent_hws = (const struct clk_hw*[]){
2980 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2981 },
2982 .num_parents = 1,
2983 .flags = CLK_SET_RATE_PARENT,
2984 .ops = &clk_branch2_ops,
2985 },
2986 },
2987};
2988
2989static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2990 .halt_reg = 0x9e058,
2991 .halt_check = BRANCH_HALT,
2992 .clkr = {
2993 .enable_reg = 0x9e058,
2994 .enable_mask = BIT(0),
2995 .hw.init = &(struct clk_init_data){
2996 .name = "gcc_usb3_sec_phy_com_aux_clk",
2997 .parent_hws = (const struct clk_hw*[]){
2998 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2999 },
3000 .num_parents = 1,
3001 .flags = CLK_SET_RATE_PARENT,
3002 .ops = &clk_branch2_ops,
3003 },
3004 },
3005};
3006
3007static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3008 .halt_reg = 0x9e05c,
3009 .halt_check = BRANCH_HALT_SKIP,
3010 .hwcg_reg = 0x9e05c,
3011 .hwcg_bit = 1,
3012 .clkr = {
3013 .enable_reg = 0x9e05c,
3014 .enable_mask = BIT(0),
3015 .hw.init = &(struct clk_init_data){
3016 .name = "gcc_usb3_sec_phy_pipe_clk",
3017 .parent_hws = (const struct clk_hw*[]){
3018 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3019 },
3020 .num_parents = 1,
3021 .flags = CLK_SET_RATE_PARENT,
3022 .ops = &clk_branch2_ops,
3023 },
3024 },
3025};
3026
3027static struct clk_branch gcc_video_axi0_clk = {
3028 .halt_reg = 0x2800c,
3029 .halt_check = BRANCH_HALT_SKIP,
3030 .hwcg_reg = 0x2800c,
3031 .hwcg_bit = 1,
3032 .clkr = {
3033 .enable_reg = 0x2800c,
3034 .enable_mask = BIT(0),
3035 .hw.init = &(struct clk_init_data){
3036 .name = "gcc_video_axi0_clk",
3037 .ops = &clk_branch2_ops,
3038 },
3039 },
3040};
3041
3042static struct clk_branch gcc_video_mvp_throttle_core_clk = {
3043 .halt_reg = 0x28010,
3044 .halt_check = BRANCH_HALT_SKIP,
3045 .hwcg_reg = 0x28010,
3046 .hwcg_bit = 1,
3047 .clkr = {
3048 .enable_reg = 0x28010,
3049 .enable_mask = BIT(0),
3050 .hw.init = &(struct clk_init_data){
3051 .name = "gcc_video_mvp_throttle_core_clk",
3052 .ops = &clk_branch2_ops,
3053 },
3054 },
3055};
3056
3057static struct clk_branch gcc_wpss_ahb_clk = {
3058 .halt_reg = 0x9d154,
3059 .halt_check = BRANCH_HALT,
3060 .clkr = {
3061 .enable_reg = 0x9d154,
3062 .enable_mask = BIT(0),
3063 .hw.init = &(struct clk_init_data){
3064 .name = "gcc_wpss_ahb_clk",
3065 .ops = &clk_branch2_ops,
3066 },
3067 },
3068};
3069
3070static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = {
3071 .halt_reg = 0x9d158,
3072 .halt_check = BRANCH_HALT,
3073 .clkr = {
3074 .enable_reg = 0x9d158,
3075 .enable_mask = BIT(0),
3076 .hw.init = &(struct clk_init_data){
3077 .name = "gcc_wpss_ahb_bdg_mst_clk",
3078 .ops = &clk_branch2_ops,
3079 },
3080 },
3081};
3082
3083static struct clk_branch gcc_wpss_rscp_clk = {
3084 .halt_reg = 0x9d16c,
3085 .halt_check = BRANCH_HALT,
3086 .clkr = {
3087 .enable_reg = 0x9d16c,
3088 .enable_mask = BIT(0),
3089 .hw.init = &(struct clk_init_data){
3090 .name = "gcc_wpss_rscp_clk",
3091 .ops = &clk_branch2_ops,
3092 },
3093 },
3094};
3095
3096static struct gdsc gcc_pcie_0_gdsc = {
3097 .gdscr = 0x6b004,
3098 .en_rest_wait_val = 0x2,
3099 .en_few_wait_val = 0x2,
3100 .clk_dis_wait_val = 0xf,
3101 .pd = {
3102 .name = "gcc_pcie_0_gdsc",
3103 },
3104 .pwrsts = PWRSTS_OFF_ON,
3105 .flags = VOTABLE,
3106};
3107
3108static struct gdsc gcc_pcie_1_gdsc = {
3109 .gdscr = 0x8d004,
3110 .pd = {
3111 .name = "gcc_pcie_1_gdsc",
3112 },
3113 .pwrsts = PWRSTS_RET_ON,
3114 .flags = VOTABLE,
3115};
3116
3117static struct gdsc gcc_ufs_phy_gdsc = {
3118 .gdscr = 0x77004,
3119 .en_rest_wait_val = 0x2,
3120 .en_few_wait_val = 0x2,
3121 .clk_dis_wait_val = 0xf,
3122 .pd = {
3123 .name = "gcc_ufs_phy_gdsc",
3124 },
3125 .pwrsts = PWRSTS_OFF_ON,
3126 .flags = VOTABLE,
3127};
3128
3129static struct gdsc gcc_usb30_prim_gdsc = {
3130 .gdscr = 0xf004,
3131 .en_rest_wait_val = 0x2,
3132 .en_few_wait_val = 0x2,
3133 .clk_dis_wait_val = 0xf,
3134 .pd = {
3135 .name = "gcc_usb30_prim_gdsc",
3136 },
3137 .pwrsts = PWRSTS_RET_ON,
3138 .flags = VOTABLE,
3139};
3140
3141static struct gdsc gcc_usb30_sec_gdsc = {
3142 .gdscr = 0x9e004,
3143 .pd = {
3144 .name = "gcc_usb30_sec_gdsc",
3145 },
3146 .pwrsts = PWRSTS_RET_ON,
3147 .flags = VOTABLE,
3148};
3149
3150static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3151 .gdscr = 0x7d050,
3152 .pd = {
3153 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3154 },
3155 .pwrsts = PWRSTS_OFF_ON,
3156 .flags = VOTABLE,
3157};
3158
3159static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3160 .gdscr = 0x7d058,
3161 .pd = {
3162 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3163 },
3164 .pwrsts = PWRSTS_OFF_ON,
3165 .flags = VOTABLE,
3166};
3167
3168static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3169 .gdscr = 0x7d054,
3170 .pd = {
3171 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3172 },
3173 .pwrsts = PWRSTS_OFF_ON,
3174 .flags = VOTABLE,
3175};
3176
3177static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3178 .gdscr = 0x7d05c,
3179 .pd = {
3180 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3181 },
3182 .pwrsts = PWRSTS_OFF_ON,
3183 .flags = VOTABLE,
3184};
3185
3186static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3187 .gdscr = 0x7d060,
3188 .pd = {
3189 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3190 },
3191 .pwrsts = PWRSTS_OFF_ON,
3192 .flags = VOTABLE,
3193};
3194
3195static struct clk_regmap *gcc_sc7280_clocks[] = {
3196 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3197 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3198 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3199 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3200 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3201 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3202 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3203 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3204 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3205 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3206 [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
3207 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3208 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3209 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3210 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3211 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3212 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3213 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3214 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3215 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3216 [GCC_GPLL0] = &gcc_gpll0.clkr,
3217 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3218 [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
3219 [GCC_GPLL1] = &gcc_gpll1.clkr,
3220 [GCC_GPLL10] = &gcc_gpll10.clkr,
3221 [GCC_GPLL4] = &gcc_gpll4.clkr,
3222 [GCC_GPLL9] = &gcc_gpll9.clkr,
3223 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3224 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3225 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3226 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3227 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3228 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3229 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3230 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3231 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3232 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3233 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3234 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3235 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3236 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3237 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3238 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3239 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3240 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3241 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3242 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3243 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3244 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3245 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3246 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3247 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3248 [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr,
3249 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3250 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3251 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3252 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3253 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3254 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3255 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3256 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3257 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3258 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3259 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3260 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3261 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3262 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3263 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3264 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3265 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3266 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3267 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3268 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3269 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3270 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3271 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3272 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3273 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3274 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3275 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3276 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3277 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3278 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3279 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3280 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3281 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3282 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3283 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3284 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3285 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3286 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3287 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3288 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3289 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3290 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3291 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3292 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3293 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3294 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3295 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3296 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3297 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3298 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3299 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3300 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3301 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3302 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3303 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3304 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3305 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3306 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3307 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3308 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3309 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3310 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3311 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3312 [GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
3313 &gcc_titan_nrt_throttle_core_clk.clkr,
3314 [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
3315 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3316 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3317 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3318 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3319 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3320 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3321 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3322 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3323 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3324 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =
3325 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3326 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3327 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =
3328 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3329 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3330 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =
3331 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3332 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3333 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3334 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3335 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3336 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3337 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3338 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3339 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3340 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3341 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3342 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3343 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3344 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3345 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3346 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3347 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3348 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
3349 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3350 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3351 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3352 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3353 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3354 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3355 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3356 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3357 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3358 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3359 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3360 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3361 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3362 [GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
3363 &gcc_video_mvp_throttle_core_clk.clkr,
3364 [GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr,
3365 [GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr,
3366 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3367 [GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr,
3368 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3369 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3370 [GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr,
3371 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3372 [GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] =
3373 &gcc_aggre_noc_pcie_center_sf_axi_clk.clkr,
3374 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
3375 [GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
3376 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
3377 [GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr,
3378 [GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr,
3379 [GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr,
3380};
3381
3382static struct gdsc *gcc_sc7280_gdscs[] = {
3383 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3384 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
3385 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3386 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3387 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
3388 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3389 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3390 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3391 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3392 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3393};
3394
3395static const struct qcom_reset_map gcc_sc7280_resets[] = {
3396 [GCC_PCIE_0_BCR] = { 0x6b000 },
3397 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3398 [GCC_PCIE_1_BCR] = { 0x8d000 },
3399 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3400 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3401 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3402 [GCC_SDCC1_BCR] = { 0x75000 },
3403 [GCC_SDCC2_BCR] = { 0x14000 },
3404 [GCC_SDCC4_BCR] = { 0x16000 },
3405 [GCC_UFS_PHY_BCR] = { 0x77000 },
3406 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3407 [GCC_USB30_SEC_BCR] = { 0x9e000 },
3408 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3409 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3410 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3411 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3412};
3413
3414static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3415 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3416 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3417 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3418 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3419 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3420 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3421 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3422 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3423 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3424 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3425 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3426 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3427 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3428 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3429 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3430 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3431};
3432
3433static const struct regmap_config gcc_sc7280_regmap_config = {
3434 .reg_bits = 32,
3435 .reg_stride = 4,
3436 .val_bits = 32,
3437 .max_register = 0x9f128,
3438 .fast_io = true,
3439};
3440
3441static const struct qcom_cc_desc gcc_sc7280_desc = {
3442 .config = &gcc_sc7280_regmap_config,
3443 .clks = gcc_sc7280_clocks,
3444 .num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
3445 .resets = gcc_sc7280_resets,
3446 .num_resets = ARRAY_SIZE(gcc_sc7280_resets),
3447 .gdscs = gcc_sc7280_gdscs,
3448 .num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
3449};
3450
3451static const struct of_device_id gcc_sc7280_match_table[] = {
3452 { .compatible = "qcom,gcc-sc7280" },
3453 { }
3454};
3455MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
3456
3457static int gcc_sc7280_probe(struct platform_device *pdev)
3458{
3459 struct regmap *regmap;
3460 int ret;
3461
3462 regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
3463 if (IS_ERR(regmap))
3464 return PTR_ERR(regmap);
3465
3466 /* Keep some clocks always-on */
3467 qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */
3468 qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */
3469 qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */
3470 qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */
3471 qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */
3472 qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */
3473 qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */
3474 regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
3475
3476 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3477 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3478
3479 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3480 ARRAY_SIZE(gcc_dfs_clocks));
3481 if (ret)
3482 return ret;
3483
3484 return qcom_cc_really_probe(&pdev->dev, &gcc_sc7280_desc, regmap);
3485}
3486
3487static struct platform_driver gcc_sc7280_driver = {
3488 .probe = gcc_sc7280_probe,
3489 .driver = {
3490 .name = "gcc-sc7280",
3491 .of_match_table = gcc_sc7280_match_table,
3492 },
3493};
3494
3495static int __init gcc_sc7280_init(void)
3496{
3497 return platform_driver_register(&gcc_sc7280_driver);
3498}
3499subsys_initcall(gcc_sc7280_init);
3500
3501static void __exit gcc_sc7280_exit(void)
3502{
3503 platform_driver_unregister(&gcc_sc7280_driver);
3504}
3505module_exit(gcc_sc7280_exit);
3506
3507MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
3508MODULE_LICENSE("GPL v2");