1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/module.h>
   8#include <linux/mod_devicetable.h>
   9#include <linux/of.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-pll.h"
  18#include "clk-rcg.h"
  19#include "clk-regmap.h"
  20#include "clk-regmap-divider.h"
  21#include "clk-regmap-mux.h"
  22#include "clk-regmap-phy-mux.h"
  23#include "common.h"
  24#include "gdsc.h"
  25#include "reset.h"
  26
  27enum {
  28	DT_BI_TCXO,
  29	DT_SLEEP_CLK,
  30	DT_PCIE_0_PIPE_CLK,
  31	DT_PCIE_1_PIPE_CLK,
  32	DT_PCIE_PHY_AUX_CLK,
  33	DT_RXC0_REF_CLK,
  34	DT_UFS_PHY_RX_SYMBOL_0_CLK,
  35	DT_UFS_PHY_RX_SYMBOL_1_CLK,
  36	DT_UFS_PHY_TX_SYMBOL_0_CLK,
  37	DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
  38};
  39
  40enum {
  41	P_BI_TCXO,
  42	P_GCC_GPLL0_OUT_EVEN,
  43	P_GCC_GPLL0_OUT_MAIN,
  44	P_GCC_GPLL1_OUT_MAIN,
  45	P_GCC_GPLL4_OUT_MAIN,
  46	P_GCC_GPLL7_OUT_MAIN,
  47	P_GCC_GPLL9_OUT_MAIN,
  48	P_PCIE_0_PIPE_CLK,
  49	P_PCIE_1_PIPE_CLK,
  50	P_PCIE_PHY_AUX_CLK,
  51	P_RXC0_REF_CLK,
  52	P_SLEEP_CLK,
  53	P_UFS_PHY_RX_SYMBOL_0_CLK,
  54	P_UFS_PHY_RX_SYMBOL_1_CLK,
  55	P_UFS_PHY_TX_SYMBOL_0_CLK,
  56	P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
  57};
  58
  59static struct clk_alpha_pll gcc_gpll0 = {
  60	.offset = 0x0,
  61	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  62	.clkr = {
  63		.enable_reg = 0x4b028,
  64		.enable_mask = BIT(0),
  65		.hw.init = &(const struct clk_init_data) {
  66			.name = "gcc_gpll0",
  67			.parent_data = &(const struct clk_parent_data) {
  68				.index = DT_BI_TCXO,
  69			},
  70			.num_parents = 1,
  71			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
  72		},
  73	},
  74};
  75
  76static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  77	{ 0x1, 2 },
  78	{ }
  79};
  80
  81static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  82	.offset = 0x0,
  83	.post_div_shift = 10,
  84	.post_div_table = post_div_table_gcc_gpll0_out_even,
  85	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  86	.width = 4,
  87	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  88	.clkr.hw.init = &(const struct clk_init_data) {
  89		.name = "gcc_gpll0_out_even",
  90		.parent_hws = (const struct clk_hw*[]) {
  91			&gcc_gpll0.clkr.hw,
  92		},
  93		.num_parents = 1,
  94		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
  95	},
  96};
  97
  98static struct clk_alpha_pll gcc_gpll1 = {
  99	.offset = 0x1000,
 100	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 101	.clkr = {
 102		.enable_reg = 0x4b028,
 103		.enable_mask = BIT(1),
 104		.hw.init = &(const struct clk_init_data) {
 105			.name = "gcc_gpll1",
 106			.parent_data = &(const struct clk_parent_data) {
 107				.index = DT_BI_TCXO,
 108			},
 109			.num_parents = 1,
 110			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 111		},
 112	},
 113};
 114
 115static struct clk_alpha_pll gcc_gpll4 = {
 116	.offset = 0x4000,
 117	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 118	.clkr = {
 119		.enable_reg = 0x4b028,
 120		.enable_mask = BIT(4),
 121		.hw.init = &(const struct clk_init_data) {
 122			.name = "gcc_gpll4",
 123			.parent_data = &(const struct clk_parent_data) {
 124				.index = DT_BI_TCXO,
 125			},
 126			.num_parents = 1,
 127			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 128		},
 129	},
 130};
 131
 132static struct clk_alpha_pll gcc_gpll7 = {
 133	.offset = 0x7000,
 134	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 135	.clkr = {
 136		.enable_reg = 0x4b028,
 137		.enable_mask = BIT(7),
 138		.hw.init = &(const struct clk_init_data) {
 139			.name = "gcc_gpll7",
 140			.parent_data = &(const struct clk_parent_data) {
 141				.index = DT_BI_TCXO,
 142			},
 143			.num_parents = 1,
 144			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 145		},
 146	},
 147};
 148
 149static struct clk_alpha_pll gcc_gpll9 = {
 150	.offset = 0x9000,
 151	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 152	.clkr = {
 153		.enable_reg = 0x4b028,
 154		.enable_mask = BIT(9),
 155		.hw.init = &(const struct clk_init_data) {
 156			.name = "gcc_gpll9",
 157			.parent_data = &(const struct clk_parent_data) {
 158				.index = DT_BI_TCXO,
 159			},
 160			.num_parents = 1,
 161			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 162		},
 163	},
 164};
 165
 166static const struct parent_map gcc_parent_map_0[] = {
 167	{ P_BI_TCXO, 0 },
 168	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 169	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 170};
 171
 172static const struct clk_parent_data gcc_parent_data_0[] = {
 173	{ .index = DT_BI_TCXO },
 174	{ .hw = &gcc_gpll0.clkr.hw },
 175	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 176};
 177
 178static const struct parent_map gcc_parent_map_1[] = {
 179	{ P_BI_TCXO, 0 },
 180	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 181	{ P_SLEEP_CLK, 5 },
 182	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 183};
 184
 185static const struct clk_parent_data gcc_parent_data_1[] = {
 186	{ .index = DT_BI_TCXO },
 187	{ .hw = &gcc_gpll0.clkr.hw },
 188	{ .index = DT_SLEEP_CLK },
 189	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 190};
 191
 192static const struct parent_map gcc_parent_map_2[] = {
 193	{ P_BI_TCXO, 0 },
 194	{ P_SLEEP_CLK, 5 },
 195};
 196
 197static const struct clk_parent_data gcc_parent_data_2[] = {
 198	{ .index = DT_BI_TCXO },
 199	{ .index = DT_SLEEP_CLK },
 200};
 201
 202static const struct parent_map gcc_parent_map_3[] = {
 203	{ P_BI_TCXO, 0 },
 204	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 205	{ P_GCC_GPLL1_OUT_MAIN, 4 },
 206	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 207	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 208};
 209
 210static const struct clk_parent_data gcc_parent_data_3[] = {
 211	{ .index = DT_BI_TCXO },
 212	{ .hw = &gcc_gpll0.clkr.hw },
 213	{ .hw = &gcc_gpll1.clkr.hw },
 214	{ .hw = &gcc_gpll4.clkr.hw },
 215	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 216};
 217
 218static const struct parent_map gcc_parent_map_4[] = {
 219	{ P_BI_TCXO, 0 },
 220	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 221	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 222	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 223};
 224
 225static const struct clk_parent_data gcc_parent_data_4[] = {
 226	{ .index = DT_BI_TCXO },
 227	{ .hw = &gcc_gpll0.clkr.hw },
 228	{ .hw = &gcc_gpll4.clkr.hw },
 229	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 230};
 231
 232static const struct parent_map gcc_parent_map_5[] = {
 233	{ P_BI_TCXO, 0 },
 234};
 235
 236static const struct clk_parent_data gcc_parent_data_5[] = {
 237	{ .index = DT_BI_TCXO },
 238};
 239
 240static const struct parent_map gcc_parent_map_6[] = {
 241	{ P_BI_TCXO, 0 },
 242	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 243	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 244	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 245};
 246
 247static const struct clk_parent_data gcc_parent_data_6[] = {
 248	{ .index = DT_BI_TCXO },
 249	{ .hw = &gcc_gpll7.clkr.hw },
 250	{ .hw = &gcc_gpll4.clkr.hw },
 251	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 252};
 253
 254static const struct parent_map gcc_parent_map_7[] = {
 255	{ P_BI_TCXO, 0 },
 256	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 257	{ P_RXC0_REF_CLK, 3 },
 258	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 259};
 260
 261static const struct clk_parent_data gcc_parent_data_7[] = {
 262	{ .index = DT_BI_TCXO },
 263	{ .hw = &gcc_gpll7.clkr.hw },
 264	{ .index = DT_RXC0_REF_CLK },
 265	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 266};
 267
 268static const struct parent_map gcc_parent_map_8[] = {
 269	{ P_PCIE_PHY_AUX_CLK, 1 },
 270	{ P_BI_TCXO, 2 },
 271};
 272
 273static const struct clk_parent_data gcc_parent_data_8[] = {
 274	{ .index = DT_PCIE_PHY_AUX_CLK },
 275	{ .index = DT_BI_TCXO },
 276};
 277
 278static const struct parent_map gcc_parent_map_10[] = {
 279	{ P_PCIE_PHY_AUX_CLK, 1 },
 280	{ P_BI_TCXO, 2 },
 281};
 282
 283static const struct clk_parent_data gcc_parent_data_10[] = {
 284	{ .index = DT_PCIE_PHY_AUX_CLK },
 285	{ .index = DT_BI_TCXO },
 286};
 287
 288static const struct parent_map gcc_parent_map_12[] = {
 289	{ P_BI_TCXO, 0 },
 290	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 291	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 292	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 293	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 294};
 295
 296static const struct clk_parent_data gcc_parent_data_12[] = {
 297	{ .index = DT_BI_TCXO },
 298	{ .hw = &gcc_gpll0.clkr.hw },
 299	{ .hw = &gcc_gpll9.clkr.hw },
 300	{ .hw = &gcc_gpll4.clkr.hw },
 301	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 302};
 303
 304static const struct parent_map gcc_parent_map_13[] = {
 305	{ P_BI_TCXO, 0 },
 306	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 307};
 308
 309static const struct clk_parent_data gcc_parent_data_13[] = {
 310	{ .index = DT_BI_TCXO },
 311	{ .hw = &gcc_gpll0.clkr.hw },
 312};
 313
 314static const struct parent_map gcc_parent_map_14[] = {
 315	{ P_BI_TCXO, 0 },
 316	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 317	{ P_GCC_GPLL4_OUT_MAIN, 3 },
 318	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 319};
 320
 321static const struct clk_parent_data gcc_parent_data_14[] = {
 322	{ .index = DT_BI_TCXO },
 323	{ .hw = &gcc_gpll0.clkr.hw },
 324	{ .hw = &gcc_gpll4.clkr.hw },
 325	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 326};
 327
 328static const struct parent_map gcc_parent_map_15[] = {
 329	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 330	{ P_BI_TCXO, 2 },
 331};
 332
 333static const struct clk_parent_data gcc_parent_data_15[] = {
 334	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
 335	{ .index = DT_BI_TCXO },
 336};
 337
 338static const struct parent_map gcc_parent_map_16[] = {
 339	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 340	{ P_BI_TCXO, 2 },
 341};
 342
 343static const struct clk_parent_data gcc_parent_data_16[] = {
 344	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
 345	{ .index = DT_BI_TCXO },
 346};
 347
 348static const struct parent_map gcc_parent_map_17[] = {
 349	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 350	{ P_BI_TCXO, 2 },
 351};
 352
 353static const struct clk_parent_data gcc_parent_data_17[] = {
 354	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
 355	{ .index = DT_BI_TCXO },
 356};
 357
 358static const struct parent_map gcc_parent_map_18[] = {
 359	{ P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
 360	{ P_BI_TCXO, 2 },
 361};
 362
 363static const struct clk_parent_data gcc_parent_data_18[] = {
 364	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK },
 365	{ .index = DT_BI_TCXO },
 366};
 367
 368static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
 369	.reg = 0xa9074,
 370	.shift = 0,
 371	.width = 2,
 372	.parent_map = gcc_parent_map_8,
 373	.clkr = {
 374		.hw.init = &(const struct clk_init_data) {
 375			.name = "gcc_pcie_0_phy_aux_clk_src",
 376			.parent_data = gcc_parent_data_8,
 377			.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 378			.ops = &clk_regmap_mux_closest_ops,
 379		},
 380	},
 381};
 382
 383static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
 384	.reg = 0xa906c,
 385	.clkr = {
 386		.hw.init = &(const struct clk_init_data) {
 387			.name = "gcc_pcie_0_pipe_clk_src",
 388			.parent_data = &(const struct clk_parent_data) {
 389				.index = DT_PCIE_0_PIPE_CLK,
 390			},
 391			.num_parents = 1,
 392			.ops = &clk_regmap_phy_mux_ops,
 393		},
 394	},
 395};
 396
 397static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
 398	.reg = 0x77074,
 399	.shift = 0,
 400	.width = 2,
 401	.parent_map = gcc_parent_map_10,
 402	.clkr = {
 403		.hw.init = &(const struct clk_init_data) {
 404			.name = "gcc_pcie_1_phy_aux_clk_src",
 405			.parent_data = gcc_parent_data_10,
 406			.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 407			.ops = &clk_regmap_mux_closest_ops,
 408		},
 409	},
 410};
 411
 412static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
 413	.reg = 0x7706c,
 414	.clkr = {
 415		.hw.init = &(const struct clk_init_data) {
 416			.name = "gcc_pcie_1_pipe_clk_src",
 417			.parent_data = &(const struct clk_parent_data) {
 418				.index = DT_PCIE_1_PIPE_CLK,
 419			},
 420			.num_parents = 1,
 421			.ops = &clk_regmap_phy_mux_ops,
 422		},
 423	},
 424};
 425
 426static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 427	.reg = 0x83060,
 428	.shift = 0,
 429	.width = 2,
 430	.parent_map = gcc_parent_map_15,
 431	.clkr = {
 432		.hw.init = &(const struct clk_init_data) {
 433			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 434			.parent_data = gcc_parent_data_15,
 435			.num_parents = ARRAY_SIZE(gcc_parent_data_15),
 436			.ops = &clk_regmap_mux_closest_ops,
 437		},
 438	},
 439};
 440
 441static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 442	.reg = 0x830d0,
 443	.shift = 0,
 444	.width = 2,
 445	.parent_map = gcc_parent_map_16,
 446	.clkr = {
 447		.hw.init = &(const struct clk_init_data) {
 448			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 449			.parent_data = gcc_parent_data_16,
 450			.num_parents = ARRAY_SIZE(gcc_parent_data_16),
 451			.ops = &clk_regmap_mux_closest_ops,
 452		},
 453	},
 454};
 455
 456static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 457	.reg = 0x83050,
 458	.shift = 0,
 459	.width = 2,
 460	.parent_map = gcc_parent_map_17,
 461	.clkr = {
 462		.hw.init = &(const struct clk_init_data) {
 463			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 464			.parent_data = gcc_parent_data_17,
 465			.num_parents = ARRAY_SIZE(gcc_parent_data_17),
 466			.ops = &clk_regmap_mux_closest_ops,
 467		},
 468	},
 469};
 470
 471static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 472	.reg = 0x1b068,
 473	.shift = 0,
 474	.width = 2,
 475	.parent_map = gcc_parent_map_18,
 476	.clkr = {
 477		.hw.init = &(const struct clk_init_data) {
 478			.name = "gcc_usb3_prim_phy_pipe_clk_src",
 479			.parent_data = gcc_parent_data_18,
 480			.num_parents = ARRAY_SIZE(gcc_parent_data_18),
 481			.ops = &clk_regmap_mux_closest_ops,
 482		},
 483	},
 484};
 485
 486static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
 487	F(19200000, P_BI_TCXO, 1, 0, 0),
 488	{ }
 489};
 490
 491static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {
 492	.cmd_rcgr = 0xb6028,
 493	.mnd_width = 0,
 494	.hid_width = 5,
 495	.parent_map = gcc_parent_map_2,
 496	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 497	.clkr.hw.init = &(const struct clk_init_data) {
 498		.name = "gcc_emac0_phy_aux_clk_src",
 499		.parent_data = gcc_parent_data_2,
 500		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 501		.flags = CLK_SET_RATE_PARENT,
 502		.ops = &clk_rcg2_shared_ops,
 503	},
 504};
 505
 506static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
 507	F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
 508	F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
 509	{ }
 510};
 511
 512static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
 513	.cmd_rcgr = 0xb6060,
 514	.mnd_width = 16,
 515	.hid_width = 5,
 516	.parent_map = gcc_parent_map_6,
 517	.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
 518	.clkr.hw.init = &(const struct clk_init_data) {
 519		.name = "gcc_emac0_ptp_clk_src",
 520		.parent_data = gcc_parent_data_6,
 521		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
 522		.flags = CLK_SET_RATE_PARENT,
 523		.ops = &clk_rcg2_shared_ops,
 524	},
 525};
 526
 527static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
 528	F(5000000, P_GCC_GPLL0_OUT_EVEN, 10, 1, 6),
 529	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 530	F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
 531	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
 532	{ }
 533};
 534
 535static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
 536	.cmd_rcgr = 0xb6048,
 537	.mnd_width = 16,
 538	.hid_width = 5,
 539	.parent_map = gcc_parent_map_7,
 540	.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
 541	.clkr.hw.init = &(const struct clk_init_data) {
 542		.name = "gcc_emac0_rgmii_clk_src",
 543		.parent_data = gcc_parent_data_7,
 544		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
 545		.flags = CLK_SET_RATE_PARENT,
 546		.ops = &clk_rcg2_shared_ops,
 547	},
 548};
 549
 550static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 551	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 552	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 553	{ }
 554};
 555
 556static struct clk_rcg2 gcc_gp1_clk_src = {
 557	.cmd_rcgr = 0x70004,
 558	.mnd_width = 16,
 559	.hid_width = 5,
 560	.parent_map = gcc_parent_map_1,
 561	.freq_tbl = ftbl_gcc_gp1_clk_src,
 562	.clkr.hw.init = &(const struct clk_init_data) {
 563		.name = "gcc_gp1_clk_src",
 564		.parent_data = gcc_parent_data_1,
 565		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 566		.flags = CLK_SET_RATE_PARENT,
 567		.ops = &clk_rcg2_shared_ops,
 568	},
 569};
 570
 571static struct clk_rcg2 gcc_gp2_clk_src = {
 572	.cmd_rcgr = 0x71004,
 573	.mnd_width = 16,
 574	.hid_width = 5,
 575	.parent_map = gcc_parent_map_1,
 576	.freq_tbl = ftbl_gcc_gp1_clk_src,
 577	.clkr.hw.init = &(const struct clk_init_data) {
 578		.name = "gcc_gp2_clk_src",
 579		.parent_data = gcc_parent_data_1,
 580		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 581		.flags = CLK_SET_RATE_PARENT,
 582		.ops = &clk_rcg2_shared_ops,
 583	},
 584};
 585
 586static struct clk_rcg2 gcc_gp3_clk_src = {
 587	.cmd_rcgr = 0x62004,
 588	.mnd_width = 16,
 589	.hid_width = 5,
 590	.parent_map = gcc_parent_map_1,
 591	.freq_tbl = ftbl_gcc_gp1_clk_src,
 592	.clkr.hw.init = &(const struct clk_init_data) {
 593		.name = "gcc_gp3_clk_src",
 594		.parent_data = gcc_parent_data_1,
 595		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 596		.flags = CLK_SET_RATE_PARENT,
 597		.ops = &clk_rcg2_shared_ops,
 598	},
 599};
 600
 601static struct clk_rcg2 gcc_gp4_clk_src = {
 602	.cmd_rcgr = 0x1e004,
 603	.mnd_width = 16,
 604	.hid_width = 5,
 605	.parent_map = gcc_parent_map_1,
 606	.freq_tbl = ftbl_gcc_gp1_clk_src,
 607	.clkr.hw.init = &(const struct clk_init_data) {
 608		.name = "gcc_gp4_clk_src",
 609		.parent_data = gcc_parent_data_1,
 610		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 611		.flags = CLK_SET_RATE_PARENT,
 612		.ops = &clk_rcg2_shared_ops,
 613	},
 614};
 615
 616static struct clk_rcg2 gcc_gp5_clk_src = {
 617	.cmd_rcgr = 0x1f004,
 618	.mnd_width = 16,
 619	.hid_width = 5,
 620	.parent_map = gcc_parent_map_1,
 621	.freq_tbl = ftbl_gcc_gp1_clk_src,
 622	.clkr.hw.init = &(const struct clk_init_data) {
 623		.name = "gcc_gp5_clk_src",
 624		.parent_data = gcc_parent_data_1,
 625		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 626		.flags = CLK_SET_RATE_PARENT,
 627		.ops = &clk_rcg2_shared_ops,
 628	},
 629};
 630
 631static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 632	.cmd_rcgr = 0xa9078,
 633	.mnd_width = 16,
 634	.hid_width = 5,
 635	.parent_map = gcc_parent_map_2,
 636	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 637	.clkr.hw.init = &(const struct clk_init_data) {
 638		.name = "gcc_pcie_0_aux_clk_src",
 639		.parent_data = gcc_parent_data_2,
 640		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 641		.flags = CLK_SET_RATE_PARENT,
 642		.ops = &clk_rcg2_shared_ops,
 643	},
 644};
 645
 646static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 647	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 648	{ }
 649};
 650
 651static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 652	.cmd_rcgr = 0xa9054,
 653	.mnd_width = 0,
 654	.hid_width = 5,
 655	.parent_map = gcc_parent_map_0,
 656	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 657	.clkr.hw.init = &(const struct clk_init_data) {
 658		.name = "gcc_pcie_0_phy_rchng_clk_src",
 659		.parent_data = gcc_parent_data_0,
 660		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 661		.flags = CLK_SET_RATE_PARENT,
 662		.ops = &clk_rcg2_shared_ops,
 663	},
 664};
 665
 666static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 667	.cmd_rcgr = 0x77078,
 668	.mnd_width = 16,
 669	.hid_width = 5,
 670	.parent_map = gcc_parent_map_2,
 671	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 672	.clkr.hw.init = &(const struct clk_init_data) {
 673		.name = "gcc_pcie_1_aux_clk_src",
 674		.parent_data = gcc_parent_data_2,
 675		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 676		.flags = CLK_SET_RATE_PARENT,
 677		.ops = &clk_rcg2_shared_ops,
 678	},
 679};
 680
 681static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 682	.cmd_rcgr = 0x77054,
 683	.mnd_width = 0,
 684	.hid_width = 5,
 685	.parent_map = gcc_parent_map_0,
 686	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 687	.clkr.hw.init = &(const struct clk_init_data) {
 688		.name = "gcc_pcie_1_phy_rchng_clk_src",
 689		.parent_data = gcc_parent_data_0,
 690		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 691		.flags = CLK_SET_RATE_PARENT,
 692		.ops = &clk_rcg2_shared_ops,
 693	},
 694};
 695
 696static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 697	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 698	{ }
 699};
 700
 701static struct clk_rcg2 gcc_pdm2_clk_src = {
 702	.cmd_rcgr = 0x3f010,
 703	.mnd_width = 0,
 704	.hid_width = 5,
 705	.parent_map = gcc_parent_map_0,
 706	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 707	.clkr.hw.init = &(const struct clk_init_data) {
 708		.name = "gcc_pdm2_clk_src",
 709		.parent_data = gcc_parent_data_0,
 710		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 711		.flags = CLK_SET_RATE_PARENT,
 712		.ops = &clk_rcg2_shared_ops,
 713	},
 714};
 715
 716static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 717	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 718	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 719	F(19200000, P_BI_TCXO, 1, 0, 0),
 720	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 721	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 722	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 723	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 724	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 725	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 726	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 727	{ }
 728};
 729
 730static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 731	.name = "gcc_qupv3_wrap0_s0_clk_src",
 732	.parent_data = gcc_parent_data_0,
 733	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 734	.flags = CLK_SET_RATE_PARENT,
 735	.ops = &clk_rcg2_shared_ops,
 736};
 737
 738static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 739	.cmd_rcgr = 0x23154,
 740	.mnd_width = 16,
 741	.hid_width = 5,
 742	.parent_map = gcc_parent_map_0,
 743	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 744	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 745};
 746
 747static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 748	.name = "gcc_qupv3_wrap0_s1_clk_src",
 749	.parent_data = gcc_parent_data_0,
 750	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 751	.flags = CLK_SET_RATE_PARENT,
 752	.ops = &clk_rcg2_shared_ops,
 753};
 754
 755static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 756	.cmd_rcgr = 0x23288,
 757	.mnd_width = 16,
 758	.hid_width = 5,
 759	.parent_map = gcc_parent_map_0,
 760	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 761	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 762};
 763
 764static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
 765	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 766	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 767	F(19200000, P_BI_TCXO, 1, 0, 0),
 768	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 769	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 770	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 771	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 772	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 773	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 774	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 775	{ }
 776};
 777
 778static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 779	.name = "gcc_qupv3_wrap0_s2_clk_src",
 780	.parent_data = gcc_parent_data_0,
 781	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 782	.flags = CLK_SET_RATE_PARENT,
 783	.ops = &clk_rcg2_shared_ops,
 784};
 785
 786static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 787	.cmd_rcgr = 0x233bc,
 788	.mnd_width = 16,
 789	.hid_width = 5,
 790	.parent_map = gcc_parent_map_0,
 791	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 792	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 793};
 794
 795static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 796	.name = "gcc_qupv3_wrap0_s3_clk_src",
 797	.parent_data = gcc_parent_data_0,
 798	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 799	.flags = CLK_SET_RATE_PARENT,
 800	.ops = &clk_rcg2_shared_ops,
 801};
 802
 803static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 804	.cmd_rcgr = 0x234f0,
 805	.mnd_width = 16,
 806	.hid_width = 5,
 807	.parent_map = gcc_parent_map_0,
 808	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 809	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 810};
 811
 812static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 813	.name = "gcc_qupv3_wrap0_s4_clk_src",
 814	.parent_data = gcc_parent_data_4,
 815	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 816	.flags = CLK_SET_RATE_PARENT,
 817	.ops = &clk_rcg2_shared_ops,
 818};
 819
 820static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 821	.cmd_rcgr = 0x23624,
 822	.mnd_width = 16,
 823	.hid_width = 5,
 824	.parent_map = gcc_parent_map_4,
 825	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 826	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 827};
 828
 829static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 830	.name = "gcc_qupv3_wrap0_s5_clk_src",
 831	.parent_data = gcc_parent_data_0,
 832	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 833	.flags = CLK_SET_RATE_PARENT,
 834	.ops = &clk_rcg2_shared_ops,
 835};
 836
 837static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 838	.cmd_rcgr = 0x23758,
 839	.mnd_width = 16,
 840	.hid_width = 5,
 841	.parent_map = gcc_parent_map_0,
 842	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 843	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 844};
 845
 846static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 847	.name = "gcc_qupv3_wrap0_s6_clk_src",
 848	.parent_data = gcc_parent_data_0,
 849	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 850	.flags = CLK_SET_RATE_PARENT,
 851	.ops = &clk_rcg2_shared_ops,
 852};
 853
 854static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 855	.cmd_rcgr = 0x2388c,
 856	.mnd_width = 16,
 857	.hid_width = 5,
 858	.parent_map = gcc_parent_map_0,
 859	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 860	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 861};
 862
 863static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 864	.name = "gcc_qupv3_wrap0_s7_clk_src",
 865	.parent_data = gcc_parent_data_0,
 866	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 867	.flags = CLK_SET_RATE_PARENT,
 868	.ops = &clk_rcg2_shared_ops,
 869};
 870
 871static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 872	.cmd_rcgr = 0x239c0,
 873	.mnd_width = 16,
 874	.hid_width = 5,
 875	.parent_map = gcc_parent_map_0,
 876	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 877	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 878};
 879
 880static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 881	.name = "gcc_qupv3_wrap1_s0_clk_src",
 882	.parent_data = gcc_parent_data_0,
 883	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 884	.flags = CLK_SET_RATE_PARENT,
 885	.ops = &clk_rcg2_shared_ops,
 886};
 887
 888static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 889	.cmd_rcgr = 0x24154,
 890	.mnd_width = 16,
 891	.hid_width = 5,
 892	.parent_map = gcc_parent_map_0,
 893	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 894	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 895};
 896
 897static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 898	.name = "gcc_qupv3_wrap1_s1_clk_src",
 899	.parent_data = gcc_parent_data_0,
 900	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 901	.flags = CLK_SET_RATE_PARENT,
 902	.ops = &clk_rcg2_shared_ops,
 903};
 904
 905static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 906	.cmd_rcgr = 0x24288,
 907	.mnd_width = 16,
 908	.hid_width = 5,
 909	.parent_map = gcc_parent_map_0,
 910	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 911	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 912};
 913
 914static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 915	.name = "gcc_qupv3_wrap1_s2_clk_src",
 916	.parent_data = gcc_parent_data_0,
 917	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 918	.flags = CLK_SET_RATE_PARENT,
 919	.ops = &clk_rcg2_shared_ops,
 920};
 921
 922static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 923	.cmd_rcgr = 0x243bc,
 924	.mnd_width = 16,
 925	.hid_width = 5,
 926	.parent_map = gcc_parent_map_0,
 927	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 928	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 929};
 930
 931static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 932	.name = "gcc_qupv3_wrap1_s3_clk_src",
 933	.parent_data = gcc_parent_data_0,
 934	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 935	.flags = CLK_SET_RATE_PARENT,
 936	.ops = &clk_rcg2_shared_ops,
 937};
 938
 939static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 940	.cmd_rcgr = 0x244f0,
 941	.mnd_width = 16,
 942	.hid_width = 5,
 943	.parent_map = gcc_parent_map_0,
 944	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 945	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 946};
 947
 948static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 949	.name = "gcc_qupv3_wrap1_s4_clk_src",
 950	.parent_data = gcc_parent_data_4,
 951	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 952	.flags = CLK_SET_RATE_PARENT,
 953	.ops = &clk_rcg2_shared_ops,
 954};
 955
 956static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 957	.cmd_rcgr = 0x24624,
 958	.mnd_width = 16,
 959	.hid_width = 5,
 960	.parent_map = gcc_parent_map_4,
 961	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 962	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 963};
 964
 965static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 966	.name = "gcc_qupv3_wrap1_s5_clk_src",
 967	.parent_data = gcc_parent_data_0,
 968	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 969	.flags = CLK_SET_RATE_PARENT,
 970	.ops = &clk_rcg2_shared_ops,
 971};
 972
 973static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 974	.cmd_rcgr = 0x24758,
 975	.mnd_width = 16,
 976	.hid_width = 5,
 977	.parent_map = gcc_parent_map_0,
 978	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 979	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 980};
 981
 982static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 983	.name = "gcc_qupv3_wrap1_s6_clk_src",
 984	.parent_data = gcc_parent_data_0,
 985	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 986	.flags = CLK_SET_RATE_PARENT,
 987	.ops = &clk_rcg2_shared_ops,
 988};
 989
 990static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 991	.cmd_rcgr = 0x2488c,
 992	.mnd_width = 16,
 993	.hid_width = 5,
 994	.parent_map = gcc_parent_map_0,
 995	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 996	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 997};
 998
 999static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
1000	.name = "gcc_qupv3_wrap1_s7_clk_src",
1001	.parent_data = gcc_parent_data_0,
1002	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1003	.flags = CLK_SET_RATE_PARENT,
1004	.ops = &clk_rcg2_shared_ops,
1005};
1006
1007static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
1008	.cmd_rcgr = 0x249c0,
1009	.mnd_width = 16,
1010	.hid_width = 5,
1011	.parent_map = gcc_parent_map_0,
1012	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1013	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
1014};
1015
1016static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
1017	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1018	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1019	F(19200000, P_BI_TCXO, 1, 0, 0),
1020	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1021	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1022	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1023	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1024	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1025	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1026	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1027	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1028	F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1029	{ }
1030};
1031
1032static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = {
1033	.name = "gcc_qupv3_wrap3_s0_clk_src",
1034	.parent_data = gcc_parent_data_3,
1035	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1036	.flags = CLK_SET_RATE_PARENT,
1037	.ops = &clk_rcg2_shared_ops,
1038};
1039
1040static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = {
1041	.cmd_rcgr = 0xc4158,
1042	.mnd_width = 16,
1043	.hid_width = 5,
1044	.parent_map = gcc_parent_map_3,
1045	.freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src,
1046	.clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init,
1047};
1048
1049static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1050	F(144000, P_BI_TCXO, 16, 3, 25),
1051	F(400000, P_BI_TCXO, 12, 1, 4),
1052	F(19200000, P_BI_TCXO, 1, 0, 0),
1053	F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
1054	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1055	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1056	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1057	F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1058	F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
1059	{ }
1060};
1061
1062static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1063	.cmd_rcgr = 0x20014,
1064	.mnd_width = 8,
1065	.hid_width = 5,
1066	.parent_map = gcc_parent_map_12,
1067	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1068	.clkr.hw.init = &(const struct clk_init_data) {
1069		.name = "gcc_sdcc1_apps_clk_src",
1070		.parent_data = gcc_parent_data_12,
1071		.num_parents = ARRAY_SIZE(gcc_parent_data_12),
1072		.flags = CLK_SET_RATE_PARENT,
1073		.ops = &clk_rcg2_floor_ops,
1074	},
1075};
1076
1077static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1078	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1079	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1080	{ }
1081};
1082
1083static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1084	.cmd_rcgr = 0x2002c,
1085	.mnd_width = 0,
1086	.hid_width = 5,
1087	.parent_map = gcc_parent_map_13,
1088	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1089	.clkr.hw.init = &(const struct clk_init_data) {
1090		.name = "gcc_sdcc1_ice_core_clk_src",
1091		.parent_data = gcc_parent_data_13,
1092		.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1093		.flags = CLK_SET_RATE_PARENT,
1094		.ops = &clk_rcg2_floor_ops,
1095	},
1096};
1097
1098static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1099	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1100	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1101	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1102	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1103	{ }
1104};
1105
1106static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1107	.cmd_rcgr = 0x8302c,
1108	.mnd_width = 8,
1109	.hid_width = 5,
1110	.parent_map = gcc_parent_map_0,
1111	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1112	.clkr.hw.init = &(const struct clk_init_data) {
1113		.name = "gcc_ufs_phy_axi_clk_src",
1114		.parent_data = gcc_parent_data_0,
1115		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1116		.flags = CLK_SET_RATE_PARENT,
1117		.ops = &clk_rcg2_shared_ops,
1118	},
1119};
1120
1121static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1122	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1123	F(201600000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1124	F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1125	{ }
1126};
1127
1128static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1129	.cmd_rcgr = 0x83074,
1130	.mnd_width = 0,
1131	.hid_width = 5,
1132	.parent_map = gcc_parent_map_14,
1133	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1134	.clkr.hw.init = &(const struct clk_init_data) {
1135		.name = "gcc_ufs_phy_ice_core_clk_src",
1136		.parent_data = gcc_parent_data_14,
1137		.num_parents = ARRAY_SIZE(gcc_parent_data_14),
1138		.flags = CLK_SET_RATE_PARENT,
1139		.ops = &clk_rcg2_shared_ops,
1140	},
1141};
1142
1143static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1144	.cmd_rcgr = 0x830a8,
1145	.mnd_width = 0,
1146	.hid_width = 5,
1147	.parent_map = gcc_parent_map_5,
1148	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1149	.clkr.hw.init = &(const struct clk_init_data) {
1150		.name = "gcc_ufs_phy_phy_aux_clk_src",
1151		.parent_data = gcc_parent_data_5,
1152		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1153		.flags = CLK_SET_RATE_PARENT,
1154		.ops = &clk_rcg2_shared_ops,
1155	},
1156};
1157
1158static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1159	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1160	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1161	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1162	{ }
1163};
1164
1165static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1166	.cmd_rcgr = 0x8308c,
1167	.mnd_width = 0,
1168	.hid_width = 5,
1169	.parent_map = gcc_parent_map_0,
1170	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1171	.clkr.hw.init = &(const struct clk_init_data) {
1172		.name = "gcc_ufs_phy_unipro_core_clk_src",
1173		.parent_data = gcc_parent_data_0,
1174		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1175		.flags = CLK_SET_RATE_PARENT,
1176		.ops = &clk_rcg2_shared_ops,
1177	},
1178};
1179
1180static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
1181	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1182	{ }
1183};
1184
1185static struct clk_rcg2 gcc_usb20_master_clk_src = {
1186	.cmd_rcgr = 0x1c028,
1187	.mnd_width = 8,
1188	.hid_width = 5,
1189	.parent_map = gcc_parent_map_0,
1190	.freq_tbl = ftbl_gcc_usb20_master_clk_src,
1191	.clkr.hw.init = &(const struct clk_init_data) {
1192		.name = "gcc_usb20_master_clk_src",
1193		.parent_data = gcc_parent_data_0,
1194		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1195		.flags = CLK_SET_RATE_PARENT,
1196		.ops = &clk_rcg2_shared_ops,
1197	},
1198};
1199
1200static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
1201	.cmd_rcgr = 0x1c040,
1202	.mnd_width = 0,
1203	.hid_width = 5,
1204	.parent_map = gcc_parent_map_0,
1205	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1206	.clkr.hw.init = &(const struct clk_init_data) {
1207		.name = "gcc_usb20_mock_utmi_clk_src",
1208		.parent_data = gcc_parent_data_0,
1209		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1210		.flags = CLK_SET_RATE_PARENT,
1211		.ops = &clk_rcg2_shared_ops,
1212	},
1213};
1214
1215static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1216	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1217	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1218	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1219	{ }
1220};
1221
1222static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1223	.cmd_rcgr = 0x1b028,
1224	.mnd_width = 8,
1225	.hid_width = 5,
1226	.parent_map = gcc_parent_map_0,
1227	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1228	.clkr.hw.init = &(const struct clk_init_data) {
1229		.name = "gcc_usb30_prim_master_clk_src",
1230		.parent_data = gcc_parent_data_0,
1231		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1232		.flags = CLK_SET_RATE_PARENT,
1233		.ops = &clk_rcg2_shared_ops,
1234	},
1235};
1236
1237static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1238	.cmd_rcgr = 0x1b040,
1239	.mnd_width = 0,
1240	.hid_width = 5,
1241	.parent_map = gcc_parent_map_0,
1242	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1243	.clkr.hw.init = &(const struct clk_init_data) {
1244		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1245		.parent_data = gcc_parent_data_0,
1246		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1247		.flags = CLK_SET_RATE_PARENT,
1248		.ops = &clk_rcg2_shared_ops,
1249	},
1250};
1251
1252static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1253	.cmd_rcgr = 0x1b06c,
1254	.mnd_width = 0,
1255	.hid_width = 5,
1256	.parent_map = gcc_parent_map_2,
1257	.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1258	.clkr.hw.init = &(const struct clk_init_data) {
1259		.name = "gcc_usb3_prim_phy_aux_clk_src",
1260		.parent_data = gcc_parent_data_2,
1261		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1262		.flags = CLK_SET_RATE_PARENT,
1263		.ops = &clk_rcg2_shared_ops,
1264	},
1265};
1266
1267static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = {
1268	.reg = 0xa9070,
1269	.shift = 0,
1270	.width = 4,
1271	.clkr.hw.init = &(const struct clk_init_data) {
1272		.name = "gcc_pcie_0_pipe_div_clk_src",
1273		.parent_hws = (const struct clk_hw*[]) {
1274			&gcc_pcie_0_pipe_clk_src.clkr.hw,
1275		},
1276		.num_parents = 1,
1277		.flags = CLK_SET_RATE_PARENT,
1278		.ops = &clk_regmap_div_ro_ops,
1279	},
1280};
1281
1282static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = {
1283	.reg = 0x77070,
1284	.shift = 0,
1285	.width = 4,
1286	.clkr.hw.init = &(const struct clk_init_data) {
1287		.name = "gcc_pcie_1_pipe_div_clk_src",
1288		.parent_hws = (const struct clk_hw*[]) {
1289			&gcc_pcie_1_pipe_clk_src.clkr.hw,
1290		},
1291		.num_parents = 1,
1292		.flags = CLK_SET_RATE_PARENT,
1293		.ops = &clk_regmap_div_ro_ops,
1294	},
1295};
1296
1297static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = {
1298	.reg = 0xc4288,
1299	.shift = 0,
1300	.width = 4,
1301	.clkr.hw.init = &(const struct clk_init_data) {
1302		.name = "gcc_qupv3_wrap3_s0_div_clk_src",
1303		.parent_hws = (const struct clk_hw*[]) {
1304			&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
1305		},
1306		.num_parents = 1,
1307		.flags = CLK_SET_RATE_PARENT,
1308		.ops = &clk_regmap_div_ro_ops,
1309	},
1310};
1311
1312static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
1313	.reg = 0x1c058,
1314	.shift = 0,
1315	.width = 4,
1316	.clkr.hw.init = &(const struct clk_init_data) {
1317		.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
1318		.parent_hws = (const struct clk_hw*[]) {
1319			&gcc_usb20_mock_utmi_clk_src.clkr.hw,
1320		},
1321		.num_parents = 1,
1322		.flags = CLK_SET_RATE_PARENT,
1323		.ops = &clk_regmap_div_ro_ops,
1324	},
1325};
1326
1327static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1328	.reg = 0x1b058,
1329	.shift = 0,
1330	.width = 4,
1331	.clkr.hw.init = &(const struct clk_init_data) {
1332		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1333		.parent_hws = (const struct clk_hw*[]) {
1334			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1335		},
1336		.num_parents = 1,
1337		.flags = CLK_SET_RATE_PARENT,
1338		.ops = &clk_regmap_div_ro_ops,
1339	},
1340};
1341
1342static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = {
1343	.halt_reg = 0x8e200,
1344	.halt_check = BRANCH_HALT_VOTED,
1345	.hwcg_reg = 0x8e200,
1346	.hwcg_bit = 1,
1347	.clkr = {
1348		.enable_reg = 0x4b000,
1349		.enable_mask = BIT(28),
1350		.hw.init = &(const struct clk_init_data) {
1351			.name = "gcc_aggre_noc_qupv3_axi_clk",
1352			.ops = &clk_branch2_ops,
1353		},
1354	},
1355};
1356
1357static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1358	.halt_reg = 0x830d4,
1359	.halt_check = BRANCH_HALT_VOTED,
1360	.hwcg_reg = 0x830d4,
1361	.hwcg_bit = 1,
1362	.clkr = {
1363		.enable_reg = 0x830d4,
1364		.enable_mask = BIT(0),
1365		.hw.init = &(const struct clk_init_data) {
1366			.name = "gcc_aggre_ufs_phy_axi_clk",
1367			.parent_hws = (const struct clk_hw*[]) {
1368				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1369			},
1370			.num_parents = 1,
1371			.flags = CLK_SET_RATE_PARENT,
1372			.ops = &clk_branch2_ops,
1373		},
1374	},
1375};
1376
1377static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
1378	.halt_reg = 0x1c05c,
1379	.halt_check = BRANCH_HALT_VOTED,
1380	.hwcg_reg = 0x1c05c,
1381	.hwcg_bit = 1,
1382	.clkr = {
1383		.enable_reg = 0x1c05c,
1384		.enable_mask = BIT(0),
1385		.hw.init = &(const struct clk_init_data) {
1386			.name = "gcc_aggre_usb2_prim_axi_clk",
1387			.parent_hws = (const struct clk_hw*[]) {
1388				&gcc_usb20_master_clk_src.clkr.hw,
1389			},
1390			.num_parents = 1,
1391			.flags = CLK_SET_RATE_PARENT,
1392			.ops = &clk_branch2_ops,
1393		},
1394	},
1395};
1396
1397static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1398	.halt_reg = 0x1b084,
1399	.halt_check = BRANCH_HALT_VOTED,
1400	.hwcg_reg = 0x1b084,
1401	.hwcg_bit = 1,
1402	.clkr = {
1403		.enable_reg = 0x1b084,
1404		.enable_mask = BIT(0),
1405		.hw.init = &(const struct clk_init_data) {
1406			.name = "gcc_aggre_usb3_prim_axi_clk",
1407			.parent_hws = (const struct clk_hw*[]) {
1408				&gcc_usb30_prim_master_clk_src.clkr.hw,
1409			},
1410			.num_parents = 1,
1411			.flags = CLK_SET_RATE_PARENT,
1412			.ops = &clk_branch2_ops,
1413		},
1414	},
1415};
1416
1417static struct clk_branch gcc_ahb2phy0_clk = {
1418	.halt_reg = 0x76004,
1419	.halt_check = BRANCH_HALT_VOTED,
1420	.hwcg_reg = 0x76004,
1421	.hwcg_bit = 1,
1422	.clkr = {
1423		.enable_reg = 0x76004,
1424		.enable_mask = BIT(0),
1425		.hw.init = &(const struct clk_init_data) {
1426			.name = "gcc_ahb2phy0_clk",
1427			.ops = &clk_branch2_ops,
1428		},
1429	},
1430};
1431
1432static struct clk_branch gcc_ahb2phy2_clk = {
1433	.halt_reg = 0x76008,
1434	.halt_check = BRANCH_HALT_VOTED,
1435	.hwcg_reg = 0x76008,
1436	.hwcg_bit = 1,
1437	.clkr = {
1438		.enable_reg = 0x76008,
1439		.enable_mask = BIT(0),
1440		.hw.init = &(const struct clk_init_data) {
1441			.name = "gcc_ahb2phy2_clk",
1442			.ops = &clk_branch2_ops,
1443		},
1444	},
1445};
1446
1447static struct clk_branch gcc_ahb2phy3_clk = {
1448	.halt_reg = 0x7600c,
1449	.halt_check = BRANCH_HALT_VOTED,
1450	.hwcg_reg = 0x7600c,
1451	.hwcg_bit = 1,
1452	.clkr = {
1453		.enable_reg = 0x7600c,
1454		.enable_mask = BIT(0),
1455		.hw.init = &(const struct clk_init_data) {
1456			.name = "gcc_ahb2phy3_clk",
1457			.ops = &clk_branch2_ops,
1458		},
1459	},
1460};
1461
1462static struct clk_branch gcc_boot_rom_ahb_clk = {
1463	.halt_reg = 0x44004,
1464	.halt_check = BRANCH_HALT_VOTED,
1465	.hwcg_reg = 0x44004,
1466	.hwcg_bit = 1,
1467	.clkr = {
1468		.enable_reg = 0x4b000,
1469		.enable_mask = BIT(10),
1470		.hw.init = &(const struct clk_init_data) {
1471			.name = "gcc_boot_rom_ahb_clk",
1472			.ops = &clk_branch2_ops,
1473		},
1474	},
1475};
1476
1477static struct clk_branch gcc_camera_hf_axi_clk = {
1478	.halt_reg = 0x32010,
1479	.halt_check = BRANCH_HALT_SKIP,
1480	.hwcg_reg = 0x32010,
1481	.hwcg_bit = 1,
1482	.clkr = {
1483		.enable_reg = 0x32010,
1484		.enable_mask = BIT(0),
1485		.hw.init = &(const struct clk_init_data) {
1486			.name = "gcc_camera_hf_axi_clk",
1487			.ops = &clk_branch2_ops,
1488		},
1489	},
1490};
1491
1492static struct clk_branch gcc_camera_sf_axi_clk = {
1493	.halt_reg = 0x32018,
1494	.halt_check = BRANCH_HALT_SKIP,
1495	.hwcg_reg = 0x32018,
1496	.hwcg_bit = 1,
1497	.clkr = {
1498		.enable_reg = 0x32018,
1499		.enable_mask = BIT(0),
1500		.hw.init = &(const struct clk_init_data) {
1501			.name = "gcc_camera_sf_axi_clk",
1502			.ops = &clk_branch2_ops,
1503		},
1504	},
1505};
1506
1507static struct clk_branch gcc_camera_throttle_xo_clk = {
1508	.halt_reg = 0x32024,
1509	.halt_check = BRANCH_HALT,
1510	.clkr = {
1511		.enable_reg = 0x32024,
1512		.enable_mask = BIT(0),
1513		.hw.init = &(const struct clk_init_data) {
1514			.name = "gcc_camera_throttle_xo_clk",
1515			.ops = &clk_branch2_ops,
1516		},
1517	},
1518};
1519
1520static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
1521	.halt_reg = 0x1c060,
1522	.halt_check = BRANCH_HALT_VOTED,
1523	.hwcg_reg = 0x1c060,
1524	.hwcg_bit = 1,
1525	.clkr = {
1526		.enable_reg = 0x1c060,
1527		.enable_mask = BIT(0),
1528		.hw.init = &(const struct clk_init_data) {
1529			.name = "gcc_cfg_noc_usb2_prim_axi_clk",
1530			.parent_hws = (const struct clk_hw*[]) {
1531				&gcc_usb20_master_clk_src.clkr.hw,
1532			},
1533			.num_parents = 1,
1534			.flags = CLK_SET_RATE_PARENT,
1535			.ops = &clk_branch2_ops,
1536		},
1537	},
1538};
1539
1540static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1541	.halt_reg = 0x1b088,
1542	.halt_check = BRANCH_HALT_VOTED,
1543	.hwcg_reg = 0x1b088,
1544	.hwcg_bit = 1,
1545	.clkr = {
1546		.enable_reg = 0x1b088,
1547		.enable_mask = BIT(0),
1548		.hw.init = &(const struct clk_init_data) {
1549			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1550			.parent_hws = (const struct clk_hw*[]) {
1551				&gcc_usb30_prim_master_clk_src.clkr.hw,
1552			},
1553			.num_parents = 1,
1554			.flags = CLK_SET_RATE_PARENT,
1555			.ops = &clk_branch2_ops,
1556		},
1557	},
1558};
1559
1560static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1561	.halt_reg = 0x7d164,
1562	.halt_check = BRANCH_HALT_VOTED,
1563	.hwcg_reg = 0x7d164,
1564	.hwcg_bit = 1,
1565	.clkr = {
1566		.enable_reg = 0x7d164,
1567		.enable_mask = BIT(0),
1568		.hw.init = &(const struct clk_init_data) {
1569			.name = "gcc_ddrss_gpu_axi_clk",
1570			.ops = &clk_branch2_aon_ops,
1571		},
1572	},
1573};
1574
1575static struct clk_branch gcc_disp_hf_axi_clk = {
1576	.halt_reg = 0x33010,
1577	.halt_check = BRANCH_HALT_VOTED,
1578	.hwcg_reg = 0x33010,
1579	.hwcg_bit = 1,
1580	.clkr = {
1581		.enable_reg = 0x33010,
1582		.enable_mask = BIT(0),
1583		.hw.init = &(const struct clk_init_data) {
1584			.name = "gcc_disp_hf_axi_clk",
1585			.ops = &clk_branch2_ops,
1586		},
1587	},
1588};
1589
1590static struct clk_branch gcc_edp_ref_clkref_en = {
1591	.halt_reg = 0x97448,
1592	.halt_check = BRANCH_HALT_DELAY,
1593	.clkr = {
1594		.enable_reg = 0x97448,
1595		.enable_mask = BIT(0),
1596		.hw.init = &(const struct clk_init_data) {
1597			.name = "gcc_edp_ref_clkref_en",
1598			.ops = &clk_branch2_ops,
1599		},
1600	},
1601};
1602
1603static struct clk_branch gcc_emac0_axi_clk = {
1604	.halt_reg = 0xb6018,
1605	.halt_check = BRANCH_HALT_VOTED,
1606	.hwcg_reg = 0xb6018,
1607	.hwcg_bit = 1,
1608	.clkr = {
1609		.enable_reg = 0xb6018,
1610		.enable_mask = BIT(0),
1611		.hw.init = &(const struct clk_init_data) {
1612			.name = "gcc_emac0_axi_clk",
1613			.ops = &clk_branch2_ops,
1614		},
1615	},
1616};
1617
1618static struct clk_branch gcc_emac0_phy_aux_clk = {
1619	.halt_reg = 0xb6024,
1620	.halt_check = BRANCH_HALT,
1621	.clkr = {
1622		.enable_reg = 0xb6024,
1623		.enable_mask = BIT(0),
1624		.hw.init = &(const struct clk_init_data) {
1625			.name = "gcc_emac0_phy_aux_clk",
1626			.parent_hws = (const struct clk_hw*[]) {
1627				&gcc_emac0_phy_aux_clk_src.clkr.hw,
1628			},
1629			.num_parents = 1,
1630			.flags = CLK_SET_RATE_PARENT,
1631			.ops = &clk_branch2_ops,
1632		},
1633	},
1634};
1635
1636static struct clk_branch gcc_emac0_ptp_clk = {
1637	.halt_reg = 0xb6040,
1638	.halt_check = BRANCH_HALT,
1639	.clkr = {
1640		.enable_reg = 0xb6040,
1641		.enable_mask = BIT(0),
1642		.hw.init = &(const struct clk_init_data) {
1643			.name = "gcc_emac0_ptp_clk",
1644			.parent_hws = (const struct clk_hw*[]) {
1645				&gcc_emac0_ptp_clk_src.clkr.hw,
1646			},
1647			.num_parents = 1,
1648			.flags = CLK_SET_RATE_PARENT,
1649			.ops = &clk_branch2_ops,
1650		},
1651	},
1652};
1653
1654static struct clk_branch gcc_emac0_rgmii_clk = {
1655	.halt_reg = 0xb6044,
1656	.halt_check = BRANCH_HALT,
1657	.clkr = {
1658		.enable_reg = 0xb6044,
1659		.enable_mask = BIT(0),
1660		.hw.init = &(const struct clk_init_data) {
1661			.name = "gcc_emac0_rgmii_clk",
1662			.parent_hws = (const struct clk_hw*[]) {
1663				&gcc_emac0_rgmii_clk_src.clkr.hw,
1664			},
1665			.num_parents = 1,
1666			.flags = CLK_SET_RATE_PARENT,
1667			.ops = &clk_branch2_ops,
1668		},
1669	},
1670};
1671
1672static struct clk_branch gcc_emac0_slv_ahb_clk = {
1673	.halt_reg = 0xb6020,
1674	.halt_check = BRANCH_HALT_VOTED,
1675	.hwcg_reg = 0xb6020,
1676	.hwcg_bit = 1,
1677	.clkr = {
1678		.enable_reg = 0xb6020,
1679		.enable_mask = BIT(0),
1680		.hw.init = &(const struct clk_init_data) {
1681			.name = "gcc_emac0_slv_ahb_clk",
1682			.ops = &clk_branch2_ops,
1683		},
1684	},
1685};
1686
1687static struct clk_branch gcc_gp1_clk = {
1688	.halt_reg = 0x70000,
1689	.halt_check = BRANCH_HALT,
1690	.clkr = {
1691		.enable_reg = 0x70000,
1692		.enable_mask = BIT(0),
1693		.hw.init = &(const struct clk_init_data) {
1694			.name = "gcc_gp1_clk",
1695			.parent_hws = (const struct clk_hw*[]) {
1696				&gcc_gp1_clk_src.clkr.hw,
1697			},
1698			.num_parents = 1,
1699			.flags = CLK_SET_RATE_PARENT,
1700			.ops = &clk_branch2_ops,
1701		},
1702	},
1703};
1704
1705static struct clk_branch gcc_gp2_clk = {
1706	.halt_reg = 0x71000,
1707	.halt_check = BRANCH_HALT,
1708	.clkr = {
1709		.enable_reg = 0x71000,
1710		.enable_mask = BIT(0),
1711		.hw.init = &(const struct clk_init_data) {
1712			.name = "gcc_gp2_clk",
1713			.parent_hws = (const struct clk_hw*[]) {
1714				&gcc_gp2_clk_src.clkr.hw,
1715			},
1716			.num_parents = 1,
1717			.flags = CLK_SET_RATE_PARENT,
1718			.ops = &clk_branch2_ops,
1719		},
1720	},
1721};
1722
1723static struct clk_branch gcc_gp3_clk = {
1724	.halt_reg = 0x62000,
1725	.halt_check = BRANCH_HALT,
1726	.clkr = {
1727		.enable_reg = 0x62000,
1728		.enable_mask = BIT(0),
1729		.hw.init = &(const struct clk_init_data) {
1730			.name = "gcc_gp3_clk",
1731			.parent_hws = (const struct clk_hw*[]) {
1732				&gcc_gp3_clk_src.clkr.hw,
1733			},
1734			.num_parents = 1,
1735			.flags = CLK_SET_RATE_PARENT,
1736			.ops = &clk_branch2_ops,
1737		},
1738	},
1739};
1740
1741static struct clk_branch gcc_gp4_clk = {
1742	.halt_reg = 0x1e000,
1743	.halt_check = BRANCH_HALT,
1744	.clkr = {
1745		.enable_reg = 0x1e000,
1746		.enable_mask = BIT(0),
1747		.hw.init = &(const struct clk_init_data) {
1748			.name = "gcc_gp4_clk",
1749			.parent_hws = (const struct clk_hw*[]) {
1750				&gcc_gp4_clk_src.clkr.hw,
1751			},
1752			.num_parents = 1,
1753			.flags = CLK_SET_RATE_PARENT,
1754			.ops = &clk_branch2_ops,
1755		},
1756	},
1757};
1758
1759static struct clk_branch gcc_gp5_clk = {
1760	.halt_reg = 0x1f000,
1761	.halt_check = BRANCH_HALT,
1762	.clkr = {
1763		.enable_reg = 0x1f000,
1764		.enable_mask = BIT(0),
1765		.hw.init = &(const struct clk_init_data) {
1766			.name = "gcc_gp5_clk",
1767			.parent_hws = (const struct clk_hw*[]) {
1768				&gcc_gp5_clk_src.clkr.hw,
1769			},
1770			.num_parents = 1,
1771			.flags = CLK_SET_RATE_PARENT,
1772			.ops = &clk_branch2_ops,
1773		},
1774	},
1775};
1776
1777static struct clk_branch gcc_gpu_gpll0_clk_src = {
1778	.halt_check = BRANCH_HALT_DELAY,
1779	.clkr = {
1780		.enable_reg = 0x4b000,
1781		.enable_mask = BIT(15),
1782		.hw.init = &(const struct clk_init_data) {
1783			.name = "gcc_gpu_gpll0_clk_src",
1784			.parent_hws = (const struct clk_hw*[]) {
1785				&gcc_gpll0.clkr.hw,
1786			},
1787			.num_parents = 1,
1788			.flags = CLK_SET_RATE_PARENT,
1789			.ops = &clk_branch2_ops,
1790		},
1791	},
1792};
1793
1794static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1795	.halt_check = BRANCH_HALT_DELAY,
1796	.clkr = {
1797		.enable_reg = 0x4b000,
1798		.enable_mask = BIT(16),
1799		.hw.init = &(const struct clk_init_data) {
1800			.name = "gcc_gpu_gpll0_div_clk_src",
1801			.parent_hws = (const struct clk_hw*[]) {
1802				&gcc_gpll0_out_even.clkr.hw,
1803			},
1804			.num_parents = 1,
1805			.flags = CLK_SET_RATE_PARENT,
1806			.ops = &clk_branch2_ops,
1807		},
1808	},
1809};
1810
1811static struct clk_branch gcc_gpu_memnoc_gfx_center_pipeline_clk = {
1812	.halt_reg = 0x7d160,
1813	.halt_check = BRANCH_HALT_VOTED,
1814	.hwcg_reg = 0x7d160,
1815	.hwcg_bit = 1,
1816	.clkr = {
1817		.enable_reg = 0x7d160,
1818		.enable_mask = BIT(0),
1819		.hw.init = &(const struct clk_init_data) {
1820			.name = "gcc_gpu_memnoc_gfx_center_pipeline_clk",
1821			.ops = &clk_branch2_ops,
1822		},
1823	},
1824};
1825
1826static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1827	.halt_reg = 0x7d010,
1828	.halt_check = BRANCH_HALT_VOTED,
1829	.hwcg_reg = 0x7d010,
1830	.hwcg_bit = 1,
1831	.clkr = {
1832		.enable_reg = 0x7d010,
1833		.enable_mask = BIT(0),
1834		.hw.init = &(const struct clk_init_data) {
1835			.name = "gcc_gpu_memnoc_gfx_clk",
1836			.ops = &clk_branch2_aon_ops,
1837		},
1838	},
1839};
1840
1841static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1842	.halt_reg = 0x7d01c,
1843	.halt_check = BRANCH_HALT_DELAY,
1844	.clkr = {
1845		.enable_reg = 0x7d01c,
1846		.enable_mask = BIT(0),
1847		.hw.init = &(const struct clk_init_data) {
1848			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1849			.ops = &clk_branch2_aon_ops,
1850		},
1851	},
1852};
1853
1854static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {
1855	.halt_reg = 0x7d008,
1856	.halt_check = BRANCH_HALT_VOTED,
1857	.hwcg_reg = 0x7d008,
1858	.hwcg_bit = 1,
1859	.clkr = {
1860		.enable_reg = 0x7d008,
1861		.enable_mask = BIT(0),
1862		.hw.init = &(const struct clk_init_data) {
1863			.name = "gcc_gpu_tcu_throttle_ahb_clk",
1864			.ops = &clk_branch2_ops,
1865		},
1866	},
1867};
1868
1869static struct clk_branch gcc_gpu_tcu_throttle_clk = {
1870	.halt_reg = 0x7d014,
1871	.halt_check = BRANCH_HALT_VOTED,
1872	.hwcg_reg = 0x7d014,
1873	.hwcg_bit = 1,
1874	.clkr = {
1875		.enable_reg = 0x7d014,
1876		.enable_mask = BIT(0),
1877		.hw.init = &(const struct clk_init_data) {
1878			.name = "gcc_gpu_tcu_throttle_clk",
1879			.ops = &clk_branch2_ops,
1880		},
1881	},
1882};
1883
1884static struct clk_branch gcc_pcie_0_aux_clk = {
1885	.halt_reg = 0xa9038,
1886	.halt_check = BRANCH_HALT_VOTED,
1887	.clkr = {
1888		.enable_reg = 0x4b010,
1889		.enable_mask = BIT(16),
1890		.hw.init = &(const struct clk_init_data) {
1891			.name = "gcc_pcie_0_aux_clk",
1892			.parent_hws = (const struct clk_hw*[]) {
1893				&gcc_pcie_0_aux_clk_src.clkr.hw,
1894			},
1895			.num_parents = 1,
1896			.flags = CLK_SET_RATE_PARENT,
1897			.ops = &clk_branch2_ops,
1898		},
1899	},
1900};
1901
1902static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1903	.halt_reg = 0xa902c,
1904	.halt_check = BRANCH_HALT_VOTED,
1905	.hwcg_reg = 0xa902c,
1906	.hwcg_bit = 1,
1907	.clkr = {
1908		.enable_reg = 0x4b010,
1909		.enable_mask = BIT(12),
1910		.hw.init = &(const struct clk_init_data) {
1911			.name = "gcc_pcie_0_cfg_ahb_clk",
1912			.ops = &clk_branch2_ops,
1913		},
1914	},
1915};
1916
1917static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1918	.halt_reg = 0xa9024,
1919	.halt_check = BRANCH_HALT_VOTED,
1920	.clkr = {
1921		.enable_reg = 0x4b010,
1922		.enable_mask = BIT(11),
1923		.hw.init = &(const struct clk_init_data) {
1924			.name = "gcc_pcie_0_mstr_axi_clk",
1925			.ops = &clk_branch2_ops,
1926		},
1927	},
1928};
1929
1930static struct clk_branch gcc_pcie_0_phy_aux_clk = {
1931	.halt_reg = 0xa9030,
1932	.halt_check = BRANCH_HALT_VOTED,
1933	.clkr = {
1934		.enable_reg = 0x4b010,
1935		.enable_mask = BIT(13),
1936		.hw.init = &(const struct clk_init_data) {
1937			.name = "gcc_pcie_0_phy_aux_clk",
1938			.parent_hws = (const struct clk_hw*[]) {
1939				&gcc_pcie_0_phy_aux_clk_src.clkr.hw,
1940			},
1941			.num_parents = 1,
1942			.flags = CLK_SET_RATE_PARENT,
1943			.ops = &clk_branch2_ops,
1944		},
1945	},
1946};
1947
1948static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1949	.halt_reg = 0xa9050,
1950	.halt_check = BRANCH_HALT_VOTED,
1951	.clkr = {
1952		.enable_reg = 0x4b010,
1953		.enable_mask = BIT(15),
1954		.hw.init = &(const struct clk_init_data) {
1955			.name = "gcc_pcie_0_phy_rchng_clk",
1956			.parent_hws = (const struct clk_hw*[]) {
1957				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1958			},
1959			.num_parents = 1,
1960			.flags = CLK_SET_RATE_PARENT,
1961			.ops = &clk_branch2_ops,
1962		},
1963	},
1964};
1965
1966static struct clk_branch gcc_pcie_0_pipe_clk = {
1967	.halt_reg = 0xa9040,
1968	.halt_check = BRANCH_HALT_SKIP,
1969	.clkr = {
1970		.enable_reg = 0x4b010,
1971		.enable_mask = BIT(14),
1972		.hw.init = &(const struct clk_init_data) {
1973			.name = "gcc_pcie_0_pipe_clk",
1974			.parent_hws = (const struct clk_hw*[]) {
1975				&gcc_pcie_0_pipe_clk_src.clkr.hw,
1976			},
1977			.num_parents = 1,
1978			.flags = CLK_SET_RATE_PARENT,
1979			.ops = &clk_branch2_ops,
1980		},
1981	},
1982};
1983
1984static struct clk_branch gcc_pcie_0_pipediv2_clk = {
1985	.halt_reg = 0xa9048,
1986	.halt_check = BRANCH_HALT_SKIP,
1987	.clkr = {
1988		.enable_reg = 0x4b018,
1989		.enable_mask = BIT(22),
1990		.hw.init = &(const struct clk_init_data) {
1991			.name = "gcc_pcie_0_pipediv2_clk",
1992			.parent_hws = (const struct clk_hw*[]) {
1993				&gcc_pcie_0_pipe_div_clk_src.clkr.hw,
1994			},
1995			.num_parents = 1,
1996			.flags = CLK_SET_RATE_PARENT,
1997			.ops = &clk_branch2_ops,
1998		},
1999	},
2000};
2001
2002static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2003	.halt_reg = 0xa901c,
2004	.halt_check = BRANCH_HALT_VOTED,
2005	.clkr = {
2006		.enable_reg = 0x4b010,
2007		.enable_mask = BIT(10),
2008		.hw.init = &(const struct clk_init_data) {
2009			.name = "gcc_pcie_0_slv_axi_clk",
2010			.ops = &clk_branch2_ops,
2011		},
2012	},
2013};
2014
2015static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2016	.halt_reg = 0xa9018,
2017	.halt_check = BRANCH_HALT_VOTED,
2018	.clkr = {
2019		.enable_reg = 0x4b018,
2020		.enable_mask = BIT(12),
2021		.hw.init = &(const struct clk_init_data) {
2022			.name = "gcc_pcie_0_slv_q2a_axi_clk",
2023			.ops = &clk_branch2_ops,
2024		},
2025	},
2026};
2027
2028static struct clk_branch gcc_pcie_1_aux_clk = {
2029	.halt_reg = 0x77038,
2030	.halt_check = BRANCH_HALT_VOTED,
2031	.clkr = {
2032		.enable_reg = 0x4b000,
2033		.enable_mask = BIT(31),
2034		.hw.init = &(const struct clk_init_data) {
2035			.name = "gcc_pcie_1_aux_clk",
2036			.parent_hws = (const struct clk_hw*[]) {
2037				&gcc_pcie_1_aux_clk_src.clkr.hw,
2038			},
2039			.num_parents = 1,
2040			.flags = CLK_SET_RATE_PARENT,
2041			.ops = &clk_branch2_ops,
2042		},
2043	},
2044};
2045
2046static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2047	.halt_reg = 0x7702c,
2048	.halt_check = BRANCH_HALT_VOTED,
2049	.hwcg_reg = 0x7702c,
2050	.hwcg_bit = 1,
2051	.clkr = {
2052		.enable_reg = 0x4b008,
2053		.enable_mask = BIT(2),
2054		.hw.init = &(const struct clk_init_data) {
2055			.name = "gcc_pcie_1_cfg_ahb_clk",
2056			.ops = &clk_branch2_ops,
2057		},
2058	},
2059};
2060
2061static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2062	.halt_reg = 0x77024,
2063	.halt_check = BRANCH_HALT_VOTED,
2064	.clkr = {
2065		.enable_reg = 0x4b008,
2066		.enable_mask = BIT(1),
2067		.hw.init = &(const struct clk_init_data) {
2068			.name = "gcc_pcie_1_mstr_axi_clk",
2069			.ops = &clk_branch2_ops,
2070		},
2071	},
2072};
2073
2074static struct clk_branch gcc_pcie_1_phy_aux_clk = {
2075	.halt_reg = 0x77030,
2076	.halt_check = BRANCH_HALT_VOTED,
2077	.clkr = {
2078		.enable_reg = 0x4b008,
2079		.enable_mask = BIT(3),
2080		.hw.init = &(const struct clk_init_data) {
2081			.name = "gcc_pcie_1_phy_aux_clk",
2082			.parent_hws = (const struct clk_hw*[]) {
2083				&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
2084			},
2085			.num_parents = 1,
2086			.flags = CLK_SET_RATE_PARENT,
2087			.ops = &clk_branch2_ops,
2088		},
2089	},
2090};
2091
2092static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
2093	.halt_reg = 0x77050,
2094	.halt_check = BRANCH_HALT_VOTED,
2095	.clkr = {
2096		.enable_reg = 0x4b000,
2097		.enable_mask = BIT(22),
2098		.hw.init = &(const struct clk_init_data) {
2099			.name = "gcc_pcie_1_phy_rchng_clk",
2100			.parent_hws = (const struct clk_hw*[]) {
2101				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
2102			},
2103			.num_parents = 1,
2104			.flags = CLK_SET_RATE_PARENT,
2105			.ops = &clk_branch2_ops,
2106		},
2107	},
2108};
2109
2110static struct clk_branch gcc_pcie_1_pipe_clk = {
2111	.halt_reg = 0x77040,
2112	.halt_check = BRANCH_HALT_SKIP,
2113	.clkr = {
2114		.enable_reg = 0x4b008,
2115		.enable_mask = BIT(4),
2116		.hw.init = &(const struct clk_init_data) {
2117			.name = "gcc_pcie_1_pipe_clk",
2118			.parent_hws = (const struct clk_hw*[]) {
2119				&gcc_pcie_1_pipe_clk_src.clkr.hw,
2120			},
2121			.num_parents = 1,
2122			.flags = CLK_SET_RATE_PARENT,
2123			.ops = &clk_branch2_ops,
2124		},
2125	},
2126};
2127
2128static struct clk_branch gcc_pcie_1_pipediv2_clk = {
2129	.halt_reg = 0x77048,
2130	.halt_check = BRANCH_HALT_SKIP,
2131	.clkr = {
2132		.enable_reg = 0x4b018,
2133		.enable_mask = BIT(16),
2134		.hw.init = &(const struct clk_init_data) {
2135			.name = "gcc_pcie_1_pipediv2_clk",
2136			.parent_hws = (const struct clk_hw*[]) {
2137				&gcc_pcie_1_pipe_div_clk_src.clkr.hw,
2138			},
2139			.num_parents = 1,
2140			.flags = CLK_SET_RATE_PARENT,
2141			.ops = &clk_branch2_ops,
2142		},
2143	},
2144};
2145
2146static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2147	.halt_reg = 0x7701c,
2148	.halt_check = BRANCH_HALT_VOTED,
2149	.clkr = {
2150		.enable_reg = 0x4b008,
2151		.enable_mask = BIT(0),
2152		.hw.init = &(const struct clk_init_data) {
2153			.name = "gcc_pcie_1_slv_axi_clk",
2154			.ops = &clk_branch2_ops,
2155		},
2156	},
2157};
2158
2159static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2160	.halt_reg = 0x77018,
2161	.halt_check = BRANCH_HALT_VOTED,
2162	.clkr = {
2163		.enable_reg = 0x4b008,
2164		.enable_mask = BIT(5),
2165		.hw.init = &(const struct clk_init_data) {
2166			.name = "gcc_pcie_1_slv_q2a_axi_clk",
2167			.ops = &clk_branch2_ops,
2168		},
2169	},
2170};
2171
2172static struct clk_branch gcc_pcie_clkref_en = {
2173	.halt_reg = 0x9746c,
2174	.halt_check = BRANCH_HALT_DELAY,
2175	.clkr = {
2176		.enable_reg = 0x9746c,
2177		.enable_mask = BIT(0),
2178		.hw.init = &(const struct clk_init_data) {
2179			.name = "gcc_pcie_clkref_en",
2180			.ops = &clk_branch2_ops,
2181		},
2182	},
2183};
2184
2185static struct clk_branch gcc_pcie_throttle_cfg_clk = {
2186	.halt_reg = 0xb2034,
2187	.halt_check = BRANCH_HALT_VOTED,
2188	.clkr = {
2189		.enable_reg = 0x4b020,
2190		.enable_mask = BIT(15),
2191		.hw.init = &(const struct clk_init_data) {
2192			.name = "gcc_pcie_throttle_cfg_clk",
2193			.ops = &clk_branch2_ops,
2194		},
2195	},
2196};
2197
2198static struct clk_branch gcc_pdm2_clk = {
2199	.halt_reg = 0x3f00c,
2200	.halt_check = BRANCH_HALT,
2201	.clkr = {
2202		.enable_reg = 0x3f00c,
2203		.enable_mask = BIT(0),
2204		.hw.init = &(const struct clk_init_data) {
2205			.name = "gcc_pdm2_clk",
2206			.parent_hws = (const struct clk_hw*[]) {
2207				&gcc_pdm2_clk_src.clkr.hw,
2208			},
2209			.num_parents = 1,
2210			.flags = CLK_SET_RATE_PARENT,
2211			.ops = &clk_branch2_ops,
2212		},
2213	},
2214};
2215
2216static struct clk_branch gcc_pdm_ahb_clk = {
2217	.halt_reg = 0x3f004,
2218	.halt_check = BRANCH_HALT_VOTED,
2219	.hwcg_reg = 0x3f004,
2220	.hwcg_bit = 1,
2221	.clkr = {
2222		.enable_reg = 0x3f004,
2223		.enable_mask = BIT(0),
2224		.hw.init = &(const struct clk_init_data) {
2225			.name = "gcc_pdm_ahb_clk",
2226			.ops = &clk_branch2_ops,
2227		},
2228	},
2229};
2230
2231static struct clk_branch gcc_pdm_xo4_clk = {
2232	.halt_reg = 0x3f008,
2233	.halt_check = BRANCH_HALT,
2234	.clkr = {
2235		.enable_reg = 0x3f008,
2236		.enable_mask = BIT(0),
2237		.hw.init = &(const struct clk_init_data) {
2238			.name = "gcc_pdm_xo4_clk",
2239			.ops = &clk_branch2_ops,
2240		},
2241	},
2242};
2243
2244static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2245	.halt_reg = 0x32008,
2246	.halt_check = BRANCH_HALT_VOTED,
2247	.hwcg_reg = 0x32008,
2248	.hwcg_bit = 1,
2249	.clkr = {
2250		.enable_reg = 0x32008,
2251		.enable_mask = BIT(0),
2252		.hw.init = &(const struct clk_init_data) {
2253			.name = "gcc_qmip_camera_nrt_ahb_clk",
2254			.ops = &clk_branch2_ops,
2255		},
2256	},
2257};
2258
2259static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2260	.halt_reg = 0x3200c,
2261	.halt_check = BRANCH_HALT_VOTED,
2262	.hwcg_reg = 0x3200c,
2263	.hwcg_bit = 1,
2264	.clkr = {
2265		.enable_reg = 0x3200c,
2266		.enable_mask = BIT(0),
2267		.hw.init = &(const struct clk_init_data) {
2268			.name = "gcc_qmip_camera_rt_ahb_clk",
2269			.ops = &clk_branch2_ops,
2270		},
2271	},
2272};
2273
2274static struct clk_branch gcc_qmip_disp_ahb_clk = {
2275	.halt_reg = 0x33008,
2276	.halt_check = BRANCH_HALT_VOTED,
2277	.hwcg_reg = 0x33008,
2278	.hwcg_bit = 1,
2279	.clkr = {
2280		.enable_reg = 0x33008,
2281		.enable_mask = BIT(0),
2282		.hw.init = &(const struct clk_init_data) {
2283			.name = "gcc_qmip_disp_ahb_clk",
2284			.ops = &clk_branch2_ops,
2285		},
2286	},
2287};
2288
2289static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {
2290	.halt_reg = 0x3300c,
2291	.halt_check = BRANCH_HALT_VOTED,
2292	.clkr = {
2293		.enable_reg = 0x3300c,
2294		.enable_mask = BIT(0),
2295		.hw.init = &(const struct clk_init_data) {
2296			.name = "gcc_qmip_disp_rot_ahb_clk",
2297			.ops = &clk_branch2_ops,
2298		},
2299	},
2300};
2301
2302static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2303	.halt_reg = 0x34008,
2304	.halt_check = BRANCH_HALT_VOTED,
2305	.hwcg_reg = 0x34008,
2306	.hwcg_bit = 1,
2307	.clkr = {
2308		.enable_reg = 0x34008,
2309		.enable_mask = BIT(0),
2310		.hw.init = &(const struct clk_init_data) {
2311			.name = "gcc_qmip_video_cvp_ahb_clk",
2312			.ops = &clk_branch2_ops,
2313		},
2314	},
2315};
2316
2317static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2318	.halt_reg = 0x3400c,
2319	.halt_check = BRANCH_HALT_VOTED,
2320	.hwcg_reg = 0x3400c,
2321	.hwcg_bit = 1,
2322	.clkr = {
2323		.enable_reg = 0x3400c,
2324		.enable_mask = BIT(0),
2325		.hw.init = &(const struct clk_init_data) {
2326			.name = "gcc_qmip_video_vcodec_ahb_clk",
2327			.ops = &clk_branch2_ops,
2328		},
2329	},
2330};
2331
2332static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = {
2333	.halt_reg = 0x34010,
2334	.halt_check = BRANCH_HALT_VOTED,
2335	.hwcg_reg = 0x34010,
2336	.hwcg_bit = 1,
2337	.clkr = {
2338		.enable_reg = 0x34010,
2339		.enable_mask = BIT(0),
2340		.hw.init = &(const struct clk_init_data) {
2341			.name = "gcc_qmip_video_vcpu_ahb_clk",
2342			.ops = &clk_branch2_ops,
2343		},
2344	},
2345};
2346
2347static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2348	.halt_reg = 0x23018,
2349	.halt_check = BRANCH_HALT_VOTED,
2350	.clkr = {
2351		.enable_reg = 0x4b008,
2352		.enable_mask = BIT(9),
2353		.hw.init = &(const struct clk_init_data) {
2354			.name = "gcc_qupv3_wrap0_core_2x_clk",
2355			.ops = &clk_branch2_ops,
2356		},
2357	},
2358};
2359
2360static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2361	.halt_reg = 0x2300c,
2362	.halt_check = BRANCH_HALT_VOTED,
2363	.clkr = {
2364		.enable_reg = 0x4b008,
2365		.enable_mask = BIT(8),
2366		.hw.init = &(const struct clk_init_data) {
2367			.name = "gcc_qupv3_wrap0_core_clk",
2368			.ops = &clk_branch2_ops,
2369		},
2370	},
2371};
2372
2373static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2374	.halt_reg = 0x2314c,
2375	.halt_check = BRANCH_HALT_VOTED,
2376	.clkr = {
2377		.enable_reg = 0x4b008,
2378		.enable_mask = BIT(10),
2379		.hw.init = &(const struct clk_init_data) {
2380			.name = "gcc_qupv3_wrap0_s0_clk",
2381			.parent_hws = (const struct clk_hw*[]) {
2382				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2383			},
2384			.num_parents = 1,
2385			.flags = CLK_SET_RATE_PARENT,
2386			.ops = &clk_branch2_ops,
2387		},
2388	},
2389};
2390
2391static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2392	.halt_reg = 0x23280,
2393	.halt_check = BRANCH_HALT_VOTED,
2394	.clkr = {
2395		.enable_reg = 0x4b008,
2396		.enable_mask = BIT(11),
2397		.hw.init = &(const struct clk_init_data) {
2398			.name = "gcc_qupv3_wrap0_s1_clk",
2399			.parent_hws = (const struct clk_hw*[]) {
2400				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2401			},
2402			.num_parents = 1,
2403			.flags = CLK_SET_RATE_PARENT,
2404			.ops = &clk_branch2_ops,
2405		},
2406	},
2407};
2408
2409static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2410	.halt_reg = 0x233b4,
2411	.halt_check = BRANCH_HALT_VOTED,
2412	.clkr = {
2413		.enable_reg = 0x4b008,
2414		.enable_mask = BIT(12),
2415		.hw.init = &(const struct clk_init_data) {
2416			.name = "gcc_qupv3_wrap0_s2_clk",
2417			.parent_hws = (const struct clk_hw*[]) {
2418				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2419			},
2420			.num_parents = 1,
2421			.flags = CLK_SET_RATE_PARENT,
2422			.ops = &clk_branch2_ops,
2423		},
2424	},
2425};
2426
2427static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2428	.halt_reg = 0x234e8,
2429	.halt_check = BRANCH_HALT_VOTED,
2430	.clkr = {
2431		.enable_reg = 0x4b008,
2432		.enable_mask = BIT(13),
2433		.hw.init = &(const struct clk_init_data) {
2434			.name = "gcc_qupv3_wrap0_s3_clk",
2435			.parent_hws = (const struct clk_hw*[]) {
2436				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2437			},
2438			.num_parents = 1,
2439			.flags = CLK_SET_RATE_PARENT,
2440			.ops = &clk_branch2_ops,
2441		},
2442	},
2443};
2444
2445static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2446	.halt_reg = 0x2361c,
2447	.halt_check = BRANCH_HALT_VOTED,
2448	.clkr = {
2449		.enable_reg = 0x4b008,
2450		.enable_mask = BIT(14),
2451		.hw.init = &(const struct clk_init_data) {
2452			.name = "gcc_qupv3_wrap0_s4_clk",
2453			.parent_hws = (const struct clk_hw*[]) {
2454				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2455			},
2456			.num_parents = 1,
2457			.flags = CLK_SET_RATE_PARENT,
2458			.ops = &clk_branch2_ops,
2459		},
2460	},
2461};
2462
2463static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2464	.halt_reg = 0x23750,
2465	.halt_check = BRANCH_HALT_VOTED,
2466	.clkr = {
2467		.enable_reg = 0x4b008,
2468		.enable_mask = BIT(15),
2469		.hw.init = &(const struct clk_init_data) {
2470			.name = "gcc_qupv3_wrap0_s5_clk",
2471			.parent_hws = (const struct clk_hw*[]) {
2472				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2473			},
2474			.num_parents = 1,
2475			.flags = CLK_SET_RATE_PARENT,
2476			.ops = &clk_branch2_ops,
2477		},
2478	},
2479};
2480
2481static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2482	.halt_reg = 0x23884,
2483	.halt_check = BRANCH_HALT_VOTED,
2484	.clkr = {
2485		.enable_reg = 0x4b008,
2486		.enable_mask = BIT(16),
2487		.hw.init = &(const struct clk_init_data) {
2488			.name = "gcc_qupv3_wrap0_s6_clk",
2489			.parent_hws = (const struct clk_hw*[]) {
2490				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2491			},
2492			.num_parents = 1,
2493			.flags = CLK_SET_RATE_PARENT,
2494			.ops = &clk_branch2_ops,
2495		},
2496	},
2497};
2498
2499static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2500	.halt_reg = 0x239b8,
2501	.halt_check = BRANCH_HALT_VOTED,
2502	.clkr = {
2503		.enable_reg = 0x4b008,
2504		.enable_mask = BIT(17),
2505		.hw.init = &(const struct clk_init_data) {
2506			.name = "gcc_qupv3_wrap0_s7_clk",
2507			.parent_hws = (const struct clk_hw*[]) {
2508				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2509			},
2510			.num_parents = 1,
2511			.flags = CLK_SET_RATE_PARENT,
2512			.ops = &clk_branch2_ops,
2513		},
2514	},
2515};
2516
2517static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2518	.halt_reg = 0x24018,
2519	.halt_check = BRANCH_HALT_VOTED,
2520	.clkr = {
2521		.enable_reg = 0x4b008,
2522		.enable_mask = BIT(18),
2523		.hw.init = &(const struct clk_init_data) {
2524			.name = "gcc_qupv3_wrap1_core_2x_clk",
2525			.ops = &clk_branch2_ops,
2526		},
2527	},
2528};
2529
2530static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2531	.halt_reg = 0x2400c,
2532	.halt_check = BRANCH_HALT_VOTED,
2533	.clkr = {
2534		.enable_reg = 0x4b008,
2535		.enable_mask = BIT(19),
2536		.hw.init = &(const struct clk_init_data) {
2537			.name = "gcc_qupv3_wrap1_core_clk",
2538			.ops = &clk_branch2_ops,
2539		},
2540	},
2541};
2542
2543static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2544	.halt_reg = 0x2414c,
2545	.halt_check = BRANCH_HALT_VOTED,
2546	.clkr = {
2547		.enable_reg = 0x4b008,
2548		.enable_mask = BIT(22),
2549		.hw.init = &(const struct clk_init_data) {
2550			.name = "gcc_qupv3_wrap1_s0_clk",
2551			.parent_hws = (const struct clk_hw*[]) {
2552				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2553			},
2554			.num_parents = 1,
2555			.flags = CLK_SET_RATE_PARENT,
2556			.ops = &clk_branch2_ops,
2557		},
2558	},
2559};
2560
2561static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2562	.halt_reg = 0x24280,
2563	.halt_check = BRANCH_HALT_VOTED,
2564	.clkr = {
2565		.enable_reg = 0x4b008,
2566		.enable_mask = BIT(23),
2567		.hw.init = &(const struct clk_init_data) {
2568			.name = "gcc_qupv3_wrap1_s1_clk",
2569			.parent_hws = (const struct clk_hw*[]) {
2570				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2571			},
2572			.num_parents = 1,
2573			.flags = CLK_SET_RATE_PARENT,
2574			.ops = &clk_branch2_ops,
2575		},
2576	},
2577};
2578
2579static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2580	.halt_reg = 0x243b4,
2581	.halt_check = BRANCH_HALT_VOTED,
2582	.clkr = {
2583		.enable_reg = 0x4b008,
2584		.enable_mask = BIT(24),
2585		.hw.init = &(const struct clk_init_data) {
2586			.name = "gcc_qupv3_wrap1_s2_clk",
2587			.parent_hws = (const struct clk_hw*[]) {
2588				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2589			},
2590			.num_parents = 1,
2591			.flags = CLK_SET_RATE_PARENT,
2592			.ops = &clk_branch2_ops,
2593		},
2594	},
2595};
2596
2597static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2598	.halt_reg = 0x244e8,
2599	.halt_check = BRANCH_HALT_VOTED,
2600	.clkr = {
2601		.enable_reg = 0x4b008,
2602		.enable_mask = BIT(25),
2603		.hw.init = &(const struct clk_init_data) {
2604			.name = "gcc_qupv3_wrap1_s3_clk",
2605			.parent_hws = (const struct clk_hw*[]) {
2606				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2607			},
2608			.num_parents = 1,
2609			.flags = CLK_SET_RATE_PARENT,
2610			.ops = &clk_branch2_ops,
2611		},
2612	},
2613};
2614
2615static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2616	.halt_reg = 0x2461c,
2617	.halt_check = BRANCH_HALT_VOTED,
2618	.clkr = {
2619		.enable_reg = 0x4b008,
2620		.enable_mask = BIT(26),
2621		.hw.init = &(const struct clk_init_data) {
2622			.name = "gcc_qupv3_wrap1_s4_clk",
2623			.parent_hws = (const struct clk_hw*[]) {
2624				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2625			},
2626			.num_parents = 1,
2627			.flags = CLK_SET_RATE_PARENT,
2628			.ops = &clk_branch2_ops,
2629		},
2630	},
2631};
2632
2633static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2634	.halt_reg = 0x24750,
2635	.halt_check = BRANCH_HALT_VOTED,
2636	.clkr = {
2637		.enable_reg = 0x4b008,
2638		.enable_mask = BIT(27),
2639		.hw.init = &(const struct clk_init_data) {
2640			.name = "gcc_qupv3_wrap1_s5_clk",
2641			.parent_hws = (const struct clk_hw*[]) {
2642				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2643			},
2644			.num_parents = 1,
2645			.flags = CLK_SET_RATE_PARENT,
2646			.ops = &clk_branch2_ops,
2647		},
2648	},
2649};
2650
2651static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2652	.halt_reg = 0x24884,
2653	.halt_check = BRANCH_HALT_VOTED,
2654	.clkr = {
2655		.enable_reg = 0x4b018,
2656		.enable_mask = BIT(27),
2657		.hw.init = &(const struct clk_init_data) {
2658			.name = "gcc_qupv3_wrap1_s6_clk",
2659			.parent_hws = (const struct clk_hw*[]) {
2660				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2661			},
2662			.num_parents = 1,
2663			.flags = CLK_SET_RATE_PARENT,
2664			.ops = &clk_branch2_ops,
2665		},
2666	},
2667};
2668
2669static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2670	.halt_reg = 0x249b8,
2671	.halt_check = BRANCH_HALT_VOTED,
2672	.clkr = {
2673		.enable_reg = 0x4b018,
2674		.enable_mask = BIT(28),
2675		.hw.init = &(const struct clk_init_data) {
2676			.name = "gcc_qupv3_wrap1_s7_clk",
2677			.parent_hws = (const struct clk_hw*[]) {
2678				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2679			},
2680			.num_parents = 1,
2681			.flags = CLK_SET_RATE_PARENT,
2682			.ops = &clk_branch2_ops,
2683		},
2684	},
2685};
2686
2687static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
2688	.halt_reg = 0xc4018,
2689	.halt_check = BRANCH_HALT_VOTED,
2690	.clkr = {
2691		.enable_reg = 0x4b000,
2692		.enable_mask = BIT(24),
2693		.hw.init = &(const struct clk_init_data) {
2694			.name = "gcc_qupv3_wrap3_core_2x_clk",
2695			.ops = &clk_branch2_ops,
2696		},
2697	},
2698};
2699
2700static struct clk_branch gcc_qupv3_wrap3_core_clk = {
2701	.halt_reg = 0xc400c,
2702	.halt_check = BRANCH_HALT_VOTED,
2703	.clkr = {
2704		.enable_reg = 0x4b000,
2705		.enable_mask = BIT(23),
2706		.hw.init = &(const struct clk_init_data) {
2707			.name = "gcc_qupv3_wrap3_core_clk",
2708			.ops = &clk_branch2_ops,
2709		},
2710	},
2711};
2712
2713static struct clk_branch gcc_qupv3_wrap3_qspi_clk = {
2714	.halt_reg = 0xc4284,
2715	.halt_check = BRANCH_HALT_VOTED,
2716	.clkr = {
2717		.enable_reg = 0x4b000,
2718		.enable_mask = BIT(26),
2719		.hw.init = &(const struct clk_init_data) {
2720			.name = "gcc_qupv3_wrap3_qspi_clk",
2721			.parent_hws = (const struct clk_hw*[]) {
2722				&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
2723			},
2724			.num_parents = 1,
2725			.flags = CLK_SET_RATE_PARENT,
2726			.ops = &clk_branch2_ops,
2727		},
2728	},
2729};
2730
2731static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
2732	.halt_reg = 0xc4150,
2733	.halt_check = BRANCH_HALT_VOTED,
2734	.clkr = {
2735		.enable_reg = 0x4b000,
2736		.enable_mask = BIT(25),
2737		.hw.init = &(const struct clk_init_data) {
2738			.name = "gcc_qupv3_wrap3_s0_clk",
2739			.parent_hws = (const struct clk_hw*[]) {
2740				&gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw,
2741			},
2742			.num_parents = 1,
2743			.flags = CLK_SET_RATE_PARENT,
2744			.ops = &clk_branch2_ops,
2745		},
2746	},
2747};
2748
2749static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2750	.halt_reg = 0x23004,
2751	.halt_check = BRANCH_HALT_VOTED,
2752	.hwcg_reg = 0x23004,
2753	.hwcg_bit = 1,
2754	.clkr = {
2755		.enable_reg = 0x4b008,
2756		.enable_mask = BIT(6),
2757		.hw.init = &(const struct clk_init_data) {
2758			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2759			.ops = &clk_branch2_ops,
2760		},
2761	},
2762};
2763
2764static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2765	.halt_reg = 0x23008,
2766	.halt_check = BRANCH_HALT_VOTED,
2767	.hwcg_reg = 0x23008,
2768	.hwcg_bit = 1,
2769	.clkr = {
2770		.enable_reg = 0x4b008,
2771		.enable_mask = BIT(7),
2772		.hw.init = &(const struct clk_init_data) {
2773			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2774			.ops = &clk_branch2_ops,
2775		},
2776	},
2777};
2778
2779static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2780	.halt_reg = 0x24004,
2781	.halt_check = BRANCH_HALT_VOTED,
2782	.hwcg_reg = 0x24004,
2783	.hwcg_bit = 1,
2784	.clkr = {
2785		.enable_reg = 0x4b008,
2786		.enable_mask = BIT(20),
2787		.hw.init = &(const struct clk_init_data) {
2788			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2789			.ops = &clk_branch2_ops,
2790		},
2791	},
2792};
2793
2794static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2795	.halt_reg = 0x24008,
2796	.halt_check = BRANCH_HALT_VOTED,
2797	.hwcg_reg = 0x24008,
2798	.hwcg_bit = 1,
2799	.clkr = {
2800		.enable_reg = 0x4b008,
2801		.enable_mask = BIT(21),
2802		.hw.init = &(const struct clk_init_data) {
2803			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2804			.ops = &clk_branch2_ops,
2805		},
2806	},
2807};
2808
2809static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = {
2810	.halt_reg = 0xc4004,
2811	.halt_check = BRANCH_HALT_VOTED,
2812	.hwcg_reg = 0xc4004,
2813	.hwcg_bit = 1,
2814	.clkr = {
2815		.enable_reg = 0x4b000,
2816		.enable_mask = BIT(27),
2817		.hw.init = &(const struct clk_init_data) {
2818			.name = "gcc_qupv3_wrap_3_m_ahb_clk",
2819			.ops = &clk_branch2_ops,
2820		},
2821	},
2822};
2823
2824static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = {
2825	.halt_reg = 0xc4008,
2826	.halt_check = BRANCH_HALT_VOTED,
2827	.hwcg_reg = 0xc4008,
2828	.hwcg_bit = 1,
2829	.clkr = {
2830		.enable_reg = 0x4b000,
2831		.enable_mask = BIT(20),
2832		.hw.init = &(const struct clk_init_data) {
2833			.name = "gcc_qupv3_wrap_3_s_ahb_clk",
2834			.ops = &clk_branch2_ops,
2835		},
2836	},
2837};
2838
2839static struct clk_branch gcc_sdcc1_ahb_clk = {
2840	.halt_reg = 0x2000c,
2841	.halt_check = BRANCH_HALT,
2842	.clkr = {
2843		.enable_reg = 0x2000c,
2844		.enable_mask = BIT(0),
2845		.hw.init = &(const struct clk_init_data) {
2846			.name = "gcc_sdcc1_ahb_clk",
2847			.ops = &clk_branch2_ops,
2848		},
2849	},
2850};
2851
2852static struct clk_branch gcc_sdcc1_apps_clk = {
2853	.halt_reg = 0x20004,
2854	.halt_check = BRANCH_HALT,
2855	.clkr = {
2856		.enable_reg = 0x20004,
2857		.enable_mask = BIT(0),
2858		.hw.init = &(const struct clk_init_data) {
2859			.name = "gcc_sdcc1_apps_clk",
2860			.parent_hws = (const struct clk_hw*[]) {
2861				&gcc_sdcc1_apps_clk_src.clkr.hw,
2862			},
2863			.num_parents = 1,
2864			.flags = CLK_SET_RATE_PARENT,
2865			.ops = &clk_branch2_ops,
2866		},
2867	},
2868};
2869
2870static struct clk_branch gcc_sdcc1_ice_core_clk = {
2871	.halt_reg = 0x20044,
2872	.halt_check = BRANCH_HALT_VOTED,
2873	.hwcg_reg = 0x20044,
2874	.hwcg_bit = 1,
2875	.clkr = {
2876		.enable_reg = 0x20044,
2877		.enable_mask = BIT(0),
2878		.hw.init = &(const struct clk_init_data) {
2879			.name = "gcc_sdcc1_ice_core_clk",
2880			.parent_hws = (const struct clk_hw*[]) {
2881				&gcc_sdcc1_ice_core_clk_src.clkr.hw,
2882			},
2883			.num_parents = 1,
2884			.flags = CLK_SET_RATE_PARENT,
2885			.ops = &clk_branch2_ops,
2886		},
2887	},
2888};
2889
2890static struct clk_branch gcc_sgmi_clkref_en = {
2891	.halt_reg = 0x97034,
2892	.halt_check = BRANCH_HALT_DELAY,
2893	.clkr = {
2894		.enable_reg = 0x97034,
2895		.enable_mask = BIT(0),
2896		.hw.init = &(const struct clk_init_data) {
2897			.name = "gcc_sgmi_clkref_en",
2898			.ops = &clk_branch2_ops,
2899		},
2900	},
2901};
2902
2903static struct clk_branch gcc_ufs_phy_ahb_clk = {
2904	.halt_reg = 0x83020,
2905	.halt_check = BRANCH_HALT_VOTED,
2906	.hwcg_reg = 0x83020,
2907	.hwcg_bit = 1,
2908	.clkr = {
2909		.enable_reg = 0x83020,
2910		.enable_mask = BIT(0),
2911		.hw.init = &(const struct clk_init_data) {
2912			.name = "gcc_ufs_phy_ahb_clk",
2913			.ops = &clk_branch2_ops,
2914		},
2915	},
2916};
2917
2918static struct clk_branch gcc_ufs_phy_axi_clk = {
2919	.halt_reg = 0x83018,
2920	.halt_check = BRANCH_HALT_VOTED,
2921	.hwcg_reg = 0x83018,
2922	.hwcg_bit = 1,
2923	.clkr = {
2924		.enable_reg = 0x83018,
2925		.enable_mask = BIT(0),
2926		.hw.init = &(const struct clk_init_data) {
2927			.name = "gcc_ufs_phy_axi_clk",
2928			.parent_hws = (const struct clk_hw*[]) {
2929				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2930			},
2931			.num_parents = 1,
2932			.flags = CLK_SET_RATE_PARENT,
2933			.ops = &clk_branch2_ops,
2934		},
2935	},
2936};
2937
2938static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2939	.halt_reg = 0x8306c,
2940	.halt_check = BRANCH_HALT_VOTED,
2941	.hwcg_reg = 0x8306c,
2942	.hwcg_bit = 1,
2943	.clkr = {
2944		.enable_reg = 0x8306c,
2945		.enable_mask = BIT(0),
2946		.hw.init = &(const struct clk_init_data) {
2947			.name = "gcc_ufs_phy_ice_core_clk",
2948			.parent_hws = (const struct clk_hw*[]) {
2949				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2950			},
2951			.num_parents = 1,
2952			.flags = CLK_SET_RATE_PARENT,
2953			.ops = &clk_branch2_ops,
2954		},
2955	},
2956};
2957
2958static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2959	.halt_reg = 0x830a4,
2960	.halt_check = BRANCH_HALT_VOTED,
2961	.hwcg_reg = 0x830a4,
2962	.hwcg_bit = 1,
2963	.clkr = {
2964		.enable_reg = 0x830a4,
2965		.enable_mask = BIT(0),
2966		.hw.init = &(const struct clk_init_data) {
2967			.name = "gcc_ufs_phy_phy_aux_clk",
2968			.parent_hws = (const struct clk_hw*[]) {
2969				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2970			},
2971			.num_parents = 1,
2972			.flags = CLK_SET_RATE_PARENT,
2973			.ops = &clk_branch2_ops,
2974		},
2975	},
2976};
2977
2978static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2979	.halt_reg = 0x83028,
2980	.halt_check = BRANCH_HALT_DELAY,
2981	.clkr = {
2982		.enable_reg = 0x83028,
2983		.enable_mask = BIT(0),
2984		.hw.init = &(const struct clk_init_data) {
2985			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2986			.parent_hws = (const struct clk_hw*[]) {
2987				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2988			},
2989			.num_parents = 1,
2990			.flags = CLK_SET_RATE_PARENT,
2991			.ops = &clk_branch2_ops,
2992		},
2993	},
2994};
2995
2996static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2997	.halt_reg = 0x830c0,
2998	.halt_check = BRANCH_HALT_DELAY,
2999	.clkr = {
3000		.enable_reg = 0x830c0,
3001		.enable_mask = BIT(0),
3002		.hw.init = &(const struct clk_init_data) {
3003			.name = "gcc_ufs_phy_rx_symbol_1_clk",
3004			.parent_hws = (const struct clk_hw*[]) {
3005				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3006			},
3007			.num_parents = 1,
3008			.flags = CLK_SET_RATE_PARENT,
3009			.ops = &clk_branch2_ops,
3010		},
3011	},
3012};
3013
3014static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3015	.halt_reg = 0x83024,
3016	.halt_check = BRANCH_HALT_DELAY,
3017	.clkr = {
3018		.enable_reg = 0x83024,
3019		.enable_mask = BIT(0),
3020		.hw.init = &(const struct clk_init_data) {
3021			.name = "gcc_ufs_phy_tx_symbol_0_clk",
3022			.parent_hws = (const struct clk_hw*[]) {
3023				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3024			},
3025			.num_parents = 1,
3026			.flags = CLK_SET_RATE_PARENT,
3027			.ops = &clk_branch2_ops,
3028		},
3029	},
3030};
3031
3032static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3033	.halt_reg = 0x83064,
3034	.halt_check = BRANCH_HALT_VOTED,
3035	.hwcg_reg = 0x83064,
3036	.hwcg_bit = 1,
3037	.clkr = {
3038		.enable_reg = 0x83064,
3039		.enable_mask = BIT(0),
3040		.hw.init = &(const struct clk_init_data) {
3041			.name = "gcc_ufs_phy_unipro_core_clk",
3042			.parent_hws = (const struct clk_hw*[]) {
3043				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3044			},
3045			.num_parents = 1,
3046			.flags = CLK_SET_RATE_PARENT,
3047			.ops = &clk_branch2_ops,
3048		},
3049	},
3050};
3051
3052static struct clk_branch gcc_usb20_master_clk = {
3053	.halt_reg = 0x1c018,
3054	.halt_check = BRANCH_HALT,
3055	.clkr = {
3056		.enable_reg = 0x1c018,
3057		.enable_mask = BIT(0),
3058		.hw.init = &(const struct clk_init_data) {
3059			.name = "gcc_usb20_master_clk",
3060			.parent_hws = (const struct clk_hw*[]) {
3061				&gcc_usb20_master_clk_src.clkr.hw,
3062			},
3063			.num_parents = 1,
3064			.flags = CLK_SET_RATE_PARENT,
3065			.ops = &clk_branch2_ops,
3066		},
3067	},
3068};
3069
3070static struct clk_branch gcc_usb20_mock_utmi_clk = {
3071	.halt_reg = 0x1c024,
3072	.halt_check = BRANCH_HALT,
3073	.clkr = {
3074		.enable_reg = 0x1c024,
3075		.enable_mask = BIT(0),
3076		.hw.init = &(const struct clk_init_data) {
3077			.name = "gcc_usb20_mock_utmi_clk",
3078			.parent_hws = (const struct clk_hw*[]) {
3079				&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
3080			},
3081			.num_parents = 1,
3082			.flags = CLK_SET_RATE_PARENT,
3083			.ops = &clk_branch2_ops,
3084		},
3085	},
3086};
3087
3088static struct clk_branch gcc_usb20_sleep_clk = {
3089	.halt_reg = 0x1c020,
3090	.halt_check = BRANCH_HALT,
3091	.clkr = {
3092		.enable_reg = 0x1c020,
3093		.enable_mask = BIT(0),
3094		.hw.init = &(const struct clk_init_data) {
3095			.name = "gcc_usb20_sleep_clk",
3096			.ops = &clk_branch2_ops,
3097		},
3098	},
3099};
3100
3101static struct clk_branch gcc_usb30_prim_master_clk = {
3102	.halt_reg = 0x1b018,
3103	.halt_check = BRANCH_HALT,
3104	.clkr = {
3105		.enable_reg = 0x1b018,
3106		.enable_mask = BIT(0),
3107		.hw.init = &(const struct clk_init_data) {
3108			.name = "gcc_usb30_prim_master_clk",
3109			.parent_hws = (const struct clk_hw*[]) {
3110				&gcc_usb30_prim_master_clk_src.clkr.hw,
3111			},
3112			.num_parents = 1,
3113			.flags = CLK_SET_RATE_PARENT,
3114			.ops = &clk_branch2_ops,
3115		},
3116	},
3117};
3118
3119static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3120	.halt_reg = 0x1b024,
3121	.halt_check = BRANCH_HALT,
3122	.clkr = {
3123		.enable_reg = 0x1b024,
3124		.enable_mask = BIT(0),
3125		.hw.init = &(const struct clk_init_data) {
3126			.name = "gcc_usb30_prim_mock_utmi_clk",
3127			.parent_hws = (const struct clk_hw*[]) {
3128				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3129			},
3130			.num_parents = 1,
3131			.flags = CLK_SET_RATE_PARENT,
3132			.ops = &clk_branch2_ops,
3133		},
3134	},
3135};
3136
3137static struct clk_branch gcc_usb30_prim_sleep_clk = {
3138	.halt_reg = 0x1b020,
3139	.halt_check = BRANCH_HALT,
3140	.clkr = {
3141		.enable_reg = 0x1b020,
3142		.enable_mask = BIT(0),
3143		.hw.init = &(const struct clk_init_data) {
3144			.name = "gcc_usb30_prim_sleep_clk",
3145			.ops = &clk_branch2_ops,
3146		},
3147	},
3148};
3149
3150static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3151	.halt_reg = 0x1b05c,
3152	.halt_check = BRANCH_HALT,
3153	.clkr = {
3154		.enable_reg = 0x1b05c,
3155		.enable_mask = BIT(0),
3156		.hw.init = &(const struct clk_init_data) {
3157			.name = "gcc_usb3_prim_phy_aux_clk",
3158			.parent_hws = (const struct clk_hw*[]) {
3159				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3160			},
3161			.num_parents = 1,
3162			.flags = CLK_SET_RATE_PARENT,
3163			.ops = &clk_branch2_ops,
3164		},
3165	},
3166};
3167
3168static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3169	.halt_reg = 0x1b060,
3170	.halt_check = BRANCH_HALT,
3171	.clkr = {
3172		.enable_reg = 0x1b060,
3173		.enable_mask = BIT(0),
3174		.hw.init = &(const struct clk_init_data) {
3175			.name = "gcc_usb3_prim_phy_com_aux_clk",
3176			.parent_hws = (const struct clk_hw*[]) {
3177				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3178			},
3179			.num_parents = 1,
3180			.flags = CLK_SET_RATE_PARENT,
3181			.ops = &clk_branch2_ops,
3182		},
3183	},
3184};
3185
3186static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3187	.halt_reg = 0x1b064,
3188	.halt_check = BRANCH_HALT_DELAY,
3189	.hwcg_reg = 0x1b064,
3190	.hwcg_bit = 1,
3191	.clkr = {
3192		.enable_reg = 0x1b064,
3193		.enable_mask = BIT(0),
3194		.hw.init = &(const struct clk_init_data) {
3195			.name = "gcc_usb3_prim_phy_pipe_clk",
3196			.parent_hws = (const struct clk_hw*[]) {
3197				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3198			},
3199			.num_parents = 1,
3200			.flags = CLK_SET_RATE_PARENT,
3201			.ops = &clk_branch2_ops,
3202		},
3203	},
3204};
3205
3206static struct clk_branch gcc_usb_clkref_en = {
3207	.halt_reg = 0x97468,
3208	.halt_check = BRANCH_HALT_DELAY,
3209	.clkr = {
3210		.enable_reg = 0x97468,
3211		.enable_mask = BIT(0),
3212		.hw.init = &(const struct clk_init_data) {
3213			.name = "gcc_usb_clkref_en",
3214			.ops = &clk_branch2_ops,
3215		},
3216	},
3217};
3218
3219static struct clk_branch gcc_video_axi0_clk = {
3220	.halt_reg = 0x34014,
3221	.halt_check = BRANCH_HALT_VOTED,
3222	.hwcg_reg = 0x34014,
3223	.hwcg_bit = 1,
3224	.clkr = {
3225		.enable_reg = 0x34014,
3226		.enable_mask = BIT(0),
3227		.hw.init = &(const struct clk_init_data) {
3228			.name = "gcc_video_axi0_clk",
3229			.ops = &clk_branch2_ops,
3230		},
3231	},
3232};
3233
3234static struct clk_branch gcc_video_axi1_clk = {
3235	.halt_reg = 0x3401c,
3236	.halt_check = BRANCH_HALT_VOTED,
3237	.hwcg_reg = 0x3401c,
3238	.hwcg_bit = 1,
3239	.clkr = {
3240		.enable_reg = 0x3401c,
3241		.enable_mask = BIT(0),
3242		.hw.init = &(const struct clk_init_data) {
3243			.name = "gcc_video_axi1_clk",
3244			.ops = &clk_branch2_ops,
3245		},
3246	},
3247};
3248
3249static struct gdsc gcc_emac0_gdsc = {
3250	.gdscr = 0xb6004,
3251	.en_rest_wait_val = 0x2,
3252	.en_few_wait_val = 0x2,
3253	.clk_dis_wait_val = 0xf,
3254	.pd = {
3255		.name = "gcc_emac0_gdsc",
3256	},
3257	.pwrsts = PWRSTS_OFF_ON,
3258	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3259};
3260
3261static struct gdsc gcc_pcie_0_gdsc = {
3262	.gdscr = 0xa9004,
3263	.collapse_ctrl = 0x4b104,
3264	.collapse_mask = BIT(0),
3265	.en_rest_wait_val = 0x2,
3266	.en_few_wait_val = 0x2,
3267	.clk_dis_wait_val = 0xf,
3268	.pd = {
3269		.name = "gcc_pcie_0_gdsc",
3270	},
3271	.pwrsts = PWRSTS_OFF_ON,
3272	.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
3273};
3274
3275static struct gdsc gcc_pcie_1_gdsc = {
3276	.gdscr = 0x77004,
3277	.collapse_ctrl = 0x4b104,
3278	.collapse_mask = BIT(1),
3279	.en_rest_wait_val = 0x2,
3280	.en_few_wait_val = 0x2,
3281	.clk_dis_wait_val = 0xf,
3282	.pd = {
3283		.name = "gcc_pcie_1_gdsc",
3284	},
3285	.pwrsts = PWRSTS_OFF_ON,
3286	.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
3287};
3288
3289static struct gdsc gcc_ufs_phy_gdsc = {
3290	.gdscr = 0x83004,
3291	.en_rest_wait_val = 0x2,
3292	.en_few_wait_val = 0x2,
3293	.clk_dis_wait_val = 0xf,
3294	.pd = {
3295		.name = "gcc_ufs_phy_gdsc",
3296	},
3297	.pwrsts = PWRSTS_OFF_ON,
3298	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
3299};
3300
3301static struct gdsc gcc_usb20_prim_gdsc = {
3302	.gdscr = 0x1c004,
3303	.en_rest_wait_val = 0x2,
3304	.en_few_wait_val = 0x2,
3305	.clk_dis_wait_val = 0xf,
3306	.pd = {
3307		.name = "gcc_usb20_prim_gdsc",
3308	},
3309	.pwrsts = PWRSTS_OFF_ON,
3310	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
3311};
3312
3313static struct gdsc gcc_usb30_prim_gdsc = {
3314	.gdscr = 0x1b004,
3315	.en_rest_wait_val = 0x2,
3316	.en_few_wait_val = 0x2,
3317	.clk_dis_wait_val = 0xf,
3318	.pd = {
3319		.name = "gcc_usb30_prim_gdsc",
3320	},
3321	.pwrsts = PWRSTS_OFF_ON,
3322	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
3323};
3324
3325static struct clk_regmap *gcc_qcs8300_clocks[] = {
3326	[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
3327	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3328	[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
3329	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3330	[GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,
3331	[GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,
3332	[GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr,
3333	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3334	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3335	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3336	[GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,
3337	[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
3338	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3339	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3340	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3341	[GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr,
3342	[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
3343	[GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,
3344	[GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,
3345	[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
3346	[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
3347	[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
3348	[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
3349	[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
3350	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3351	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3352	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3353	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3354	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3355	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3356	[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
3357	[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
3358	[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
3359	[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
3360	[GCC_GPLL0] = &gcc_gpll0.clkr,
3361	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3362	[GCC_GPLL1] = &gcc_gpll1.clkr,
3363	[GCC_GPLL4] = &gcc_gpll4.clkr,
3364	[GCC_GPLL7] = &gcc_gpll7.clkr,
3365	[GCC_GPLL9] = &gcc_gpll9.clkr,
3366	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3367	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3368	[GCC_GPU_MEMNOC_GFX_CENTER_PIPELINE_CLK] = &gcc_gpu_memnoc_gfx_center_pipeline_clk.clkr,
3369	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3370	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3371	[GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,
3372	[GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,
3373	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3374	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3375	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3376	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3377	[GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
3378	[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
3379	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3380	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3381	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3382	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3383	[GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr,
3384	[GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr,
3385	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3386	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3387	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3388	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3389	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3390	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3391	[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3392	[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3393	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3394	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3395	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3396	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3397	[GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr,
3398	[GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr,
3399	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3400	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3401	[GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
3402	[GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,
3403	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3404	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3405	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3406	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3407	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3408	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3409	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3410	[GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,
3411	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3412	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3413	[GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr,
3414	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3415	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3416	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3417	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3418	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3419	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3420	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3421	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3422	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3423	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3424	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3425	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3426	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3427	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3428	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3429	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3430	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3431	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3432	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3433	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3434	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3435	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3436	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3437	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3438	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3439	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3440	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3441	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3442	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3443	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3444	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3445	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3446	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3447	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3448	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3449	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3450	[GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
3451	[GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
3452	[GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr,
3453	[GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
3454	[GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
3455	[GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr,
3456	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3457	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3458	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3459	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3460	[GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr,
3461	[GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr,
3462	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3463	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3464	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3465	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3466	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3467	[GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr,
3468	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3469	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3470	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3471	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3472	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3473	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3474	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3475	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3476	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3477	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3478	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3479	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3480	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3481	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3482	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3483	[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3484	[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
3485	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3486	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
3487	[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
3488	[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3489	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3490	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3491	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3492	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3493	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3494	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3495	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3496	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3497	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3498	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3499	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3500	[GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr,
3501	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3502	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3503};
3504
3505static struct gdsc *gcc_qcs8300_gdscs[] = {
3506	[GCC_EMAC0_GDSC] = &gcc_emac0_gdsc,
3507	[GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3508	[GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
3509	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3510	[GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
3511	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3512};
3513
3514static const struct qcom_reset_map gcc_qcs8300_resets[] = {
3515	[GCC_EMAC0_BCR] = { 0xb6000 },
3516	[GCC_PCIE_0_BCR] = { 0xa9000 },
3517	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
3518	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
3519	[GCC_PCIE_0_PHY_BCR] = { 0xa9144 },
3520	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
3521	[GCC_PCIE_1_BCR] = { 0x77000 },
3522	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
3523	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
3524	[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
3525	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
3526	[GCC_SDCC1_BCR] = { 0x20000 },
3527	[GCC_UFS_PHY_BCR] = { 0x83000 },
3528	[GCC_USB20_PRIM_BCR] = { 0x1c000 },
3529	[GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c },
3530	[GCC_USB2_PHY_SEC_BCR] = { 0x5c020 },
3531	[GCC_USB30_PRIM_BCR] = { 0x1b000 },
3532	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
3533	[GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
3534	[GCC_USB3_PHY_TERT_BCR] = { 0x5c024 },
3535	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c00c },
3536	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c010 },
3537	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
3538	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c014 },
3539	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c018 },
3540	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
3541	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
3542	[GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
3543	[GCC_VIDEO_BCR] = { 0x34000 },
3544};
3545
3546static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3547	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3548	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3549	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3550	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3551	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3552	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3553	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3554	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3555	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3556	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3557	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3558	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3559	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3560	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3561	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3562	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3563	DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src),
3564};
3565
3566static const struct regmap_config gcc_qcs8300_regmap_config = {
3567	.reg_bits = 32,
3568	.reg_stride = 4,
3569	.val_bits = 32,
3570	.max_register = 0x472cffc,
3571	.fast_io = true,
3572};
3573
3574static const struct qcom_cc_desc gcc_qcs8300_desc = {
3575	.config = &gcc_qcs8300_regmap_config,
3576	.clks = gcc_qcs8300_clocks,
3577	.num_clks = ARRAY_SIZE(gcc_qcs8300_clocks),
3578	.resets = gcc_qcs8300_resets,
3579	.num_resets = ARRAY_SIZE(gcc_qcs8300_resets),
3580	.gdscs = gcc_qcs8300_gdscs,
3581	.num_gdscs = ARRAY_SIZE(gcc_qcs8300_gdscs),
3582};
3583
3584static const struct of_device_id gcc_qcs8300_match_table[] = {
3585	{ .compatible = "qcom,qcs8300-gcc" },
3586	{ }
3587};
3588MODULE_DEVICE_TABLE(of, gcc_qcs8300_match_table);
3589
3590static int gcc_qcs8300_probe(struct platform_device *pdev)
3591{
3592	struct regmap *regmap;
3593	int ret;
3594
3595	regmap = qcom_cc_map(pdev, &gcc_qcs8300_desc);
3596	if (IS_ERR(regmap))
3597		return PTR_ERR(regmap);
3598
3599	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3600				       ARRAY_SIZE(gcc_dfs_clocks));
3601	if (ret)
3602		return ret;
3603
3604	/* Keep some clocks always enabled */
3605	qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */
3606	qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */
3607	qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */
3608	qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */
3609	qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */
3610	qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
3611	qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
3612
3613	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3614	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3615
3616	return qcom_cc_really_probe(&pdev->dev, &gcc_qcs8300_desc, regmap);
3617}
3618
3619static struct platform_driver gcc_qcs8300_driver = {
3620	.probe = gcc_qcs8300_probe,
3621	.driver = {
3622		.name = "gcc-qcs8300",
3623		.of_match_table = gcc_qcs8300_match_table,
3624	},
3625};
3626
3627static int __init gcc_qcs8300_init(void)
3628{
3629	return platform_driver_register(&gcc_qcs8300_driver);
3630}
3631subsys_initcall(gcc_qcs8300_init);
3632
3633static void __exit gcc_qcs8300_exit(void)
3634{
3635	platform_driver_unregister(&gcc_qcs8300_driver);
3636}
3637module_exit(gcc_qcs8300_exit);
3638
3639MODULE_DESCRIPTION("QTI GCC QCS8300 Driver");
3640MODULE_LICENSE("GPL");