1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/err.h>
   8#include <linux/platform_device.h>
   9#include <linux/module.h>
  10#include <linux/of.h>
  11#include <linux/clk-provider.h>
  12#include <linux/regmap.h>
  13
  14#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  15
  16#include "common.h"
  17#include "clk-regmap.h"
  18#include "clk-pll.h"
  19#include "clk-rcg.h"
  20#include "clk-branch.h"
  21#include "clk-alpha-pll.h"
  22#include "clk-regmap-divider.h"
  23#include "clk-regmap-mux.h"
  24#include "gdsc.h"
  25#include "reset.h"
  26
  27enum {
  28	P_XO,
  29	P_GPLL0,
  30	P_GPLL0_DIV2,
  31	P_GPLL2,
  32	P_GPLL4,
  33	P_GPLL6,
  34	P_SLEEP_CLK,
  35	P_PCIE20_PHY0_PIPE,
  36	P_PCIE20_PHY1_PIPE,
  37	P_USB3PHY_0_PIPE,
  38	P_USB3PHY_1_PIPE,
  39	P_UBI32_PLL,
  40	P_NSS_CRYPTO_PLL,
  41	P_BIAS_PLL,
  42	P_BIAS_PLL_NSS_NOC,
  43	P_UNIPHY0_RX,
  44	P_UNIPHY0_TX,
  45	P_UNIPHY1_RX,
  46	P_UNIPHY1_TX,
  47	P_UNIPHY2_RX,
  48	P_UNIPHY2_TX,
  49};
  50
  51static struct clk_alpha_pll gpll0_main = {
  52	.offset = 0x21000,
  53	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  54	.clkr = {
  55		.enable_reg = 0x0b000,
  56		.enable_mask = BIT(0),
  57		.hw.init = &(struct clk_init_data){
  58			.name = "gpll0_main",
  59			.parent_data = &(const struct clk_parent_data){
  60				.fw_name = "xo",
  61				.name = "xo",
  62			},
  63			.num_parents = 1,
  64			.ops = &clk_alpha_pll_ops,
  65		},
  66	},
  67};
  68
  69static struct clk_fixed_factor gpll0_out_main_div2 = {
  70	.mult = 1,
  71	.div = 2,
  72	.hw.init = &(struct clk_init_data){
  73		.name = "gpll0_out_main_div2",
  74		.parent_hws = (const struct clk_hw *[]){
  75				&gpll0_main.clkr.hw },
  76		.num_parents = 1,
  77		.ops = &clk_fixed_factor_ops,
  78	},
  79};
  80
  81static struct clk_alpha_pll_postdiv gpll0 = {
  82	.offset = 0x21000,
  83	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  84	.width = 4,
  85	.clkr.hw.init = &(struct clk_init_data){
  86		.name = "gpll0",
  87		.parent_hws = (const struct clk_hw *[]){
  88				&gpll0_main.clkr.hw },
  89		.num_parents = 1,
  90		.ops = &clk_alpha_pll_postdiv_ro_ops,
  91	},
  92};
  93
  94static struct clk_alpha_pll gpll2_main = {
  95	.offset = 0x4a000,
  96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  97	.clkr = {
  98		.enable_reg = 0x0b000,
  99		.enable_mask = BIT(2),
 100		.hw.init = &(struct clk_init_data){
 101			.name = "gpll2_main",
 102			.parent_data = &(const struct clk_parent_data){
 103				.fw_name = "xo",
 104				.name = "xo",
 105			},
 106			.num_parents = 1,
 107			.ops = &clk_alpha_pll_ops,
 108			.flags = CLK_IS_CRITICAL,
 109		},
 110	},
 111};
 112
 113static struct clk_alpha_pll_postdiv gpll2 = {
 114	.offset = 0x4a000,
 115	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 116	.width = 4,
 117	.clkr.hw.init = &(struct clk_init_data){
 118		.name = "gpll2",
 119		.parent_hws = (const struct clk_hw *[]){
 120				&gpll2_main.clkr.hw },
 121		.num_parents = 1,
 122		.ops = &clk_alpha_pll_postdiv_ro_ops,
 123	},
 124};
 125
 126static struct clk_alpha_pll gpll4_main = {
 127	.offset = 0x24000,
 128	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 129	.clkr = {
 130		.enable_reg = 0x0b000,
 131		.enable_mask = BIT(5),
 132		.hw.init = &(struct clk_init_data){
 133			.name = "gpll4_main",
 134			.parent_data = &(const struct clk_parent_data){
 135				.fw_name = "xo",
 136				.name = "xo",
 137			},
 138			.num_parents = 1,
 139			.ops = &clk_alpha_pll_ops,
 140			.flags = CLK_IS_CRITICAL,
 141		},
 142	},
 143};
 144
 145static struct clk_alpha_pll_postdiv gpll4 = {
 146	.offset = 0x24000,
 147	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 148	.width = 4,
 149	.clkr.hw.init = &(struct clk_init_data){
 150		.name = "gpll4",
 151		.parent_hws = (const struct clk_hw *[]){
 152				&gpll4_main.clkr.hw },
 153		.num_parents = 1,
 154		.ops = &clk_alpha_pll_postdiv_ro_ops,
 155	},
 156};
 157
 158static struct clk_alpha_pll gpll6_main = {
 159	.offset = 0x37000,
 160	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 161	.flags = SUPPORTS_DYNAMIC_UPDATE,
 162	.clkr = {
 163		.enable_reg = 0x0b000,
 164		.enable_mask = BIT(7),
 165		.hw.init = &(struct clk_init_data){
 166			.name = "gpll6_main",
 167			.parent_data = &(const struct clk_parent_data){
 168				.fw_name = "xo",
 169				.name = "xo",
 170			},
 171			.num_parents = 1,
 172			.ops = &clk_alpha_pll_ops,
 173			.flags = CLK_IS_CRITICAL,
 174		},
 175	},
 176};
 177
 178static struct clk_alpha_pll_postdiv gpll6 = {
 179	.offset = 0x37000,
 180	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 181	.width = 2,
 182	.clkr.hw.init = &(struct clk_init_data){
 183		.name = "gpll6",
 184		.parent_hws = (const struct clk_hw *[]){
 185				&gpll6_main.clkr.hw },
 186		.num_parents = 1,
 187		.ops = &clk_alpha_pll_postdiv_ro_ops,
 188	},
 189};
 190
 191static struct clk_fixed_factor gpll6_out_main_div2 = {
 192	.mult = 1,
 193	.div = 2,
 194	.hw.init = &(struct clk_init_data){
 195		.name = "gpll6_out_main_div2",
 196		.parent_hws = (const struct clk_hw *[]){
 197				&gpll6_main.clkr.hw },
 198		.num_parents = 1,
 199		.ops = &clk_fixed_factor_ops,
 200	},
 201};
 202
 203static struct clk_alpha_pll ubi32_pll_main = {
 204	.offset = 0x25000,
 205	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 206	.flags = SUPPORTS_DYNAMIC_UPDATE,
 207	.clkr = {
 208		.enable_reg = 0x0b000,
 209		.enable_mask = BIT(6),
 210		.hw.init = &(struct clk_init_data){
 211			.name = "ubi32_pll_main",
 212			.parent_data = &(const struct clk_parent_data){
 213				.fw_name = "xo",
 214				.name = "xo",
 215			},
 216			.num_parents = 1,
 217			.ops = &clk_alpha_pll_huayra_ops,
 218		},
 219	},
 220};
 221
 222static struct clk_alpha_pll_postdiv ubi32_pll = {
 223	.offset = 0x25000,
 224	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 225	.width = 2,
 226	.clkr.hw.init = &(struct clk_init_data){
 227		.name = "ubi32_pll",
 228		.parent_hws = (const struct clk_hw *[]){
 229				&ubi32_pll_main.clkr.hw },
 230		.num_parents = 1,
 231		.ops = &clk_alpha_pll_postdiv_ro_ops,
 232		.flags = CLK_SET_RATE_PARENT,
 233	},
 234};
 235
 236static struct clk_alpha_pll nss_crypto_pll_main = {
 237	.offset = 0x22000,
 238	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 239	.clkr = {
 240		.enable_reg = 0x0b000,
 241		.enable_mask = BIT(4),
 242		.hw.init = &(struct clk_init_data){
 243			.name = "nss_crypto_pll_main",
 244			.parent_data = &(const struct clk_parent_data){
 245				.fw_name = "xo",
 246				.name = "xo",
 247			},
 248			.num_parents = 1,
 249			.ops = &clk_alpha_pll_ops,
 250		},
 251	},
 252};
 253
 254static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 255	.offset = 0x22000,
 256	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 257	.width = 4,
 258	.clkr.hw.init = &(struct clk_init_data){
 259		.name = "nss_crypto_pll",
 260		.parent_hws = (const struct clk_hw *[]){
 261				&nss_crypto_pll_main.clkr.hw },
 262		.num_parents = 1,
 263		.ops = &clk_alpha_pll_postdiv_ro_ops,
 264	},
 265};
 266
 267static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 268	F(19200000, P_XO, 1, 0, 0),
 269	F(50000000, P_GPLL0, 16, 0, 0),
 270	F(100000000, P_GPLL0, 8, 0, 0),
 271	{ }
 272};
 273
 274static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 275	{ .fw_name = "xo", .name = "xo" },
 276	{ .hw = &gpll0.clkr.hw},
 277	{ .hw = &gpll0_out_main_div2.hw},
 278};
 279
 280static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 281	{ P_XO, 0 },
 282	{ P_GPLL0, 1 },
 283	{ P_GPLL0_DIV2, 4 },
 284};
 285
 286static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 287	.cmd_rcgr = 0x27000,
 288	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 289	.hid_width = 5,
 290	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 291	.clkr.hw.init = &(struct clk_init_data){
 292		.name = "pcnoc_bfdcd_clk_src",
 293		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 294		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 295		.ops = &clk_rcg2_ops,
 296		.flags = CLK_IS_CRITICAL,
 297	},
 298};
 299
 300static struct clk_fixed_factor pcnoc_clk_src = {
 301	.mult = 1,
 302	.div = 1,
 303	.hw.init = &(struct clk_init_data){
 304		.name = "pcnoc_clk_src",
 305		.parent_hws = (const struct clk_hw *[]){
 306				&pcnoc_bfdcd_clk_src.clkr.hw },
 307		.num_parents = 1,
 308		.ops = &clk_fixed_factor_ops,
 309		.flags = CLK_SET_RATE_PARENT,
 310	},
 311};
 312
 313static struct clk_branch gcc_sleep_clk_src = {
 314	.halt_reg = 0x30000,
 315	.clkr = {
 316		.enable_reg = 0x30000,
 317		.enable_mask = BIT(1),
 318		.hw.init = &(struct clk_init_data){
 319			.name = "gcc_sleep_clk_src",
 320			.parent_data = &(const struct clk_parent_data){
 321				.fw_name = "sleep_clk",
 322				.name = "sleep_clk",
 323			},
 324			.num_parents = 1,
 325			.ops = &clk_branch2_ops,
 326			.flags = CLK_IS_CRITICAL,
 327		},
 328	},
 329};
 330
 331static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 332	F(19200000, P_XO, 1, 0, 0),
 333	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 334	F(50000000, P_GPLL0, 16, 0, 0),
 335	{ }
 336};
 337
 338static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 339	.cmd_rcgr = 0x0200c,
 340	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 341	.hid_width = 5,
 342	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 343	.clkr.hw.init = &(struct clk_init_data){
 344		.name = "blsp1_qup1_i2c_apps_clk_src",
 345		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 346		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 347		.ops = &clk_rcg2_ops,
 348	},
 349};
 350
 351static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 352	F(960000, P_XO, 10, 1, 2),
 353	F(4800000, P_XO, 4, 0, 0),
 354	F(9600000, P_XO, 2, 0, 0),
 355	F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 356	F(16000000, P_GPLL0, 10, 1, 5),
 357	F(19200000, P_XO, 1, 0, 0),
 358	F(25000000, P_GPLL0, 16, 1, 2),
 359	F(50000000, P_GPLL0, 16, 0, 0),
 360	{ }
 361};
 362
 363static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 364	.cmd_rcgr = 0x02024,
 365	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 366	.mnd_width = 8,
 367	.hid_width = 5,
 368	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 369	.clkr.hw.init = &(struct clk_init_data){
 370		.name = "blsp1_qup1_spi_apps_clk_src",
 371		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 372		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 373		.ops = &clk_rcg2_ops,
 374	},
 375};
 376
 377static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 378	.cmd_rcgr = 0x03000,
 379	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 380	.hid_width = 5,
 381	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 382	.clkr.hw.init = &(struct clk_init_data){
 383		.name = "blsp1_qup2_i2c_apps_clk_src",
 384		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 385		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 386		.ops = &clk_rcg2_ops,
 387	},
 388};
 389
 390static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 391	.cmd_rcgr = 0x03014,
 392	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 393	.mnd_width = 8,
 394	.hid_width = 5,
 395	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 396	.clkr.hw.init = &(struct clk_init_data){
 397		.name = "blsp1_qup2_spi_apps_clk_src",
 398		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 399		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 400		.ops = &clk_rcg2_ops,
 401	},
 402};
 403
 404static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 405	.cmd_rcgr = 0x04000,
 406	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 407	.hid_width = 5,
 408	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 409	.clkr.hw.init = &(struct clk_init_data){
 410		.name = "blsp1_qup3_i2c_apps_clk_src",
 411		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 412		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 413		.ops = &clk_rcg2_ops,
 414	},
 415};
 416
 417static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 418	.cmd_rcgr = 0x04014,
 419	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 420	.mnd_width = 8,
 421	.hid_width = 5,
 422	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 423	.clkr.hw.init = &(struct clk_init_data){
 424		.name = "blsp1_qup3_spi_apps_clk_src",
 425		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 426		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 427		.ops = &clk_rcg2_ops,
 428	},
 429};
 430
 431static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 432	.cmd_rcgr = 0x05000,
 433	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 434	.hid_width = 5,
 435	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 436	.clkr.hw.init = &(struct clk_init_data){
 437		.name = "blsp1_qup4_i2c_apps_clk_src",
 438		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 439		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 440		.ops = &clk_rcg2_ops,
 441	},
 442};
 443
 444static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 445	.cmd_rcgr = 0x05014,
 446	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 447	.mnd_width = 8,
 448	.hid_width = 5,
 449	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 450	.clkr.hw.init = &(struct clk_init_data){
 451		.name = "blsp1_qup4_spi_apps_clk_src",
 452		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 453		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 454		.ops = &clk_rcg2_ops,
 455	},
 456};
 457
 458static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 459	.cmd_rcgr = 0x06000,
 460	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 461	.hid_width = 5,
 462	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 463	.clkr.hw.init = &(struct clk_init_data){
 464		.name = "blsp1_qup5_i2c_apps_clk_src",
 465		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 466		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 467		.ops = &clk_rcg2_ops,
 468	},
 469};
 470
 471static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 472	.cmd_rcgr = 0x06014,
 473	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 474	.mnd_width = 8,
 475	.hid_width = 5,
 476	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 477	.clkr.hw.init = &(struct clk_init_data){
 478		.name = "blsp1_qup5_spi_apps_clk_src",
 479		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 480		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 481		.ops = &clk_rcg2_ops,
 482	},
 483};
 484
 485static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 486	.cmd_rcgr = 0x07000,
 487	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 488	.hid_width = 5,
 489	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 490	.clkr.hw.init = &(struct clk_init_data){
 491		.name = "blsp1_qup6_i2c_apps_clk_src",
 492		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 493		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 494		.ops = &clk_rcg2_ops,
 495	},
 496};
 497
 498static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 499	.cmd_rcgr = 0x07014,
 500	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 501	.mnd_width = 8,
 502	.hid_width = 5,
 503	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 504	.clkr.hw.init = &(struct clk_init_data){
 505		.name = "blsp1_qup6_spi_apps_clk_src",
 506		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 507		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 508		.ops = &clk_rcg2_ops,
 509	},
 510};
 511
 512static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 513	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 514	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 515	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 516	F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 517	F(19200000, P_XO, 1, 0, 0),
 518	F(24000000, P_GPLL0, 1, 3, 100),
 519	F(25000000, P_GPLL0, 16, 1, 2),
 520	F(32000000, P_GPLL0, 1, 1, 25),
 521	F(40000000, P_GPLL0, 1, 1, 20),
 522	F(46400000, P_GPLL0, 1, 29, 500),
 523	F(48000000, P_GPLL0, 1, 3, 50),
 524	F(51200000, P_GPLL0, 1, 8, 125),
 525	F(56000000, P_GPLL0, 1, 7, 100),
 526	F(58982400, P_GPLL0, 1, 1152, 15625),
 527	F(60000000, P_GPLL0, 1, 3, 40),
 528	F(64000000, P_GPLL0, 12.5, 1, 1),
 529	{ }
 530};
 531
 532static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 533	.cmd_rcgr = 0x02044,
 534	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 535	.mnd_width = 16,
 536	.hid_width = 5,
 537	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 538	.clkr.hw.init = &(struct clk_init_data){
 539		.name = "blsp1_uart1_apps_clk_src",
 540		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 541		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 542		.ops = &clk_rcg2_ops,
 543	},
 544};
 545
 546static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 547	.cmd_rcgr = 0x03034,
 548	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 549	.mnd_width = 16,
 550	.hid_width = 5,
 551	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 552	.clkr.hw.init = &(struct clk_init_data){
 553		.name = "blsp1_uart2_apps_clk_src",
 554		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 555		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 556		.ops = &clk_rcg2_ops,
 557	},
 558};
 559
 560static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 561	.cmd_rcgr = 0x04034,
 562	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 563	.mnd_width = 16,
 564	.hid_width = 5,
 565	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 566	.clkr.hw.init = &(struct clk_init_data){
 567		.name = "blsp1_uart3_apps_clk_src",
 568		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 569		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 570		.ops = &clk_rcg2_ops,
 571	},
 572};
 573
 574static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 575	.cmd_rcgr = 0x05034,
 576	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 577	.mnd_width = 16,
 578	.hid_width = 5,
 579	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 580	.clkr.hw.init = &(struct clk_init_data){
 581		.name = "blsp1_uart4_apps_clk_src",
 582		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 583		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 584		.ops = &clk_rcg2_ops,
 585	},
 586};
 587
 588static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 589	.cmd_rcgr = 0x06034,
 590	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 591	.mnd_width = 16,
 592	.hid_width = 5,
 593	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 594	.clkr.hw.init = &(struct clk_init_data){
 595		.name = "blsp1_uart5_apps_clk_src",
 596		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 597		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 598		.ops = &clk_rcg2_ops,
 599	},
 600};
 601
 602static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 603	.cmd_rcgr = 0x07034,
 604	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 605	.mnd_width = 16,
 606	.hid_width = 5,
 607	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 608	.clkr.hw.init = &(struct clk_init_data){
 609		.name = "blsp1_uart6_apps_clk_src",
 610		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 611		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 612		.ops = &clk_rcg2_ops,
 613	},
 614};
 615
 616static const struct clk_parent_data gcc_xo_gpll0[] = {
 617	{ .fw_name = "xo" },
 618	{ .hw = &gpll0.clkr.hw },
 619};
 620
 621static const struct parent_map gcc_xo_gpll0_map[] = {
 622	{ P_XO, 0 },
 623	{ P_GPLL0, 1 },
 624};
 625
 626static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 627	F(19200000, P_XO, 1, 0, 0),
 628	F(200000000, P_GPLL0, 4, 0, 0),
 629	{ }
 630};
 631
 632static struct clk_rcg2 pcie0_axi_clk_src = {
 633	.cmd_rcgr = 0x75054,
 634	.freq_tbl = ftbl_pcie_axi_clk_src,
 635	.hid_width = 5,
 636	.parent_map = gcc_xo_gpll0_map,
 637	.clkr.hw.init = &(struct clk_init_data){
 638		.name = "pcie0_axi_clk_src",
 639		.parent_data = gcc_xo_gpll0,
 640		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 641		.ops = &clk_rcg2_ops,
 642	},
 643};
 644
 645static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 646	F(19200000, P_XO, 1, 0, 0),
 647	{ }
 648};
 649
 650static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
 651	{ .fw_name = "xo", .name = "xo" },
 652	{ .hw = &gpll0.clkr.hw },
 653	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 654};
 655
 656static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
 657	{ P_XO, 0 },
 658	{ P_GPLL0, 2 },
 659	{ P_SLEEP_CLK, 6 },
 660};
 661
 662static struct clk_rcg2 pcie0_aux_clk_src = {
 663	.cmd_rcgr = 0x75024,
 664	.freq_tbl = ftbl_pcie_aux_clk_src,
 665	.mnd_width = 16,
 666	.hid_width = 5,
 667	.parent_map = gcc_xo_gpll0_sleep_clk_map,
 668	.clkr.hw.init = &(struct clk_init_data){
 669		.name = "pcie0_aux_clk_src",
 670		.parent_data = gcc_xo_gpll0_sleep_clk,
 671		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 672		.ops = &clk_rcg2_ops,
 673	},
 674};
 675
 676static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
 677	{ .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
 678	{ .fw_name = "xo", .name = "xo" },
 679};
 680
 681static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 682	{ P_PCIE20_PHY0_PIPE, 0 },
 683	{ P_XO, 2 },
 684};
 685
 686static struct clk_regmap_mux pcie0_pipe_clk_src = {
 687	.reg = 0x7501c,
 688	.shift = 8,
 689	.width = 2,
 690	.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
 691	.clkr = {
 692		.hw.init = &(struct clk_init_data){
 693			.name = "pcie0_pipe_clk_src",
 694			.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
 695			.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
 696			.ops = &clk_regmap_mux_closest_ops,
 697			.flags = CLK_SET_RATE_PARENT,
 698		},
 699	},
 700};
 701
 702static struct clk_rcg2 pcie1_axi_clk_src = {
 703	.cmd_rcgr = 0x76054,
 704	.freq_tbl = ftbl_pcie_axi_clk_src,
 705	.hid_width = 5,
 706	.parent_map = gcc_xo_gpll0_map,
 707	.clkr.hw.init = &(struct clk_init_data){
 708		.name = "pcie1_axi_clk_src",
 709		.parent_data = gcc_xo_gpll0,
 710		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 711		.ops = &clk_rcg2_ops,
 712	},
 713};
 714
 715static struct clk_rcg2 pcie1_aux_clk_src = {
 716	.cmd_rcgr = 0x76024,
 717	.freq_tbl = ftbl_pcie_aux_clk_src,
 718	.mnd_width = 16,
 719	.hid_width = 5,
 720	.parent_map = gcc_xo_gpll0_sleep_clk_map,
 721	.clkr.hw.init = &(struct clk_init_data){
 722		.name = "pcie1_aux_clk_src",
 723		.parent_data = gcc_xo_gpll0_sleep_clk,
 724		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 725		.ops = &clk_rcg2_ops,
 726	},
 727};
 728
 729static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
 730	{ .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
 731	{ .fw_name = "xo", .name = "xo" },
 732};
 733
 734static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 735	{ P_PCIE20_PHY1_PIPE, 0 },
 736	{ P_XO, 2 },
 737};
 738
 739static struct clk_regmap_mux pcie1_pipe_clk_src = {
 740	.reg = 0x7601c,
 741	.shift = 8,
 742	.width = 2,
 743	.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
 744	.clkr = {
 745		.hw.init = &(struct clk_init_data){
 746			.name = "pcie1_pipe_clk_src",
 747			.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
 748			.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
 749			.ops = &clk_regmap_mux_closest_ops,
 750			.flags = CLK_SET_RATE_PARENT,
 751		},
 752	},
 753};
 754
 755static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 756	F(144000, P_XO, 16, 3, 25),
 757	F(400000, P_XO, 12, 1, 4),
 758	F(24000000, P_GPLL2, 12, 1, 4),
 759	F(48000000, P_GPLL2, 12, 1, 2),
 760	F(96000000, P_GPLL2, 12, 0, 0),
 761	F(177777778, P_GPLL0, 4.5, 0, 0),
 762	F(192000000, P_GPLL2, 6, 0, 0),
 763	F(384000000, P_GPLL2, 3, 0, 0),
 764	{ }
 765};
 766
 767static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 768	{ .fw_name = "xo", .name = "xo" },
 769	{ .hw = &gpll0.clkr.hw },
 770	{ .hw = &gpll2.clkr.hw },
 771	{ .hw = &gpll0_out_main_div2.hw },
 772};
 773
 774static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 775	{ P_XO, 0 },
 776	{ P_GPLL0, 1 },
 777	{ P_GPLL2, 2 },
 778	{ P_GPLL0_DIV2, 4 },
 779};
 780
 781static struct clk_rcg2 sdcc1_apps_clk_src = {
 782	.cmd_rcgr = 0x42004,
 783	.freq_tbl = ftbl_sdcc_apps_clk_src,
 784	.mnd_width = 8,
 785	.hid_width = 5,
 786	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 787	.clkr.hw.init = &(struct clk_init_data){
 788		.name = "sdcc1_apps_clk_src",
 789		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 790		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
 791		.ops = &clk_rcg2_floor_ops,
 792	},
 793};
 794
 795static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
 796	F(19200000, P_XO, 1, 0, 0),
 797	F(160000000, P_GPLL0, 5, 0, 0),
 798	F(308570000, P_GPLL6, 3.5, 0, 0),
 799	{ }
 800};
 801
 802static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 803	{ .fw_name = "xo", .name = "xo" },
 804	{ .hw = &gpll0.clkr.hw },
 805	{ .hw = &gpll6.clkr.hw },
 806	{ .hw = &gpll0_out_main_div2.hw },
 807};
 808
 809static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 810	{ P_XO, 0 },
 811	{ P_GPLL0, 1 },
 812	{ P_GPLL6, 2 },
 813	{ P_GPLL0_DIV2, 4 },
 814};
 815
 816static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 817	.cmd_rcgr = 0x5d000,
 818	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
 819	.mnd_width = 8,
 820	.hid_width = 5,
 821	.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
 822	.clkr.hw.init = &(struct clk_init_data){
 823		.name = "sdcc1_ice_core_clk_src",
 824		.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
 825		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
 826		.ops = &clk_rcg2_ops,
 827	},
 828};
 829
 830static struct clk_rcg2 sdcc2_apps_clk_src = {
 831	.cmd_rcgr = 0x43004,
 832	.freq_tbl = ftbl_sdcc_apps_clk_src,
 833	.mnd_width = 8,
 834	.hid_width = 5,
 835	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 836	.clkr.hw.init = &(struct clk_init_data){
 837		.name = "sdcc2_apps_clk_src",
 838		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 839		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
 840		.ops = &clk_rcg2_floor_ops,
 841	},
 842};
 843
 844static const struct freq_tbl ftbl_usb_master_clk_src[] = {
 845	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 846	F(100000000, P_GPLL0, 8, 0, 0),
 847	F(133330000, P_GPLL0, 6, 0, 0),
 848	{ }
 849};
 850
 851static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 852	{ .fw_name = "xo", .name = "xo" },
 853	{ .hw = &gpll0_out_main_div2.hw },
 854	{ .hw = &gpll0.clkr.hw },
 855};
 856
 857static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 858	{ P_XO, 0 },
 859	{ P_GPLL0_DIV2, 2 },
 860	{ P_GPLL0, 1 },
 861};
 862
 863static struct clk_rcg2 usb0_master_clk_src = {
 864	.cmd_rcgr = 0x3e00c,
 865	.freq_tbl = ftbl_usb_master_clk_src,
 866	.mnd_width = 8,
 867	.hid_width = 5,
 868	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 869	.clkr.hw.init = &(struct clk_init_data){
 870		.name = "usb0_master_clk_src",
 871		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 872		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
 873		.ops = &clk_rcg2_ops,
 874	},
 875};
 876
 877static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
 878	F(19200000, P_XO, 1, 0, 0),
 879	{ }
 880};
 881
 882static struct clk_rcg2 usb0_aux_clk_src = {
 883	.cmd_rcgr = 0x3e05c,
 884	.freq_tbl = ftbl_usb_aux_clk_src,
 885	.mnd_width = 16,
 886	.hid_width = 5,
 887	.parent_map = gcc_xo_gpll0_sleep_clk_map,
 888	.clkr.hw.init = &(struct clk_init_data){
 889		.name = "usb0_aux_clk_src",
 890		.parent_data = gcc_xo_gpll0_sleep_clk,
 891		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 892		.ops = &clk_rcg2_ops,
 893	},
 894};
 895
 896static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
 897	F(19200000, P_XO, 1, 0, 0),
 898	F(20000000, P_GPLL6, 6, 1, 9),
 899	F(60000000, P_GPLL6, 6, 1, 3),
 900	{ }
 901};
 902
 903static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 904	{ .fw_name = "xo", .name = "xo" },
 905	{ .hw = &gpll6.clkr.hw },
 906	{ .hw = &gpll0.clkr.hw },
 907	{ .hw = &gpll0_out_main_div2.hw },
 908};
 909
 910static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 911	{ P_XO, 0 },
 912	{ P_GPLL6, 1 },
 913	{ P_GPLL0, 3 },
 914	{ P_GPLL0_DIV2, 4 },
 915};
 916
 917static struct clk_rcg2 usb0_mock_utmi_clk_src = {
 918	.cmd_rcgr = 0x3e020,
 919	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
 920	.mnd_width = 8,
 921	.hid_width = 5,
 922	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
 923	.clkr.hw.init = &(struct clk_init_data){
 924		.name = "usb0_mock_utmi_clk_src",
 925		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
 926		.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
 927		.ops = &clk_rcg2_ops,
 928	},
 929};
 930
 931static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 932	{ .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
 933	{ .fw_name = "xo", .name = "xo" },
 934};
 935
 936static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 937	{ P_USB3PHY_0_PIPE, 0 },
 938	{ P_XO, 2 },
 939};
 940
 941static struct clk_regmap_mux usb0_pipe_clk_src = {
 942	.reg = 0x3e048,
 943	.shift = 8,
 944	.width = 2,
 945	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
 946	.clkr = {
 947		.hw.init = &(struct clk_init_data){
 948			.name = "usb0_pipe_clk_src",
 949			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
 950			.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
 951			.ops = &clk_regmap_mux_closest_ops,
 952			.flags = CLK_SET_RATE_PARENT,
 953		},
 954	},
 955};
 956
 957static struct clk_rcg2 usb1_master_clk_src = {
 958	.cmd_rcgr = 0x3f00c,
 959	.freq_tbl = ftbl_usb_master_clk_src,
 960	.mnd_width = 8,
 961	.hid_width = 5,
 962	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 963	.clkr.hw.init = &(struct clk_init_data){
 964		.name = "usb1_master_clk_src",
 965		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 966		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
 967		.ops = &clk_rcg2_ops,
 968	},
 969};
 970
 971static struct clk_rcg2 usb1_aux_clk_src = {
 972	.cmd_rcgr = 0x3f05c,
 973	.freq_tbl = ftbl_usb_aux_clk_src,
 974	.mnd_width = 16,
 975	.hid_width = 5,
 976	.parent_map = gcc_xo_gpll0_sleep_clk_map,
 977	.clkr.hw.init = &(struct clk_init_data){
 978		.name = "usb1_aux_clk_src",
 979		.parent_data = gcc_xo_gpll0_sleep_clk,
 980		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
 981		.ops = &clk_rcg2_ops,
 982	},
 983};
 984
 985static struct clk_rcg2 usb1_mock_utmi_clk_src = {
 986	.cmd_rcgr = 0x3f020,
 987	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
 988	.mnd_width = 8,
 989	.hid_width = 5,
 990	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
 991	.clkr.hw.init = &(struct clk_init_data){
 992		.name = "usb1_mock_utmi_clk_src",
 993		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
 994		.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
 995		.ops = &clk_rcg2_ops,
 996	},
 997};
 998
 999static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
1000	{ .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
1001	{ .fw_name = "xo", .name = "xo" },
1002};
1003
1004static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
1005	{ P_USB3PHY_1_PIPE, 0 },
1006	{ P_XO, 2 },
1007};
1008
1009static struct clk_regmap_mux usb1_pipe_clk_src = {
1010	.reg = 0x3f048,
1011	.shift = 8,
1012	.width = 2,
1013	.parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1014	.clkr = {
1015		.hw.init = &(struct clk_init_data){
1016			.name = "usb1_pipe_clk_src",
1017			.parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
1018			.num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
1019			.ops = &clk_regmap_mux_closest_ops,
1020			.flags = CLK_SET_RATE_PARENT,
1021		},
1022	},
1023};
1024
1025static struct clk_branch gcc_xo_clk_src = {
1026	.halt_reg = 0x30018,
1027	.clkr = {
1028		.enable_reg = 0x30018,
1029		.enable_mask = BIT(1),
1030		.hw.init = &(struct clk_init_data){
1031			.name = "gcc_xo_clk_src",
1032			.parent_data = &(const struct clk_parent_data){
1033				.fw_name = "xo",
1034				.name = "xo",
1035			},
1036			.num_parents = 1,
1037			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1038			.ops = &clk_branch2_ops,
1039		},
1040	},
1041};
1042
1043static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1044	.mult = 1,
1045	.div = 4,
1046	.hw.init = &(struct clk_init_data){
1047		.name = "gcc_xo_div4_clk_src",
1048		.parent_hws = (const struct clk_hw *[]){
1049				&gcc_xo_clk_src.clkr.hw },
1050		.num_parents = 1,
1051		.ops = &clk_fixed_factor_ops,
1052		.flags = CLK_SET_RATE_PARENT,
1053	},
1054};
1055
1056static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1057	F(19200000, P_XO, 1, 0, 0),
1058	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1059	F(100000000, P_GPLL0, 8, 0, 0),
1060	F(133333333, P_GPLL0, 6, 0, 0),
1061	F(160000000, P_GPLL0, 5, 0, 0),
1062	F(200000000, P_GPLL0, 4, 0, 0),
1063	F(266666667, P_GPLL0, 3, 0, 0),
1064	{ }
1065};
1066
1067static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
1068	{ .fw_name = "xo", .name = "xo" },
1069	{ .hw = &gpll0.clkr.hw },
1070	{ .hw = &gpll6.clkr.hw },
1071	{ .hw = &gpll0_out_main_div2.hw },
1072};
1073
1074static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
1075	{ P_XO, 0 },
1076	{ P_GPLL0, 1 },
1077	{ P_GPLL6, 2 },
1078	{ P_GPLL0_DIV2, 3 },
1079};
1080
1081static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1082	.cmd_rcgr = 0x26004,
1083	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1084	.hid_width = 5,
1085	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1086	.clkr.hw.init = &(struct clk_init_data){
1087		.name = "system_noc_bfdcd_clk_src",
1088		.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1089		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
1090		.ops = &clk_rcg2_ops,
1091		.flags = CLK_IS_CRITICAL,
1092	},
1093};
1094
1095static struct clk_fixed_factor system_noc_clk_src = {
1096	.mult = 1,
1097	.div = 1,
1098	.hw.init = &(struct clk_init_data){
1099		.name = "system_noc_clk_src",
1100		.parent_hws = (const struct clk_hw *[]){
1101				&system_noc_bfdcd_clk_src.clkr.hw },
1102		.num_parents = 1,
1103		.ops = &clk_fixed_factor_ops,
1104		.flags = CLK_SET_RATE_PARENT,
1105	},
1106};
1107
1108static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1109	F(19200000, P_XO, 1, 0, 0),
1110	F(200000000, P_GPLL0, 4, 0, 0),
1111	{ }
1112};
1113
1114static struct clk_rcg2 nss_ce_clk_src = {
1115	.cmd_rcgr = 0x68098,
1116	.freq_tbl = ftbl_nss_ce_clk_src,
1117	.hid_width = 5,
1118	.parent_map = gcc_xo_gpll0_map,
1119	.clkr.hw.init = &(struct clk_init_data){
1120		.name = "nss_ce_clk_src",
1121		.parent_data = gcc_xo_gpll0,
1122		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1123		.ops = &clk_rcg2_ops,
1124	},
1125};
1126
1127static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1128	F(19200000, P_XO, 1, 0, 0),
1129	F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1130	{ }
1131};
1132
1133static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
1134	{ .fw_name = "xo", .name = "xo" },
1135	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
1136	{ .hw = &gpll0.clkr.hw },
1137	{ .hw = &gpll2.clkr.hw },
1138};
1139
1140static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
1141	{ P_XO, 0 },
1142	{ P_BIAS_PLL_NSS_NOC, 1 },
1143	{ P_GPLL0, 2 },
1144	{ P_GPLL2, 3 },
1145};
1146
1147static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1148	.cmd_rcgr = 0x68088,
1149	.freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1150	.hid_width = 5,
1151	.parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1152	.clkr.hw.init = &(struct clk_init_data){
1153		.name = "nss_noc_bfdcd_clk_src",
1154		.parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1155		.num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
1156		.ops = &clk_rcg2_ops,
1157	},
1158};
1159
1160static struct clk_fixed_factor nss_noc_clk_src = {
1161	.mult = 1,
1162	.div = 1,
1163	.hw.init = &(struct clk_init_data){
1164		.name = "nss_noc_clk_src",
1165		.parent_hws = (const struct clk_hw *[]){
1166				&nss_noc_bfdcd_clk_src.clkr.hw },
1167		.num_parents = 1,
1168		.ops = &clk_fixed_factor_ops,
1169		.flags = CLK_SET_RATE_PARENT,
1170	},
1171};
1172
1173static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1174	F(19200000, P_XO, 1, 0, 0),
1175	F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1176	{ }
1177};
1178
1179static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
1180	{ .fw_name = "xo", .name = "xo" },
1181	{ .hw = &nss_crypto_pll.clkr.hw },
1182	{ .hw = &gpll0.clkr.hw },
1183};
1184
1185static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
1186	{ P_XO, 0 },
1187	{ P_NSS_CRYPTO_PLL, 1 },
1188	{ P_GPLL0, 2 },
1189};
1190
1191static struct clk_rcg2 nss_crypto_clk_src = {
1192	.cmd_rcgr = 0x68144,
1193	.freq_tbl = ftbl_nss_crypto_clk_src,
1194	.mnd_width = 16,
1195	.hid_width = 5,
1196	.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1197	.clkr.hw.init = &(struct clk_init_data){
1198		.name = "nss_crypto_clk_src",
1199		.parent_data = gcc_xo_nss_crypto_pll_gpll0,
1200		.num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
1201		.ops = &clk_rcg2_ops,
1202	},
1203};
1204
1205static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1206	F(19200000, P_XO, 1, 0, 0),
1207	F(187200000, P_UBI32_PLL, 8, 0, 0),
1208	F(748800000, P_UBI32_PLL, 2, 0, 0),
1209	F(1497600000, P_UBI32_PLL, 1, 0, 0),
1210	F(1689600000, P_UBI32_PLL, 1, 0, 0),
1211	{ }
1212};
1213
1214static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1215	{ .fw_name = "xo", .name = "xo" },
1216	{ .hw = &ubi32_pll.clkr.hw },
1217	{ .hw = &gpll0.clkr.hw },
1218	{ .hw = &gpll2.clkr.hw },
1219	{ .hw = &gpll4.clkr.hw },
1220	{ .hw = &gpll6.clkr.hw },
1221};
1222
1223static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1224	{ P_XO, 0 },
1225	{ P_UBI32_PLL, 1 },
1226	{ P_GPLL0, 2 },
1227	{ P_GPLL2, 3 },
1228	{ P_GPLL4, 4 },
1229	{ P_GPLL6, 5 },
1230};
1231
1232static struct clk_rcg2 nss_ubi0_clk_src = {
1233	.cmd_rcgr = 0x68104,
1234	.freq_tbl = ftbl_nss_ubi_clk_src,
1235	.hid_width = 5,
1236	.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1237	.clkr.hw.init = &(struct clk_init_data){
1238		.name = "nss_ubi0_clk_src",
1239		.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1240		.num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1241		.ops = &clk_rcg2_ops,
1242		.flags = CLK_SET_RATE_PARENT,
1243	},
1244};
1245
1246static struct clk_regmap_div nss_ubi0_div_clk_src = {
1247	.reg = 0x68118,
1248	.shift = 0,
1249	.width = 4,
1250	.clkr = {
1251		.hw.init = &(struct clk_init_data){
1252			.name = "nss_ubi0_div_clk_src",
1253			.parent_hws = (const struct clk_hw *[]){
1254				&nss_ubi0_clk_src.clkr.hw },
1255			.num_parents = 1,
1256			.ops = &clk_regmap_div_ro_ops,
1257			.flags = CLK_SET_RATE_PARENT,
1258		},
1259	},
1260};
1261
1262static struct clk_rcg2 nss_ubi1_clk_src = {
1263	.cmd_rcgr = 0x68124,
1264	.freq_tbl = ftbl_nss_ubi_clk_src,
1265	.hid_width = 5,
1266	.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1267	.clkr.hw.init = &(struct clk_init_data){
1268		.name = "nss_ubi1_clk_src",
1269		.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1270		.num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1271		.ops = &clk_rcg2_ops,
1272		.flags = CLK_SET_RATE_PARENT,
1273	},
1274};
1275
1276static struct clk_regmap_div nss_ubi1_div_clk_src = {
1277	.reg = 0x68138,
1278	.shift = 0,
1279	.width = 4,
1280	.clkr = {
1281		.hw.init = &(struct clk_init_data){
1282			.name = "nss_ubi1_div_clk_src",
1283			.parent_hws = (const struct clk_hw *[]){
1284				&nss_ubi1_clk_src.clkr.hw },
1285			.num_parents = 1,
1286			.ops = &clk_regmap_div_ro_ops,
1287			.flags = CLK_SET_RATE_PARENT,
1288		},
1289	},
1290};
1291
1292static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1293	F(19200000, P_XO, 1, 0, 0),
1294	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1295	{ }
1296};
1297
1298static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
1299	{ .fw_name = "xo", .name = "xo" },
1300	{ .hw = &gpll0_out_main_div2.hw },
1301};
1302
1303static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
1304	{ P_XO, 0 },
1305	{ P_GPLL0_DIV2, 1 },
1306};
1307
1308static struct clk_rcg2 ubi_mpt_clk_src = {
1309	.cmd_rcgr = 0x68090,
1310	.freq_tbl = ftbl_ubi_mpt_clk_src,
1311	.hid_width = 5,
1312	.parent_map = gcc_xo_gpll0_out_main_div2_map,
1313	.clkr.hw.init = &(struct clk_init_data){
1314		.name = "ubi_mpt_clk_src",
1315		.parent_data = gcc_xo_gpll0_out_main_div2,
1316		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
1317		.ops = &clk_rcg2_ops,
1318	},
1319};
1320
1321static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1322	F(19200000, P_XO, 1, 0, 0),
1323	F(400000000, P_GPLL0, 2, 0, 0),
1324	{ }
1325};
1326
1327static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
1328	{ .fw_name = "xo", .name = "xo" },
1329	{ .hw = &gpll0.clkr.hw },
1330	{ .hw = &gpll4.clkr.hw },
1331};
1332
1333static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
1334	{ P_XO, 0 },
1335	{ P_GPLL0, 1 },
1336	{ P_GPLL4, 2 },
1337};
1338
1339static struct clk_rcg2 nss_imem_clk_src = {
1340	.cmd_rcgr = 0x68158,
1341	.freq_tbl = ftbl_nss_imem_clk_src,
1342	.hid_width = 5,
1343	.parent_map = gcc_xo_gpll0_gpll4_map,
1344	.clkr.hw.init = &(struct clk_init_data){
1345		.name = "nss_imem_clk_src",
1346		.parent_data = gcc_xo_gpll0_gpll4,
1347		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1348		.ops = &clk_rcg2_ops,
1349	},
1350};
1351
1352static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1353	F(19200000, P_XO, 1, 0, 0),
1354	F(300000000, P_BIAS_PLL, 1, 0, 0),
1355	{ }
1356};
1357
1358static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
1359	{ .fw_name = "xo", .name = "xo" },
1360	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1361	{ .hw = &gpll0.clkr.hw },
1362	{ .hw = &gpll4.clkr.hw },
1363	{ .hw = &nss_crypto_pll.clkr.hw },
1364	{ .hw = &ubi32_pll.clkr.hw },
1365};
1366
1367static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
1368	{ P_XO, 0 },
1369	{ P_BIAS_PLL, 1 },
1370	{ P_GPLL0, 2 },
1371	{ P_GPLL4, 3 },
1372	{ P_NSS_CRYPTO_PLL, 4 },
1373	{ P_UBI32_PLL, 5 },
1374};
1375
1376static struct clk_rcg2 nss_ppe_clk_src = {
1377	.cmd_rcgr = 0x68080,
1378	.freq_tbl = ftbl_nss_ppe_clk_src,
1379	.hid_width = 5,
1380	.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1381	.clkr.hw.init = &(struct clk_init_data){
1382		.name = "nss_ppe_clk_src",
1383		.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1384		.num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
1385		.ops = &clk_rcg2_ops,
1386	},
1387};
1388
1389static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1390	.mult = 1,
1391	.div = 4,
1392	.hw.init = &(struct clk_init_data){
1393		.name = "nss_ppe_cdiv_clk_src",
1394		.parent_hws = (const struct clk_hw *[]){
1395				&nss_ppe_clk_src.clkr.hw },
1396		.num_parents = 1,
1397		.ops = &clk_fixed_factor_ops,
1398		.flags = CLK_SET_RATE_PARENT,
1399	},
1400};
1401
1402static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1403	F(19200000, P_XO, 1, 0, 0),
1404	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1405	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1406	{ }
1407};
1408
1409static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
1410	{ .fw_name = "xo", .name = "xo" },
1411	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1412	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1413	{ .hw = &ubi32_pll.clkr.hw },
1414	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1415};
1416
1417static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
1418	{ P_XO, 0 },
1419	{ P_UNIPHY0_RX, 1 },
1420	{ P_UNIPHY0_TX, 2 },
1421	{ P_UBI32_PLL, 5 },
1422	{ P_BIAS_PLL, 6 },
1423};
1424
1425static struct clk_rcg2 nss_port1_rx_clk_src = {
1426	.cmd_rcgr = 0x68020,
1427	.freq_tbl = ftbl_nss_port1_rx_clk_src,
1428	.hid_width = 5,
1429	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1430	.clkr.hw.init = &(struct clk_init_data){
1431		.name = "nss_port1_rx_clk_src",
1432		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1433		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1434		.ops = &clk_rcg2_ops,
1435	},
1436};
1437
1438static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1439	.reg = 0x68400,
1440	.shift = 0,
1441	.width = 4,
1442	.clkr = {
1443		.hw.init = &(struct clk_init_data){
1444			.name = "nss_port1_rx_div_clk_src",
1445			.parent_hws = (const struct clk_hw *[]){
1446				&nss_port1_rx_clk_src.clkr.hw },
1447			.num_parents = 1,
1448			.ops = &clk_regmap_div_ops,
1449			.flags = CLK_SET_RATE_PARENT,
1450		},
1451	},
1452};
1453
1454static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1455	F(19200000, P_XO, 1, 0, 0),
1456	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1457	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1458	{ }
1459};
1460
1461static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
1462	{ .fw_name = "xo", .name = "xo" },
1463	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1464	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1465	{ .hw = &ubi32_pll.clkr.hw },
1466	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1467};
1468
1469static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
1470	{ P_XO, 0 },
1471	{ P_UNIPHY0_TX, 1 },
1472	{ P_UNIPHY0_RX, 2 },
1473	{ P_UBI32_PLL, 5 },
1474	{ P_BIAS_PLL, 6 },
1475};
1476
1477static struct clk_rcg2 nss_port1_tx_clk_src = {
1478	.cmd_rcgr = 0x68028,
1479	.freq_tbl = ftbl_nss_port1_tx_clk_src,
1480	.hid_width = 5,
1481	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1482	.clkr.hw.init = &(struct clk_init_data){
1483		.name = "nss_port1_tx_clk_src",
1484		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1485		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1486		.ops = &clk_rcg2_ops,
1487	},
1488};
1489
1490static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1491	.reg = 0x68404,
1492	.shift = 0,
1493	.width = 4,
1494	.clkr = {
1495		.hw.init = &(struct clk_init_data){
1496			.name = "nss_port1_tx_div_clk_src",
1497			.parent_hws = (const struct clk_hw *[]){
1498				&nss_port1_tx_clk_src.clkr.hw },
1499			.num_parents = 1,
1500			.ops = &clk_regmap_div_ops,
1501			.flags = CLK_SET_RATE_PARENT,
1502		},
1503	},
1504};
1505
1506static struct clk_rcg2 nss_port2_rx_clk_src = {
1507	.cmd_rcgr = 0x68030,
1508	.freq_tbl = ftbl_nss_port1_rx_clk_src,
1509	.hid_width = 5,
1510	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1511	.clkr.hw.init = &(struct clk_init_data){
1512		.name = "nss_port2_rx_clk_src",
1513		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1514		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1515		.ops = &clk_rcg2_ops,
1516	},
1517};
1518
1519static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1520	.reg = 0x68410,
1521	.shift = 0,
1522	.width = 4,
1523	.clkr = {
1524		.hw.init = &(struct clk_init_data){
1525			.name = "nss_port2_rx_div_clk_src",
1526			.parent_hws = (const struct clk_hw *[]){
1527				&nss_port2_rx_clk_src.clkr.hw },
1528			.num_parents = 1,
1529			.ops = &clk_regmap_div_ops,
1530			.flags = CLK_SET_RATE_PARENT,
1531		},
1532	},
1533};
1534
1535static struct clk_rcg2 nss_port2_tx_clk_src = {
1536	.cmd_rcgr = 0x68038,
1537	.freq_tbl = ftbl_nss_port1_tx_clk_src,
1538	.hid_width = 5,
1539	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1540	.clkr.hw.init = &(struct clk_init_data){
1541		.name = "nss_port2_tx_clk_src",
1542		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1543		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1544		.ops = &clk_rcg2_ops,
1545	},
1546};
1547
1548static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1549	.reg = 0x68414,
1550	.shift = 0,
1551	.width = 4,
1552	.clkr = {
1553		.hw.init = &(struct clk_init_data){
1554			.name = "nss_port2_tx_div_clk_src",
1555			.parent_hws = (const struct clk_hw *[]){
1556				&nss_port2_tx_clk_src.clkr.hw },
1557			.num_parents = 1,
1558			.ops = &clk_regmap_div_ops,
1559			.flags = CLK_SET_RATE_PARENT,
1560		},
1561	},
1562};
1563
1564static struct clk_rcg2 nss_port3_rx_clk_src = {
1565	.cmd_rcgr = 0x68040,
1566	.freq_tbl = ftbl_nss_port1_rx_clk_src,
1567	.hid_width = 5,
1568	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1569	.clkr.hw.init = &(struct clk_init_data){
1570		.name = "nss_port3_rx_clk_src",
1571		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1572		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1573		.ops = &clk_rcg2_ops,
1574	},
1575};
1576
1577static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1578	.reg = 0x68420,
1579	.shift = 0,
1580	.width = 4,
1581	.clkr = {
1582		.hw.init = &(struct clk_init_data){
1583			.name = "nss_port3_rx_div_clk_src",
1584			.parent_hws = (const struct clk_hw *[]){
1585				&nss_port3_rx_clk_src.clkr.hw },
1586			.num_parents = 1,
1587			.ops = &clk_regmap_div_ops,
1588			.flags = CLK_SET_RATE_PARENT,
1589		},
1590	},
1591};
1592
1593static struct clk_rcg2 nss_port3_tx_clk_src = {
1594	.cmd_rcgr = 0x68048,
1595	.freq_tbl = ftbl_nss_port1_tx_clk_src,
1596	.hid_width = 5,
1597	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1598	.clkr.hw.init = &(struct clk_init_data){
1599		.name = "nss_port3_tx_clk_src",
1600		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1601		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1602		.ops = &clk_rcg2_ops,
1603	},
1604};
1605
1606static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1607	.reg = 0x68424,
1608	.shift = 0,
1609	.width = 4,
1610	.clkr = {
1611		.hw.init = &(struct clk_init_data){
1612			.name = "nss_port3_tx_div_clk_src",
1613			.parent_hws = (const struct clk_hw *[]){
1614				&nss_port3_tx_clk_src.clkr.hw },
1615			.num_parents = 1,
1616			.ops = &clk_regmap_div_ops,
1617			.flags = CLK_SET_RATE_PARENT,
1618		},
1619	},
1620};
1621
1622static struct clk_rcg2 nss_port4_rx_clk_src = {
1623	.cmd_rcgr = 0x68050,
1624	.freq_tbl = ftbl_nss_port1_rx_clk_src,
1625	.hid_width = 5,
1626	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1627	.clkr.hw.init = &(struct clk_init_data){
1628		.name = "nss_port4_rx_clk_src",
1629		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1630		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1631		.ops = &clk_rcg2_ops,
1632	},
1633};
1634
1635static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1636	.reg = 0x68430,
1637	.shift = 0,
1638	.width = 4,
1639	.clkr = {
1640		.hw.init = &(struct clk_init_data){
1641			.name = "nss_port4_rx_div_clk_src",
1642			.parent_hws = (const struct clk_hw *[]){
1643				&nss_port4_rx_clk_src.clkr.hw },
1644			.num_parents = 1,
1645			.ops = &clk_regmap_div_ops,
1646			.flags = CLK_SET_RATE_PARENT,
1647		},
1648	},
1649};
1650
1651static struct clk_rcg2 nss_port4_tx_clk_src = {
1652	.cmd_rcgr = 0x68058,
1653	.freq_tbl = ftbl_nss_port1_tx_clk_src,
1654	.hid_width = 5,
1655	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1656	.clkr.hw.init = &(struct clk_init_data){
1657		.name = "nss_port4_tx_clk_src",
1658		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1659		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1660		.ops = &clk_rcg2_ops,
1661	},
1662};
1663
1664static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1665	.reg = 0x68434,
1666	.shift = 0,
1667	.width = 4,
1668	.clkr = {
1669		.hw.init = &(struct clk_init_data){
1670			.name = "nss_port4_tx_div_clk_src",
1671			.parent_hws = (const struct clk_hw *[]){
1672				&nss_port4_tx_clk_src.clkr.hw },
1673			.num_parents = 1,
1674			.ops = &clk_regmap_div_ops,
1675			.flags = CLK_SET_RATE_PARENT,
1676		},
1677	},
1678};
1679
1680static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
1681	C(P_UNIPHY1_RX, 12.5, 0, 0),
1682	C(P_UNIPHY0_RX, 5, 0, 0),
1683};
1684
1685static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
1686	C(P_UNIPHY1_RX, 2.5, 0, 0),
1687	C(P_UNIPHY0_RX, 1, 0, 0),
1688};
1689
1690static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
1691	FMS(19200000, P_XO, 1, 0, 0),
1692	FM(25000000, ftbl_nss_port5_rx_clk_src_25),
1693	FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1694	FM(125000000, ftbl_nss_port5_rx_clk_src_125),
1695	FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1696	FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1697	{ }
1698};
1699
1700static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
1701	{ .fw_name = "xo", .name = "xo" },
1702	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1703	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1704	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1705	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1706	{ .hw = &ubi32_pll.clkr.hw },
1707	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1708};
1709
1710static const struct parent_map
1711gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
1712	{ P_XO, 0 },
1713	{ P_UNIPHY0_RX, 1 },
1714	{ P_UNIPHY0_TX, 2 },
1715	{ P_UNIPHY1_RX, 3 },
1716	{ P_UNIPHY1_TX, 4 },
1717	{ P_UBI32_PLL, 5 },
1718	{ P_BIAS_PLL, 6 },
1719};
1720
1721static struct clk_rcg2 nss_port5_rx_clk_src = {
1722	.cmd_rcgr = 0x68060,
1723	.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
1724	.hid_width = 5,
1725	.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1726	.clkr.hw.init = &(struct clk_init_data){
1727		.name = "nss_port5_rx_clk_src",
1728		.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1729		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1730		.ops = &clk_rcg2_fm_ops,
1731	},
1732};
1733
1734static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1735	.reg = 0x68440,
1736	.shift = 0,
1737	.width = 4,
1738	.clkr = {
1739		.hw.init = &(struct clk_init_data){
1740			.name = "nss_port5_rx_div_clk_src",
1741			.parent_hws = (const struct clk_hw *[]){
1742				&nss_port5_rx_clk_src.clkr.hw },
1743			.num_parents = 1,
1744			.ops = &clk_regmap_div_ops,
1745			.flags = CLK_SET_RATE_PARENT,
1746		},
1747	},
1748};
1749
1750static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
1751	C(P_UNIPHY1_TX, 12.5, 0, 0),
1752	C(P_UNIPHY0_TX, 5, 0, 0),
1753};
1754
1755static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
1756	C(P_UNIPHY1_TX, 2.5, 0, 0),
1757	C(P_UNIPHY0_TX, 1, 0, 0),
1758};
1759
1760static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
1761	FMS(19200000, P_XO, 1, 0, 0),
1762	FM(25000000, ftbl_nss_port5_tx_clk_src_25),
1763	FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
1764	FM(125000000, ftbl_nss_port5_tx_clk_src_125),
1765	FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
1766	FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
1767	{ }
1768};
1769
1770static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
1771	{ .fw_name = "xo", .name = "xo" },
1772	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1773	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1774	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1775	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1776	{ .hw = &ubi32_pll.clkr.hw },
1777	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1778};
1779
1780static const struct parent_map
1781gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
1782	{ P_XO, 0 },
1783	{ P_UNIPHY0_TX, 1 },
1784	{ P_UNIPHY0_RX, 2 },
1785	{ P_UNIPHY1_TX, 3 },
1786	{ P_UNIPHY1_RX, 4 },
1787	{ P_UBI32_PLL, 5 },
1788	{ P_BIAS_PLL, 6 },
1789};
1790
1791static struct clk_rcg2 nss_port5_tx_clk_src = {
1792	.cmd_rcgr = 0x68068,
1793	.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
1794	.hid_width = 5,
1795	.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1796	.clkr.hw.init = &(struct clk_init_data){
1797		.name = "nss_port5_tx_clk_src",
1798		.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1799		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1800		.ops = &clk_rcg2_fm_ops,
1801	},
1802};
1803
1804static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1805	.reg = 0x68444,
1806	.shift = 0,
1807	.width = 4,
1808	.clkr = {
1809		.hw.init = &(struct clk_init_data){
1810			.name = "nss_port5_tx_div_clk_src",
1811			.parent_hws = (const struct clk_hw *[]){
1812				&nss_port5_tx_clk_src.clkr.hw },
1813			.num_parents = 1,
1814			.ops = &clk_regmap_div_ops,
1815			.flags = CLK_SET_RATE_PARENT,
1816		},
1817	},
1818};
1819
1820static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
1821	C(P_UNIPHY2_RX, 5, 0, 0),
1822	C(P_UNIPHY2_RX, 12.5, 0, 0),
1823};
1824
1825static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
1826	C(P_UNIPHY2_RX, 1, 0, 0),
1827	C(P_UNIPHY2_RX, 2.5, 0, 0),
1828};
1829
1830static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
1831	FMS(19200000, P_XO, 1, 0, 0),
1832	FM(25000000, ftbl_nss_port6_rx_clk_src_25),
1833	FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
1834	FM(125000000, ftbl_nss_port6_rx_clk_src_125),
1835	FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
1836	FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
1837	{ }
1838};
1839
1840static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
1841	{ .fw_name = "xo", .name = "xo" },
1842	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1843	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1844	{ .hw = &ubi32_pll.clkr.hw },
1845	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1846};
1847
1848static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
1849	{ P_XO, 0 },
1850	{ P_UNIPHY2_RX, 1 },
1851	{ P_UNIPHY2_TX, 2 },
1852	{ P_UBI32_PLL, 5 },
1853	{ P_BIAS_PLL, 6 },
1854};
1855
1856static struct clk_rcg2 nss_port6_rx_clk_src = {
1857	.cmd_rcgr = 0x68070,
1858	.freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
1859	.hid_width = 5,
1860	.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1861	.clkr.hw.init = &(struct clk_init_data){
1862		.name = "nss_port6_rx_clk_src",
1863		.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1864		.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1865		.ops = &clk_rcg2_fm_ops,
1866	},
1867};
1868
1869static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1870	.reg = 0x68450,
1871	.shift = 0,
1872	.width = 4,
1873	.clkr = {
1874		.hw.init = &(struct clk_init_data){
1875			.name = "nss_port6_rx_div_clk_src",
1876			.parent_hws = (const struct clk_hw *[]){
1877				&nss_port6_rx_clk_src.clkr.hw },
1878			.num_parents = 1,
1879			.ops = &clk_regmap_div_ops,
1880			.flags = CLK_SET_RATE_PARENT,
1881		},
1882	},
1883};
1884
1885static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
1886	C(P_UNIPHY2_TX, 5, 0, 0),
1887	C(P_UNIPHY2_TX, 12.5, 0, 0),
1888};
1889
1890static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
1891	C(P_UNIPHY2_TX, 1, 0, 0),
1892	C(P_UNIPHY2_TX, 2.5, 0, 0),
1893};
1894
1895static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
1896	FMS(19200000, P_XO, 1, 0, 0),
1897	FM(25000000, ftbl_nss_port6_tx_clk_src_25),
1898	FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1899	FM(125000000, ftbl_nss_port6_tx_clk_src_125),
1900	FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1901	FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1902	{ }
1903};
1904
1905static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
1906	{ .fw_name = "xo", .name = "xo" },
1907	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1908	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1909	{ .hw = &ubi32_pll.clkr.hw },
1910	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1911};
1912
1913static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
1914	{ P_XO, 0 },
1915	{ P_UNIPHY2_TX, 1 },
1916	{ P_UNIPHY2_RX, 2 },
1917	{ P_UBI32_PLL, 5 },
1918	{ P_BIAS_PLL, 6 },
1919};
1920
1921static struct clk_rcg2 nss_port6_tx_clk_src = {
1922	.cmd_rcgr = 0x68078,
1923	.freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
1924	.hid_width = 5,
1925	.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1926	.clkr.hw.init = &(struct clk_init_data){
1927		.name = "nss_port6_tx_clk_src",
1928		.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1929		.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1930		.ops = &clk_rcg2_fm_ops,
1931	},
1932};
1933
1934static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1935	.reg = 0x68454,
1936	.shift = 0,
1937	.width = 4,
1938	.clkr = {
1939		.hw.init = &(struct clk_init_data){
1940			.name = "nss_port6_tx_div_clk_src",
1941			.parent_hws = (const struct clk_hw *[]){
1942				&nss_port6_tx_clk_src.clkr.hw },
1943			.num_parents = 1,
1944			.ops = &clk_regmap_div_ops,
1945			.flags = CLK_SET_RATE_PARENT,
1946		},
1947	},
1948};
1949
1950static const struct freq_tbl ftbl_crypto_clk_src[] = {
1951	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1952	F(80000000, P_GPLL0, 10, 0, 0),
1953	F(100000000, P_GPLL0, 8, 0, 0),
1954	F(160000000, P_GPLL0, 5, 0, 0),
1955	{ }
1956};
1957
1958static struct clk_rcg2 crypto_clk_src = {
1959	.cmd_rcgr = 0x16004,
1960	.freq_tbl = ftbl_crypto_clk_src,
1961	.hid_width = 5,
1962	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1963	.clkr.hw.init = &(struct clk_init_data){
1964		.name = "crypto_clk_src",
1965		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1966		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1967		.ops = &clk_rcg2_ops,
1968	},
1969};
1970
1971static const struct freq_tbl ftbl_gp_clk_src[] = {
1972	F(19200000, P_XO, 1, 0, 0),
1973	{ }
1974};
1975
1976static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1977	{ .fw_name = "xo", .name = "xo" },
1978	{ .hw = &gpll0.clkr.hw },
1979	{ .hw = &gpll6.clkr.hw },
1980	{ .hw = &gpll0_out_main_div2.hw },
1981	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
1982};
1983
1984static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1985	{ P_XO, 0 },
1986	{ P_GPLL0, 1 },
1987	{ P_GPLL6, 2 },
1988	{ P_GPLL0_DIV2, 4 },
1989	{ P_SLEEP_CLK, 6 },
1990};
1991
1992static struct clk_rcg2 gp1_clk_src = {
1993	.cmd_rcgr = 0x08004,
1994	.freq_tbl = ftbl_gp_clk_src,
1995	.mnd_width = 8,
1996	.hid_width = 5,
1997	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1998	.clkr.hw.init = &(struct clk_init_data){
1999		.name = "gp1_clk_src",
2000		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2001		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
2002		.ops = &clk_rcg2_ops,
2003	},
2004};
2005
2006static struct clk_rcg2 gp2_clk_src = {
2007	.cmd_rcgr = 0x09004,
2008	.freq_tbl = ftbl_gp_clk_src,
2009	.mnd_width = 8,
2010	.hid_width = 5,
2011	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2012	.clkr.hw.init = &(struct clk_init_data){
2013		.name = "gp2_clk_src",
2014		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2015		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
2016		.ops = &clk_rcg2_ops,
2017	},
2018};
2019
2020static struct clk_rcg2 gp3_clk_src = {
2021	.cmd_rcgr = 0x0a004,
2022	.freq_tbl = ftbl_gp_clk_src,
2023	.mnd_width = 8,
2024	.hid_width = 5,
2025	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2026	.clkr.hw.init = &(struct clk_init_data){
2027		.name = "gp3_clk_src",
2028		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2029		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
2030		.ops = &clk_rcg2_ops,
2031	},
2032};
2033
2034static struct clk_branch gcc_blsp1_ahb_clk = {
2035	.halt_reg = 0x01008,
2036	.clkr = {
2037		.enable_reg = 0x01008,
2038		.enable_mask = BIT(0),
2039		.hw.init = &(struct clk_init_data){
2040			.name = "gcc_blsp1_ahb_clk",
2041			.parent_hws = (const struct clk_hw *[]){
2042				&pcnoc_clk_src.hw },
2043			.num_parents = 1,
2044			.flags = CLK_SET_RATE_PARENT,
2045			.ops = &clk_branch2_ops,
2046		},
2047	},
2048};
2049
2050static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2051	.halt_reg = 0x02008,
2052	.clkr = {
2053		.enable_reg = 0x02008,
2054		.enable_mask = BIT(0),
2055		.hw.init = &(struct clk_init_data){
2056			.name = "gcc_blsp1_qup1_i2c_apps_clk",
2057			.parent_hws = (const struct clk_hw *[]){
2058				&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
2059			.num_parents = 1,
2060			.flags = CLK_SET_RATE_PARENT,
2061			.ops = &clk_branch2_ops,
2062		},
2063	},
2064};
2065
2066static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2067	.halt_reg = 0x02004,
2068	.clkr = {
2069		.enable_reg = 0x02004,
2070		.enable_mask = BIT(0),
2071		.hw.init = &(struct clk_init_data){
2072			.name = "gcc_blsp1_qup1_spi_apps_clk",
2073			.parent_hws = (const struct clk_hw *[]){
2074				&blsp1_qup1_spi_apps_clk_src.clkr.hw },
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2083	.halt_reg = 0x03010,
2084	.clkr = {
2085		.enable_reg = 0x03010,
2086		.enable_mask = BIT(0),
2087		.hw.init = &(struct clk_init_data){
2088			.name = "gcc_blsp1_qup2_i2c_apps_clk",
2089			.parent_hws = (const struct clk_hw *[]){
2090				&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2091			.num_parents = 1,
2092			.flags = CLK_SET_RATE_PARENT,
2093			.ops = &clk_branch2_ops,
2094		},
2095	},
2096};
2097
2098static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2099	.halt_reg = 0x0300c,
2100	.clkr = {
2101		.enable_reg = 0x0300c,
2102		.enable_mask = BIT(0),
2103		.hw.init = &(struct clk_init_data){
2104			.name = "gcc_blsp1_qup2_spi_apps_clk",
2105			.parent_hws = (const struct clk_hw *[]){
2106				&blsp1_qup2_spi_apps_clk_src.clkr.hw },
2107			.num_parents = 1,
2108			.flags = CLK_SET_RATE_PARENT,
2109			.ops = &clk_branch2_ops,
2110		},
2111	},
2112};
2113
2114static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2115	.halt_reg = 0x04010,
2116	.clkr = {
2117		.enable_reg = 0x04010,
2118		.enable_mask = BIT(0),
2119		.hw.init = &(struct clk_init_data){
2120			.name = "gcc_blsp1_qup3_i2c_apps_clk",
2121			.parent_hws = (const struct clk_hw *[]){
2122				&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2123			.num_parents = 1,
2124			.flags = CLK_SET_RATE_PARENT,
2125			.ops = &clk_branch2_ops,
2126		},
2127	},
2128};
2129
2130static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2131	.halt_reg = 0x0400c,
2132	.clkr = {
2133		.enable_reg = 0x0400c,
2134		.enable_mask = BIT(0),
2135		.hw.init = &(struct clk_init_data){
2136			.name = "gcc_blsp1_qup3_spi_apps_clk",
2137			.parent_hws = (const struct clk_hw *[]){
2138				&blsp1_qup3_spi_apps_clk_src.clkr.hw },
2139			.num_parents = 1,
2140			.flags = CLK_SET_RATE_PARENT,
2141			.ops = &clk_branch2_ops,
2142		},
2143	},
2144};
2145
2146static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2147	.halt_reg = 0x05010,
2148	.clkr = {
2149		.enable_reg = 0x05010,
2150		.enable_mask = BIT(0),
2151		.hw.init = &(struct clk_init_data){
2152			.name = "gcc_blsp1_qup4_i2c_apps_clk",
2153			.parent_hws = (const struct clk_hw *[]){
2154				&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2155			.num_parents = 1,
2156			.flags = CLK_SET_RATE_PARENT,
2157			.ops = &clk_branch2_ops,
2158		},
2159	},
2160};
2161
2162static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2163	.halt_reg = 0x0500c,
2164	.clkr = {
2165		.enable_reg = 0x0500c,
2166		.enable_mask = BIT(0),
2167		.hw.init = &(struct clk_init_data){
2168			.name = "gcc_blsp1_qup4_spi_apps_clk",
2169			.parent_hws = (const struct clk_hw *[]){
2170				&blsp1_qup4_spi_apps_clk_src.clkr.hw },
2171			.num_parents = 1,
2172			.flags = CLK_SET_RATE_PARENT,
2173			.ops = &clk_branch2_ops,
2174		},
2175	},
2176};
2177
2178static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2179	.halt_reg = 0x06010,
2180	.clkr = {
2181		.enable_reg = 0x06010,
2182		.enable_mask = BIT(0),
2183		.hw.init = &(struct clk_init_data){
2184			.name = "gcc_blsp1_qup5_i2c_apps_clk",
2185			.parent_hws = (const struct clk_hw *[]){
2186				&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2187			.num_parents = 1,
2188			.flags = CLK_SET_RATE_PARENT,
2189			.ops = &clk_branch2_ops,
2190		},
2191	},
2192};
2193
2194static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2195	.halt_reg = 0x0600c,
2196	.clkr = {
2197		.enable_reg = 0x0600c,
2198		.enable_mask = BIT(0),
2199		.hw.init = &(struct clk_init_data){
2200			.name = "gcc_blsp1_qup5_spi_apps_clk",
2201			.parent_hws = (const struct clk_hw *[]){
2202				&blsp1_qup5_spi_apps_clk_src.clkr.hw },
2203			.num_parents = 1,
2204			.flags = CLK_SET_RATE_PARENT,
2205			.ops = &clk_branch2_ops,
2206		},
2207	},
2208};
2209
2210static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2211	.halt_reg = 0x07010,
2212	.clkr = {
2213		.enable_reg = 0x07010,
2214		.enable_mask = BIT(0),
2215		.hw.init = &(struct clk_init_data){
2216			.name = "gcc_blsp1_qup6_i2c_apps_clk",
2217			.parent_hws = (const struct clk_hw *[]){
2218				&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2219			.num_parents = 1,
2220			.flags = CLK_SET_RATE_PARENT,
2221			.ops = &clk_branch2_ops,
2222		},
2223	},
2224};
2225
2226static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2227	.halt_reg = 0x0700c,
2228	.clkr = {
2229		.enable_reg = 0x0700c,
2230		.enable_mask = BIT(0),
2231		.hw.init = &(struct clk_init_data){
2232			.name = "gcc_blsp1_qup6_spi_apps_clk",
2233			.parent_hws = (const struct clk_hw *[]){
2234				&blsp1_qup6_spi_apps_clk_src.clkr.hw },
2235			.num_parents = 1,
2236			.flags = CLK_SET_RATE_PARENT,
2237			.ops = &clk_branch2_ops,
2238		},
2239	},
2240};
2241
2242static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2243	.halt_reg = 0x0203c,
2244	.clkr = {
2245		.enable_reg = 0x0203c,
2246		.enable_mask = BIT(0),
2247		.hw.init = &(struct clk_init_data){
2248			.name = "gcc_blsp1_uart1_apps_clk",
2249			.parent_hws = (const struct clk_hw *[]){
2250				&blsp1_uart1_apps_clk_src.clkr.hw },
2251			.num_parents = 1,
2252			.flags = CLK_SET_RATE_PARENT,
2253			.ops = &clk_branch2_ops,
2254		},
2255	},
2256};
2257
2258static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2259	.halt_reg = 0x0302c,
2260	.clkr = {
2261		.enable_reg = 0x0302c,
2262		.enable_mask = BIT(0),
2263		.hw.init = &(struct clk_init_data){
2264			.name = "gcc_blsp1_uart2_apps_clk",
2265			.parent_hws = (const struct clk_hw *[]){
2266				&blsp1_uart2_apps_clk_src.clkr.hw },
2267			.num_parents = 1,
2268			.flags = CLK_SET_RATE_PARENT,
2269			.ops = &clk_branch2_ops,
2270		},
2271	},
2272};
2273
2274static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2275	.halt_reg = 0x0402c,
2276	.clkr = {
2277		.enable_reg = 0x0402c,
2278		.enable_mask = BIT(0),
2279		.hw.init = &(struct clk_init_data){
2280			.name = "gcc_blsp1_uart3_apps_clk",
2281			.parent_hws = (const struct clk_hw *[]){
2282				&blsp1_uart3_apps_clk_src.clkr.hw },
2283			.num_parents = 1,
2284			.flags = CLK_SET_RATE_PARENT,
2285			.ops = &clk_branch2_ops,
2286		},
2287	},
2288};
2289
2290static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2291	.halt_reg = 0x0502c,
2292	.clkr = {
2293		.enable_reg = 0x0502c,
2294		.enable_mask = BIT(0),
2295		.hw.init = &(struct clk_init_data){
2296			.name = "gcc_blsp1_uart4_apps_clk",
2297			.parent_hws = (const struct clk_hw *[]){
2298				&blsp1_uart4_apps_clk_src.clkr.hw },
2299			.num_parents = 1,
2300			.flags = CLK_SET_RATE_PARENT,
2301			.ops = &clk_branch2_ops,
2302		},
2303	},
2304};
2305
2306static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2307	.halt_reg = 0x0602c,
2308	.clkr = {
2309		.enable_reg = 0x0602c,
2310		.enable_mask = BIT(0),
2311		.hw.init = &(struct clk_init_data){
2312			.name = "gcc_blsp1_uart5_apps_clk",
2313			.parent_hws = (const struct clk_hw *[]){
2314				&blsp1_uart5_apps_clk_src.clkr.hw },
2315			.num_parents = 1,
2316			.flags = CLK_SET_RATE_PARENT,
2317			.ops = &clk_branch2_ops,
2318		},
2319	},
2320};
2321
2322static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2323	.halt_reg = 0x0702c,
2324	.clkr = {
2325		.enable_reg = 0x0702c,
2326		.enable_mask = BIT(0),
2327		.hw.init = &(struct clk_init_data){
2328			.name = "gcc_blsp1_uart6_apps_clk",
2329			.parent_hws = (const struct clk_hw *[]){
2330				&blsp1_uart6_apps_clk_src.clkr.hw },
2331			.num_parents = 1,
2332			.flags = CLK_SET_RATE_PARENT,
2333			.ops = &clk_branch2_ops,
2334		},
2335	},
2336};
2337
2338static struct clk_branch gcc_prng_ahb_clk = {
2339	.halt_reg = 0x13004,
2340	.halt_check = BRANCH_HALT_VOTED,
2341	.clkr = {
2342		.enable_reg = 0x0b004,
2343		.enable_mask = BIT(8),
2344		.hw.init = &(struct clk_init_data){
2345			.name = "gcc_prng_ahb_clk",
2346			.parent_hws = (const struct clk_hw *[]){
2347				&pcnoc_clk_src.hw },
2348			.num_parents = 1,
2349			.flags = CLK_SET_RATE_PARENT,
2350			.ops = &clk_branch2_ops,
2351		},
2352	},
2353};
2354
2355static struct clk_branch gcc_qpic_ahb_clk = {
2356	.halt_reg = 0x57024,
2357	.clkr = {
2358		.enable_reg = 0x57024,
2359		.enable_mask = BIT(0),
2360		.hw.init = &(struct clk_init_data){
2361			.name = "gcc_qpic_ahb_clk",
2362			.parent_hws = (const struct clk_hw *[]){
2363				&pcnoc_clk_src.hw },
2364			.num_parents = 1,
2365			.flags = CLK_SET_RATE_PARENT,
2366			.ops = &clk_branch2_ops,
2367		},
2368	},
2369};
2370
2371static struct clk_branch gcc_qpic_clk = {
2372	.halt_reg = 0x57020,
2373	.clkr = {
2374		.enable_reg = 0x57020,
2375		.enable_mask = BIT(0),
2376		.hw.init = &(struct clk_init_data){
2377			.name = "gcc_qpic_clk",
2378			.parent_hws = (const struct clk_hw *[]){
2379				&pcnoc_clk_src.hw },
2380			.num_parents = 1,
2381			.flags = CLK_SET_RATE_PARENT,
2382			.ops = &clk_branch2_ops,
2383		},
2384	},
2385};
2386
2387static struct clk_branch gcc_pcie0_ahb_clk = {
2388	.halt_reg = 0x75010,
2389	.clkr = {
2390		.enable_reg = 0x75010,
2391		.enable_mask = BIT(0),
2392		.hw.init = &(struct clk_init_data){
2393			.name = "gcc_pcie0_ahb_clk",
2394			.parent_hws = (const struct clk_hw *[]){
2395				&pcnoc_clk_src.hw },
2396			.num_parents = 1,
2397			.flags = CLK_SET_RATE_PARENT,
2398			.ops = &clk_branch2_ops,
2399		},
2400	},
2401};
2402
2403static struct clk_branch gcc_pcie0_aux_clk = {
2404	.halt_reg = 0x75014,
2405	.clkr = {
2406		.enable_reg = 0x75014,
2407		.enable_mask = BIT(0),
2408		.hw.init = &(struct clk_init_data){
2409			.name = "gcc_pcie0_aux_clk",
2410			.parent_hws = (const struct clk_hw *[]){
2411				&pcie0_aux_clk_src.clkr.hw },
2412			.num_parents = 1,
2413			.flags = CLK_SET_RATE_PARENT,
2414			.ops = &clk_branch2_ops,
2415		},
2416	},
2417};
2418
2419static struct clk_branch gcc_pcie0_axi_m_clk = {
2420	.halt_reg = 0x75008,
2421	.clkr = {
2422		.enable_reg = 0x75008,
2423		.enable_mask = BIT(0),
2424		.hw.init = &(struct clk_init_data){
2425			.name = "gcc_pcie0_axi_m_clk",
2426			.parent_hws = (const struct clk_hw *[]){
2427				&pcie0_axi_clk_src.clkr.hw },
2428			.num_parents = 1,
2429			.flags = CLK_SET_RATE_PARENT,
2430			.ops = &clk_branch2_ops,
2431		},
2432	},
2433};
2434
2435static struct clk_branch gcc_pcie0_axi_s_clk = {
2436	.halt_reg = 0x7500c,
2437	.clkr = {
2438		.enable_reg = 0x7500c,
2439		.enable_mask = BIT(0),
2440		.hw.init = &(struct clk_init_data){
2441			.name = "gcc_pcie0_axi_s_clk",
2442			.parent_hws = (const struct clk_hw *[]){
2443				&pcie0_axi_clk_src.clkr.hw },
2444			.num_parents = 1,
2445			.flags = CLK_SET_RATE_PARENT,
2446			.ops = &clk_branch2_ops,
2447		},
2448	},
2449};
2450
2451static struct clk_branch gcc_pcie0_pipe_clk = {
2452	.halt_reg = 0x75018,
2453	.halt_check = BRANCH_HALT_DELAY,
2454	.clkr = {
2455		.enable_reg = 0x75018,
2456		.enable_mask = BIT(0),
2457		.hw.init = &(struct clk_init_data){
2458			.name = "gcc_pcie0_pipe_clk",
2459			.parent_hws = (const struct clk_hw *[]){
2460				&pcie0_pipe_clk_src.clkr.hw },
2461			.num_parents = 1,
2462			.flags = CLK_SET_RATE_PARENT,
2463			.ops = &clk_branch2_ops,
2464		},
2465	},
2466};
2467
2468static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2469	.halt_reg = 0x26048,
2470	.clkr = {
2471		.enable_reg = 0x26048,
2472		.enable_mask = BIT(0),
2473		.hw.init = &(struct clk_init_data){
2474			.name = "gcc_sys_noc_pcie0_axi_clk",
2475			.parent_hws = (const struct clk_hw *[]){
2476				&pcie0_axi_clk_src.clkr.hw },
2477			.num_parents = 1,
2478			.flags = CLK_SET_RATE_PARENT,
2479			.ops = &clk_branch2_ops,
2480		},
2481	},
2482};
2483
2484static struct clk_branch gcc_pcie1_ahb_clk = {
2485	.halt_reg = 0x76010,
2486	.clkr = {
2487		.enable_reg = 0x76010,
2488		.enable_mask = BIT(0),
2489		.hw.init = &(struct clk_init_data){
2490			.name = "gcc_pcie1_ahb_clk",
2491			.parent_hws = (const struct clk_hw *[]){
2492				&pcnoc_clk_src.hw },
2493			.num_parents = 1,
2494			.flags = CLK_SET_RATE_PARENT,
2495			.ops = &clk_branch2_ops,
2496		},
2497	},
2498};
2499
2500static struct clk_branch gcc_pcie1_aux_clk = {
2501	.halt_reg = 0x76014,
2502	.clkr = {
2503		.enable_reg = 0x76014,
2504		.enable_mask = BIT(0),
2505		.hw.init = &(struct clk_init_data){
2506			.name = "gcc_pcie1_aux_clk",
2507			.parent_hws = (const struct clk_hw *[]){
2508				&pcie1_aux_clk_src.clkr.hw },
2509			.num_parents = 1,
2510			.flags = CLK_SET_RATE_PARENT,
2511			.ops = &clk_branch2_ops,
2512		},
2513	},
2514};
2515
2516static struct clk_branch gcc_pcie1_axi_m_clk = {
2517	.halt_reg = 0x76008,
2518	.clkr = {
2519		.enable_reg = 0x76008,
2520		.enable_mask = BIT(0),
2521		.hw.init = &(struct clk_init_data){
2522			.name = "gcc_pcie1_axi_m_clk",
2523			.parent_hws = (const struct clk_hw *[]){
2524				&pcie1_axi_clk_src.clkr.hw },
2525			.num_parents = 1,
2526			.flags = CLK_SET_RATE_PARENT,
2527			.ops = &clk_branch2_ops,
2528		},
2529	},
2530};
2531
2532static struct clk_branch gcc_pcie1_axi_s_clk = {
2533	.halt_reg = 0x7600c,
2534	.clkr = {
2535		.enable_reg = 0x7600c,
2536		.enable_mask = BIT(0),
2537		.hw.init = &(struct clk_init_data){
2538			.name = "gcc_pcie1_axi_s_clk",
2539			.parent_hws = (const struct clk_hw *[]){
2540				&pcie1_axi_clk_src.clkr.hw },
2541			.num_parents = 1,
2542			.flags = CLK_SET_RATE_PARENT,
2543			.ops = &clk_branch2_ops,
2544		},
2545	},
2546};
2547
2548static struct clk_branch gcc_pcie1_pipe_clk = {
2549	.halt_reg = 0x76018,
2550	.halt_check = BRANCH_HALT_DELAY,
2551	.clkr = {
2552		.enable_reg = 0x76018,
2553		.enable_mask = BIT(0),
2554		.hw.init = &(struct clk_init_data){
2555			.name = "gcc_pcie1_pipe_clk",
2556			.parent_hws = (const struct clk_hw *[]){
2557				&pcie1_pipe_clk_src.clkr.hw },
2558			.num_parents = 1,
2559			.flags = CLK_SET_RATE_PARENT,
2560			.ops = &clk_branch2_ops,
2561		},
2562	},
2563};
2564
2565static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2566	.halt_reg = 0x2604c,
2567	.clkr = {
2568		.enable_reg = 0x2604c,
2569		.enable_mask = BIT(0),
2570		.hw.init = &(struct clk_init_data){
2571			.name = "gcc_sys_noc_pcie1_axi_clk",
2572			.parent_hws = (const struct clk_hw *[]){
2573				&pcie1_axi_clk_src.clkr.hw },
2574			.num_parents = 1,
2575			.flags = CLK_SET_RATE_PARENT,
2576			.ops = &clk_branch2_ops,
2577		},
2578	},
2579};
2580
2581static struct clk_branch gcc_usb0_aux_clk = {
2582	.halt_reg = 0x3e044,
2583	.clkr = {
2584		.enable_reg = 0x3e044,
2585		.enable_mask = BIT(0),
2586		.hw.init = &(struct clk_init_data){
2587			.name = "gcc_usb0_aux_clk",
2588			.parent_hws = (const struct clk_hw *[]){
2589				&usb0_aux_clk_src.clkr.hw },
2590			.num_parents = 1,
2591			.flags = CLK_SET_RATE_PARENT,
2592			.ops = &clk_branch2_ops,
2593		},
2594	},
2595};
2596
2597static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2598	.halt_reg = 0x26040,
2599	.clkr = {
2600		.enable_reg = 0x26040,
2601		.enable_mask = BIT(0),
2602		.hw.init = &(struct clk_init_data){
2603			.name = "gcc_sys_noc_usb0_axi_clk",
2604			.parent_hws = (const struct clk_hw *[]){
2605				&usb0_master_clk_src.clkr.hw },
2606			.num_parents = 1,
2607			.flags = CLK_SET_RATE_PARENT,
2608			.ops = &clk_branch2_ops,
2609		},
2610	},
2611};
2612
2613static struct clk_branch gcc_usb0_master_clk = {
2614	.halt_reg = 0x3e000,
2615	.clkr = {
2616		.enable_reg = 0x3e000,
2617		.enable_mask = BIT(0),
2618		.hw.init = &(struct clk_init_data){
2619			.name = "gcc_usb0_master_clk",
2620			.parent_hws = (const struct clk_hw *[]){
2621				&usb0_master_clk_src.clkr.hw },
2622			.num_parents = 1,
2623			.flags = CLK_SET_RATE_PARENT,
2624			.ops = &clk_branch2_ops,
2625		},
2626	},
2627};
2628
2629static struct clk_branch gcc_usb0_mock_utmi_clk = {
2630	.halt_reg = 0x3e008,
2631	.clkr = {
2632		.enable_reg = 0x3e008,
2633		.enable_mask = BIT(0),
2634		.hw.init = &(struct clk_init_data){
2635			.name = "gcc_usb0_mock_utmi_clk",
2636			.parent_hws = (const struct clk_hw *[]){
2637				&usb0_mock_utmi_clk_src.clkr.hw },
2638			.num_parents = 1,
2639			.flags = CLK_SET_RATE_PARENT,
2640			.ops = &clk_branch2_ops,
2641		},
2642	},
2643};
2644
2645static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2646	.halt_reg = 0x3e080,
2647	.clkr = {
2648		.enable_reg = 0x3e080,
2649		.enable_mask = BIT(0),
2650		.hw.init = &(struct clk_init_data){
2651			.name = "gcc_usb0_phy_cfg_ahb_clk",
2652			.parent_hws = (const struct clk_hw *[]){
2653				&pcnoc_clk_src.hw },
2654			.num_parents = 1,
2655			.flags = CLK_SET_RATE_PARENT,
2656			.ops = &clk_branch2_ops,
2657		},
2658	},
2659};
2660
2661static struct clk_branch gcc_usb0_pipe_clk = {
2662	.halt_reg = 0x3e040,
2663	.halt_check = BRANCH_HALT_DELAY,
2664	.clkr = {
2665		.enable_reg = 0x3e040,
2666		.enable_mask = BIT(0),
2667		.hw.init = &(struct clk_init_data){
2668			.name = "gcc_usb0_pipe_clk",
2669			.parent_hws = (const struct clk_hw *[]){
2670				&usb0_pipe_clk_src.clkr.hw },
2671			.num_parents = 1,
2672			.flags = CLK_SET_RATE_PARENT,
2673			.ops = &clk_branch2_ops,
2674		},
2675	},
2676};
2677
2678static struct clk_branch gcc_usb0_sleep_clk = {
2679	.halt_reg = 0x3e004,
2680	.clkr = {
2681		.enable_reg = 0x3e004,
2682		.enable_mask = BIT(0),
2683		.hw.init = &(struct clk_init_data){
2684			.name = "gcc_usb0_sleep_clk",
2685			.parent_hws = (const struct clk_hw *[]){
2686				&gcc_sleep_clk_src.clkr.hw },
2687			.num_parents = 1,
2688			.flags = CLK_SET_RATE_PARENT,
2689			.ops = &clk_branch2_ops,
2690		},
2691	},
2692};
2693
2694static struct clk_branch gcc_usb1_aux_clk = {
2695	.halt_reg = 0x3f044,
2696	.clkr = {
2697		.enable_reg = 0x3f044,
2698		.enable_mask = BIT(0),
2699		.hw.init = &(struct clk_init_data){
2700			.name = "gcc_usb1_aux_clk",
2701			.parent_hws = (const struct clk_hw *[]){
2702				&usb1_aux_clk_src.clkr.hw },
2703			.num_parents = 1,
2704			.flags = CLK_SET_RATE_PARENT,
2705			.ops = &clk_branch2_ops,
2706		},
2707	},
2708};
2709
2710static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2711	.halt_reg = 0x26044,
2712	.clkr = {
2713		.enable_reg = 0x26044,
2714		.enable_mask = BIT(0),
2715		.hw.init = &(struct clk_init_data){
2716			.name = "gcc_sys_noc_usb1_axi_clk",
2717			.parent_hws = (const struct clk_hw *[]){
2718				&usb1_master_clk_src.clkr.hw },
2719			.num_parents = 1,
2720			.flags = CLK_SET_RATE_PARENT,
2721			.ops = &clk_branch2_ops,
2722		},
2723	},
2724};
2725
2726static struct clk_branch gcc_usb1_master_clk = {
2727	.halt_reg = 0x3f000,
2728	.clkr = {
2729		.enable_reg = 0x3f000,
2730		.enable_mask = BIT(0),
2731		.hw.init = &(struct clk_init_data){
2732			.name = "gcc_usb1_master_clk",
2733			.parent_hws = (const struct clk_hw *[]){
2734				&usb1_master_clk_src.clkr.hw },
2735			.num_parents = 1,
2736			.flags = CLK_SET_RATE_PARENT,
2737			.ops = &clk_branch2_ops,
2738		},
2739	},
2740};
2741
2742static struct clk_branch gcc_usb1_mock_utmi_clk = {
2743	.halt_reg = 0x3f008,
2744	.clkr = {
2745		.enable_reg = 0x3f008,
2746		.enable_mask = BIT(0),
2747		.hw.init = &(struct clk_init_data){
2748			.name = "gcc_usb1_mock_utmi_clk",
2749			.parent_hws = (const struct clk_hw *[]){
2750				&usb1_mock_utmi_clk_src.clkr.hw },
2751			.num_parents = 1,
2752			.flags = CLK_SET_RATE_PARENT,
2753			.ops = &clk_branch2_ops,
2754		},
2755	},
2756};
2757
2758static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2759	.halt_reg = 0x3f080,
2760	.clkr = {
2761		.enable_reg = 0x3f080,
2762		.enable_mask = BIT(0),
2763		.hw.init = &(struct clk_init_data){
2764			.name = "gcc_usb1_phy_cfg_ahb_clk",
2765			.parent_hws = (const struct clk_hw *[]){
2766				&pcnoc_clk_src.hw },
2767			.num_parents = 1,
2768			.flags = CLK_SET_RATE_PARENT,
2769			.ops = &clk_branch2_ops,
2770		},
2771	},
2772};
2773
2774static struct clk_branch gcc_usb1_pipe_clk = {
2775	.halt_reg = 0x3f040,
2776	.halt_check = BRANCH_HALT_DELAY,
2777	.clkr = {
2778		.enable_reg = 0x3f040,
2779		.enable_mask = BIT(0),
2780		.hw.init = &(struct clk_init_data){
2781			.name = "gcc_usb1_pipe_clk",
2782			.parent_hws = (const struct clk_hw *[]){
2783				&usb1_pipe_clk_src.clkr.hw },
2784			.num_parents = 1,
2785			.flags = CLK_SET_RATE_PARENT,
2786			.ops = &clk_branch2_ops,
2787		},
2788	},
2789};
2790
2791static struct clk_branch gcc_usb1_sleep_clk = {
2792	.halt_reg = 0x3f004,
2793	.clkr = {
2794		.enable_reg = 0x3f004,
2795		.enable_mask = BIT(0),
2796		.hw.init = &(struct clk_init_data){
2797			.name = "gcc_usb1_sleep_clk",
2798			.parent_hws = (const struct clk_hw *[]){
2799				&gcc_sleep_clk_src.clkr.hw },
2800			.num_parents = 1,
2801			.flags = CLK_SET_RATE_PARENT,
2802			.ops = &clk_branch2_ops,
2803		},
2804	},
2805};
2806
2807static struct clk_branch gcc_sdcc1_ahb_clk = {
2808	.halt_reg = 0x4201c,
2809	.clkr = {
2810		.enable_reg = 0x4201c,
2811		.enable_mask = BIT(0),
2812		.hw.init = &(struct clk_init_data){
2813			.name = "gcc_sdcc1_ahb_clk",
2814			.parent_hws = (const struct clk_hw *[]){
2815				&pcnoc_clk_src.hw },
2816			.num_parents = 1,
2817			.flags = CLK_SET_RATE_PARENT,
2818			.ops = &clk_branch2_ops,
2819		},
2820	},
2821};
2822
2823static struct clk_branch gcc_sdcc1_apps_clk = {
2824	.halt_reg = 0x42018,
2825	.clkr = {
2826		.enable_reg = 0x42018,
2827		.enable_mask = BIT(0),
2828		.hw.init = &(struct clk_init_data){
2829			.name = "gcc_sdcc1_apps_clk",
2830			.parent_hws = (const struct clk_hw *[]){
2831				&sdcc1_apps_clk_src.clkr.hw },
2832			.num_parents = 1,
2833			.flags = CLK_SET_RATE_PARENT,
2834			.ops = &clk_branch2_ops,
2835		},
2836	},
2837};
2838
2839static struct clk_branch gcc_sdcc1_ice_core_clk = {
2840	.halt_reg = 0x5d014,
2841	.clkr = {
2842		.enable_reg = 0x5d014,
2843		.enable_mask = BIT(0),
2844		.hw.init = &(struct clk_init_data){
2845			.name = "gcc_sdcc1_ice_core_clk",
2846			.parent_hws = (const struct clk_hw *[]){
2847				&sdcc1_ice_core_clk_src.clkr.hw },
2848			.num_parents = 1,
2849			.flags = CLK_SET_RATE_PARENT,
2850			.ops = &clk_branch2_ops,
2851		},
2852	},
2853};
2854
2855static struct clk_branch gcc_sdcc2_ahb_clk = {
2856	.halt_reg = 0x4301c,
2857	.clkr = {
2858		.enable_reg = 0x4301c,
2859		.enable_mask = BIT(0),
2860		.hw.init = &(struct clk_init_data){
2861			.name = "gcc_sdcc2_ahb_clk",
2862			.parent_hws = (const struct clk_hw *[]){
2863				&pcnoc_clk_src.hw },
2864			.num_parents = 1,
2865			.flags = CLK_SET_RATE_PARENT,
2866			.ops = &clk_branch2_ops,
2867		},
2868	},
2869};
2870
2871static struct clk_branch gcc_sdcc2_apps_clk = {
2872	.halt_reg = 0x43018,
2873	.clkr = {
2874		.enable_reg = 0x43018,
2875		.enable_mask = BIT(0),
2876		.hw.init = &(struct clk_init_data){
2877			.name = "gcc_sdcc2_apps_clk",
2878			.parent_hws = (const struct clk_hw *[]){
2879				&sdcc2_apps_clk_src.clkr.hw },
2880			.num_parents = 1,
2881			.flags = CLK_SET_RATE_PARENT,
2882			.ops = &clk_branch2_ops,
2883		},
2884	},
2885};
2886
2887static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2888	.halt_reg = 0x1d03c,
2889	.clkr = {
2890		.enable_reg = 0x1d03c,
2891		.enable_mask = BIT(0),
2892		.hw.init = &(struct clk_init_data){
2893			.name = "gcc_mem_noc_nss_axi_clk",
2894			.parent_hws = (const struct clk_hw *[]){
2895				&nss_noc_clk_src.hw },
2896			.num_parents = 1,
2897			.flags = CLK_SET_RATE_PARENT,
2898			.ops = &clk_branch2_ops,
2899		},
2900	},
2901};
2902
2903static struct clk_branch gcc_nss_ce_apb_clk = {
2904	.halt_reg = 0x68174,
2905	.clkr = {
2906		.enable_reg = 0x68174,
2907		.enable_mask = BIT(0),
2908		.hw.init = &(struct clk_init_data){
2909			.name = "gcc_nss_ce_apb_clk",
2910			.parent_hws = (const struct clk_hw *[]){
2911				&nss_ce_clk_src.clkr.hw },
2912			.num_parents = 1,
2913			.flags = CLK_SET_RATE_PARENT,
2914			.ops = &clk_branch2_ops,
2915		},
2916	},
2917};
2918
2919static struct clk_branch gcc_nss_ce_axi_clk = {
2920	.halt_reg = 0x68170,
2921	.clkr = {
2922		.enable_reg = 0x68170,
2923		.enable_mask = BIT(0),
2924		.hw.init = &(struct clk_init_data){
2925			.name = "gcc_nss_ce_axi_clk",
2926			.parent_hws = (const struct clk_hw *[]){
2927				&nss_ce_clk_src.clkr.hw },
2928			.num_parents = 1,
2929			.flags = CLK_SET_RATE_PARENT,
2930			.ops = &clk_branch2_ops,
2931		},
2932	},
2933};
2934
2935static struct clk_branch gcc_nss_cfg_clk = {
2936	.halt_reg = 0x68160,
2937	.clkr = {
2938		.enable_reg = 0x68160,
2939		.enable_mask = BIT(0),
2940		.hw.init = &(struct clk_init_data){
2941			.name = "gcc_nss_cfg_clk",
2942			.parent_hws = (const struct clk_hw *[]){
2943				&pcnoc_clk_src.hw },
2944			.num_parents = 1,
2945			.flags = CLK_SET_RATE_PARENT,
2946			.ops = &clk_branch2_ops,
2947		},
2948	},
2949};
2950
2951static struct clk_branch gcc_nss_crypto_clk = {
2952	.halt_reg = 0x68164,
2953	.clkr = {
2954		.enable_reg = 0x68164,
2955		.enable_mask = BIT(0),
2956		.hw.init = &(struct clk_init_data){
2957			.name = "gcc_nss_crypto_clk",
2958			.parent_hws = (const struct clk_hw *[]){
2959				&nss_crypto_clk_src.clkr.hw },
2960			.num_parents = 1,
2961			.flags = CLK_SET_RATE_PARENT,
2962			.ops = &clk_branch2_ops,
2963		},
2964	},
2965};
2966
2967static struct clk_branch gcc_nss_csr_clk = {
2968	.halt_reg = 0x68318,
2969	.clkr = {
2970		.enable_reg = 0x68318,
2971		.enable_mask = BIT(0),
2972		.hw.init = &(struct clk_init_data){
2973			.name = "gcc_nss_csr_clk",
2974			.parent_hws = (const struct clk_hw *[]){
2975				&nss_ce_clk_src.clkr.hw },
2976			.num_parents = 1,
2977			.flags = CLK_SET_RATE_PARENT,
2978			.ops = &clk_branch2_ops,
2979		},
2980	},
2981};
2982
2983static struct clk_branch gcc_nss_edma_cfg_clk = {
2984	.halt_reg = 0x6819c,
2985	.clkr = {
2986		.enable_reg = 0x6819c,
2987		.enable_mask = BIT(0),
2988		.hw.init = &(struct clk_init_data){
2989			.name = "gcc_nss_edma_cfg_clk",
2990			.parent_hws = (const struct clk_hw *[]){
2991				&nss_ppe_clk_src.clkr.hw },
2992			.num_parents = 1,
2993			.flags = CLK_SET_RATE_PARENT,
2994			.ops = &clk_branch2_ops,
2995		},
2996	},
2997};
2998
2999static struct clk_branch gcc_nss_edma_clk = {
3000	.halt_reg = 0x68198,
3001	.clkr = {
3002		.enable_reg = 0x68198,
3003		.enable_mask = BIT(0),
3004		.hw.init = &(struct clk_init_data){
3005			.name = "gcc_nss_edma_clk",
3006			.parent_hws = (const struct clk_hw *[]){
3007				&nss_ppe_clk_src.clkr.hw },
3008			.num_parents = 1,
3009			.flags = CLK_SET_RATE_PARENT,
3010			.ops = &clk_branch2_ops,
3011		},
3012	},
3013};
3014
3015static struct clk_branch gcc_nss_imem_clk = {
3016	.halt_reg = 0x68178,
3017	.clkr = {
3018		.enable_reg = 0x68178,
3019		.enable_mask = BIT(0),
3020		.hw.init = &(struct clk_init_data){
3021			.name = "gcc_nss_imem_clk",
3022			.parent_hws = (const struct clk_hw *[]){
3023				&nss_imem_clk_src.clkr.hw },
3024			.num_parents = 1,
3025			.flags = CLK_SET_RATE_PARENT,
3026			.ops = &clk_branch2_ops,
3027		},
3028	},
3029};
3030
3031static struct clk_branch gcc_nss_noc_clk = {
3032	.halt_reg = 0x68168,
3033	.clkr = {
3034		.enable_reg = 0x68168,
3035		.enable_mask = BIT(0),
3036		.hw.init = &(struct clk_init_data){
3037			.name = "gcc_nss_noc_clk",
3038			.parent_hws = (const struct clk_hw *[]){
3039				&nss_noc_clk_src.hw },
3040			.num_parents = 1,
3041			.flags = CLK_SET_RATE_PARENT,
3042			.ops = &clk_branch2_ops,
3043		},
3044	},
3045};
3046
3047static struct clk_branch gcc_nss_ppe_btq_clk = {
3048	.halt_reg = 0x6833c,
3049	.clkr = {
3050		.enable_reg = 0x6833c,
3051		.enable_mask = BIT(0),
3052		.hw.init = &(struct clk_init_data){
3053			.name = "gcc_nss_ppe_btq_clk",
3054			.parent_hws = (const struct clk_hw *[]){
3055				&nss_ppe_clk_src.clkr.hw },
3056			.num_parents = 1,
3057			.flags = CLK_SET_RATE_PARENT,
3058			.ops = &clk_branch2_ops,
3059		},
3060	},
3061};
3062
3063static struct clk_branch gcc_nss_ppe_cfg_clk = {
3064	.halt_reg = 0x68194,
3065	.clkr = {
3066		.enable_reg = 0x68194,
3067		.enable_mask = BIT(0),
3068		.hw.init = &(struct clk_init_data){
3069			.name = "gcc_nss_ppe_cfg_clk",
3070			.parent_hws = (const struct clk_hw *[]){
3071				&nss_ppe_clk_src.clkr.hw },
3072			.num_parents = 1,
3073			.flags = CLK_SET_RATE_PARENT,
3074			.ops = &clk_branch2_ops,
3075		},
3076	},
3077};
3078
3079static struct clk_branch gcc_nss_ppe_clk = {
3080	.halt_reg = 0x68190,
3081	.clkr = {
3082		.enable_reg = 0x68190,
3083		.enable_mask = BIT(0),
3084		.hw.init = &(struct clk_init_data){
3085			.name = "gcc_nss_ppe_clk",
3086			.parent_hws = (const struct clk_hw *[]){
3087				&nss_ppe_clk_src.clkr.hw },
3088			.num_parents = 1,
3089			.flags = CLK_SET_RATE_PARENT,
3090			.ops = &clk_branch2_ops,
3091		},
3092	},
3093};
3094
3095static struct clk_branch gcc_nss_ppe_ipe_clk = {
3096	.halt_reg = 0x68338,
3097	.clkr = {
3098		.enable_reg = 0x68338,
3099		.enable_mask = BIT(0),
3100		.hw.init = &(struct clk_init_data){
3101			.name = "gcc_nss_ppe_ipe_clk",
3102			.parent_hws = (const struct clk_hw *[]){
3103				&nss_ppe_clk_src.clkr.hw },
3104			.num_parents = 1,
3105			.flags = CLK_SET_RATE_PARENT,
3106			.ops = &clk_branch2_ops,
3107		},
3108	},
3109};
3110
3111static struct clk_branch gcc_nss_ptp_ref_clk = {
3112	.halt_reg = 0x6816c,
3113	.clkr = {
3114		.enable_reg = 0x6816c,
3115		.enable_mask = BIT(0),
3116		.hw.init = &(struct clk_init_data){
3117			.name = "gcc_nss_ptp_ref_clk",
3118			.parent_hws = (const struct clk_hw *[]){
3119				&nss_ppe_cdiv_clk_src.hw },
3120			.num_parents = 1,
3121			.flags = CLK_SET_RATE_PARENT,
3122			.ops = &clk_branch2_ops,
3123		},
3124	},
3125};
3126
3127static struct clk_branch gcc_crypto_ppe_clk = {
3128	.halt_reg = 0x68310,
3129	.halt_bit = 31,
3130	.clkr = {
3131		.enable_reg = 0x68310,
3132		.enable_mask = BIT(0),
3133		.hw.init = &(struct clk_init_data){
3134			.name = "gcc_crypto_ppe_clk",
3135			.parent_hws = (const struct clk_hw *[]){
3136				&nss_ppe_clk_src.clkr.hw },
3137			.num_parents = 1,
3138			.flags = CLK_SET_RATE_PARENT,
3139			.ops = &clk_branch2_ops,
3140		},
3141	},
3142};
3143
3144static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3145	.halt_reg = 0x6830c,
3146	.clkr = {
3147		.enable_reg = 0x6830c,
3148		.enable_mask = BIT(0),
3149		.hw.init = &(struct clk_init_data){
3150			.name = "gcc_nssnoc_ce_apb_clk",
3151			.parent_hws = (const struct clk_hw *[]){
3152				&nss_ce_clk_src.clkr.hw },
3153			.num_parents = 1,
3154			.flags = CLK_SET_RATE_PARENT,
3155			.ops = &clk_branch2_ops,
3156		},
3157	},
3158};
3159
3160static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3161	.halt_reg = 0x68308,
3162	.clkr = {
3163		.enable_reg = 0x68308,
3164		.enable_mask = BIT(0),
3165		.hw.init = &(struct clk_init_data){
3166			.name = "gcc_nssnoc_ce_axi_clk",
3167			.parent_hws = (const struct clk_hw *[]){
3168				&nss_ce_clk_src.clkr.hw },
3169			.num_parents = 1,
3170			.flags = CLK_SET_RATE_PARENT,
3171			.ops = &clk_branch2_ops,
3172		},
3173	},
3174};
3175
3176static struct clk_branch gcc_nssnoc_crypto_clk = {
3177	.halt_reg = 0x68314,
3178	.clkr = {
3179		.enable_reg = 0x68314,
3180		.enable_mask = BIT(0),
3181		.hw.init = &(struct clk_init_data){
3182			.name = "gcc_nssnoc_crypto_clk",
3183			.parent_hws = (const struct clk_hw *[]){
3184				&nss_crypto_clk_src.clkr.hw },
3185			.num_parents = 1,
3186			.flags = CLK_SET_RATE_PARENT,
3187			.ops = &clk_branch2_ops,
3188		},
3189	},
3190};
3191
3192static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3193	.halt_reg = 0x68304,
3194	.clkr = {
3195		.enable_reg = 0x68304,
3196		.enable_mask = BIT(0),
3197		.hw.init = &(struct clk_init_data){
3198			.name = "gcc_nssnoc_ppe_cfg_clk",
3199			.parent_hws = (const struct clk_hw *[]){
3200				&nss_ppe_clk_src.clkr.hw },
3201			.num_parents = 1,
3202			.flags = CLK_SET_RATE_PARENT,
3203			.ops = &clk_branch2_ops,
3204		},
3205	},
3206};
3207
3208static struct clk_branch gcc_nssnoc_ppe_clk = {
3209	.halt_reg = 0x68300,
3210	.clkr = {
3211		.enable_reg = 0x68300,
3212		.enable_mask = BIT(0),
3213		.hw.init = &(struct clk_init_data){
3214			.name = "gcc_nssnoc_ppe_clk",
3215			.parent_hws = (const struct clk_hw *[]){
3216				&nss_ppe_clk_src.clkr.hw },
3217			.num_parents = 1,
3218			.flags = CLK_SET_RATE_PARENT,
3219			.ops = &clk_branch2_ops,
3220		},
3221	},
3222};
3223
3224static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3225	.halt_reg = 0x68180,
3226	.clkr = {
3227		.enable_reg = 0x68180,
3228		.enable_mask = BIT(0),
3229		.hw.init = &(struct clk_init_data){
3230			.name = "gcc_nssnoc_qosgen_ref_clk",
3231			.parent_hws = (const struct clk_hw *[]){
3232				&gcc_xo_clk_src.clkr.hw },
3233			.num_parents = 1,
3234			.flags = CLK_SET_RATE_PARENT,
3235			.ops = &clk_branch2_ops,
3236		},
3237	},
3238};
3239
3240static struct clk_branch gcc_nssnoc_snoc_clk = {
3241	.halt_reg = 0x68188,
3242	.clkr = {
3243		.enable_reg = 0x68188,
3244		.enable_mask = BIT(0),
3245		.hw.init = &(struct clk_init_data){
3246			.name = "gcc_nssnoc_snoc_clk",
3247			.parent_hws = (const struct clk_hw *[]){
3248				&system_noc_clk_src.hw },
3249			.num_parents = 1,
3250			.flags = CLK_SET_RATE_PARENT,
3251			.ops = &clk_branch2_ops,
3252		},
3253	},
3254};
3255
3256static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3257	.halt_reg = 0x68184,
3258	.clkr = {
3259		.enable_reg = 0x68184,
3260		.enable_mask = BIT(0),
3261		.hw.init = &(struct clk_init_data){
3262			.name = "gcc_nssnoc_timeout_ref_clk",
3263			.parent_hws = (const struct clk_hw *[]){
3264				&gcc_xo_div4_clk_src.hw },
3265			.num_parents = 1,
3266			.flags = CLK_SET_RATE_PARENT,
3267			.ops = &clk_branch2_ops,
3268		},
3269	},
3270};
3271
3272static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3273	.halt_reg = 0x68270,
3274	.clkr = {
3275		.enable_reg = 0x68270,
3276		.enable_mask = BIT(0),
3277		.hw.init = &(struct clk_init_data){
3278			.name = "gcc_nssnoc_ubi0_ahb_clk",
3279			.parent_hws = (const struct clk_hw *[]){
3280				&nss_ce_clk_src.clkr.hw },
3281			.num_parents = 1,
3282			.flags = CLK_SET_RATE_PARENT,
3283			.ops = &clk_branch2_ops,
3284		},
3285	},
3286};
3287
3288static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3289	.halt_reg = 0x68274,
3290	.clkr = {
3291		.enable_reg = 0x68274,
3292		.enable_mask = BIT(0),
3293		.hw.init = &(struct clk_init_data){
3294			.name = "gcc_nssnoc_ubi1_ahb_clk",
3295			.parent_hws = (const struct clk_hw *[]){
3296				&nss_ce_clk_src.clkr.hw },
3297			.num_parents = 1,
3298			.flags = CLK_SET_RATE_PARENT,
3299			.ops = &clk_branch2_ops,
3300		},
3301	},
3302};
3303
3304static struct clk_branch gcc_ubi0_ahb_clk = {
3305	.halt_reg = 0x6820c,
3306	.halt_check = BRANCH_HALT_DELAY,
3307	.clkr = {
3308		.enable_reg = 0x6820c,
3309		.enable_mask = BIT(0),
3310		.hw.init = &(struct clk_init_data){
3311			.name = "gcc_ubi0_ahb_clk",
3312			.parent_hws = (const struct clk_hw *[]){
3313				&nss_ce_clk_src.clkr.hw },
3314			.num_parents = 1,
3315			.flags = CLK_SET_RATE_PARENT,
3316			.ops = &clk_branch2_ops,
3317		},
3318	},
3319};
3320
3321static struct clk_branch gcc_ubi0_axi_clk = {
3322	.halt_reg = 0x68200,
3323	.halt_check = BRANCH_HALT_DELAY,
3324	.clkr = {
3325		.enable_reg = 0x68200,
3326		.enable_mask = BIT(0),
3327		.hw.init = &(struct clk_init_data){
3328			.name = "gcc_ubi0_axi_clk",
3329			.parent_hws = (const struct clk_hw *[]){
3330				&nss_noc_clk_src.hw },
3331			.num_parents = 1,
3332			.flags = CLK_SET_RATE_PARENT,
3333			.ops = &clk_branch2_ops,
3334		},
3335	},
3336};
3337
3338static struct clk_branch gcc_ubi0_nc_axi_clk = {
3339	.halt_reg = 0x68204,
3340	.halt_check = BRANCH_HALT_DELAY,
3341	.clkr = {
3342		.enable_reg = 0x68204,
3343		.enable_mask = BIT(0),
3344		.hw.init = &(struct clk_init_data){
3345			.name = "gcc_ubi0_nc_axi_clk",
3346			.parent_hws = (const struct clk_hw *[]){
3347				&nss_noc_clk_src.hw },
3348			.num_parents = 1,
3349			.flags = CLK_SET_RATE_PARENT,
3350			.ops = &clk_branch2_ops,
3351		},
3352	},
3353};
3354
3355static struct clk_branch gcc_ubi0_core_clk = {
3356	.halt_reg = 0x68210,
3357	.halt_check = BRANCH_HALT_DELAY,
3358	.clkr = {
3359		.enable_reg = 0x68210,
3360		.enable_mask = BIT(0),
3361		.hw.init = &(struct clk_init_data){
3362			.name = "gcc_ubi0_core_clk",
3363			.parent_hws = (const struct clk_hw *[]){
3364				&nss_ubi0_div_clk_src.clkr.hw },
3365			.num_parents = 1,
3366			.flags = CLK_SET_RATE_PARENT,
3367			.ops = &clk_branch2_ops,
3368		},
3369	},
3370};
3371
3372static struct clk_branch gcc_ubi0_mpt_clk = {
3373	.halt_reg = 0x68208,
3374	.halt_check = BRANCH_HALT_DELAY,
3375	.clkr = {
3376		.enable_reg = 0x68208,
3377		.enable_mask = BIT(0),
3378		.hw.init = &(struct clk_init_data){
3379			.name = "gcc_ubi0_mpt_clk",
3380			.parent_hws = (const struct clk_hw *[]){
3381				&ubi_mpt_clk_src.clkr.hw },
3382			.num_parents = 1,
3383			.flags = CLK_SET_RATE_PARENT,
3384			.ops = &clk_branch2_ops,
3385		},
3386	},
3387};
3388
3389static struct clk_branch gcc_ubi1_ahb_clk = {
3390	.halt_reg = 0x6822c,
3391	.halt_check = BRANCH_HALT_DELAY,
3392	.clkr = {
3393		.enable_reg = 0x6822c,
3394		.enable_mask = BIT(0),
3395		.hw.init = &(struct clk_init_data){
3396			.name = "gcc_ubi1_ahb_clk",
3397			.parent_hws = (const struct clk_hw *[]){
3398				&nss_ce_clk_src.clkr.hw },
3399			.num_parents = 1,
3400			.flags = CLK_SET_RATE_PARENT,
3401			.ops = &clk_branch2_ops,
3402		},
3403	},
3404};
3405
3406static struct clk_branch gcc_ubi1_axi_clk = {
3407	.halt_reg = 0x68220,
3408	.halt_check = BRANCH_HALT_DELAY,
3409	.clkr = {
3410		.enable_reg = 0x68220,
3411		.enable_mask = BIT(0),
3412		.hw.init = &(struct clk_init_data){
3413			.name = "gcc_ubi1_axi_clk",
3414			.parent_hws = (const struct clk_hw *[]){
3415				&nss_noc_clk_src.hw },
3416			.num_parents = 1,
3417			.flags = CLK_SET_RATE_PARENT,
3418			.ops = &clk_branch2_ops,
3419		},
3420	},
3421};
3422
3423static struct clk_branch gcc_ubi1_nc_axi_clk = {
3424	.halt_reg = 0x68224,
3425	.halt_check = BRANCH_HALT_DELAY,
3426	.clkr = {
3427		.enable_reg = 0x68224,
3428		.enable_mask = BIT(0),
3429		.hw.init = &(struct clk_init_data){
3430			.name = "gcc_ubi1_nc_axi_clk",
3431			.parent_hws = (const struct clk_hw *[]){
3432				&nss_noc_clk_src.hw },
3433			.num_parents = 1,
3434			.flags = CLK_SET_RATE_PARENT,
3435			.ops = &clk_branch2_ops,
3436		},
3437	},
3438};
3439
3440static struct clk_branch gcc_ubi1_core_clk = {
3441	.halt_reg = 0x68230,
3442	.halt_check = BRANCH_HALT_DELAY,
3443	.clkr = {
3444		.enable_reg = 0x68230,
3445		.enable_mask = BIT(0),
3446		.hw.init = &(struct clk_init_data){
3447			.name = "gcc_ubi1_core_clk",
3448			.parent_hws = (const struct clk_hw *[]){
3449				&nss_ubi1_div_clk_src.clkr.hw },
3450			.num_parents = 1,
3451			.flags = CLK_SET_RATE_PARENT,
3452			.ops = &clk_branch2_ops,
3453		},
3454	},
3455};
3456
3457static struct clk_branch gcc_ubi1_mpt_clk = {
3458	.halt_reg = 0x68228,
3459	.halt_check = BRANCH_HALT_DELAY,
3460	.clkr = {
3461		.enable_reg = 0x68228,
3462		.enable_mask = BIT(0),
3463		.hw.init = &(struct clk_init_data){
3464			.name = "gcc_ubi1_mpt_clk",
3465			.parent_hws = (const struct clk_hw *[]){
3466				&ubi_mpt_clk_src.clkr.hw },
3467			.num_parents = 1,
3468			.flags = CLK_SET_RATE_PARENT,
3469			.ops = &clk_branch2_ops,
3470		},
3471	},
3472};
3473
3474static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3475	.halt_reg = 0x56308,
3476	.clkr = {
3477		.enable_reg = 0x56308,
3478		.enable_mask = BIT(0),
3479		.hw.init = &(struct clk_init_data){
3480			.name = "gcc_cmn_12gpll_ahb_clk",
3481			.parent_hws = (const struct clk_hw *[]){
3482				&pcnoc_clk_src.hw },
3483			.num_parents = 1,
3484			.flags = CLK_SET_RATE_PARENT,
3485			.ops = &clk_branch2_ops,
3486		},
3487	},
3488};
3489
3490static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3491	.halt_reg = 0x5630c,
3492	.clkr = {
3493		.enable_reg = 0x5630c,
3494		.enable_mask = BIT(0),
3495		.hw.init = &(struct clk_init_data){
3496			.name = "gcc_cmn_12gpll_sys_clk",
3497			.parent_hws = (const struct clk_hw *[]){
3498				&gcc_xo_clk_src.clkr.hw },
3499			.num_parents = 1,
3500			.flags = CLK_SET_RATE_PARENT,
3501			.ops = &clk_branch2_ops,
3502		},
3503	},
3504};
3505
3506static struct clk_branch gcc_mdio_ahb_clk = {
3507	.halt_reg = 0x58004,
3508	.clkr = {
3509		.enable_reg = 0x58004,
3510		.enable_mask = BIT(0),
3511		.hw.init = &(struct clk_init_data){
3512			.name = "gcc_mdio_ahb_clk",
3513			.parent_hws = (const struct clk_hw *[]){
3514				&pcnoc_clk_src.hw },
3515			.num_parents = 1,
3516			.flags = CLK_SET_RATE_PARENT,
3517			.ops = &clk_branch2_ops,
3518		},
3519	},
3520};
3521
3522static struct clk_branch gcc_uniphy0_ahb_clk = {
3523	.halt_reg = 0x56008,
3524	.clkr = {
3525		.enable_reg = 0x56008,
3526		.enable_mask = BIT(0),
3527		.hw.init = &(struct clk_init_data){
3528			.name = "gcc_uniphy0_ahb_clk",
3529			.parent_hws = (const struct clk_hw *[]){
3530				&pcnoc_clk_src.hw },
3531			.num_parents = 1,
3532			.flags = CLK_SET_RATE_PARENT,
3533			.ops = &clk_branch2_ops,
3534		},
3535	},
3536};
3537
3538static struct clk_branch gcc_uniphy0_sys_clk = {
3539	.halt_reg = 0x5600c,
3540	.clkr = {
3541		.enable_reg = 0x5600c,
3542		.enable_mask = BIT(0),
3543		.hw.init = &(struct clk_init_data){
3544			.name = "gcc_uniphy0_sys_clk",
3545			.parent_hws = (const struct clk_hw *[]){
3546				&gcc_xo_clk_src.clkr.hw },
3547			.num_parents = 1,
3548			.flags = CLK_SET_RATE_PARENT,
3549			.ops = &clk_branch2_ops,
3550		},
3551	},
3552};
3553
3554static struct clk_branch gcc_uniphy1_ahb_clk = {
3555	.halt_reg = 0x56108,
3556	.clkr = {
3557		.enable_reg = 0x56108,
3558		.enable_mask = BIT(0),
3559		.hw.init = &(struct clk_init_data){
3560			.name = "gcc_uniphy1_ahb_clk",
3561			.parent_hws = (const struct clk_hw *[]){
3562				&pcnoc_clk_src.hw },
3563			.num_parents = 1,
3564			.flags = CLK_SET_RATE_PARENT,
3565			.ops = &clk_branch2_ops,
3566		},
3567	},
3568};
3569
3570static struct clk_branch gcc_uniphy1_sys_clk = {
3571	.halt_reg = 0x5610c,
3572	.clkr = {
3573		.enable_reg = 0x5610c,
3574		.enable_mask = BIT(0),
3575		.hw.init = &(struct clk_init_data){
3576			.name = "gcc_uniphy1_sys_clk",
3577			.parent_hws = (const struct clk_hw *[]){
3578				&gcc_xo_clk_src.clkr.hw },
3579			.num_parents = 1,
3580			.flags = CLK_SET_RATE_PARENT,
3581			.ops = &clk_branch2_ops,
3582		},
3583	},
3584};
3585
3586static struct clk_branch gcc_uniphy2_ahb_clk = {
3587	.halt_reg = 0x56208,
3588	.clkr = {
3589		.enable_reg = 0x56208,
3590		.enable_mask = BIT(0),
3591		.hw.init = &(struct clk_init_data){
3592			.name = "gcc_uniphy2_ahb_clk",
3593			.parent_hws = (const struct clk_hw *[]){
3594				&pcnoc_clk_src.hw },
3595			.num_parents = 1,
3596			.flags = CLK_SET_RATE_PARENT,
3597			.ops = &clk_branch2_ops,
3598		},
3599	},
3600};
3601
3602static struct clk_branch gcc_uniphy2_sys_clk = {
3603	.halt_reg = 0x5620c,
3604	.clkr = {
3605		.enable_reg = 0x5620c,
3606		.enable_mask = BIT(0),
3607		.hw.init = &(struct clk_init_data){
3608			.name = "gcc_uniphy2_sys_clk",
3609			.parent_hws = (const struct clk_hw *[]){
3610				&gcc_xo_clk_src.clkr.hw },
3611			.num_parents = 1,
3612			.flags = CLK_SET_RATE_PARENT,
3613			.ops = &clk_branch2_ops,
3614		},
3615	},
3616};
3617
3618static struct clk_branch gcc_nss_port1_rx_clk = {
3619	.halt_reg = 0x68240,
3620	.clkr = {
3621		.enable_reg = 0x68240,
3622		.enable_mask = BIT(0),
3623		.hw.init = &(struct clk_init_data){
3624			.name = "gcc_nss_port1_rx_clk",
3625			.parent_hws = (const struct clk_hw *[]){
3626				&nss_port1_rx_div_clk_src.clkr.hw },
3627			.num_parents = 1,
3628			.flags = CLK_SET_RATE_PARENT,
3629			.ops = &clk_branch2_ops,
3630		},
3631	},
3632};
3633
3634static struct clk_branch gcc_nss_port1_tx_clk = {
3635	.halt_reg = 0x68244,
3636	.clkr = {
3637		.enable_reg = 0x68244,
3638		.enable_mask = BIT(0),
3639		.hw.init = &(struct clk_init_data){
3640			.name = "gcc_nss_port1_tx_clk",
3641			.parent_hws = (const struct clk_hw *[]){
3642				&nss_port1_tx_div_clk_src.clkr.hw },
3643			.num_parents = 1,
3644			.flags = CLK_SET_RATE_PARENT,
3645			.ops = &clk_branch2_ops,
3646		},
3647	},
3648};
3649
3650static struct clk_branch gcc_nss_port2_rx_clk = {
3651	.halt_reg = 0x68248,
3652	.clkr = {
3653		.enable_reg = 0x68248,
3654		.enable_mask = BIT(0),
3655		.hw.init = &(struct clk_init_data){
3656			.name = "gcc_nss_port2_rx_clk",
3657			.parent_hws = (const struct clk_hw *[]){
3658				&nss_port2_rx_div_clk_src.clkr.hw },
3659			.num_parents = 1,
3660			.flags = CLK_SET_RATE_PARENT,
3661			.ops = &clk_branch2_ops,
3662		},
3663	},
3664};
3665
3666static struct clk_branch gcc_nss_port2_tx_clk = {
3667	.halt_reg = 0x6824c,
3668	.clkr = {
3669		.enable_reg = 0x6824c,
3670		.enable_mask = BIT(0),
3671		.hw.init = &(struct clk_init_data){
3672			.name = "gcc_nss_port2_tx_clk",
3673			.parent_hws = (const struct clk_hw *[]){
3674				&nss_port2_tx_div_clk_src.clkr.hw },
3675			.num_parents = 1,
3676			.flags = CLK_SET_RATE_PARENT,
3677			.ops = &clk_branch2_ops,
3678		},
3679	},
3680};
3681
3682static struct clk_branch gcc_nss_port3_rx_clk = {
3683	.halt_reg = 0x68250,
3684	.clkr = {
3685		.enable_reg = 0x68250,
3686		.enable_mask = BIT(0),
3687		.hw.init = &(struct clk_init_data){
3688			.name = "gcc_nss_port3_rx_clk",
3689			.parent_hws = (const struct clk_hw *[]){
3690				&nss_port3_rx_div_clk_src.clkr.hw },
3691			.num_parents = 1,
3692			.flags = CLK_SET_RATE_PARENT,
3693			.ops = &clk_branch2_ops,
3694		},
3695	},
3696};
3697
3698static struct clk_branch gcc_nss_port3_tx_clk = {
3699	.halt_reg = 0x68254,
3700	.clkr = {
3701		.enable_reg = 0x68254,
3702		.enable_mask = BIT(0),
3703		.hw.init = &(struct clk_init_data){
3704			.name = "gcc_nss_port3_tx_clk",
3705			.parent_hws = (const struct clk_hw *[]){
3706				&nss_port3_tx_div_clk_src.clkr.hw },
3707			.num_parents = 1,
3708			.flags = CLK_SET_RATE_PARENT,
3709			.ops = &clk_branch2_ops,
3710		},
3711	},
3712};
3713
3714static struct clk_branch gcc_nss_port4_rx_clk = {
3715	.halt_reg = 0x68258,
3716	.clkr = {
3717		.enable_reg = 0x68258,
3718		.enable_mask = BIT(0),
3719		.hw.init = &(struct clk_init_data){
3720			.name = "gcc_nss_port4_rx_clk",
3721			.parent_hws = (const struct clk_hw *[]){
3722				&nss_port4_rx_div_clk_src.clkr.hw },
3723			.num_parents = 1,
3724			.flags = CLK_SET_RATE_PARENT,
3725			.ops = &clk_branch2_ops,
3726		},
3727	},
3728};
3729
3730static struct clk_branch gcc_nss_port4_tx_clk = {
3731	.halt_reg = 0x6825c,
3732	.clkr = {
3733		.enable_reg = 0x6825c,
3734		.enable_mask = BIT(0),
3735		.hw.init = &(struct clk_init_data){
3736			.name = "gcc_nss_port4_tx_clk",
3737			.parent_hws = (const struct clk_hw *[]){
3738				&nss_port4_tx_div_clk_src.clkr.hw },
3739			.num_parents = 1,
3740			.flags = CLK_SET_RATE_PARENT,
3741			.ops = &clk_branch2_ops,
3742		},
3743	},
3744};
3745
3746static struct clk_branch gcc_nss_port5_rx_clk = {
3747	.halt_reg = 0x68260,
3748	.clkr = {
3749		.enable_reg = 0x68260,
3750		.enable_mask = BIT(0),
3751		.hw.init = &(struct clk_init_data){
3752			.name = "gcc_nss_port5_rx_clk",
3753			.parent_hws = (const struct clk_hw *[]){
3754				&nss_port5_rx_div_clk_src.clkr.hw },
3755			.num_parents = 1,
3756			.flags = CLK_SET_RATE_PARENT,
3757			.ops = &clk_branch2_ops,
3758		},
3759	},
3760};
3761
3762static struct clk_branch gcc_nss_port5_tx_clk = {
3763	.halt_reg = 0x68264,
3764	.clkr = {
3765		.enable_reg = 0x68264,
3766		.enable_mask = BIT(0),
3767		.hw.init = &(struct clk_init_data){
3768			.name = "gcc_nss_port5_tx_clk",
3769			.parent_hws = (const struct clk_hw *[]){
3770				&nss_port5_tx_div_clk_src.clkr.hw },
3771			.num_parents = 1,
3772			.flags = CLK_SET_RATE_PARENT,
3773			.ops = &clk_branch2_ops,
3774		},
3775	},
3776};
3777
3778static struct clk_branch gcc_nss_port6_rx_clk = {
3779	.halt_reg = 0x68268,
3780	.clkr = {
3781		.enable_reg = 0x68268,
3782		.enable_mask = BIT(0),
3783		.hw.init = &(struct clk_init_data){
3784			.name = "gcc_nss_port6_rx_clk",
3785			.parent_hws = (const struct clk_hw *[]){
3786				&nss_port6_rx_div_clk_src.clkr.hw },
3787			.num_parents = 1,
3788			.flags = CLK_SET_RATE_PARENT,
3789			.ops = &clk_branch2_ops,
3790		},
3791	},
3792};
3793
3794static struct clk_branch gcc_nss_port6_tx_clk = {
3795	.halt_reg = 0x6826c,
3796	.clkr = {
3797		.enable_reg = 0x6826c,
3798		.enable_mask = BIT(0),
3799		.hw.init = &(struct clk_init_data){
3800			.name = "gcc_nss_port6_tx_clk",
3801			.parent_hws = (const struct clk_hw *[]){
3802				&nss_port6_tx_div_clk_src.clkr.hw },
3803			.num_parents = 1,
3804			.flags = CLK_SET_RATE_PARENT,
3805			.ops = &clk_branch2_ops,
3806		},
3807	},
3808};
3809
3810static struct clk_branch gcc_port1_mac_clk = {
3811	.halt_reg = 0x68320,
3812	.clkr = {
3813		.enable_reg = 0x68320,
3814		.enable_mask = BIT(0),
3815		.hw.init = &(struct clk_init_data){
3816			.name = "gcc_port1_mac_clk",
3817			.parent_hws = (const struct clk_hw *[]){
3818				&nss_ppe_clk_src.clkr.hw },
3819			.num_parents = 1,
3820			.flags = CLK_SET_RATE_PARENT,
3821			.ops = &clk_branch2_ops,
3822		},
3823	},
3824};
3825
3826static struct clk_branch gcc_port2_mac_clk = {
3827	.halt_reg = 0x68324,
3828	.clkr = {
3829		.enable_reg = 0x68324,
3830		.enable_mask = BIT(0),
3831		.hw.init = &(struct clk_init_data){
3832			.name = "gcc_port2_mac_clk",
3833			.parent_hws = (const struct clk_hw *[]){
3834				&nss_ppe_clk_src.clkr.hw },
3835			.num_parents = 1,
3836			.flags = CLK_SET_RATE_PARENT,
3837			.ops = &clk_branch2_ops,
3838		},
3839	},
3840};
3841
3842static struct clk_branch gcc_port3_mac_clk = {
3843	.halt_reg = 0x68328,
3844	.clkr = {
3845		.enable_reg = 0x68328,
3846		.enable_mask = BIT(0),
3847		.hw.init = &(struct clk_init_data){
3848			.name = "gcc_port3_mac_clk",
3849			.parent_hws = (const struct clk_hw *[]){
3850				&nss_ppe_clk_src.clkr.hw },
3851			.num_parents = 1,
3852			.flags = CLK_SET_RATE_PARENT,
3853			.ops = &clk_branch2_ops,
3854		},
3855	},
3856};
3857
3858static struct clk_branch gcc_port4_mac_clk = {
3859	.halt_reg = 0x6832c,
3860	.clkr = {
3861		.enable_reg = 0x6832c,
3862		.enable_mask = BIT(0),
3863		.hw.init = &(struct clk_init_data){
3864			.name = "gcc_port4_mac_clk",
3865			.parent_hws = (const struct clk_hw *[]){
3866				&nss_ppe_clk_src.clkr.hw },
3867			.num_parents = 1,
3868			.flags = CLK_SET_RATE_PARENT,
3869			.ops = &clk_branch2_ops,
3870		},
3871	},
3872};
3873
3874static struct clk_branch gcc_port5_mac_clk = {
3875	.halt_reg = 0x68330,
3876	.clkr = {
3877		.enable_reg = 0x68330,
3878		.enable_mask = BIT(0),
3879		.hw.init = &(struct clk_init_data){
3880			.name = "gcc_port5_mac_clk",
3881			.parent_hws = (const struct clk_hw *[]){
3882				&nss_ppe_clk_src.clkr.hw },
3883			.num_parents = 1,
3884			.flags = CLK_SET_RATE_PARENT,
3885			.ops = &clk_branch2_ops,
3886		},
3887	},
3888};
3889
3890static struct clk_branch gcc_port6_mac_clk = {
3891	.halt_reg = 0x68334,
3892	.clkr = {
3893		.enable_reg = 0x68334,
3894		.enable_mask = BIT(0),
3895		.hw.init = &(struct clk_init_data){
3896			.name = "gcc_port6_mac_clk",
3897			.parent_hws = (const struct clk_hw *[]){
3898				&nss_ppe_clk_src.clkr.hw },
3899			.num_parents = 1,
3900			.flags = CLK_SET_RATE_PARENT,
3901			.ops = &clk_branch2_ops,
3902		},
3903	},
3904};
3905
3906static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3907	.halt_reg = 0x56010,
3908	.clkr = {
3909		.enable_reg = 0x56010,
3910		.enable_mask = BIT(0),
3911		.hw.init = &(struct clk_init_data){
3912			.name = "gcc_uniphy0_port1_rx_clk",
3913			.parent_hws = (const struct clk_hw *[]){
3914				&nss_port1_rx_div_clk_src.clkr.hw },
3915			.num_parents = 1,
3916			.flags = CLK_SET_RATE_PARENT,
3917			.ops = &clk_branch2_ops,
3918		},
3919	},
3920};
3921
3922static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3923	.halt_reg = 0x56014,
3924	.clkr = {
3925		.enable_reg = 0x56014,
3926		.enable_mask = BIT(0),
3927		.hw.init = &(struct clk_init_data){
3928			.name = "gcc_uniphy0_port1_tx_clk",
3929			.parent_hws = (const struct clk_hw *[]){
3930				&nss_port1_tx_div_clk_src.clkr.hw },
3931			.num_parents = 1,
3932			.flags = CLK_SET_RATE_PARENT,
3933			.ops = &clk_branch2_ops,
3934		},
3935	},
3936};
3937
3938static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3939	.halt_reg = 0x56018,
3940	.clkr = {
3941		.enable_reg = 0x56018,
3942		.enable_mask = BIT(0),
3943		.hw.init = &(struct clk_init_data){
3944			.name = "gcc_uniphy0_port2_rx_clk",
3945			.parent_hws = (const struct clk_hw *[]){
3946				&nss_port2_rx_div_clk_src.clkr.hw },
3947			.num_parents = 1,
3948			.flags = CLK_SET_RATE_PARENT,
3949			.ops = &clk_branch2_ops,
3950		},
3951	},
3952};
3953
3954static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3955	.halt_reg = 0x5601c,
3956	.clkr = {
3957		.enable_reg = 0x5601c,
3958		.enable_mask = BIT(0),
3959		.hw.init = &(struct clk_init_data){
3960			.name = "gcc_uniphy0_port2_tx_clk",
3961			.parent_hws = (const struct clk_hw *[]){
3962				&nss_port2_tx_div_clk_src.clkr.hw },
3963			.num_parents = 1,
3964			.flags = CLK_SET_RATE_PARENT,
3965			.ops = &clk_branch2_ops,
3966		},
3967	},
3968};
3969
3970static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3971	.halt_reg = 0x56020,
3972	.clkr = {
3973		.enable_reg = 0x56020,
3974		.enable_mask = BIT(0),
3975		.hw.init = &(struct clk_init_data){
3976			.name = "gcc_uniphy0_port3_rx_clk",
3977			.parent_hws = (const struct clk_hw *[]){
3978				&nss_port3_rx_div_clk_src.clkr.hw },
3979			.num_parents = 1,
3980			.flags = CLK_SET_RATE_PARENT,
3981			.ops = &clk_branch2_ops,
3982		},
3983	},
3984};
3985
3986static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3987	.halt_reg = 0x56024,
3988	.clkr = {
3989		.enable_reg = 0x56024,
3990		.enable_mask = BIT(0),
3991		.hw.init = &(struct clk_init_data){
3992			.name = "gcc_uniphy0_port3_tx_clk",
3993			.parent_hws = (const struct clk_hw *[]){
3994				&nss_port3_tx_div_clk_src.clkr.hw },
3995			.num_parents = 1,
3996			.flags = CLK_SET_RATE_PARENT,
3997			.ops = &clk_branch2_ops,
3998		},
3999	},
4000};
4001
4002static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4003	.halt_reg = 0x56028,
4004	.clkr = {
4005		.enable_reg = 0x56028,
4006		.enable_mask = BIT(0),
4007		.hw.init = &(struct clk_init_data){
4008			.name = "gcc_uniphy0_port4_rx_clk",
4009			.parent_hws = (const struct clk_hw *[]){
4010				&nss_port4_rx_div_clk_src.clkr.hw },
4011			.num_parents = 1,
4012			.flags = CLK_SET_RATE_PARENT,
4013			.ops = &clk_branch2_ops,
4014		},
4015	},
4016};
4017
4018static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4019	.halt_reg = 0x5602c,
4020	.clkr = {
4021		.enable_reg = 0x5602c,
4022		.enable_mask = BIT(0),
4023		.hw.init = &(struct clk_init_data){
4024			.name = "gcc_uniphy0_port4_tx_clk",
4025			.parent_hws = (const struct clk_hw *[]){
4026				&nss_port4_tx_div_clk_src.clkr.hw },
4027			.num_parents = 1,
4028			.flags = CLK_SET_RATE_PARENT,
4029			.ops = &clk_branch2_ops,
4030		},
4031	},
4032};
4033
4034static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4035	.halt_reg = 0x56030,
4036	.clkr = {
4037		.enable_reg = 0x56030,
4038		.enable_mask = BIT(0),
4039		.hw.init = &(struct clk_init_data){
4040			.name = "gcc_uniphy0_port5_rx_clk",
4041			.parent_hws = (const struct clk_hw *[]){
4042				&nss_port5_rx_div_clk_src.clkr.hw },
4043			.num_parents = 1,
4044			.flags = CLK_SET_RATE_PARENT,
4045			.ops = &clk_branch2_ops,
4046		},
4047	},
4048};
4049
4050static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4051	.halt_reg = 0x56034,
4052	.clkr = {
4053		.enable_reg = 0x56034,
4054		.enable_mask = BIT(0),
4055		.hw.init = &(struct clk_init_data){
4056			.name = "gcc_uniphy0_port5_tx_clk",
4057			.parent_hws = (const struct clk_hw *[]){
4058				&nss_port5_tx_div_clk_src.clkr.hw },
4059			.num_parents = 1,
4060			.flags = CLK_SET_RATE_PARENT,
4061			.ops = &clk_branch2_ops,
4062		},
4063	},
4064};
4065
4066static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4067	.halt_reg = 0x56110,
4068	.clkr = {
4069		.enable_reg = 0x56110,
4070		.enable_mask = BIT(0),
4071		.hw.init = &(struct clk_init_data){
4072			.name = "gcc_uniphy1_port5_rx_clk",
4073			.parent_hws = (const struct clk_hw *[]){
4074				&nss_port5_rx_div_clk_src.clkr.hw },
4075			.num_parents = 1,
4076			.flags = CLK_SET_RATE_PARENT,
4077			.ops = &clk_branch2_ops,
4078		},
4079	},
4080};
4081
4082static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4083	.halt_reg = 0x56114,
4084	.clkr = {
4085		.enable_reg = 0x56114,
4086		.enable_mask = BIT(0),
4087		.hw.init = &(struct clk_init_data){
4088			.name = "gcc_uniphy1_port5_tx_clk",
4089			.parent_hws = (const struct clk_hw *[]){
4090				&nss_port5_tx_div_clk_src.clkr.hw },
4091			.num_parents = 1,
4092			.flags = CLK_SET_RATE_PARENT,
4093			.ops = &clk_branch2_ops,
4094		},
4095	},
4096};
4097
4098static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4099	.halt_reg = 0x56210,
4100	.clkr = {
4101		.enable_reg = 0x56210,
4102		.enable_mask = BIT(0),
4103		.hw.init = &(struct clk_init_data){
4104			.name = "gcc_uniphy2_port6_rx_clk",
4105			.parent_hws = (const struct clk_hw *[]){
4106				&nss_port6_rx_div_clk_src.clkr.hw },
4107			.num_parents = 1,
4108			.flags = CLK_SET_RATE_PARENT,
4109			.ops = &clk_branch2_ops,
4110		},
4111	},
4112};
4113
4114static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4115	.halt_reg = 0x56214,
4116	.clkr = {
4117		.enable_reg = 0x56214,
4118		.enable_mask = BIT(0),
4119		.hw.init = &(struct clk_init_data){
4120			.name = "gcc_uniphy2_port6_tx_clk",
4121			.parent_hws = (const struct clk_hw *[]){
4122				&nss_port6_tx_div_clk_src.clkr.hw },
4123			.num_parents = 1,
4124			.flags = CLK_SET_RATE_PARENT,
4125			.ops = &clk_branch2_ops,
4126		},
4127	},
4128};
4129
4130static struct clk_branch gcc_crypto_ahb_clk = {
4131	.halt_reg = 0x16024,
4132	.halt_check = BRANCH_HALT_VOTED,
4133	.clkr = {
4134		.enable_reg = 0x0b004,
4135		.enable_mask = BIT(0),
4136		.hw.init = &(struct clk_init_data){
4137			.name = "gcc_crypto_ahb_clk",
4138			.parent_hws = (const struct clk_hw *[]){
4139				&pcnoc_clk_src.hw },
4140			.num_parents = 1,
4141			.flags = CLK_SET_RATE_PARENT,
4142			.ops = &clk_branch2_ops,
4143		},
4144	},
4145};
4146
4147static struct clk_branch gcc_crypto_axi_clk = {
4148	.halt_reg = 0x16020,
4149	.halt_check = BRANCH_HALT_VOTED,
4150	.clkr = {
4151		.enable_reg = 0x0b004,
4152		.enable_mask = BIT(1),
4153		.hw.init = &(struct clk_init_data){
4154			.name = "gcc_crypto_axi_clk",
4155			.parent_hws = (const struct clk_hw *[]){
4156				&pcnoc_clk_src.hw },
4157			.num_parents = 1,
4158			.flags = CLK_SET_RATE_PARENT,
4159			.ops = &clk_branch2_ops,
4160		},
4161	},
4162};
4163
4164static struct clk_branch gcc_crypto_clk = {
4165	.halt_reg = 0x1601c,
4166	.halt_check = BRANCH_HALT_VOTED,
4167	.clkr = {
4168		.enable_reg = 0x0b004,
4169		.enable_mask = BIT(2),
4170		.hw.init = &(struct clk_init_data){
4171			.name = "gcc_crypto_clk",
4172			.parent_hws = (const struct clk_hw *[]){
4173				&crypto_clk_src.clkr.hw },
4174			.num_parents = 1,
4175			.flags = CLK_SET_RATE_PARENT,
4176			.ops = &clk_branch2_ops,
4177		},
4178	},
4179};
4180
4181static struct clk_branch gcc_gp1_clk = {
4182	.halt_reg = 0x08000,
4183	.clkr = {
4184		.enable_reg = 0x08000,
4185		.enable_mask = BIT(0),
4186		.hw.init = &(struct clk_init_data){
4187			.name = "gcc_gp1_clk",
4188			.parent_hws = (const struct clk_hw *[]){
4189				&gp1_clk_src.clkr.hw },
4190			.num_parents = 1,
4191			.flags = CLK_SET_RATE_PARENT,
4192			.ops = &clk_branch2_ops,
4193		},
4194	},
4195};
4196
4197static struct clk_branch gcc_gp2_clk = {
4198	.halt_reg = 0x09000,
4199	.clkr = {
4200		.enable_reg = 0x09000,
4201		.enable_mask = BIT(0),
4202		.hw.init = &(struct clk_init_data){
4203			.name = "gcc_gp2_clk",
4204			.parent_hws = (const struct clk_hw *[]){
4205				&gp2_clk_src.clkr.hw },
4206			.num_parents = 1,
4207			.flags = CLK_SET_RATE_PARENT,
4208			.ops = &clk_branch2_ops,
4209		},
4210	},
4211};
4212
4213static struct clk_branch gcc_gp3_clk = {
4214	.halt_reg = 0x0a000,
4215	.clkr = {
4216		.enable_reg = 0x0a000,
4217		.enable_mask = BIT(0),
4218		.hw.init = &(struct clk_init_data){
4219			.name = "gcc_gp3_clk",
4220			.parent_hws = (const struct clk_hw *[]){
4221				&gp3_clk_src.clkr.hw },
4222			.num_parents = 1,
4223			.flags = CLK_SET_RATE_PARENT,
4224			.ops = &clk_branch2_ops,
4225		},
4226	},
4227};
4228
4229static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
4230	F(19200000, P_XO, 1, 0, 0),
4231	F(100000000, P_GPLL0, 8, 0, 0),
4232	{ }
4233};
4234
4235static struct clk_rcg2 pcie0_rchng_clk_src = {
4236	.cmd_rcgr = 0x75070,
4237	.freq_tbl = ftbl_pcie_rchng_clk_src,
4238	.hid_width = 5,
4239	.parent_map = gcc_xo_gpll0_map,
4240	.clkr.hw.init = &(struct clk_init_data){
4241		.name = "pcie0_rchng_clk_src",
4242		.parent_data = gcc_xo_gpll0,
4243		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
4244		.ops = &clk_rcg2_ops,
4245	},
4246};
4247
4248static struct clk_branch gcc_pcie0_rchng_clk = {
4249	.halt_reg = 0x75070,
4250	.halt_bit = 31,
4251	.clkr = {
4252		.enable_reg = 0x75070,
4253		.enable_mask = BIT(1),
4254		.hw.init = &(struct clk_init_data){
4255			.name = "gcc_pcie0_rchng_clk",
4256			.parent_hws = (const struct clk_hw *[]){
4257				&pcie0_rchng_clk_src.clkr.hw,
4258			},
4259			.num_parents = 1,
4260			.flags = CLK_SET_RATE_PARENT,
4261			.ops = &clk_branch2_ops,
4262		},
4263	},
4264};
4265
4266static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
4267	.halt_reg = 0x75048,
4268	.halt_bit = 31,
4269	.clkr = {
4270		.enable_reg = 0x75048,
4271		.enable_mask = BIT(0),
4272		.hw.init = &(struct clk_init_data){
4273			.name = "gcc_pcie0_axi_s_bridge_clk",
4274			.parent_hws = (const struct clk_hw *[]){
4275				&pcie0_axi_clk_src.clkr.hw,
4276			},
4277			.num_parents = 1,
4278			.flags = CLK_SET_RATE_PARENT,
4279			.ops = &clk_branch2_ops,
4280		},
4281	},
4282};
4283
4284static struct gdsc usb0_gdsc = {
4285	.gdscr = 0x3e078,
4286	.pd = {
4287		.name = "usb0_gdsc",
4288	},
4289	.pwrsts = PWRSTS_OFF_ON,
4290};
4291
4292static struct gdsc usb1_gdsc = {
4293	.gdscr = 0x3f078,
4294	.pd = {
4295		.name = "usb1_gdsc",
4296	},
4297	.pwrsts = PWRSTS_OFF_ON,
4298};
4299
4300static const struct alpha_pll_config ubi32_pll_config = {
4301	.l = 0x4e,
4302	.config_ctl_val = 0x200d4aa8,
4303	.config_ctl_hi_val = 0x3c2,
4304	.main_output_mask = BIT(0),
4305	.aux_output_mask = BIT(1),
4306	.pre_div_val = 0x0,
4307	.pre_div_mask = BIT(12),
4308	.post_div_val = 0x0,
4309	.post_div_mask = GENMASK(9, 8),
4310};
4311
4312static const struct alpha_pll_config nss_crypto_pll_config = {
4313	.l = 0x3e,
4314	.alpha = 0x0,
4315	.alpha_hi = 0x80,
4316	.config_ctl_val = 0x4001055b,
4317	.main_output_mask = BIT(0),
4318	.pre_div_val = 0x0,
4319	.pre_div_mask = GENMASK(14, 12),
4320	.post_div_val = 0x1 << 8,
4321	.post_div_mask = GENMASK(11, 8),
4322	.vco_mask = GENMASK(21, 20),
4323	.vco_val = 0x0,
4324	.alpha_en_mask = BIT(24),
4325};
4326
4327static struct clk_hw *gcc_ipq8074_hws[] = {
4328	&gpll0_out_main_div2.hw,
4329	&gpll6_out_main_div2.hw,
4330	&pcnoc_clk_src.hw,
4331	&system_noc_clk_src.hw,
4332	&gcc_xo_div4_clk_src.hw,
4333	&nss_noc_clk_src.hw,
4334	&nss_ppe_cdiv_clk_src.hw,
4335};
4336
4337static struct clk_regmap *gcc_ipq8074_clks[] = {
4338	[GPLL0_MAIN] = &gpll0_main.clkr,
4339	[GPLL0] = &gpll0.clkr,
4340	[GPLL2_MAIN] = &gpll2_main.clkr,
4341	[GPLL2] = &gpll2.clkr,
4342	[GPLL4_MAIN] = &gpll4_main.clkr,
4343	[GPLL4] = &gpll4.clkr,
4344	[GPLL6_MAIN] = &gpll6_main.clkr,
4345	[GPLL6] = &gpll6.clkr,
4346	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4347	[UBI32_PLL] = &ubi32_pll.clkr,
4348	[NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4349	[NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4350	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4351	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4352	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4353	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4354	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4355	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4356	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4357	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4358	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4359	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4360	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4361	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4362	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4363	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4364	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4365	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4366	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4367	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4368	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4369	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4370	[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4371	[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4372	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4373	[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4374	[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4375	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4376	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4377	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4378	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4379	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4380	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4381	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4382	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4383	[USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4384	[USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4385	[USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4386	[USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4387	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4388	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4389	[NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4390	[NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4391	[NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4392	[NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4393	[NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4394	[NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4395	[NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4396	[UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4397	[NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4398	[NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4399	[NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4400	[NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4401	[NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4402	[NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4403	[NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4404	[NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4405	[NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4406	[NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4407	[NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4408	[NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4409	[NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4410	[NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4411	[NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4412	[NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4413	[NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4414	[NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4415	[NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4416	[NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4417	[NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4418	[NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4419	[NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4420	[NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4421	[NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4422	[NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4423	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4424	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4425	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4426	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4427	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4428	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4429	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4430	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4431	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4432	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4433	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4434	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4435	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4436	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4437	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4438	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4439	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4440	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4441	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4442	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4443	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4444	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4445	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4446	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4447	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4448	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4449	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4450	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4451	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4452	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4453	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4454	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4455	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4456	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4457	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4458	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4459	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4460	[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4461	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4462	[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4463	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4464	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4465	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4466	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4467	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4468	[GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4469	[GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4470	[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4471	[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4472	[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4473	[GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4474	[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4475	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4476	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4477	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4478	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4479	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4480	[GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4481	[GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4482	[GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4483	[GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4484	[GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4485	[GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4486	[GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4487	[GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4488	[GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4489	[GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4490	[GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4491	[GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4492	[GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4493	[GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4494	[GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4495	[GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4496	[GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4497	[GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4498	[GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4499	[GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4500	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4501	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4502	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4503	[GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4504	[GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4505	[GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4506	[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4507	[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4508	[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4509	[GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4510	[GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4511	[GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4512	[GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4513	[GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4514	[GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4515	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4516	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4517	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4518	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4519	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4520	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4521	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4522	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4523	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4524	[GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4525	[GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4526	[GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4527	[GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4528	[GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4529	[GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4530	[GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4531	[GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4532	[GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4533	[GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4534	[GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4535	[GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4536	[GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4537	[GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4538	[GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4539	[GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4540	[GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4541	[GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4542	[GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4543	[GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4544	[GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4545	[GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4546	[GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4547	[GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4548	[GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4549	[GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4550	[GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4551	[GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4552	[GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4553	[GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4554	[GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4555	[GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4556	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4557	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4558	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4559	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4560	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4561	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4562	[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4563	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4564	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4565	[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4566};
4567
4568static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4569	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4570	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4571	[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4572	[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4573	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4574	[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4575	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4576	[GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4577	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4578	[GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4579	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4580	[GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4581	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4582	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4583	[GCC_SMMU_BCR] = { 0x12000, 0 },
4584	[GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4585	[GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4586	[GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4587	[GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4588	[GCC_PRNG_BCR] = { 0x13000, 0 },
4589	[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4590	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4591	[GCC_WCSS_BCR] = { 0x18000, 0 },
4592	[GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4593	[GCC_NSS_BCR] = { 0x19000, 0 },
4594	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4595	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4596	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
4597	[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4598	[GCC_PCNOC_BCR] = { 0x27018, 0 },
4599	[GCC_TCSR_BCR] = { 0x28000, 0 },
4600	[GCC_QDSS_BCR] = { 0x29000, 0 },
4601	[GCC_DCD_BCR] = { 0x2a000, 0 },
4602	[GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4603	[GCC_MPM_BCR] = { 0x2c000, 0 },
4604	[GCC_SPMI_BCR] = { 0x2e000, 0 },
4605	[GCC_SPDM_BCR] = { 0x2f000, 0 },
4606	[GCC_RBCPR_BCR] = { 0x33000, 0 },
4607	[GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4608	[GCC_TLMM_BCR] = { 0x34000, 0 },
4609	[GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4610	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4611	[GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4612	[GCC_USB0_BCR] = { 0x3e070, 0 },
4613	[GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4614	[GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4615	[GCC_USB1_BCR] = { 0x3f070, 0 },
4616	[GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4617	[GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4618	[GCC_SDCC1_BCR] = { 0x42000, 0 },
4619	[GCC_SDCC2_BCR] = { 0x43000, 0 },
4620	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4621	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4622	[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4623	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4624	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4625	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4626	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4627	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4628	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4629	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4630	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4631	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4632	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4633	[GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4634	[GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4635	[GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4636	[GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4637	[GCC_QPIC_BCR] = { 0x57018, 0 },
4638	[GCC_MDIO_BCR] = { 0x58000, 0 },
4639	[GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4640	[GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4641	[GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4642	[GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4643	[GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4644	[GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4645	[GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4646	[GCC_PCIE0_BCR] = { 0x75004, 0 },
4647	[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4648	[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4649	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4650	[GCC_PCIE1_BCR] = { 0x76004, 0 },
4651	[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4652	[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4653	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4654	[GCC_DCC_BCR] = { 0x77000, 0 },
4655	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4656	[GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4657	[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4658	[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4659	[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4660	[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4661	[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4662	[GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4663	[GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4664	[GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4665	[GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4666	[GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4667	[GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4668	[GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4669	[GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4670	[GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4671	[GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4672	[GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4673	[GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4674	[GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4675	[GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4676	[GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4677	[GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4678	[GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4679	[GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4680	[GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4681	[GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4682	[GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4683	[GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4684	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4685	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4686	[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4687	[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4688	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4689	[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4690	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4691	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4692	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4693	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4694	[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4695	[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4696	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4697	[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4698	[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4699	[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4700	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4701	[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
4702	[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4703	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4704	[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4705	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4706	[GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4707	[GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
4708	[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
4709	[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4710	[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
4711	[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
4712	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
4713	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
4714	[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
4715};
4716
4717static struct gdsc *gcc_ipq8074_gdscs[] = {
4718	[USB0_GDSC] = &usb0_gdsc,
4719	[USB1_GDSC] = &usb1_gdsc,
4720};
4721
4722static const struct of_device_id gcc_ipq8074_match_table[] = {
4723	{ .compatible = "qcom,gcc-ipq8074" },
4724	{ }
4725};
4726MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4727
4728static const struct regmap_config gcc_ipq8074_regmap_config = {
4729	.reg_bits       = 32,
4730	.reg_stride     = 4,
4731	.val_bits       = 32,
4732	.max_register   = 0x7fffc,
4733	.fast_io	= true,
4734};
4735
4736static const struct qcom_cc_desc gcc_ipq8074_desc = {
4737	.config = &gcc_ipq8074_regmap_config,
4738	.clks = gcc_ipq8074_clks,
4739	.num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4740	.resets = gcc_ipq8074_resets,
4741	.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4742	.clk_hws = gcc_ipq8074_hws,
4743	.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4744	.gdscs = gcc_ipq8074_gdscs,
4745	.num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
4746};
4747
4748static int gcc_ipq8074_probe(struct platform_device *pdev)
4749{
4750	struct regmap *regmap;
4751
4752	regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
4753	if (IS_ERR(regmap))
4754		return PTR_ERR(regmap);
4755
4756	/* SW Workaround for UBI32 Huayra PLL */
4757	regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4758
4759	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4760	clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4761				&nss_crypto_pll_config);
4762
4763	return qcom_cc_really_probe(&pdev->dev, &gcc_ipq8074_desc, regmap);
4764}
4765
4766static struct platform_driver gcc_ipq8074_driver = {
4767	.probe = gcc_ipq8074_probe,
4768	.driver = {
4769		.name   = "qcom,gcc-ipq8074",
4770		.of_match_table = gcc_ipq8074_match_table,
4771	},
4772};
4773
4774static int __init gcc_ipq8074_init(void)
4775{
4776	return platform_driver_register(&gcc_ipq8074_driver);
4777}
4778core_initcall(gcc_ipq8074_init);
4779
4780static void __exit gcc_ipq8074_exit(void)
4781{
4782	platform_driver_unregister(&gcc_ipq8074_driver);
4783}
4784module_exit(gcc_ipq8074_exit);
4785
4786MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4787MODULE_LICENSE("GPL v2");
4788MODULE_ALIAS("platform:gcc-ipq8074");