1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/pm_runtime.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,sm8650-camcc.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap.h"
  19#include "common.h"
  20#include "gdsc.h"
  21#include "reset.h"
  22
  23enum {
  24	DT_IFACE,
  25	DT_BI_TCXO,
  26	DT_BI_TCXO_AO,
  27	DT_SLEEP_CLK,
  28};
  29
  30enum {
  31	P_BI_TCXO,
  32	P_BI_TCXO_AO,
  33	P_CAM_CC_PLL0_OUT_EVEN,
  34	P_CAM_CC_PLL0_OUT_MAIN,
  35	P_CAM_CC_PLL0_OUT_ODD,
  36	P_CAM_CC_PLL1_OUT_EVEN,
  37	P_CAM_CC_PLL2_OUT_EVEN,
  38	P_CAM_CC_PLL2_OUT_MAIN,
  39	P_CAM_CC_PLL3_OUT_EVEN,
  40	P_CAM_CC_PLL4_OUT_EVEN,
  41	P_CAM_CC_PLL5_OUT_EVEN,
  42	P_CAM_CC_PLL6_OUT_EVEN,
  43	P_CAM_CC_PLL7_OUT_EVEN,
  44	P_CAM_CC_PLL8_OUT_EVEN,
  45	P_CAM_CC_PLL9_OUT_EVEN,
  46	P_CAM_CC_PLL9_OUT_ODD,
  47	P_CAM_CC_PLL10_OUT_EVEN,
  48	P_SLEEP_CLK,
  49};
  50
  51static const struct pll_vco lucid_ole_vco[] = {
  52	{ 249600000, 2300000000, 0 },
  53};
  54
  55static const struct pll_vco rivian_ole_vco[] = {
  56	{ 777000000, 1285000000, 0 },
  57};
  58
  59static const struct alpha_pll_config cam_cc_pll0_config = {
  60	.l = 0x3e,
  61	.alpha = 0x8000,
  62	.config_ctl_val = 0x20485699,
  63	.config_ctl_hi_val = 0x00182261,
  64	.config_ctl_hi1_val = 0x82aa299c,
  65	.test_ctl_val = 0x00000000,
  66	.test_ctl_hi_val = 0x00000003,
  67	.test_ctl_hi1_val = 0x00009000,
  68	.test_ctl_hi2_val = 0x00000034,
  69	.user_ctl_val = 0x00008400,
  70	.user_ctl_hi_val = 0x00000005,
  71};
  72
  73static struct clk_alpha_pll cam_cc_pll0 = {
  74	.offset = 0x0,
  75	.vco_table = lucid_ole_vco,
  76	.num_vco = ARRAY_SIZE(lucid_ole_vco),
  77	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  78	.clkr = {
  79		.hw.init = &(const struct clk_init_data) {
  80			.name = "cam_cc_pll0",
  81			.parent_data = &(const struct clk_parent_data) {
  82				.index = DT_BI_TCXO,
  83			},
  84			.num_parents = 1,
  85			.ops = &clk_alpha_pll_lucid_evo_ops,
  86		},
  87	},
  88};
  89
  90static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
  91	{ 0x1, 2 },
  92	{ }
  93};
  94
  95static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
  96	.offset = 0x0,
  97	.post_div_shift = 10,
  98	.post_div_table = post_div_table_cam_cc_pll0_out_even,
  99	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
 100	.width = 4,
 101	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 102	.clkr.hw.init = &(const struct clk_init_data) {
 103		.name = "cam_cc_pll0_out_even",
 104		.parent_hws = (const struct clk_hw*[]) {
 105			&cam_cc_pll0.clkr.hw,
 106		},
 107		.num_parents = 1,
 108		.flags = CLK_SET_RATE_PARENT,
 109		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 110	},
 111};
 112
 113static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 114	{ 0x2, 3 },
 115	{ }
 116};
 117
 118static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 119	.offset = 0x0,
 120	.post_div_shift = 14,
 121	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
 122	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
 123	.width = 4,
 124	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 125	.clkr.hw.init = &(const struct clk_init_data) {
 126		.name = "cam_cc_pll0_out_odd",
 127		.parent_hws = (const struct clk_hw*[]) {
 128			&cam_cc_pll0.clkr.hw,
 129		},
 130		.num_parents = 1,
 131		.flags = CLK_SET_RATE_PARENT,
 132		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 133	},
 134};
 135
 136static const struct alpha_pll_config cam_cc_pll1_config = {
 137	.l = 0x31,
 138	.alpha = 0x7aaa,
 139	.config_ctl_val = 0x20485699,
 140	.config_ctl_hi_val = 0x00182261,
 141	.config_ctl_hi1_val = 0x82aa299c,
 142	.test_ctl_val = 0x00000000,
 143	.test_ctl_hi_val = 0x00000003,
 144	.test_ctl_hi1_val = 0x00009000,
 145	.test_ctl_hi2_val = 0x00000034,
 146	.user_ctl_val = 0x00000400,
 147	.user_ctl_hi_val = 0x00000005,
 148};
 149
 150static struct clk_alpha_pll cam_cc_pll1 = {
 151	.offset = 0x1000,
 152	.vco_table = lucid_ole_vco,
 153	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 155	.clkr = {
 156		.hw.init = &(const struct clk_init_data) {
 157			.name = "cam_cc_pll1",
 158			.parent_data = &(const struct clk_parent_data) {
 159				.index = DT_BI_TCXO,
 160			},
 161			.num_parents = 1,
 162			.ops = &clk_alpha_pll_lucid_evo_ops,
 163		},
 164	},
 165};
 166
 167static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 168	{ 0x1, 2 },
 169	{ }
 170};
 171
 172static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 173	.offset = 0x1000,
 174	.post_div_shift = 10,
 175	.post_div_table = post_div_table_cam_cc_pll1_out_even,
 176	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
 177	.width = 4,
 178	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 179	.clkr.hw.init = &(const struct clk_init_data) {
 180		.name = "cam_cc_pll1_out_even",
 181		.parent_hws = (const struct clk_hw*[]) {
 182			&cam_cc_pll1.clkr.hw,
 183		},
 184		.num_parents = 1,
 185		.flags = CLK_SET_RATE_PARENT,
 186		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 187	},
 188};
 189
 190static const struct alpha_pll_config cam_cc_pll2_config = {
 191	.l = 0x32,
 192	.alpha = 0x0,
 193	.config_ctl_val = 0x10000030,
 194	.config_ctl_hi_val = 0x80890263,
 195	.config_ctl_hi1_val = 0x00000217,
 196	.user_ctl_val = 0x00000001,
 197	.user_ctl_hi_val = 0x00000000,
 198};
 199
 200static struct clk_alpha_pll cam_cc_pll2 = {
 201	.offset = 0x2000,
 202	.vco_table = rivian_ole_vco,
 203	.num_vco = ARRAY_SIZE(rivian_ole_vco),
 204	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
 205	.clkr = {
 206		.hw.init = &(const struct clk_init_data) {
 207			.name = "cam_cc_pll2",
 208			.parent_data = &(const struct clk_parent_data) {
 209				.index = DT_BI_TCXO,
 210			},
 211			.num_parents = 1,
 212			.ops = &clk_alpha_pll_rivian_evo_ops,
 213		},
 214	},
 215};
 216
 217static const struct alpha_pll_config cam_cc_pll3_config = {
 218	.l = 0x30,
 219	.alpha = 0x8aaa,
 220	.config_ctl_val = 0x20485699,
 221	.config_ctl_hi_val = 0x00182261,
 222	.config_ctl_hi1_val = 0x82aa299c,
 223	.test_ctl_val = 0x00000000,
 224	.test_ctl_hi_val = 0x00000003,
 225	.test_ctl_hi1_val = 0x00009000,
 226	.test_ctl_hi2_val = 0x00000034,
 227	.user_ctl_val = 0x00000400,
 228	.user_ctl_hi_val = 0x00000005,
 229};
 230
 231static struct clk_alpha_pll cam_cc_pll3 = {
 232	.offset = 0x3000,
 233	.vco_table = lucid_ole_vco,
 234	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 235	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 236	.clkr = {
 237		.hw.init = &(const struct clk_init_data) {
 238			.name = "cam_cc_pll3",
 239			.parent_data = &(const struct clk_parent_data) {
 240				.index = DT_BI_TCXO,
 241			},
 242			.num_parents = 1,
 243			.ops = &clk_alpha_pll_lucid_evo_ops,
 244		},
 245	},
 246};
 247
 248static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 249	{ 0x1, 2 },
 250	{ }
 251};
 252
 253static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 254	.offset = 0x3000,
 255	.post_div_shift = 10,
 256	.post_div_table = post_div_table_cam_cc_pll3_out_even,
 257	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
 258	.width = 4,
 259	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 260	.clkr.hw.init = &(const struct clk_init_data) {
 261		.name = "cam_cc_pll3_out_even",
 262		.parent_hws = (const struct clk_hw*[]) {
 263			&cam_cc_pll3.clkr.hw,
 264		},
 265		.num_parents = 1,
 266		.flags = CLK_SET_RATE_PARENT,
 267		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 268	},
 269};
 270
 271static const struct alpha_pll_config cam_cc_pll4_config = {
 272	.l = 0x30,
 273	.alpha = 0x8aaa,
 274	.config_ctl_val = 0x20485699,
 275	.config_ctl_hi_val = 0x00182261,
 276	.config_ctl_hi1_val = 0x82aa299c,
 277	.test_ctl_val = 0x00000000,
 278	.test_ctl_hi_val = 0x00000003,
 279	.test_ctl_hi1_val = 0x00009000,
 280	.test_ctl_hi2_val = 0x00000034,
 281	.user_ctl_val = 0x00000400,
 282	.user_ctl_hi_val = 0x00000005,
 283};
 284
 285static struct clk_alpha_pll cam_cc_pll4 = {
 286	.offset = 0x4000,
 287	.vco_table = lucid_ole_vco,
 288	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 289	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 290	.clkr = {
 291		.hw.init = &(const struct clk_init_data) {
 292			.name = "cam_cc_pll4",
 293			.parent_data = &(const struct clk_parent_data) {
 294				.index = DT_BI_TCXO,
 295			},
 296			.num_parents = 1,
 297			.ops = &clk_alpha_pll_lucid_evo_ops,
 298		},
 299	},
 300};
 301
 302static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 303	{ 0x1, 2 },
 304	{ }
 305};
 306
 307static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 308	.offset = 0x4000,
 309	.post_div_shift = 10,
 310	.post_div_table = post_div_table_cam_cc_pll4_out_even,
 311	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
 312	.width = 4,
 313	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 314	.clkr.hw.init = &(const struct clk_init_data) {
 315		.name = "cam_cc_pll4_out_even",
 316		.parent_hws = (const struct clk_hw*[]) {
 317			&cam_cc_pll4.clkr.hw,
 318		},
 319		.num_parents = 1,
 320		.flags = CLK_SET_RATE_PARENT,
 321		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 322	},
 323};
 324
 325static const struct alpha_pll_config cam_cc_pll5_config = {
 326	.l = 0x30,
 327	.alpha = 0x8aaa,
 328	.config_ctl_val = 0x20485699,
 329	.config_ctl_hi_val = 0x00182261,
 330	.config_ctl_hi1_val = 0x82aa299c,
 331	.test_ctl_val = 0x00000000,
 332	.test_ctl_hi_val = 0x00000003,
 333	.test_ctl_hi1_val = 0x00009000,
 334	.test_ctl_hi2_val = 0x00000034,
 335	.user_ctl_val = 0x00000400,
 336	.user_ctl_hi_val = 0x00000005,
 337};
 338
 339static struct clk_alpha_pll cam_cc_pll5 = {
 340	.offset = 0x5000,
 341	.vco_table = lucid_ole_vco,
 342	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 343	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 344	.clkr = {
 345		.hw.init = &(const struct clk_init_data) {
 346			.name = "cam_cc_pll5",
 347			.parent_data = &(const struct clk_parent_data) {
 348				.index = DT_BI_TCXO,
 349			},
 350			.num_parents = 1,
 351			.ops = &clk_alpha_pll_lucid_evo_ops,
 352		},
 353	},
 354};
 355
 356static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
 357	{ 0x1, 2 },
 358	{ }
 359};
 360
 361static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 362	.offset = 0x5000,
 363	.post_div_shift = 10,
 364	.post_div_table = post_div_table_cam_cc_pll5_out_even,
 365	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
 366	.width = 4,
 367	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 368	.clkr.hw.init = &(const struct clk_init_data) {
 369		.name = "cam_cc_pll5_out_even",
 370		.parent_hws = (const struct clk_hw*[]) {
 371			&cam_cc_pll5.clkr.hw,
 372		},
 373		.num_parents = 1,
 374		.flags = CLK_SET_RATE_PARENT,
 375		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 376	},
 377};
 378
 379static const struct alpha_pll_config cam_cc_pll6_config = {
 380	.l = 0x30,
 381	.alpha = 0x8aaa,
 382	.config_ctl_val = 0x20485699,
 383	.config_ctl_hi_val = 0x00182261,
 384	.config_ctl_hi1_val = 0x82aa299c,
 385	.test_ctl_val = 0x00000000,
 386	.test_ctl_hi_val = 0x00000003,
 387	.test_ctl_hi1_val = 0x00009000,
 388	.test_ctl_hi2_val = 0x00000034,
 389	.user_ctl_val = 0x00000400,
 390	.user_ctl_hi_val = 0x00000005,
 391};
 392
 393static struct clk_alpha_pll cam_cc_pll6 = {
 394	.offset = 0x6000,
 395	.vco_table = lucid_ole_vco,
 396	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 397	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 398	.clkr = {
 399		.hw.init = &(const struct clk_init_data) {
 400			.name = "cam_cc_pll6",
 401			.parent_data = &(const struct clk_parent_data) {
 402				.index = DT_BI_TCXO,
 403			},
 404			.num_parents = 1,
 405			.ops = &clk_alpha_pll_lucid_evo_ops,
 406		},
 407	},
 408};
 409
 410static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
 411	{ 0x1, 2 },
 412	{ }
 413};
 414
 415static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 416	.offset = 0x6000,
 417	.post_div_shift = 10,
 418	.post_div_table = post_div_table_cam_cc_pll6_out_even,
 419	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
 420	.width = 4,
 421	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 422	.clkr.hw.init = &(const struct clk_init_data) {
 423		.name = "cam_cc_pll6_out_even",
 424		.parent_hws = (const struct clk_hw*[]) {
 425			&cam_cc_pll6.clkr.hw,
 426		},
 427		.num_parents = 1,
 428		.flags = CLK_SET_RATE_PARENT,
 429		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 430	},
 431};
 432
 433static const struct alpha_pll_config cam_cc_pll7_config = {
 434	.l = 0x30,
 435	.alpha = 0x8aaa,
 436	.config_ctl_val = 0x20485699,
 437	.config_ctl_hi_val = 0x00182261,
 438	.config_ctl_hi1_val = 0x82aa299c,
 439	.test_ctl_val = 0x00000000,
 440	.test_ctl_hi_val = 0x00000003,
 441	.test_ctl_hi1_val = 0x00009000,
 442	.test_ctl_hi2_val = 0x00000034,
 443	.user_ctl_val = 0x00000400,
 444	.user_ctl_hi_val = 0x00000005,
 445};
 446
 447static struct clk_alpha_pll cam_cc_pll7 = {
 448	.offset = 0x7000,
 449	.vco_table = lucid_ole_vco,
 450	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 451	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 452	.clkr = {
 453		.hw.init = &(const struct clk_init_data) {
 454			.name = "cam_cc_pll7",
 455			.parent_data = &(const struct clk_parent_data) {
 456				.index = DT_BI_TCXO,
 457			},
 458			.num_parents = 1,
 459			.ops = &clk_alpha_pll_lucid_evo_ops,
 460		},
 461	},
 462};
 463
 464static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
 465	{ 0x1, 2 },
 466	{ }
 467};
 468
 469static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 470	.offset = 0x7000,
 471	.post_div_shift = 10,
 472	.post_div_table = post_div_table_cam_cc_pll7_out_even,
 473	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
 474	.width = 4,
 475	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 476	.clkr.hw.init = &(const struct clk_init_data) {
 477		.name = "cam_cc_pll7_out_even",
 478		.parent_hws = (const struct clk_hw*[]) {
 479			&cam_cc_pll7.clkr.hw,
 480		},
 481		.num_parents = 1,
 482		.flags = CLK_SET_RATE_PARENT,
 483		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 484	},
 485};
 486
 487static const struct alpha_pll_config cam_cc_pll8_config = {
 488	.l = 0x14,
 489	.alpha = 0xd555,
 490	.config_ctl_val = 0x20485699,
 491	.config_ctl_hi_val = 0x00182261,
 492	.config_ctl_hi1_val = 0x82aa299c,
 493	.test_ctl_val = 0x00000000,
 494	.test_ctl_hi_val = 0x00000003,
 495	.test_ctl_hi1_val = 0x00009000,
 496	.test_ctl_hi2_val = 0x00000034,
 497	.user_ctl_val = 0x00000400,
 498	.user_ctl_hi_val = 0x00000005,
 499};
 500
 501static struct clk_alpha_pll cam_cc_pll8 = {
 502	.offset = 0x8000,
 503	.vco_table = lucid_ole_vco,
 504	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 505	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 506	.clkr = {
 507		.hw.init = &(const struct clk_init_data) {
 508			.name = "cam_cc_pll8",
 509			.parent_data = &(const struct clk_parent_data) {
 510				.index = DT_BI_TCXO,
 511			},
 512			.num_parents = 1,
 513			.ops = &clk_alpha_pll_lucid_evo_ops,
 514		},
 515	},
 516};
 517
 518static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
 519	{ 0x1, 2 },
 520	{ }
 521};
 522
 523static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
 524	.offset = 0x8000,
 525	.post_div_shift = 10,
 526	.post_div_table = post_div_table_cam_cc_pll8_out_even,
 527	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
 528	.width = 4,
 529	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 530	.clkr.hw.init = &(const struct clk_init_data) {
 531		.name = "cam_cc_pll8_out_even",
 532		.parent_hws = (const struct clk_hw*[]) {
 533			&cam_cc_pll8.clkr.hw,
 534		},
 535		.num_parents = 1,
 536		.flags = CLK_SET_RATE_PARENT,
 537		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 538	},
 539};
 540
 541static const struct alpha_pll_config cam_cc_pll9_config = {
 542	.l = 0x32,
 543	.alpha = 0x0,
 544	.config_ctl_val = 0x20485699,
 545	.config_ctl_hi_val = 0x00182261,
 546	.config_ctl_hi1_val = 0x82aa299c,
 547	.test_ctl_val = 0x00000000,
 548	.test_ctl_hi_val = 0x00000003,
 549	.test_ctl_hi1_val = 0x00009000,
 550	.test_ctl_hi2_val = 0x00000034,
 551	.user_ctl_val = 0x00008400,
 552	.user_ctl_hi_val = 0x00000005,
 553};
 554
 555static struct clk_alpha_pll cam_cc_pll9 = {
 556	.offset = 0x9000,
 557	.vco_table = lucid_ole_vco,
 558	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 559	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 560	.clkr = {
 561		.hw.init = &(const struct clk_init_data) {
 562			.name = "cam_cc_pll9",
 563			.parent_data = &(const struct clk_parent_data) {
 564				.index = DT_BI_TCXO,
 565			},
 566			.num_parents = 1,
 567			.ops = &clk_alpha_pll_lucid_evo_ops,
 568		},
 569	},
 570};
 571
 572static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
 573	{ 0x1, 2 },
 574	{ }
 575};
 576
 577static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
 578	.offset = 0x9000,
 579	.post_div_shift = 10,
 580	.post_div_table = post_div_table_cam_cc_pll9_out_even,
 581	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
 582	.width = 4,
 583	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 584	.clkr.hw.init = &(const struct clk_init_data) {
 585		.name = "cam_cc_pll9_out_even",
 586		.parent_hws = (const struct clk_hw*[]) {
 587			&cam_cc_pll9.clkr.hw,
 588		},
 589		.num_parents = 1,
 590		.flags = CLK_SET_RATE_PARENT,
 591		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 592	},
 593};
 594
 595static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = {
 596	{ 0x2, 3 },
 597	{ }
 598};
 599
 600static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = {
 601	.offset = 0x9000,
 602	.post_div_shift = 14,
 603	.post_div_table = post_div_table_cam_cc_pll9_out_odd,
 604	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd),
 605	.width = 4,
 606	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 607	.clkr.hw.init = &(const struct clk_init_data) {
 608		.name = "cam_cc_pll9_out_odd",
 609		.parent_hws = (const struct clk_hw*[]) {
 610			&cam_cc_pll9.clkr.hw,
 611		},
 612		.num_parents = 1,
 613		.flags = CLK_SET_RATE_PARENT,
 614		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 615	},
 616};
 617
 618static const struct alpha_pll_config cam_cc_pll10_config = {
 619	.l = 0x30,
 620	.alpha = 0x8aaa,
 621	.config_ctl_val = 0x20485699,
 622	.config_ctl_hi_val = 0x00182261,
 623	.config_ctl_hi1_val = 0x82aa299c,
 624	.test_ctl_val = 0x00000000,
 625	.test_ctl_hi_val = 0x00000003,
 626	.test_ctl_hi1_val = 0x00009000,
 627	.test_ctl_hi2_val = 0x00000034,
 628	.user_ctl_val = 0x00000400,
 629	.user_ctl_hi_val = 0x00000005,
 630};
 631
 632static struct clk_alpha_pll cam_cc_pll10 = {
 633	.offset = 0xa000,
 634	.vco_table = lucid_ole_vco,
 635	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 636	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 637	.clkr = {
 638		.hw.init = &(const struct clk_init_data) {
 639			.name = "cam_cc_pll10",
 640			.parent_data = &(const struct clk_parent_data) {
 641				.index = DT_BI_TCXO,
 642			},
 643			.num_parents = 1,
 644			.ops = &clk_alpha_pll_lucid_evo_ops,
 645		},
 646	},
 647};
 648
 649static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
 650	{ 0x1, 2 },
 651	{ }
 652};
 653
 654static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
 655	.offset = 0xa000,
 656	.post_div_shift = 10,
 657	.post_div_table = post_div_table_cam_cc_pll10_out_even,
 658	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
 659	.width = 4,
 660	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 661	.clkr.hw.init = &(const struct clk_init_data) {
 662		.name = "cam_cc_pll10_out_even",
 663		.parent_hws = (const struct clk_hw*[]) {
 664			&cam_cc_pll10.clkr.hw,
 665		},
 666		.num_parents = 1,
 667		.flags = CLK_SET_RATE_PARENT,
 668		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 669	},
 670};
 671
 672static const struct parent_map cam_cc_parent_map_0[] = {
 673	{ P_BI_TCXO, 0 },
 674	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
 675	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
 676	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
 677	{ P_CAM_CC_PLL9_OUT_ODD, 4 },
 678	{ P_CAM_CC_PLL9_OUT_EVEN, 5 },
 679};
 680
 681static const struct clk_parent_data cam_cc_parent_data_0[] = {
 682	{ .index = DT_BI_TCXO },
 683	{ .hw = &cam_cc_pll0.clkr.hw },
 684	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
 685	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
 686	{ .hw = &cam_cc_pll9_out_odd.clkr.hw },
 687	{ .hw = &cam_cc_pll9_out_even.clkr.hw },
 688};
 689
 690static const struct parent_map cam_cc_parent_map_1[] = {
 691	{ P_BI_TCXO, 0 },
 692	{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
 693	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
 694};
 695
 696static const struct clk_parent_data cam_cc_parent_data_1[] = {
 697	{ .index = DT_BI_TCXO },
 698	{ .hw = &cam_cc_pll2.clkr.hw },
 699	{ .hw = &cam_cc_pll2.clkr.hw },
 700};
 701
 702static const struct parent_map cam_cc_parent_map_2[] = {
 703	{ P_BI_TCXO, 0 },
 704	{ P_CAM_CC_PLL8_OUT_EVEN, 6 },
 705};
 706
 707static const struct clk_parent_data cam_cc_parent_data_2[] = {
 708	{ .index = DT_BI_TCXO },
 709	{ .hw = &cam_cc_pll8_out_even.clkr.hw },
 710};
 711
 712static const struct parent_map cam_cc_parent_map_3[] = {
 713	{ P_BI_TCXO, 0 },
 714	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
 715};
 716
 717static const struct clk_parent_data cam_cc_parent_data_3[] = {
 718	{ .index = DT_BI_TCXO },
 719	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
 720};
 721
 722static const struct parent_map cam_cc_parent_map_4[] = {
 723	{ P_BI_TCXO, 0 },
 724	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
 725};
 726
 727static const struct clk_parent_data cam_cc_parent_data_4[] = {
 728	{ .index = DT_BI_TCXO },
 729	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
 730};
 731
 732static const struct parent_map cam_cc_parent_map_5[] = {
 733	{ P_BI_TCXO, 0 },
 734	{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
 735};
 736
 737static const struct clk_parent_data cam_cc_parent_data_5[] = {
 738	{ .index = DT_BI_TCXO },
 739	{ .hw = &cam_cc_pll5_out_even.clkr.hw },
 740};
 741
 742static const struct parent_map cam_cc_parent_map_6[] = {
 743	{ P_BI_TCXO, 0 },
 744	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
 745};
 746
 747static const struct clk_parent_data cam_cc_parent_data_6[] = {
 748	{ .index = DT_BI_TCXO },
 749	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
 750};
 751
 752static const struct parent_map cam_cc_parent_map_7[] = {
 753	{ P_BI_TCXO, 0 },
 754	{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
 755};
 756
 757static const struct clk_parent_data cam_cc_parent_data_7[] = {
 758	{ .index = DT_BI_TCXO },
 759	{ .hw = &cam_cc_pll6_out_even.clkr.hw },
 760};
 761
 762static const struct parent_map cam_cc_parent_map_8[] = {
 763	{ P_BI_TCXO, 0 },
 764	{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
 765};
 766
 767static const struct clk_parent_data cam_cc_parent_data_8[] = {
 768	{ .index = DT_BI_TCXO },
 769	{ .hw = &cam_cc_pll7_out_even.clkr.hw },
 770};
 771
 772static const struct parent_map cam_cc_parent_map_9[] = {
 773	{ P_BI_TCXO, 0 },
 774	{ P_CAM_CC_PLL10_OUT_EVEN, 6 },
 775};
 776
 777static const struct clk_parent_data cam_cc_parent_data_9[] = {
 778	{ .index = DT_BI_TCXO },
 779	{ .hw = &cam_cc_pll10_out_even.clkr.hw },
 780};
 781
 782static const struct parent_map cam_cc_parent_map_10[] = {
 783	{ P_SLEEP_CLK, 0 },
 784};
 785
 786static const struct clk_parent_data cam_cc_parent_data_10[] = {
 787	{ .index = DT_SLEEP_CLK },
 788};
 789
 790static const struct parent_map cam_cc_parent_map_11_ao[] = {
 791	{ P_BI_TCXO_AO, 0 },
 792};
 793
 794static const struct clk_parent_data cam_cc_parent_data_11_ao[] = {
 795	{ .index = DT_BI_TCXO_AO },
 796};
 797
 798static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 799	F(19200000, P_BI_TCXO, 1, 0, 0),
 800	F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 801	F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 802	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 803	F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 804	{ }
 805};
 806
 807static struct clk_rcg2 cam_cc_bps_clk_src = {
 808	.cmd_rcgr = 0x10050,
 809	.mnd_width = 0,
 810	.hid_width = 5,
 811	.parent_map = cam_cc_parent_map_2,
 812	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 813	.clkr.hw.init = &(const struct clk_init_data) {
 814		.name = "cam_cc_bps_clk_src",
 815		.parent_data = cam_cc_parent_data_2,
 816		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 817		.flags = CLK_SET_RATE_PARENT,
 818		.ops = &clk_rcg2_shared_ops,
 819	},
 820};
 821
 822static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = {
 823	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 824	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 825	{ }
 826};
 827
 828static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = {
 829	.cmd_rcgr = 0x1325c,
 830	.mnd_width = 0,
 831	.hid_width = 5,
 832	.parent_map = cam_cc_parent_map_0,
 833	.freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src,
 834	.clkr.hw.init = &(const struct clk_init_data) {
 835		.name = "cam_cc_camnoc_axi_rt_clk_src",
 836		.parent_data = cam_cc_parent_data_0,
 837		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 838		.flags = CLK_SET_RATE_PARENT,
 839		.ops = &clk_rcg2_shared_ops,
 840	},
 841};
 842
 843static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 844	F(19200000, P_BI_TCXO, 1, 0, 0),
 845	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 846	{ }
 847};
 848
 849static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 850	.cmd_rcgr = 0x131cc,
 851	.mnd_width = 8,
 852	.hid_width = 5,
 853	.parent_map = cam_cc_parent_map_0,
 854	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 855	.clkr.hw.init = &(const struct clk_init_data) {
 856		.name = "cam_cc_cci_0_clk_src",
 857		.parent_data = cam_cc_parent_data_0,
 858		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 859		.flags = CLK_SET_RATE_PARENT,
 860		.ops = &clk_rcg2_shared_ops,
 861	},
 862};
 863
 864static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 865	.cmd_rcgr = 0x131e8,
 866	.mnd_width = 8,
 867	.hid_width = 5,
 868	.parent_map = cam_cc_parent_map_0,
 869	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 870	.clkr.hw.init = &(const struct clk_init_data) {
 871		.name = "cam_cc_cci_1_clk_src",
 872		.parent_data = cam_cc_parent_data_0,
 873		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 874		.flags = CLK_SET_RATE_PARENT,
 875		.ops = &clk_rcg2_shared_ops,
 876	},
 877};
 878
 879static struct clk_rcg2 cam_cc_cci_2_clk_src = {
 880	.cmd_rcgr = 0x13204,
 881	.mnd_width = 8,
 882	.hid_width = 5,
 883	.parent_map = cam_cc_parent_map_0,
 884	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 885	.clkr.hw.init = &(const struct clk_init_data) {
 886		.name = "cam_cc_cci_2_clk_src",
 887		.parent_data = cam_cc_parent_data_0,
 888		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 889		.flags = CLK_SET_RATE_PARENT,
 890		.ops = &clk_rcg2_shared_ops,
 891	},
 892};
 893
 894static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
 895	F(19200000, P_BI_TCXO, 1, 0, 0),
 896	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 897	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
 898	{ }
 899};
 900
 901static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 902	.cmd_rcgr = 0x1104c,
 903	.mnd_width = 0,
 904	.hid_width = 5,
 905	.parent_map = cam_cc_parent_map_0,
 906	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 907	.clkr.hw.init = &(const struct clk_init_data) {
 908		.name = "cam_cc_cphy_rx_clk_src",
 909		.parent_data = cam_cc_parent_data_0,
 910		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 911		.flags = CLK_SET_RATE_PARENT,
 912		.ops = &clk_rcg2_shared_ops,
 913	},
 914};
 915
 916static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
 917	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
 918	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 919	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
 920	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 921	{ }
 922};
 923
 924static struct clk_rcg2 cam_cc_cre_clk_src = {
 925	.cmd_rcgr = 0x13144,
 926	.mnd_width = 0,
 927	.hid_width = 5,
 928	.parent_map = cam_cc_parent_map_0,
 929	.freq_tbl = ftbl_cam_cc_cre_clk_src,
 930	.clkr.hw.init = &(const struct clk_init_data) {
 931		.name = "cam_cc_cre_clk_src",
 932		.parent_data = cam_cc_parent_data_0,
 933		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 934		.flags = CLK_SET_RATE_PARENT,
 935		.ops = &clk_rcg2_shared_ops,
 936	},
 937};
 938
 939static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
 940	F(19200000, P_BI_TCXO, 1, 0, 0),
 941	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 942	{ }
 943};
 944
 945static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 946	.cmd_rcgr = 0x150e0,
 947	.mnd_width = 0,
 948	.hid_width = 5,
 949	.parent_map = cam_cc_parent_map_0,
 950	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 951	.clkr.hw.init = &(const struct clk_init_data) {
 952		.name = "cam_cc_csi0phytimer_clk_src",
 953		.parent_data = cam_cc_parent_data_0,
 954		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 955		.flags = CLK_SET_RATE_PARENT,
 956		.ops = &clk_rcg2_shared_ops,
 957	},
 958};
 959
 960static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 961	.cmd_rcgr = 0x15104,
 962	.mnd_width = 0,
 963	.hid_width = 5,
 964	.parent_map = cam_cc_parent_map_0,
 965	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 966	.clkr.hw.init = &(const struct clk_init_data) {
 967		.name = "cam_cc_csi1phytimer_clk_src",
 968		.parent_data = cam_cc_parent_data_0,
 969		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 970		.flags = CLK_SET_RATE_PARENT,
 971		.ops = &clk_rcg2_shared_ops,
 972	},
 973};
 974
 975static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 976	.cmd_rcgr = 0x15124,
 977	.mnd_width = 0,
 978	.hid_width = 5,
 979	.parent_map = cam_cc_parent_map_0,
 980	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 981	.clkr.hw.init = &(const struct clk_init_data) {
 982		.name = "cam_cc_csi2phytimer_clk_src",
 983		.parent_data = cam_cc_parent_data_0,
 984		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 985		.flags = CLK_SET_RATE_PARENT,
 986		.ops = &clk_rcg2_shared_ops,
 987	},
 988};
 989
 990static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 991	.cmd_rcgr = 0x15144,
 992	.mnd_width = 0,
 993	.hid_width = 5,
 994	.parent_map = cam_cc_parent_map_0,
 995	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 996	.clkr.hw.init = &(const struct clk_init_data) {
 997		.name = "cam_cc_csi3phytimer_clk_src",
 998		.parent_data = cam_cc_parent_data_0,
 999		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1000		.flags = CLK_SET_RATE_PARENT,
1001		.ops = &clk_rcg2_shared_ops,
1002	},
1003};
1004
1005static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
1006	.cmd_rcgr = 0x15164,
1007	.mnd_width = 0,
1008	.hid_width = 5,
1009	.parent_map = cam_cc_parent_map_0,
1010	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1011	.clkr.hw.init = &(const struct clk_init_data) {
1012		.name = "cam_cc_csi4phytimer_clk_src",
1013		.parent_data = cam_cc_parent_data_0,
1014		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1015		.flags = CLK_SET_RATE_PARENT,
1016		.ops = &clk_rcg2_shared_ops,
1017	},
1018};
1019
1020static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
1021	.cmd_rcgr = 0x15184,
1022	.mnd_width = 0,
1023	.hid_width = 5,
1024	.parent_map = cam_cc_parent_map_0,
1025	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1026	.clkr.hw.init = &(const struct clk_init_data) {
1027		.name = "cam_cc_csi5phytimer_clk_src",
1028		.parent_data = cam_cc_parent_data_0,
1029		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1030		.flags = CLK_SET_RATE_PARENT,
1031		.ops = &clk_rcg2_shared_ops,
1032	},
1033};
1034
1035static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
1036	.cmd_rcgr = 0x151a4,
1037	.mnd_width = 0,
1038	.hid_width = 5,
1039	.parent_map = cam_cc_parent_map_0,
1040	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1041	.clkr.hw.init = &(const struct clk_init_data) {
1042		.name = "cam_cc_csi6phytimer_clk_src",
1043		.parent_data = cam_cc_parent_data_0,
1044		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1045		.flags = CLK_SET_RATE_PARENT,
1046		.ops = &clk_rcg2_shared_ops,
1047	},
1048};
1049
1050static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
1051	.cmd_rcgr = 0x151c4,
1052	.mnd_width = 0,
1053	.hid_width = 5,
1054	.parent_map = cam_cc_parent_map_0,
1055	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1056	.clkr.hw.init = &(const struct clk_init_data) {
1057		.name = "cam_cc_csi7phytimer_clk_src",
1058		.parent_data = cam_cc_parent_data_0,
1059		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1060		.flags = CLK_SET_RATE_PARENT,
1061		.ops = &clk_rcg2_shared_ops,
1062	},
1063};
1064
1065static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
1066	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1067	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1068	{ }
1069};
1070
1071static struct clk_rcg2 cam_cc_csid_clk_src = {
1072	.cmd_rcgr = 0x13238,
1073	.mnd_width = 0,
1074	.hid_width = 5,
1075	.parent_map = cam_cc_parent_map_0,
1076	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1077	.clkr.hw.init = &(const struct clk_init_data) {
1078		.name = "cam_cc_csid_clk_src",
1079		.parent_data = cam_cc_parent_data_0,
1080		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1081		.flags = CLK_SET_RATE_PARENT,
1082		.ops = &clk_rcg2_shared_ops,
1083	},
1084};
1085
1086static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
1087	F(19200000, P_BI_TCXO, 1, 0, 0),
1088	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1089	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1090	{ }
1091};
1092
1093static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
1094	.cmd_rcgr = 0x10018,
1095	.mnd_width = 0,
1096	.hid_width = 5,
1097	.parent_map = cam_cc_parent_map_0,
1098	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
1099	.clkr.hw.init = &(const struct clk_init_data) {
1100		.name = "cam_cc_fast_ahb_clk_src",
1101		.parent_data = cam_cc_parent_data_0,
1102		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1103		.flags = CLK_SET_RATE_PARENT,
1104		.ops = &clk_rcg2_shared_ops,
1105	},
1106};
1107
1108static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
1109	F(19200000, P_BI_TCXO, 1, 0, 0),
1110	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1111	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1112	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
1113	{ }
1114};
1115
1116static struct clk_rcg2 cam_cc_icp_clk_src = {
1117	.cmd_rcgr = 0x131a4,
1118	.mnd_width = 0,
1119	.hid_width = 5,
1120	.parent_map = cam_cc_parent_map_0,
1121	.freq_tbl = ftbl_cam_cc_icp_clk_src,
1122	.clkr.hw.init = &(const struct clk_init_data) {
1123		.name = "cam_cc_icp_clk_src",
1124		.parent_data = cam_cc_parent_data_0,
1125		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1126		.flags = CLK_SET_RATE_PARENT,
1127		.ops = &clk_rcg2_shared_ops,
1128	},
1129};
1130
1131static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
1132	F(19200000, P_BI_TCXO, 1, 0, 0),
1133	F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1134	F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1135	F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1136	F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1137	{ }
1138};
1139
1140static struct clk_rcg2 cam_cc_ife_0_clk_src = {
1141	.cmd_rcgr = 0x11018,
1142	.mnd_width = 0,
1143	.hid_width = 5,
1144	.parent_map = cam_cc_parent_map_3,
1145	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
1146	.clkr.hw.init = &(const struct clk_init_data) {
1147		.name = "cam_cc_ife_0_clk_src",
1148		.parent_data = cam_cc_parent_data_3,
1149		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1150		.flags = CLK_SET_RATE_PARENT,
1151		.ops = &clk_rcg2_shared_ops,
1152	},
1153};
1154
1155static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
1156	F(19200000, P_BI_TCXO, 1, 0, 0),
1157	F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1158	F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1159	F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1160	F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1161	{ }
1162};
1163
1164static struct clk_rcg2 cam_cc_ife_1_clk_src = {
1165	.cmd_rcgr = 0x12018,
1166	.mnd_width = 0,
1167	.hid_width = 5,
1168	.parent_map = cam_cc_parent_map_4,
1169	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
1170	.clkr.hw.init = &(const struct clk_init_data) {
1171		.name = "cam_cc_ife_1_clk_src",
1172		.parent_data = cam_cc_parent_data_4,
1173		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
1174		.flags = CLK_SET_RATE_PARENT,
1175		.ops = &clk_rcg2_shared_ops,
1176	},
1177};
1178
1179static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
1180	F(19200000, P_BI_TCXO, 1, 0, 0),
1181	F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1182	F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1183	F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1184	F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1185	{ }
1186};
1187
1188static struct clk_rcg2 cam_cc_ife_2_clk_src = {
1189	.cmd_rcgr = 0x12068,
1190	.mnd_width = 0,
1191	.hid_width = 5,
1192	.parent_map = cam_cc_parent_map_5,
1193	.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
1194	.clkr.hw.init = &(const struct clk_init_data) {
1195		.name = "cam_cc_ife_2_clk_src",
1196		.parent_data = cam_cc_parent_data_5,
1197		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
1198		.flags = CLK_SET_RATE_PARENT,
1199		.ops = &clk_rcg2_shared_ops,
1200	},
1201};
1202
1203static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
1204	.cmd_rcgr = 0x13000,
1205	.mnd_width = 0,
1206	.hid_width = 5,
1207	.parent_map = cam_cc_parent_map_0,
1208	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1209	.clkr.hw.init = &(const struct clk_init_data) {
1210		.name = "cam_cc_ife_lite_clk_src",
1211		.parent_data = cam_cc_parent_data_0,
1212		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1213		.flags = CLK_SET_RATE_PARENT,
1214		.ops = &clk_rcg2_shared_ops,
1215	},
1216};
1217
1218static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
1219	.cmd_rcgr = 0x13028,
1220	.mnd_width = 0,
1221	.hid_width = 5,
1222	.parent_map = cam_cc_parent_map_0,
1223	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1224	.clkr.hw.init = &(const struct clk_init_data) {
1225		.name = "cam_cc_ife_lite_csid_clk_src",
1226		.parent_data = cam_cc_parent_data_0,
1227		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1228		.flags = CLK_SET_RATE_PARENT,
1229		.ops = &clk_rcg2_shared_ops,
1230	},
1231};
1232
1233static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
1234	F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1235	F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1236	F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1237	F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1238	{ }
1239};
1240
1241static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
1242	.cmd_rcgr = 0x10094,
1243	.mnd_width = 0,
1244	.hid_width = 5,
1245	.parent_map = cam_cc_parent_map_6,
1246	.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
1247	.clkr.hw.init = &(const struct clk_init_data) {
1248		.name = "cam_cc_ipe_nps_clk_src",
1249		.parent_data = cam_cc_parent_data_6,
1250		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1251		.flags = CLK_SET_RATE_PARENT,
1252		.ops = &clk_rcg2_shared_ops,
1253	},
1254};
1255
1256static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
1257	F(19200000, P_BI_TCXO, 1, 0, 0),
1258	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
1259	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1260	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1261	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
1262	{ }
1263};
1264
1265static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1266	.cmd_rcgr = 0x13168,
1267	.mnd_width = 0,
1268	.hid_width = 5,
1269	.parent_map = cam_cc_parent_map_0,
1270	.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
1271	.clkr.hw.init = &(const struct clk_init_data) {
1272		.name = "cam_cc_jpeg_clk_src",
1273		.parent_data = cam_cc_parent_data_0,
1274		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1275		.flags = CLK_SET_RATE_PARENT,
1276		.ops = &clk_rcg2_shared_ops,
1277	},
1278};
1279
1280static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1281	F(19200000, P_BI_TCXO, 1, 0, 0),
1282	F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4),
1283	F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1284	{ }
1285};
1286
1287static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1288	.cmd_rcgr = 0x15000,
1289	.mnd_width = 8,
1290	.hid_width = 5,
1291	.parent_map = cam_cc_parent_map_1,
1292	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1293	.clkr.hw.init = &(const struct clk_init_data) {
1294		.name = "cam_cc_mclk0_clk_src",
1295		.parent_data = cam_cc_parent_data_1,
1296		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1297		.flags = CLK_SET_RATE_PARENT,
1298		.ops = &clk_rcg2_shared_ops,
1299	},
1300};
1301
1302static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1303	.cmd_rcgr = 0x1501c,
1304	.mnd_width = 8,
1305	.hid_width = 5,
1306	.parent_map = cam_cc_parent_map_1,
1307	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1308	.clkr.hw.init = &(const struct clk_init_data) {
1309		.name = "cam_cc_mclk1_clk_src",
1310		.parent_data = cam_cc_parent_data_1,
1311		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1312		.flags = CLK_SET_RATE_PARENT,
1313		.ops = &clk_rcg2_shared_ops,
1314	},
1315};
1316
1317static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1318	.cmd_rcgr = 0x15038,
1319	.mnd_width = 8,
1320	.hid_width = 5,
1321	.parent_map = cam_cc_parent_map_1,
1322	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1323	.clkr.hw.init = &(const struct clk_init_data) {
1324		.name = "cam_cc_mclk2_clk_src",
1325		.parent_data = cam_cc_parent_data_1,
1326		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1327		.flags = CLK_SET_RATE_PARENT,
1328		.ops = &clk_rcg2_shared_ops,
1329	},
1330};
1331
1332static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1333	.cmd_rcgr = 0x15054,
1334	.mnd_width = 8,
1335	.hid_width = 5,
1336	.parent_map = cam_cc_parent_map_1,
1337	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1338	.clkr.hw.init = &(const struct clk_init_data) {
1339		.name = "cam_cc_mclk3_clk_src",
1340		.parent_data = cam_cc_parent_data_1,
1341		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1342		.flags = CLK_SET_RATE_PARENT,
1343		.ops = &clk_rcg2_shared_ops,
1344	},
1345};
1346
1347static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1348	.cmd_rcgr = 0x15070,
1349	.mnd_width = 8,
1350	.hid_width = 5,
1351	.parent_map = cam_cc_parent_map_1,
1352	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1353	.clkr.hw.init = &(const struct clk_init_data) {
1354		.name = "cam_cc_mclk4_clk_src",
1355		.parent_data = cam_cc_parent_data_1,
1356		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1357		.flags = CLK_SET_RATE_PARENT,
1358		.ops = &clk_rcg2_shared_ops,
1359	},
1360};
1361
1362static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1363	.cmd_rcgr = 0x1508c,
1364	.mnd_width = 8,
1365	.hid_width = 5,
1366	.parent_map = cam_cc_parent_map_1,
1367	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1368	.clkr.hw.init = &(const struct clk_init_data) {
1369		.name = "cam_cc_mclk5_clk_src",
1370		.parent_data = cam_cc_parent_data_1,
1371		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1372		.flags = CLK_SET_RATE_PARENT,
1373		.ops = &clk_rcg2_shared_ops,
1374	},
1375};
1376
1377static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1378	.cmd_rcgr = 0x150a8,
1379	.mnd_width = 8,
1380	.hid_width = 5,
1381	.parent_map = cam_cc_parent_map_1,
1382	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1383	.clkr.hw.init = &(const struct clk_init_data) {
1384		.name = "cam_cc_mclk6_clk_src",
1385		.parent_data = cam_cc_parent_data_1,
1386		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1387		.flags = CLK_SET_RATE_PARENT,
1388		.ops = &clk_rcg2_shared_ops,
1389	},
1390};
1391
1392static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1393	.cmd_rcgr = 0x150c4,
1394	.mnd_width = 8,
1395	.hid_width = 5,
1396	.parent_map = cam_cc_parent_map_1,
1397	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1398	.clkr.hw.init = &(const struct clk_init_data) {
1399		.name = "cam_cc_mclk7_clk_src",
1400		.parent_data = cam_cc_parent_data_1,
1401		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1402		.flags = CLK_SET_RATE_PARENT,
1403		.ops = &clk_rcg2_shared_ops,
1404	},
1405};
1406
1407static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1408	F(19200000, P_BI_TCXO, 1, 0, 0),
1409	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1410	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1411	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1412	{ }
1413};
1414
1415static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1416	.cmd_rcgr = 0x1329c,
1417	.mnd_width = 0,
1418	.hid_width = 5,
1419	.parent_map = cam_cc_parent_map_0,
1420	.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1421	.clkr.hw.init = &(const struct clk_init_data) {
1422		.name = "cam_cc_qdss_debug_clk_src",
1423		.parent_data = cam_cc_parent_data_0,
1424		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1425		.flags = CLK_SET_RATE_PARENT,
1426		.ops = &clk_rcg2_shared_ops,
1427	},
1428};
1429
1430static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1431	F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1432	F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1433	F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1434	F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1435	{ }
1436};
1437
1438static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1439	.cmd_rcgr = 0x1306c,
1440	.mnd_width = 0,
1441	.hid_width = 5,
1442	.parent_map = cam_cc_parent_map_7,
1443	.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1444	.clkr.hw.init = &(const struct clk_init_data) {
1445		.name = "cam_cc_sfe_0_clk_src",
1446		.parent_data = cam_cc_parent_data_7,
1447		.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1448		.flags = CLK_SET_RATE_PARENT,
1449		.ops = &clk_rcg2_shared_ops,
1450	},
1451};
1452
1453static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1454	F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1455	F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1456	F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1457	F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1458	{ }
1459};
1460
1461static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1462	.cmd_rcgr = 0x130bc,
1463	.mnd_width = 0,
1464	.hid_width = 5,
1465	.parent_map = cam_cc_parent_map_8,
1466	.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1467	.clkr.hw.init = &(const struct clk_init_data) {
1468		.name = "cam_cc_sfe_1_clk_src",
1469		.parent_data = cam_cc_parent_data_8,
1470		.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1471		.flags = CLK_SET_RATE_PARENT,
1472		.ops = &clk_rcg2_shared_ops,
1473	},
1474};
1475
1476static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = {
1477	F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1478	F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1479	F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1480	F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1481	{ }
1482};
1483
1484static struct clk_rcg2 cam_cc_sfe_2_clk_src = {
1485	.cmd_rcgr = 0x1310c,
1486	.mnd_width = 0,
1487	.hid_width = 5,
1488	.parent_map = cam_cc_parent_map_9,
1489	.freq_tbl = ftbl_cam_cc_sfe_2_clk_src,
1490	.clkr.hw.init = &(const struct clk_init_data) {
1491		.name = "cam_cc_sfe_2_clk_src",
1492		.parent_data = cam_cc_parent_data_9,
1493		.num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
1494		.flags = CLK_SET_RATE_PARENT,
1495		.ops = &clk_rcg2_shared_ops,
1496	},
1497};
1498
1499static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1500	F(32000, P_SLEEP_CLK, 1, 0, 0),
1501	{ }
1502};
1503
1504static struct clk_rcg2 cam_cc_sleep_clk_src = {
1505	.cmd_rcgr = 0x132f0,
1506	.mnd_width = 0,
1507	.hid_width = 5,
1508	.parent_map = cam_cc_parent_map_10,
1509	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1510	.clkr.hw.init = &(const struct clk_init_data) {
1511		.name = "cam_cc_sleep_clk_src",
1512		.parent_data = cam_cc_parent_data_10,
1513		.num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
1514		.flags = CLK_SET_RATE_PARENT,
1515		.ops = &clk_rcg2_shared_ops,
1516	},
1517};
1518
1519static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1520	F(19200000, P_BI_TCXO, 1, 0, 0),
1521	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1522	{ }
1523};
1524
1525static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1526	.cmd_rcgr = 0x10034,
1527	.mnd_width = 0,
1528	.hid_width = 5,
1529	.parent_map = cam_cc_parent_map_0,
1530	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1531	.clkr.hw.init = &(const struct clk_init_data) {
1532		.name = "cam_cc_slow_ahb_clk_src",
1533		.parent_data = cam_cc_parent_data_0,
1534		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1535		.flags = CLK_SET_RATE_PARENT,
1536		.ops = &clk_rcg2_shared_ops,
1537	},
1538};
1539
1540static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1541	F(19200000, P_BI_TCXO_AO, 1, 0, 0),
1542	{ }
1543};
1544
1545static struct clk_rcg2 cam_cc_xo_clk_src = {
1546	.cmd_rcgr = 0x132d4,
1547	.mnd_width = 0,
1548	.hid_width = 5,
1549	.parent_map = cam_cc_parent_map_11_ao,
1550	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1551	.clkr.hw.init = &(const struct clk_init_data) {
1552		.name = "cam_cc_xo_clk_src",
1553		.parent_data = cam_cc_parent_data_11_ao,
1554		.num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao),
1555		.flags = CLK_SET_RATE_PARENT,
1556		.ops = &clk_rcg2_shared_ops,
1557	},
1558};
1559
1560static struct clk_branch cam_cc_bps_ahb_clk = {
1561	.halt_reg = 0x1004c,
1562	.halt_check = BRANCH_HALT,
1563	.clkr = {
1564		.enable_reg = 0x1004c,
1565		.enable_mask = BIT(0),
1566		.hw.init = &(const struct clk_init_data) {
1567			.name = "cam_cc_bps_ahb_clk",
1568			.parent_hws = (const struct clk_hw*[]) {
1569				&cam_cc_slow_ahb_clk_src.clkr.hw,
1570			},
1571			.num_parents = 1,
1572			.flags = CLK_SET_RATE_PARENT,
1573			.ops = &clk_branch2_ops,
1574		},
1575	},
1576};
1577
1578static struct clk_branch cam_cc_bps_clk = {
1579	.halt_reg = 0x10068,
1580	.halt_check = BRANCH_HALT,
1581	.clkr = {
1582		.enable_reg = 0x10068,
1583		.enable_mask = BIT(0),
1584		.hw.init = &(const struct clk_init_data) {
1585			.name = "cam_cc_bps_clk",
1586			.parent_hws = (const struct clk_hw*[]) {
1587				&cam_cc_bps_clk_src.clkr.hw,
1588			},
1589			.num_parents = 1,
1590			.flags = CLK_SET_RATE_PARENT,
1591			.ops = &clk_branch2_ops,
1592		},
1593	},
1594};
1595
1596static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1597	.halt_reg = 0x10030,
1598	.halt_check = BRANCH_HALT,
1599	.clkr = {
1600		.enable_reg = 0x10030,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(const struct clk_init_data) {
1603			.name = "cam_cc_bps_fast_ahb_clk",
1604			.parent_hws = (const struct clk_hw*[]) {
1605				&cam_cc_fast_ahb_clk_src.clkr.hw,
1606			},
1607			.num_parents = 1,
1608			.flags = CLK_SET_RATE_PARENT,
1609			.ops = &clk_branch2_ops,
1610		},
1611	},
1612};
1613
1614static struct clk_branch cam_cc_bps_shift_clk = {
1615	.halt_reg = 0x10078,
1616	.halt_check = BRANCH_HALT_VOTED,
1617	.clkr = {
1618		.enable_reg = 0x10078,
1619		.enable_mask = BIT(0),
1620		.hw.init = &(const struct clk_init_data) {
1621			.name = "cam_cc_bps_shift_clk",
1622			.parent_hws = (const struct clk_hw*[]) {
1623				&cam_cc_xo_clk_src.clkr.hw,
1624			},
1625			.num_parents = 1,
1626			.flags = CLK_SET_RATE_PARENT,
1627			.ops = &clk_branch2_ops,
1628		},
1629	},
1630};
1631
1632static struct clk_branch cam_cc_camnoc_axi_nrt_clk = {
1633	.halt_reg = 0x13284,
1634	.halt_check = BRANCH_HALT,
1635	.clkr = {
1636		.enable_reg = 0x13284,
1637		.enable_mask = BIT(0),
1638		.hw.init = &(const struct clk_init_data) {
1639			.name = "cam_cc_camnoc_axi_nrt_clk",
1640			.parent_hws = (const struct clk_hw*[]) {
1641				&cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
1642			},
1643			.num_parents = 1,
1644			.flags = CLK_SET_RATE_PARENT,
1645			.ops = &clk_branch2_ops,
1646		},
1647	},
1648};
1649
1650static struct clk_branch cam_cc_camnoc_axi_rt_clk = {
1651	.halt_reg = 0x13274,
1652	.halt_check = BRANCH_HALT,
1653	.clkr = {
1654		.enable_reg = 0x13274,
1655		.enable_mask = BIT(0),
1656		.hw.init = &(const struct clk_init_data) {
1657			.name = "cam_cc_camnoc_axi_rt_clk",
1658			.parent_hws = (const struct clk_hw*[]) {
1659				&cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
1660			},
1661			.num_parents = 1,
1662			.flags = CLK_SET_RATE_PARENT,
1663			.ops = &clk_branch2_ops,
1664		},
1665	},
1666};
1667
1668static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1669	.halt_reg = 0x13290,
1670	.halt_check = BRANCH_HALT,
1671	.clkr = {
1672		.enable_reg = 0x13290,
1673		.enable_mask = BIT(0),
1674		.hw.init = &(const struct clk_init_data) {
1675			.name = "cam_cc_camnoc_dcd_xo_clk",
1676			.parent_hws = (const struct clk_hw*[]) {
1677				&cam_cc_xo_clk_src.clkr.hw,
1678			},
1679			.num_parents = 1,
1680			.flags = CLK_SET_RATE_PARENT,
1681			.ops = &clk_branch2_ops,
1682		},
1683	},
1684};
1685
1686static struct clk_branch cam_cc_camnoc_xo_clk = {
1687	.halt_reg = 0x13294,
1688	.halt_check = BRANCH_HALT,
1689	.clkr = {
1690		.enable_reg = 0x13294,
1691		.enable_mask = BIT(0),
1692		.hw.init = &(const struct clk_init_data) {
1693			.name = "cam_cc_camnoc_xo_clk",
1694			.parent_hws = (const struct clk_hw*[]) {
1695				&cam_cc_xo_clk_src.clkr.hw,
1696			},
1697			.num_parents = 1,
1698			.flags = CLK_SET_RATE_PARENT,
1699			.ops = &clk_branch2_ops,
1700		},
1701	},
1702};
1703
1704static struct clk_branch cam_cc_cci_0_clk = {
1705	.halt_reg = 0x131e4,
1706	.halt_check = BRANCH_HALT,
1707	.clkr = {
1708		.enable_reg = 0x131e4,
1709		.enable_mask = BIT(0),
1710		.hw.init = &(const struct clk_init_data) {
1711			.name = "cam_cc_cci_0_clk",
1712			.parent_hws = (const struct clk_hw*[]) {
1713				&cam_cc_cci_0_clk_src.clkr.hw,
1714			},
1715			.num_parents = 1,
1716			.flags = CLK_SET_RATE_PARENT,
1717			.ops = &clk_branch2_ops,
1718		},
1719	},
1720};
1721
1722static struct clk_branch cam_cc_cci_1_clk = {
1723	.halt_reg = 0x13200,
1724	.halt_check = BRANCH_HALT,
1725	.clkr = {
1726		.enable_reg = 0x13200,
1727		.enable_mask = BIT(0),
1728		.hw.init = &(const struct clk_init_data) {
1729			.name = "cam_cc_cci_1_clk",
1730			.parent_hws = (const struct clk_hw*[]) {
1731				&cam_cc_cci_1_clk_src.clkr.hw,
1732			},
1733			.num_parents = 1,
1734			.flags = CLK_SET_RATE_PARENT,
1735			.ops = &clk_branch2_ops,
1736		},
1737	},
1738};
1739
1740static struct clk_branch cam_cc_cci_2_clk = {
1741	.halt_reg = 0x1321c,
1742	.halt_check = BRANCH_HALT,
1743	.clkr = {
1744		.enable_reg = 0x1321c,
1745		.enable_mask = BIT(0),
1746		.hw.init = &(const struct clk_init_data) {
1747			.name = "cam_cc_cci_2_clk",
1748			.parent_hws = (const struct clk_hw*[]) {
1749				&cam_cc_cci_2_clk_src.clkr.hw,
1750			},
1751			.num_parents = 1,
1752			.flags = CLK_SET_RATE_PARENT,
1753			.ops = &clk_branch2_ops,
1754		},
1755	},
1756};
1757
1758static struct clk_branch cam_cc_core_ahb_clk = {
1759	.halt_reg = 0x132d0,
1760	.halt_check = BRANCH_HALT_DELAY,
1761	.clkr = {
1762		.enable_reg = 0x132d0,
1763		.enable_mask = BIT(0),
1764		.hw.init = &(const struct clk_init_data) {
1765			.name = "cam_cc_core_ahb_clk",
1766			.parent_hws = (const struct clk_hw*[]) {
1767				&cam_cc_slow_ahb_clk_src.clkr.hw,
1768			},
1769			.num_parents = 1,
1770			.flags = CLK_SET_RATE_PARENT,
1771			.ops = &clk_branch2_ops,
1772		},
1773	},
1774};
1775
1776static struct clk_branch cam_cc_cpas_ahb_clk = {
1777	.halt_reg = 0x13220,
1778	.halt_check = BRANCH_HALT,
1779	.clkr = {
1780		.enable_reg = 0x13220,
1781		.enable_mask = BIT(0),
1782		.hw.init = &(const struct clk_init_data) {
1783			.name = "cam_cc_cpas_ahb_clk",
1784			.parent_hws = (const struct clk_hw*[]) {
1785				&cam_cc_slow_ahb_clk_src.clkr.hw,
1786			},
1787			.num_parents = 1,
1788			.flags = CLK_SET_RATE_PARENT,
1789			.ops = &clk_branch2_ops,
1790		},
1791	},
1792};
1793
1794static struct clk_branch cam_cc_cpas_bps_clk = {
1795	.halt_reg = 0x10074,
1796	.halt_check = BRANCH_HALT,
1797	.clkr = {
1798		.enable_reg = 0x10074,
1799		.enable_mask = BIT(0),
1800		.hw.init = &(const struct clk_init_data) {
1801			.name = "cam_cc_cpas_bps_clk",
1802			.parent_hws = (const struct clk_hw*[]) {
1803				&cam_cc_bps_clk_src.clkr.hw,
1804			},
1805			.num_parents = 1,
1806			.flags = CLK_SET_RATE_PARENT,
1807			.ops = &clk_branch2_ops,
1808		},
1809	},
1810};
1811
1812static struct clk_branch cam_cc_cpas_cre_clk = {
1813	.halt_reg = 0x13160,
1814	.halt_check = BRANCH_HALT,
1815	.clkr = {
1816		.enable_reg = 0x13160,
1817		.enable_mask = BIT(0),
1818		.hw.init = &(const struct clk_init_data) {
1819			.name = "cam_cc_cpas_cre_clk",
1820			.parent_hws = (const struct clk_hw*[]) {
1821				&cam_cc_cre_clk_src.clkr.hw,
1822			},
1823			.num_parents = 1,
1824			.flags = CLK_SET_RATE_PARENT,
1825			.ops = &clk_branch2_ops,
1826		},
1827	},
1828};
1829
1830static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1831	.halt_reg = 0x1322c,
1832	.halt_check = BRANCH_HALT,
1833	.clkr = {
1834		.enable_reg = 0x1322c,
1835		.enable_mask = BIT(0),
1836		.hw.init = &(const struct clk_init_data) {
1837			.name = "cam_cc_cpas_fast_ahb_clk",
1838			.parent_hws = (const struct clk_hw*[]) {
1839				&cam_cc_fast_ahb_clk_src.clkr.hw,
1840			},
1841			.num_parents = 1,
1842			.flags = CLK_SET_RATE_PARENT,
1843			.ops = &clk_branch2_ops,
1844		},
1845	},
1846};
1847
1848static struct clk_branch cam_cc_cpas_ife_0_clk = {
1849	.halt_reg = 0x1103c,
1850	.halt_check = BRANCH_HALT,
1851	.clkr = {
1852		.enable_reg = 0x1103c,
1853		.enable_mask = BIT(0),
1854		.hw.init = &(const struct clk_init_data) {
1855			.name = "cam_cc_cpas_ife_0_clk",
1856			.parent_hws = (const struct clk_hw*[]) {
1857				&cam_cc_ife_0_clk_src.clkr.hw,
1858			},
1859			.num_parents = 1,
1860			.flags = CLK_SET_RATE_PARENT,
1861			.ops = &clk_branch2_ops,
1862		},
1863	},
1864};
1865
1866static struct clk_branch cam_cc_cpas_ife_1_clk = {
1867	.halt_reg = 0x1203c,
1868	.halt_check = BRANCH_HALT,
1869	.clkr = {
1870		.enable_reg = 0x1203c,
1871		.enable_mask = BIT(0),
1872		.hw.init = &(const struct clk_init_data) {
1873			.name = "cam_cc_cpas_ife_1_clk",
1874			.parent_hws = (const struct clk_hw*[]) {
1875				&cam_cc_ife_1_clk_src.clkr.hw,
1876			},
1877			.num_parents = 1,
1878			.flags = CLK_SET_RATE_PARENT,
1879			.ops = &clk_branch2_ops,
1880		},
1881	},
1882};
1883
1884static struct clk_branch cam_cc_cpas_ife_2_clk = {
1885	.halt_reg = 0x1208c,
1886	.halt_check = BRANCH_HALT,
1887	.clkr = {
1888		.enable_reg = 0x1208c,
1889		.enable_mask = BIT(0),
1890		.hw.init = &(const struct clk_init_data) {
1891			.name = "cam_cc_cpas_ife_2_clk",
1892			.parent_hws = (const struct clk_hw*[]) {
1893				&cam_cc_ife_2_clk_src.clkr.hw,
1894			},
1895			.num_parents = 1,
1896			.flags = CLK_SET_RATE_PARENT,
1897			.ops = &clk_branch2_ops,
1898		},
1899	},
1900};
1901
1902static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1903	.halt_reg = 0x13024,
1904	.halt_check = BRANCH_HALT,
1905	.clkr = {
1906		.enable_reg = 0x13024,
1907		.enable_mask = BIT(0),
1908		.hw.init = &(const struct clk_init_data) {
1909			.name = "cam_cc_cpas_ife_lite_clk",
1910			.parent_hws = (const struct clk_hw*[]) {
1911				&cam_cc_ife_lite_clk_src.clkr.hw,
1912			},
1913			.num_parents = 1,
1914			.flags = CLK_SET_RATE_PARENT,
1915			.ops = &clk_branch2_ops,
1916		},
1917	},
1918};
1919
1920static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
1921	.halt_reg = 0x100b8,
1922	.halt_check = BRANCH_HALT,
1923	.clkr = {
1924		.enable_reg = 0x100b8,
1925		.enable_mask = BIT(0),
1926		.hw.init = &(const struct clk_init_data) {
1927			.name = "cam_cc_cpas_ipe_nps_clk",
1928			.parent_hws = (const struct clk_hw*[]) {
1929				&cam_cc_ipe_nps_clk_src.clkr.hw,
1930			},
1931			.num_parents = 1,
1932			.flags = CLK_SET_RATE_PARENT,
1933			.ops = &clk_branch2_ops,
1934		},
1935	},
1936};
1937
1938static struct clk_branch cam_cc_cpas_sbi_clk = {
1939	.halt_reg = 0x10104,
1940	.halt_check = BRANCH_HALT,
1941	.clkr = {
1942		.enable_reg = 0x10104,
1943		.enable_mask = BIT(0),
1944		.hw.init = &(const struct clk_init_data) {
1945			.name = "cam_cc_cpas_sbi_clk",
1946			.parent_hws = (const struct clk_hw*[]) {
1947				&cam_cc_ife_0_clk_src.clkr.hw,
1948			},
1949			.num_parents = 1,
1950			.flags = CLK_SET_RATE_PARENT,
1951			.ops = &clk_branch2_ops,
1952		},
1953	},
1954};
1955
1956static struct clk_branch cam_cc_cpas_sfe_0_clk = {
1957	.halt_reg = 0x13090,
1958	.halt_check = BRANCH_HALT,
1959	.clkr = {
1960		.enable_reg = 0x13090,
1961		.enable_mask = BIT(0),
1962		.hw.init = &(const struct clk_init_data) {
1963			.name = "cam_cc_cpas_sfe_0_clk",
1964			.parent_hws = (const struct clk_hw*[]) {
1965				&cam_cc_sfe_0_clk_src.clkr.hw,
1966			},
1967			.num_parents = 1,
1968			.flags = CLK_SET_RATE_PARENT,
1969			.ops = &clk_branch2_ops,
1970		},
1971	},
1972};
1973
1974static struct clk_branch cam_cc_cpas_sfe_1_clk = {
1975	.halt_reg = 0x130e0,
1976	.halt_check = BRANCH_HALT,
1977	.clkr = {
1978		.enable_reg = 0x130e0,
1979		.enable_mask = BIT(0),
1980		.hw.init = &(const struct clk_init_data) {
1981			.name = "cam_cc_cpas_sfe_1_clk",
1982			.parent_hws = (const struct clk_hw*[]) {
1983				&cam_cc_sfe_1_clk_src.clkr.hw,
1984			},
1985			.num_parents = 1,
1986			.flags = CLK_SET_RATE_PARENT,
1987			.ops = &clk_branch2_ops,
1988		},
1989	},
1990};
1991
1992static struct clk_branch cam_cc_cpas_sfe_2_clk = {
1993	.halt_reg = 0x13130,
1994	.halt_check = BRANCH_HALT,
1995	.clkr = {
1996		.enable_reg = 0x13130,
1997		.enable_mask = BIT(0),
1998		.hw.init = &(const struct clk_init_data) {
1999			.name = "cam_cc_cpas_sfe_2_clk",
2000			.parent_hws = (const struct clk_hw*[]) {
2001				&cam_cc_sfe_2_clk_src.clkr.hw,
2002			},
2003			.num_parents = 1,
2004			.flags = CLK_SET_RATE_PARENT,
2005			.ops = &clk_branch2_ops,
2006		},
2007	},
2008};
2009
2010static struct clk_branch cam_cc_cre_ahb_clk = {
2011	.halt_reg = 0x13164,
2012	.halt_check = BRANCH_HALT,
2013	.clkr = {
2014		.enable_reg = 0x13164,
2015		.enable_mask = BIT(0),
2016		.hw.init = &(const struct clk_init_data) {
2017			.name = "cam_cc_cre_ahb_clk",
2018			.parent_hws = (const struct clk_hw*[]) {
2019				&cam_cc_slow_ahb_clk_src.clkr.hw,
2020			},
2021			.num_parents = 1,
2022			.flags = CLK_SET_RATE_PARENT,
2023			.ops = &clk_branch2_ops,
2024		},
2025	},
2026};
2027
2028static struct clk_branch cam_cc_cre_clk = {
2029	.halt_reg = 0x1315c,
2030	.halt_check = BRANCH_HALT,
2031	.clkr = {
2032		.enable_reg = 0x1315c,
2033		.enable_mask = BIT(0),
2034		.hw.init = &(const struct clk_init_data) {
2035			.name = "cam_cc_cre_clk",
2036			.parent_hws = (const struct clk_hw*[]) {
2037				&cam_cc_cre_clk_src.clkr.hw,
2038			},
2039			.num_parents = 1,
2040			.flags = CLK_SET_RATE_PARENT,
2041			.ops = &clk_branch2_ops,
2042		},
2043	},
2044};
2045
2046static struct clk_branch cam_cc_csi0phytimer_clk = {
2047	.halt_reg = 0x150f8,
2048	.halt_check = BRANCH_HALT,
2049	.clkr = {
2050		.enable_reg = 0x150f8,
2051		.enable_mask = BIT(0),
2052		.hw.init = &(const struct clk_init_data) {
2053			.name = "cam_cc_csi0phytimer_clk",
2054			.parent_hws = (const struct clk_hw*[]) {
2055				&cam_cc_csi0phytimer_clk_src.clkr.hw,
2056			},
2057			.num_parents = 1,
2058			.flags = CLK_SET_RATE_PARENT,
2059			.ops = &clk_branch2_ops,
2060		},
2061	},
2062};
2063
2064static struct clk_branch cam_cc_csi1phytimer_clk = {
2065	.halt_reg = 0x1511c,
2066	.halt_check = BRANCH_HALT,
2067	.clkr = {
2068		.enable_reg = 0x1511c,
2069		.enable_mask = BIT(0),
2070		.hw.init = &(const struct clk_init_data) {
2071			.name = "cam_cc_csi1phytimer_clk",
2072			.parent_hws = (const struct clk_hw*[]) {
2073				&cam_cc_csi1phytimer_clk_src.clkr.hw,
2074			},
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch cam_cc_csi2phytimer_clk = {
2083	.halt_reg = 0x1513c,
2084	.halt_check = BRANCH_HALT,
2085	.clkr = {
2086		.enable_reg = 0x1513c,
2087		.enable_mask = BIT(0),
2088		.hw.init = &(const struct clk_init_data) {
2089			.name = "cam_cc_csi2phytimer_clk",
2090			.parent_hws = (const struct clk_hw*[]) {
2091				&cam_cc_csi2phytimer_clk_src.clkr.hw,
2092			},
2093			.num_parents = 1,
2094			.flags = CLK_SET_RATE_PARENT,
2095			.ops = &clk_branch2_ops,
2096		},
2097	},
2098};
2099
2100static struct clk_branch cam_cc_csi3phytimer_clk = {
2101	.halt_reg = 0x1515c,
2102	.halt_check = BRANCH_HALT,
2103	.clkr = {
2104		.enable_reg = 0x1515c,
2105		.enable_mask = BIT(0),
2106		.hw.init = &(const struct clk_init_data) {
2107			.name = "cam_cc_csi3phytimer_clk",
2108			.parent_hws = (const struct clk_hw*[]) {
2109				&cam_cc_csi3phytimer_clk_src.clkr.hw,
2110			},
2111			.num_parents = 1,
2112			.flags = CLK_SET_RATE_PARENT,
2113			.ops = &clk_branch2_ops,
2114		},
2115	},
2116};
2117
2118static struct clk_branch cam_cc_csi4phytimer_clk = {
2119	.halt_reg = 0x1517c,
2120	.halt_check = BRANCH_HALT,
2121	.clkr = {
2122		.enable_reg = 0x1517c,
2123		.enable_mask = BIT(0),
2124		.hw.init = &(const struct clk_init_data) {
2125			.name = "cam_cc_csi4phytimer_clk",
2126			.parent_hws = (const struct clk_hw*[]) {
2127				&cam_cc_csi4phytimer_clk_src.clkr.hw,
2128			},
2129			.num_parents = 1,
2130			.flags = CLK_SET_RATE_PARENT,
2131			.ops = &clk_branch2_ops,
2132		},
2133	},
2134};
2135
2136static struct clk_branch cam_cc_csi5phytimer_clk = {
2137	.halt_reg = 0x1519c,
2138	.halt_check = BRANCH_HALT,
2139	.clkr = {
2140		.enable_reg = 0x1519c,
2141		.enable_mask = BIT(0),
2142		.hw.init = &(const struct clk_init_data) {
2143			.name = "cam_cc_csi5phytimer_clk",
2144			.parent_hws = (const struct clk_hw*[]) {
2145				&cam_cc_csi5phytimer_clk_src.clkr.hw,
2146			},
2147			.num_parents = 1,
2148			.flags = CLK_SET_RATE_PARENT,
2149			.ops = &clk_branch2_ops,
2150		},
2151	},
2152};
2153
2154static struct clk_branch cam_cc_csi6phytimer_clk = {
2155	.halt_reg = 0x151bc,
2156	.halt_check = BRANCH_HALT,
2157	.clkr = {
2158		.enable_reg = 0x151bc,
2159		.enable_mask = BIT(0),
2160		.hw.init = &(const struct clk_init_data) {
2161			.name = "cam_cc_csi6phytimer_clk",
2162			.parent_hws = (const struct clk_hw*[]) {
2163				&cam_cc_csi6phytimer_clk_src.clkr.hw,
2164			},
2165			.num_parents = 1,
2166			.flags = CLK_SET_RATE_PARENT,
2167			.ops = &clk_branch2_ops,
2168		},
2169	},
2170};
2171
2172static struct clk_branch cam_cc_csi7phytimer_clk = {
2173	.halt_reg = 0x151dc,
2174	.halt_check = BRANCH_HALT,
2175	.clkr = {
2176		.enable_reg = 0x151dc,
2177		.enable_mask = BIT(0),
2178		.hw.init = &(const struct clk_init_data) {
2179			.name = "cam_cc_csi7phytimer_clk",
2180			.parent_hws = (const struct clk_hw*[]) {
2181				&cam_cc_csi7phytimer_clk_src.clkr.hw,
2182			},
2183			.num_parents = 1,
2184			.flags = CLK_SET_RATE_PARENT,
2185			.ops = &clk_branch2_ops,
2186		},
2187	},
2188};
2189
2190static struct clk_branch cam_cc_csid_clk = {
2191	.halt_reg = 0x13250,
2192	.halt_check = BRANCH_HALT,
2193	.clkr = {
2194		.enable_reg = 0x13250,
2195		.enable_mask = BIT(0),
2196		.hw.init = &(const struct clk_init_data) {
2197			.name = "cam_cc_csid_clk",
2198			.parent_hws = (const struct clk_hw*[]) {
2199				&cam_cc_csid_clk_src.clkr.hw,
2200			},
2201			.num_parents = 1,
2202			.flags = CLK_SET_RATE_PARENT,
2203			.ops = &clk_branch2_ops,
2204		},
2205	},
2206};
2207
2208static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
2209	.halt_reg = 0x15100,
2210	.halt_check = BRANCH_HALT,
2211	.clkr = {
2212		.enable_reg = 0x15100,
2213		.enable_mask = BIT(0),
2214		.hw.init = &(const struct clk_init_data) {
2215			.name = "cam_cc_csid_csiphy_rx_clk",
2216			.parent_hws = (const struct clk_hw*[]) {
2217				&cam_cc_cphy_rx_clk_src.clkr.hw,
2218			},
2219			.num_parents = 1,
2220			.flags = CLK_SET_RATE_PARENT,
2221			.ops = &clk_branch2_ops,
2222		},
2223	},
2224};
2225
2226static struct clk_branch cam_cc_csiphy0_clk = {
2227	.halt_reg = 0x150fc,
2228	.halt_check = BRANCH_HALT,
2229	.clkr = {
2230		.enable_reg = 0x150fc,
2231		.enable_mask = BIT(0),
2232		.hw.init = &(const struct clk_init_data) {
2233			.name = "cam_cc_csiphy0_clk",
2234			.parent_hws = (const struct clk_hw*[]) {
2235				&cam_cc_cphy_rx_clk_src.clkr.hw,
2236			},
2237			.num_parents = 1,
2238			.flags = CLK_SET_RATE_PARENT,
2239			.ops = &clk_branch2_ops,
2240		},
2241	},
2242};
2243
2244static struct clk_branch cam_cc_csiphy1_clk = {
2245	.halt_reg = 0x15120,
2246	.halt_check = BRANCH_HALT,
2247	.clkr = {
2248		.enable_reg = 0x15120,
2249		.enable_mask = BIT(0),
2250		.hw.init = &(const struct clk_init_data) {
2251			.name = "cam_cc_csiphy1_clk",
2252			.parent_hws = (const struct clk_hw*[]) {
2253				&cam_cc_cphy_rx_clk_src.clkr.hw,
2254			},
2255			.num_parents = 1,
2256			.flags = CLK_SET_RATE_PARENT,
2257			.ops = &clk_branch2_ops,
2258		},
2259	},
2260};
2261
2262static struct clk_branch cam_cc_csiphy2_clk = {
2263	.halt_reg = 0x15140,
2264	.halt_check = BRANCH_HALT,
2265	.clkr = {
2266		.enable_reg = 0x15140,
2267		.enable_mask = BIT(0),
2268		.hw.init = &(const struct clk_init_data) {
2269			.name = "cam_cc_csiphy2_clk",
2270			.parent_hws = (const struct clk_hw*[]) {
2271				&cam_cc_cphy_rx_clk_src.clkr.hw,
2272			},
2273			.num_parents = 1,
2274			.flags = CLK_SET_RATE_PARENT,
2275			.ops = &clk_branch2_ops,
2276		},
2277	},
2278};
2279
2280static struct clk_branch cam_cc_csiphy3_clk = {
2281	.halt_reg = 0x15160,
2282	.halt_check = BRANCH_HALT,
2283	.clkr = {
2284		.enable_reg = 0x15160,
2285		.enable_mask = BIT(0),
2286		.hw.init = &(const struct clk_init_data) {
2287			.name = "cam_cc_csiphy3_clk",
2288			.parent_hws = (const struct clk_hw*[]) {
2289				&cam_cc_cphy_rx_clk_src.clkr.hw,
2290			},
2291			.num_parents = 1,
2292			.flags = CLK_SET_RATE_PARENT,
2293			.ops = &clk_branch2_ops,
2294		},
2295	},
2296};
2297
2298static struct clk_branch cam_cc_csiphy4_clk = {
2299	.halt_reg = 0x15180,
2300	.halt_check = BRANCH_HALT,
2301	.clkr = {
2302		.enable_reg = 0x15180,
2303		.enable_mask = BIT(0),
2304		.hw.init = &(const struct clk_init_data) {
2305			.name = "cam_cc_csiphy4_clk",
2306			.parent_hws = (const struct clk_hw*[]) {
2307				&cam_cc_cphy_rx_clk_src.clkr.hw,
2308			},
2309			.num_parents = 1,
2310			.flags = CLK_SET_RATE_PARENT,
2311			.ops = &clk_branch2_ops,
2312		},
2313	},
2314};
2315
2316static struct clk_branch cam_cc_csiphy5_clk = {
2317	.halt_reg = 0x151a0,
2318	.halt_check = BRANCH_HALT,
2319	.clkr = {
2320		.enable_reg = 0x151a0,
2321		.enable_mask = BIT(0),
2322		.hw.init = &(const struct clk_init_data) {
2323			.name = "cam_cc_csiphy5_clk",
2324			.parent_hws = (const struct clk_hw*[]) {
2325				&cam_cc_cphy_rx_clk_src.clkr.hw,
2326			},
2327			.num_parents = 1,
2328			.flags = CLK_SET_RATE_PARENT,
2329			.ops = &clk_branch2_ops,
2330		},
2331	},
2332};
2333
2334static struct clk_branch cam_cc_csiphy6_clk = {
2335	.halt_reg = 0x151c0,
2336	.halt_check = BRANCH_HALT,
2337	.clkr = {
2338		.enable_reg = 0x151c0,
2339		.enable_mask = BIT(0),
2340		.hw.init = &(const struct clk_init_data) {
2341			.name = "cam_cc_csiphy6_clk",
2342			.parent_hws = (const struct clk_hw*[]) {
2343				&cam_cc_cphy_rx_clk_src.clkr.hw,
2344			},
2345			.num_parents = 1,
2346			.flags = CLK_SET_RATE_PARENT,
2347			.ops = &clk_branch2_ops,
2348		},
2349	},
2350};
2351
2352static struct clk_branch cam_cc_csiphy7_clk = {
2353	.halt_reg = 0x151e0,
2354	.halt_check = BRANCH_HALT,
2355	.clkr = {
2356		.enable_reg = 0x151e0,
2357		.enable_mask = BIT(0),
2358		.hw.init = &(const struct clk_init_data) {
2359			.name = "cam_cc_csiphy7_clk",
2360			.parent_hws = (const struct clk_hw*[]) {
2361				&cam_cc_cphy_rx_clk_src.clkr.hw,
2362			},
2363			.num_parents = 1,
2364			.flags = CLK_SET_RATE_PARENT,
2365			.ops = &clk_branch2_ops,
2366		},
2367	},
2368};
2369
2370static struct clk_branch cam_cc_icp_ahb_clk = {
2371	.halt_reg = 0x131c8,
2372	.halt_check = BRANCH_HALT,
2373	.clkr = {
2374		.enable_reg = 0x131c8,
2375		.enable_mask = BIT(0),
2376		.hw.init = &(const struct clk_init_data) {
2377			.name = "cam_cc_icp_ahb_clk",
2378			.parent_hws = (const struct clk_hw*[]) {
2379				&cam_cc_slow_ahb_clk_src.clkr.hw,
2380			},
2381			.num_parents = 1,
2382			.flags = CLK_SET_RATE_PARENT,
2383			.ops = &clk_branch2_ops,
2384		},
2385	},
2386};
2387
2388static struct clk_branch cam_cc_icp_clk = {
2389	.halt_reg = 0x131bc,
2390	.halt_check = BRANCH_HALT,
2391	.clkr = {
2392		.enable_reg = 0x131bc,
2393		.enable_mask = BIT(0),
2394		.hw.init = &(const struct clk_init_data) {
2395			.name = "cam_cc_icp_clk",
2396			.parent_hws = (const struct clk_hw*[]) {
2397				&cam_cc_icp_clk_src.clkr.hw,
2398			},
2399			.num_parents = 1,
2400			.flags = CLK_SET_RATE_PARENT,
2401			.ops = &clk_branch2_ops,
2402		},
2403	},
2404};
2405
2406static struct clk_branch cam_cc_ife_0_clk = {
2407	.halt_reg = 0x11030,
2408	.halt_check = BRANCH_HALT,
2409	.clkr = {
2410		.enable_reg = 0x11030,
2411		.enable_mask = BIT(0),
2412		.hw.init = &(const struct clk_init_data) {
2413			.name = "cam_cc_ife_0_clk",
2414			.parent_hws = (const struct clk_hw*[]) {
2415				&cam_cc_ife_0_clk_src.clkr.hw,
2416			},
2417			.num_parents = 1,
2418			.flags = CLK_SET_RATE_PARENT,
2419			.ops = &clk_branch2_ops,
2420		},
2421	},
2422};
2423
2424static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
2425	.halt_reg = 0x11048,
2426	.halt_check = BRANCH_HALT,
2427	.clkr = {
2428		.enable_reg = 0x11048,
2429		.enable_mask = BIT(0),
2430		.hw.init = &(const struct clk_init_data) {
2431			.name = "cam_cc_ife_0_fast_ahb_clk",
2432			.parent_hws = (const struct clk_hw*[]) {
2433				&cam_cc_fast_ahb_clk_src.clkr.hw,
2434			},
2435			.num_parents = 1,
2436			.flags = CLK_SET_RATE_PARENT,
2437			.ops = &clk_branch2_ops,
2438		},
2439	},
2440};
2441
2442static struct clk_branch cam_cc_ife_0_shift_clk = {
2443	.halt_reg = 0x11064,
2444	.halt_check = BRANCH_HALT_VOTED,
2445	.clkr = {
2446		.enable_reg = 0x11064,
2447		.enable_mask = BIT(0),
2448		.hw.init = &(const struct clk_init_data) {
2449			.name = "cam_cc_ife_0_shift_clk",
2450			.parent_hws = (const struct clk_hw*[]) {
2451				&cam_cc_xo_clk_src.clkr.hw,
2452			},
2453			.num_parents = 1,
2454			.flags = CLK_SET_RATE_PARENT,
2455			.ops = &clk_branch2_ops,
2456		},
2457	},
2458};
2459
2460static struct clk_branch cam_cc_ife_1_clk = {
2461	.halt_reg = 0x12030,
2462	.halt_check = BRANCH_HALT,
2463	.clkr = {
2464		.enable_reg = 0x12030,
2465		.enable_mask = BIT(0),
2466		.hw.init = &(const struct clk_init_data) {
2467			.name = "cam_cc_ife_1_clk",
2468			.parent_hws = (const struct clk_hw*[]) {
2469				&cam_cc_ife_1_clk_src.clkr.hw,
2470			},
2471			.num_parents = 1,
2472			.flags = CLK_SET_RATE_PARENT,
2473			.ops = &clk_branch2_ops,
2474		},
2475	},
2476};
2477
2478static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2479	.halt_reg = 0x12048,
2480	.halt_check = BRANCH_HALT,
2481	.clkr = {
2482		.enable_reg = 0x12048,
2483		.enable_mask = BIT(0),
2484		.hw.init = &(const struct clk_init_data) {
2485			.name = "cam_cc_ife_1_fast_ahb_clk",
2486			.parent_hws = (const struct clk_hw*[]) {
2487				&cam_cc_fast_ahb_clk_src.clkr.hw,
2488			},
2489			.num_parents = 1,
2490			.flags = CLK_SET_RATE_PARENT,
2491			.ops = &clk_branch2_ops,
2492		},
2493	},
2494};
2495
2496static struct clk_branch cam_cc_ife_1_shift_clk = {
2497	.halt_reg = 0x1204c,
2498	.halt_check = BRANCH_HALT_VOTED,
2499	.clkr = {
2500		.enable_reg = 0x1204c,
2501		.enable_mask = BIT(0),
2502		.hw.init = &(const struct clk_init_data) {
2503			.name = "cam_cc_ife_1_shift_clk",
2504			.parent_hws = (const struct clk_hw*[]) {
2505				&cam_cc_xo_clk_src.clkr.hw,
2506			},
2507			.num_parents = 1,
2508			.flags = CLK_SET_RATE_PARENT,
2509			.ops = &clk_branch2_ops,
2510		},
2511	},
2512};
2513
2514static struct clk_branch cam_cc_ife_2_clk = {
2515	.halt_reg = 0x12080,
2516	.halt_check = BRANCH_HALT,
2517	.clkr = {
2518		.enable_reg = 0x12080,
2519		.enable_mask = BIT(0),
2520		.hw.init = &(const struct clk_init_data) {
2521			.name = "cam_cc_ife_2_clk",
2522			.parent_hws = (const struct clk_hw*[]) {
2523				&cam_cc_ife_2_clk_src.clkr.hw,
2524			},
2525			.num_parents = 1,
2526			.flags = CLK_SET_RATE_PARENT,
2527			.ops = &clk_branch2_ops,
2528		},
2529	},
2530};
2531
2532static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2533	.halt_reg = 0x12098,
2534	.halt_check = BRANCH_HALT,
2535	.clkr = {
2536		.enable_reg = 0x12098,
2537		.enable_mask = BIT(0),
2538		.hw.init = &(const struct clk_init_data) {
2539			.name = "cam_cc_ife_2_fast_ahb_clk",
2540			.parent_hws = (const struct clk_hw*[]) {
2541				&cam_cc_fast_ahb_clk_src.clkr.hw,
2542			},
2543			.num_parents = 1,
2544			.flags = CLK_SET_RATE_PARENT,
2545			.ops = &clk_branch2_ops,
2546		},
2547	},
2548};
2549
2550static struct clk_branch cam_cc_ife_2_shift_clk = {
2551	.halt_reg = 0x1209c,
2552	.halt_check = BRANCH_HALT_VOTED,
2553	.clkr = {
2554		.enable_reg = 0x1209c,
2555		.enable_mask = BIT(0),
2556		.hw.init = &(const struct clk_init_data) {
2557			.name = "cam_cc_ife_2_shift_clk",
2558			.parent_hws = (const struct clk_hw*[]) {
2559				&cam_cc_xo_clk_src.clkr.hw,
2560			},
2561			.num_parents = 1,
2562			.flags = CLK_SET_RATE_PARENT,
2563			.ops = &clk_branch2_ops,
2564		},
2565	},
2566};
2567
2568static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2569	.halt_reg = 0x13050,
2570	.halt_check = BRANCH_HALT,
2571	.clkr = {
2572		.enable_reg = 0x13050,
2573		.enable_mask = BIT(0),
2574		.hw.init = &(const struct clk_init_data) {
2575			.name = "cam_cc_ife_lite_ahb_clk",
2576			.parent_hws = (const struct clk_hw*[]) {
2577				&cam_cc_slow_ahb_clk_src.clkr.hw,
2578			},
2579			.num_parents = 1,
2580			.flags = CLK_SET_RATE_PARENT,
2581			.ops = &clk_branch2_ops,
2582		},
2583	},
2584};
2585
2586static struct clk_branch cam_cc_ife_lite_clk = {
2587	.halt_reg = 0x13018,
2588	.halt_check = BRANCH_HALT,
2589	.clkr = {
2590		.enable_reg = 0x13018,
2591		.enable_mask = BIT(0),
2592		.hw.init = &(const struct clk_init_data) {
2593			.name = "cam_cc_ife_lite_clk",
2594			.parent_hws = (const struct clk_hw*[]) {
2595				&cam_cc_ife_lite_clk_src.clkr.hw,
2596			},
2597			.num_parents = 1,
2598			.flags = CLK_SET_RATE_PARENT,
2599			.ops = &clk_branch2_ops,
2600		},
2601	},
2602};
2603
2604static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2605	.halt_reg = 0x1304c,
2606	.halt_check = BRANCH_HALT,
2607	.clkr = {
2608		.enable_reg = 0x1304c,
2609		.enable_mask = BIT(0),
2610		.hw.init = &(const struct clk_init_data) {
2611			.name = "cam_cc_ife_lite_cphy_rx_clk",
2612			.parent_hws = (const struct clk_hw*[]) {
2613				&cam_cc_cphy_rx_clk_src.clkr.hw,
2614			},
2615			.num_parents = 1,
2616			.flags = CLK_SET_RATE_PARENT,
2617			.ops = &clk_branch2_ops,
2618		},
2619	},
2620};
2621
2622static struct clk_branch cam_cc_ife_lite_csid_clk = {
2623	.halt_reg = 0x13040,
2624	.halt_check = BRANCH_HALT,
2625	.clkr = {
2626		.enable_reg = 0x13040,
2627		.enable_mask = BIT(0),
2628		.hw.init = &(const struct clk_init_data) {
2629			.name = "cam_cc_ife_lite_csid_clk",
2630			.parent_hws = (const struct clk_hw*[]) {
2631				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
2632			},
2633			.num_parents = 1,
2634			.flags = CLK_SET_RATE_PARENT,
2635			.ops = &clk_branch2_ops,
2636		},
2637	},
2638};
2639
2640static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2641	.halt_reg = 0x100d0,
2642	.halt_check = BRANCH_HALT,
2643	.clkr = {
2644		.enable_reg = 0x100d0,
2645		.enable_mask = BIT(0),
2646		.hw.init = &(const struct clk_init_data) {
2647			.name = "cam_cc_ipe_nps_ahb_clk",
2648			.parent_hws = (const struct clk_hw*[]) {
2649				&cam_cc_slow_ahb_clk_src.clkr.hw,
2650			},
2651			.num_parents = 1,
2652			.flags = CLK_SET_RATE_PARENT,
2653			.ops = &clk_branch2_ops,
2654		},
2655	},
2656};
2657
2658static struct clk_branch cam_cc_ipe_nps_clk = {
2659	.halt_reg = 0x100ac,
2660	.halt_check = BRANCH_HALT,
2661	.clkr = {
2662		.enable_reg = 0x100ac,
2663		.enable_mask = BIT(0),
2664		.hw.init = &(const struct clk_init_data) {
2665			.name = "cam_cc_ipe_nps_clk",
2666			.parent_hws = (const struct clk_hw*[]) {
2667				&cam_cc_ipe_nps_clk_src.clkr.hw,
2668			},
2669			.num_parents = 1,
2670			.flags = CLK_SET_RATE_PARENT,
2671			.ops = &clk_branch2_ops,
2672		},
2673	},
2674};
2675
2676static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2677	.halt_reg = 0x100d4,
2678	.halt_check = BRANCH_HALT,
2679	.clkr = {
2680		.enable_reg = 0x100d4,
2681		.enable_mask = BIT(0),
2682		.hw.init = &(const struct clk_init_data) {
2683			.name = "cam_cc_ipe_nps_fast_ahb_clk",
2684			.parent_hws = (const struct clk_hw*[]) {
2685				&cam_cc_fast_ahb_clk_src.clkr.hw,
2686			},
2687			.num_parents = 1,
2688			.flags = CLK_SET_RATE_PARENT,
2689			.ops = &clk_branch2_ops,
2690		},
2691	},
2692};
2693
2694static struct clk_branch cam_cc_ipe_pps_clk = {
2695	.halt_reg = 0x100bc,
2696	.halt_check = BRANCH_HALT,
2697	.clkr = {
2698		.enable_reg = 0x100bc,
2699		.enable_mask = BIT(0),
2700		.hw.init = &(const struct clk_init_data) {
2701			.name = "cam_cc_ipe_pps_clk",
2702			.parent_hws = (const struct clk_hw*[]) {
2703				&cam_cc_ipe_nps_clk_src.clkr.hw,
2704			},
2705			.num_parents = 1,
2706			.flags = CLK_SET_RATE_PARENT,
2707			.ops = &clk_branch2_ops,
2708		},
2709	},
2710};
2711
2712static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2713	.halt_reg = 0x100d8,
2714	.halt_check = BRANCH_HALT,
2715	.clkr = {
2716		.enable_reg = 0x100d8,
2717		.enable_mask = BIT(0),
2718		.hw.init = &(const struct clk_init_data) {
2719			.name = "cam_cc_ipe_pps_fast_ahb_clk",
2720			.parent_hws = (const struct clk_hw*[]) {
2721				&cam_cc_fast_ahb_clk_src.clkr.hw,
2722			},
2723			.num_parents = 1,
2724			.flags = CLK_SET_RATE_PARENT,
2725			.ops = &clk_branch2_ops,
2726		},
2727	},
2728};
2729
2730static struct clk_branch cam_cc_ipe_shift_clk = {
2731	.halt_reg = 0x100dc,
2732	.halt_check = BRANCH_HALT_VOTED,
2733	.clkr = {
2734		.enable_reg = 0x100dc,
2735		.enable_mask = BIT(0),
2736		.hw.init = &(const struct clk_init_data) {
2737			.name = "cam_cc_ipe_shift_clk",
2738			.parent_hws = (const struct clk_hw*[]) {
2739				&cam_cc_xo_clk_src.clkr.hw,
2740			},
2741			.num_parents = 1,
2742			.flags = CLK_SET_RATE_PARENT,
2743			.ops = &clk_branch2_ops,
2744		},
2745	},
2746};
2747
2748static struct clk_branch cam_cc_jpeg_1_clk = {
2749	.halt_reg = 0x1318c,
2750	.halt_check = BRANCH_HALT,
2751	.clkr = {
2752		.enable_reg = 0x1318c,
2753		.enable_mask = BIT(0),
2754		.hw.init = &(const struct clk_init_data) {
2755			.name = "cam_cc_jpeg_1_clk",
2756			.parent_hws = (const struct clk_hw*[]) {
2757				&cam_cc_jpeg_clk_src.clkr.hw,
2758			},
2759			.num_parents = 1,
2760			.flags = CLK_SET_RATE_PARENT,
2761			.ops = &clk_branch2_ops,
2762		},
2763	},
2764};
2765
2766static struct clk_branch cam_cc_jpeg_clk = {
2767	.halt_reg = 0x13180,
2768	.halt_check = BRANCH_HALT,
2769	.clkr = {
2770		.enable_reg = 0x13180,
2771		.enable_mask = BIT(0),
2772		.hw.init = &(const struct clk_init_data) {
2773			.name = "cam_cc_jpeg_clk",
2774			.parent_hws = (const struct clk_hw*[]) {
2775				&cam_cc_jpeg_clk_src.clkr.hw,
2776			},
2777			.num_parents = 1,
2778			.flags = CLK_SET_RATE_PARENT,
2779			.ops = &clk_branch2_ops,
2780		},
2781	},
2782};
2783
2784static struct clk_branch cam_cc_mclk0_clk = {
2785	.halt_reg = 0x15018,
2786	.halt_check = BRANCH_HALT,
2787	.clkr = {
2788		.enable_reg = 0x15018,
2789		.enable_mask = BIT(0),
2790		.hw.init = &(const struct clk_init_data) {
2791			.name = "cam_cc_mclk0_clk",
2792			.parent_hws = (const struct clk_hw*[]) {
2793				&cam_cc_mclk0_clk_src.clkr.hw,
2794			},
2795			.num_parents = 1,
2796			.flags = CLK_SET_RATE_PARENT,
2797			.ops = &clk_branch2_ops,
2798		},
2799	},
2800};
2801
2802static struct clk_branch cam_cc_mclk1_clk = {
2803	.halt_reg = 0x15034,
2804	.halt_check = BRANCH_HALT,
2805	.clkr = {
2806		.enable_reg = 0x15034,
2807		.enable_mask = BIT(0),
2808		.hw.init = &(const struct clk_init_data) {
2809			.name = "cam_cc_mclk1_clk",
2810			.parent_hws = (const struct clk_hw*[]) {
2811				&cam_cc_mclk1_clk_src.clkr.hw,
2812			},
2813			.num_parents = 1,
2814			.flags = CLK_SET_RATE_PARENT,
2815			.ops = &clk_branch2_ops,
2816		},
2817	},
2818};
2819
2820static struct clk_branch cam_cc_mclk2_clk = {
2821	.halt_reg = 0x15050,
2822	.halt_check = BRANCH_HALT,
2823	.clkr = {
2824		.enable_reg = 0x15050,
2825		.enable_mask = BIT(0),
2826		.hw.init = &(const struct clk_init_data) {
2827			.name = "cam_cc_mclk2_clk",
2828			.parent_hws = (const struct clk_hw*[]) {
2829				&cam_cc_mclk2_clk_src.clkr.hw,
2830			},
2831			.num_parents = 1,
2832			.flags = CLK_SET_RATE_PARENT,
2833			.ops = &clk_branch2_ops,
2834		},
2835	},
2836};
2837
2838static struct clk_branch cam_cc_mclk3_clk = {
2839	.halt_reg = 0x1506c,
2840	.halt_check = BRANCH_HALT,
2841	.clkr = {
2842		.enable_reg = 0x1506c,
2843		.enable_mask = BIT(0),
2844		.hw.init = &(const struct clk_init_data) {
2845			.name = "cam_cc_mclk3_clk",
2846			.parent_hws = (const struct clk_hw*[]) {
2847				&cam_cc_mclk3_clk_src.clkr.hw,
2848			},
2849			.num_parents = 1,
2850			.flags = CLK_SET_RATE_PARENT,
2851			.ops = &clk_branch2_ops,
2852		},
2853	},
2854};
2855
2856static struct clk_branch cam_cc_mclk4_clk = {
2857	.halt_reg = 0x15088,
2858	.halt_check = BRANCH_HALT,
2859	.clkr = {
2860		.enable_reg = 0x15088,
2861		.enable_mask = BIT(0),
2862		.hw.init = &(const struct clk_init_data) {
2863			.name = "cam_cc_mclk4_clk",
2864			.parent_hws = (const struct clk_hw*[]) {
2865				&cam_cc_mclk4_clk_src.clkr.hw,
2866			},
2867			.num_parents = 1,
2868			.flags = CLK_SET_RATE_PARENT,
2869			.ops = &clk_branch2_ops,
2870		},
2871	},
2872};
2873
2874static struct clk_branch cam_cc_mclk5_clk = {
2875	.halt_reg = 0x150a4,
2876	.halt_check = BRANCH_HALT,
2877	.clkr = {
2878		.enable_reg = 0x150a4,
2879		.enable_mask = BIT(0),
2880		.hw.init = &(const struct clk_init_data) {
2881			.name = "cam_cc_mclk5_clk",
2882			.parent_hws = (const struct clk_hw*[]) {
2883				&cam_cc_mclk5_clk_src.clkr.hw,
2884			},
2885			.num_parents = 1,
2886			.flags = CLK_SET_RATE_PARENT,
2887			.ops = &clk_branch2_ops,
2888		},
2889	},
2890};
2891
2892static struct clk_branch cam_cc_mclk6_clk = {
2893	.halt_reg = 0x150c0,
2894	.halt_check = BRANCH_HALT,
2895	.clkr = {
2896		.enable_reg = 0x150c0,
2897		.enable_mask = BIT(0),
2898		.hw.init = &(const struct clk_init_data) {
2899			.name = "cam_cc_mclk6_clk",
2900			.parent_hws = (const struct clk_hw*[]) {
2901				&cam_cc_mclk6_clk_src.clkr.hw,
2902			},
2903			.num_parents = 1,
2904			.flags = CLK_SET_RATE_PARENT,
2905			.ops = &clk_branch2_ops,
2906		},
2907	},
2908};
2909
2910static struct clk_branch cam_cc_mclk7_clk = {
2911	.halt_reg = 0x150dc,
2912	.halt_check = BRANCH_HALT,
2913	.clkr = {
2914		.enable_reg = 0x150dc,
2915		.enable_mask = BIT(0),
2916		.hw.init = &(const struct clk_init_data) {
2917			.name = "cam_cc_mclk7_clk",
2918			.parent_hws = (const struct clk_hw*[]) {
2919				&cam_cc_mclk7_clk_src.clkr.hw,
2920			},
2921			.num_parents = 1,
2922			.flags = CLK_SET_RATE_PARENT,
2923			.ops = &clk_branch2_ops,
2924		},
2925	},
2926};
2927
2928static struct clk_branch cam_cc_qdss_debug_clk = {
2929	.halt_reg = 0x132b4,
2930	.halt_check = BRANCH_HALT,
2931	.clkr = {
2932		.enable_reg = 0x132b4,
2933		.enable_mask = BIT(0),
2934		.hw.init = &(const struct clk_init_data) {
2935			.name = "cam_cc_qdss_debug_clk",
2936			.parent_hws = (const struct clk_hw*[]) {
2937				&cam_cc_qdss_debug_clk_src.clkr.hw,
2938			},
2939			.num_parents = 1,
2940			.flags = CLK_SET_RATE_PARENT,
2941			.ops = &clk_branch2_ops,
2942		},
2943	},
2944};
2945
2946static struct clk_branch cam_cc_qdss_debug_xo_clk = {
2947	.halt_reg = 0x132b8,
2948	.halt_check = BRANCH_HALT,
2949	.clkr = {
2950		.enable_reg = 0x132b8,
2951		.enable_mask = BIT(0),
2952		.hw.init = &(const struct clk_init_data) {
2953			.name = "cam_cc_qdss_debug_xo_clk",
2954			.parent_hws = (const struct clk_hw*[]) {
2955				&cam_cc_xo_clk_src.clkr.hw,
2956			},
2957			.num_parents = 1,
2958			.flags = CLK_SET_RATE_PARENT,
2959			.ops = &clk_branch2_ops,
2960		},
2961	},
2962};
2963
2964static struct clk_branch cam_cc_sbi_clk = {
2965	.halt_reg = 0x100f8,
2966	.halt_check = BRANCH_HALT,
2967	.clkr = {
2968		.enable_reg = 0x100f8,
2969		.enable_mask = BIT(0),
2970		.hw.init = &(const struct clk_init_data) {
2971			.name = "cam_cc_sbi_clk",
2972			.parent_hws = (const struct clk_hw*[]) {
2973				&cam_cc_ife_0_clk_src.clkr.hw,
2974			},
2975			.num_parents = 1,
2976			.flags = CLK_SET_RATE_PARENT,
2977			.ops = &clk_branch2_ops,
2978		},
2979	},
2980};
2981
2982static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
2983	.halt_reg = 0x10108,
2984	.halt_check = BRANCH_HALT,
2985	.clkr = {
2986		.enable_reg = 0x10108,
2987		.enable_mask = BIT(0),
2988		.hw.init = &(const struct clk_init_data) {
2989			.name = "cam_cc_sbi_fast_ahb_clk",
2990			.parent_hws = (const struct clk_hw*[]) {
2991				&cam_cc_fast_ahb_clk_src.clkr.hw,
2992			},
2993			.num_parents = 1,
2994			.flags = CLK_SET_RATE_PARENT,
2995			.ops = &clk_branch2_ops,
2996		},
2997	},
2998};
2999
3000static struct clk_branch cam_cc_sbi_shift_clk = {
3001	.halt_reg = 0x1010c,
3002	.halt_check = BRANCH_HALT_VOTED,
3003	.clkr = {
3004		.enable_reg = 0x1010c,
3005		.enable_mask = BIT(0),
3006		.hw.init = &(const struct clk_init_data) {
3007			.name = "cam_cc_sbi_shift_clk",
3008			.parent_hws = (const struct clk_hw*[]) {
3009				&cam_cc_xo_clk_src.clkr.hw,
3010			},
3011			.num_parents = 1,
3012			.flags = CLK_SET_RATE_PARENT,
3013			.ops = &clk_branch2_ops,
3014		},
3015	},
3016};
3017
3018static struct clk_branch cam_cc_sfe_0_clk = {
3019	.halt_reg = 0x13084,
3020	.halt_check = BRANCH_HALT,
3021	.clkr = {
3022		.enable_reg = 0x13084,
3023		.enable_mask = BIT(0),
3024		.hw.init = &(const struct clk_init_data) {
3025			.name = "cam_cc_sfe_0_clk",
3026			.parent_hws = (const struct clk_hw*[]) {
3027				&cam_cc_sfe_0_clk_src.clkr.hw,
3028			},
3029			.num_parents = 1,
3030			.flags = CLK_SET_RATE_PARENT,
3031			.ops = &clk_branch2_ops,
3032		},
3033	},
3034};
3035
3036static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
3037	.halt_reg = 0x1309c,
3038	.halt_check = BRANCH_HALT,
3039	.clkr = {
3040		.enable_reg = 0x1309c,
3041		.enable_mask = BIT(0),
3042		.hw.init = &(const struct clk_init_data) {
3043			.name = "cam_cc_sfe_0_fast_ahb_clk",
3044			.parent_hws = (const struct clk_hw*[]) {
3045				&cam_cc_fast_ahb_clk_src.clkr.hw,
3046			},
3047			.num_parents = 1,
3048			.flags = CLK_SET_RATE_PARENT,
3049			.ops = &clk_branch2_ops,
3050		},
3051	},
3052};
3053
3054static struct clk_branch cam_cc_sfe_0_shift_clk = {
3055	.halt_reg = 0x130a0,
3056	.halt_check = BRANCH_HALT_VOTED,
3057	.clkr = {
3058		.enable_reg = 0x130a0,
3059		.enable_mask = BIT(0),
3060		.hw.init = &(const struct clk_init_data) {
3061			.name = "cam_cc_sfe_0_shift_clk",
3062			.parent_hws = (const struct clk_hw*[]) {
3063				&cam_cc_xo_clk_src.clkr.hw,
3064			},
3065			.num_parents = 1,
3066			.flags = CLK_SET_RATE_PARENT,
3067			.ops = &clk_branch2_ops,
3068		},
3069	},
3070};
3071
3072static struct clk_branch cam_cc_sfe_1_clk = {
3073	.halt_reg = 0x130d4,
3074	.halt_check = BRANCH_HALT,
3075	.clkr = {
3076		.enable_reg = 0x130d4,
3077		.enable_mask = BIT(0),
3078		.hw.init = &(const struct clk_init_data) {
3079			.name = "cam_cc_sfe_1_clk",
3080			.parent_hws = (const struct clk_hw*[]) {
3081				&cam_cc_sfe_1_clk_src.clkr.hw,
3082			},
3083			.num_parents = 1,
3084			.flags = CLK_SET_RATE_PARENT,
3085			.ops = &clk_branch2_ops,
3086		},
3087	},
3088};
3089
3090static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
3091	.halt_reg = 0x130ec,
3092	.halt_check = BRANCH_HALT,
3093	.clkr = {
3094		.enable_reg = 0x130ec,
3095		.enable_mask = BIT(0),
3096		.hw.init = &(const struct clk_init_data) {
3097			.name = "cam_cc_sfe_1_fast_ahb_clk",
3098			.parent_hws = (const struct clk_hw*[]) {
3099				&cam_cc_fast_ahb_clk_src.clkr.hw,
3100			},
3101			.num_parents = 1,
3102			.flags = CLK_SET_RATE_PARENT,
3103			.ops = &clk_branch2_ops,
3104		},
3105	},
3106};
3107
3108static struct clk_branch cam_cc_sfe_1_shift_clk = {
3109	.halt_reg = 0x130f0,
3110	.halt_check = BRANCH_HALT_VOTED,
3111	.clkr = {
3112		.enable_reg = 0x130f0,
3113		.enable_mask = BIT(0),
3114		.hw.init = &(const struct clk_init_data) {
3115			.name = "cam_cc_sfe_1_shift_clk",
3116			.parent_hws = (const struct clk_hw*[]) {
3117				&cam_cc_xo_clk_src.clkr.hw,
3118			},
3119			.num_parents = 1,
3120			.flags = CLK_SET_RATE_PARENT,
3121			.ops = &clk_branch2_ops,
3122		},
3123	},
3124};
3125
3126static struct clk_branch cam_cc_sfe_2_clk = {
3127	.halt_reg = 0x13124,
3128	.halt_check = BRANCH_HALT,
3129	.clkr = {
3130		.enable_reg = 0x13124,
3131		.enable_mask = BIT(0),
3132		.hw.init = &(const struct clk_init_data) {
3133			.name = "cam_cc_sfe_2_clk",
3134			.parent_hws = (const struct clk_hw*[]) {
3135				&cam_cc_sfe_2_clk_src.clkr.hw,
3136			},
3137			.num_parents = 1,
3138			.flags = CLK_SET_RATE_PARENT,
3139			.ops = &clk_branch2_ops,
3140		},
3141	},
3142};
3143
3144static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = {
3145	.halt_reg = 0x1313c,
3146	.halt_check = BRANCH_HALT,
3147	.clkr = {
3148		.enable_reg = 0x1313c,
3149		.enable_mask = BIT(0),
3150		.hw.init = &(const struct clk_init_data) {
3151			.name = "cam_cc_sfe_2_fast_ahb_clk",
3152			.parent_hws = (const struct clk_hw*[]) {
3153				&cam_cc_fast_ahb_clk_src.clkr.hw,
3154			},
3155			.num_parents = 1,
3156			.flags = CLK_SET_RATE_PARENT,
3157			.ops = &clk_branch2_ops,
3158		},
3159	},
3160};
3161
3162static struct clk_branch cam_cc_sfe_2_shift_clk = {
3163	.halt_reg = 0x13140,
3164	.halt_check = BRANCH_HALT_VOTED,
3165	.clkr = {
3166		.enable_reg = 0x13140,
3167		.enable_mask = BIT(0),
3168		.hw.init = &(const struct clk_init_data) {
3169			.name = "cam_cc_sfe_2_shift_clk",
3170			.parent_hws = (const struct clk_hw*[]) {
3171				&cam_cc_xo_clk_src.clkr.hw,
3172			},
3173			.num_parents = 1,
3174			.flags = CLK_SET_RATE_PARENT,
3175			.ops = &clk_branch2_ops,
3176		},
3177	},
3178};
3179
3180static struct clk_branch cam_cc_titan_top_shift_clk = {
3181	.halt_reg = 0x1330c,
3182	.halt_check = BRANCH_HALT_VOTED,
3183	.clkr = {
3184		.enable_reg = 0x1330c,
3185		.enable_mask = BIT(0),
3186		.hw.init = &(const struct clk_init_data) {
3187			.name = "cam_cc_titan_top_shift_clk",
3188			.parent_hws = (const struct clk_hw*[]) {
3189				&cam_cc_xo_clk_src.clkr.hw,
3190			},
3191			.num_parents = 1,
3192			.flags = CLK_SET_RATE_PARENT,
3193			.ops = &clk_branch2_ops,
3194		},
3195	},
3196};
3197
3198static struct gdsc cam_cc_titan_top_gdsc = {
3199	.gdscr = 0x132bc,
3200	.en_rest_wait_val = 0x2,
3201	.en_few_wait_val = 0x2,
3202	.clk_dis_wait_val = 0xf,
3203	.pd = {
3204		.name = "cam_cc_titan_top_gdsc",
3205	},
3206	.pwrsts = PWRSTS_OFF_ON,
3207	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3208};
3209
3210static struct gdsc cam_cc_bps_gdsc = {
3211	.gdscr = 0x10004,
3212	.en_rest_wait_val = 0x2,
3213	.en_few_wait_val = 0x2,
3214	.clk_dis_wait_val = 0xf,
3215	.pd = {
3216		.name = "cam_cc_bps_gdsc",
3217	},
3218	.pwrsts = PWRSTS_OFF_ON,
3219	.parent = &cam_cc_titan_top_gdsc.pd,
3220	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3221};
3222
3223static struct gdsc cam_cc_ife_0_gdsc = {
3224	.gdscr = 0x11004,
3225	.en_rest_wait_val = 0x2,
3226	.en_few_wait_val = 0x2,
3227	.clk_dis_wait_val = 0xf,
3228	.pd = {
3229		.name = "cam_cc_ife_0_gdsc",
3230	},
3231	.pwrsts = PWRSTS_OFF_ON,
3232	.parent = &cam_cc_titan_top_gdsc.pd,
3233	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3234};
3235
3236static struct gdsc cam_cc_ife_1_gdsc = {
3237	.gdscr = 0x12004,
3238	.en_rest_wait_val = 0x2,
3239	.en_few_wait_val = 0x2,
3240	.clk_dis_wait_val = 0xf,
3241	.pd = {
3242		.name = "cam_cc_ife_1_gdsc",
3243	},
3244	.pwrsts = PWRSTS_OFF_ON,
3245	.parent = &cam_cc_titan_top_gdsc.pd,
3246	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3247};
3248
3249static struct gdsc cam_cc_ife_2_gdsc = {
3250	.gdscr = 0x12054,
3251	.en_rest_wait_val = 0x2,
3252	.en_few_wait_val = 0x2,
3253	.clk_dis_wait_val = 0xf,
3254	.pd = {
3255		.name = "cam_cc_ife_2_gdsc",
3256	},
3257	.pwrsts = PWRSTS_OFF_ON,
3258	.parent = &cam_cc_titan_top_gdsc.pd,
3259	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3260};
3261
3262static struct gdsc cam_cc_ipe_0_gdsc = {
3263	.gdscr = 0x10080,
3264	.en_rest_wait_val = 0x2,
3265	.en_few_wait_val = 0x2,
3266	.clk_dis_wait_val = 0xf,
3267	.pd = {
3268		.name = "cam_cc_ipe_0_gdsc",
3269	},
3270	.pwrsts = PWRSTS_OFF_ON,
3271	.parent = &cam_cc_titan_top_gdsc.pd,
3272	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3273};
3274
3275static struct gdsc cam_cc_sbi_gdsc = {
3276	.gdscr = 0x100e4,
3277	.en_rest_wait_val = 0x2,
3278	.en_few_wait_val = 0x2,
3279	.clk_dis_wait_val = 0xf,
3280	.pd = {
3281		.name = "cam_cc_sbi_gdsc",
3282	},
3283	.pwrsts = PWRSTS_OFF_ON,
3284	.parent = &cam_cc_titan_top_gdsc.pd,
3285	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3286};
3287
3288static struct gdsc cam_cc_sfe_0_gdsc = {
3289	.gdscr = 0x13058,
3290	.en_rest_wait_val = 0x2,
3291	.en_few_wait_val = 0x2,
3292	.clk_dis_wait_val = 0xf,
3293	.pd = {
3294		.name = "cam_cc_sfe_0_gdsc",
3295	},
3296	.pwrsts = PWRSTS_OFF_ON,
3297	.parent = &cam_cc_titan_top_gdsc.pd,
3298	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3299};
3300
3301static struct gdsc cam_cc_sfe_1_gdsc = {
3302	.gdscr = 0x130a8,
3303	.en_rest_wait_val = 0x2,
3304	.en_few_wait_val = 0x2,
3305	.clk_dis_wait_val = 0xf,
3306	.pd = {
3307		.name = "cam_cc_sfe_1_gdsc",
3308	},
3309	.pwrsts = PWRSTS_OFF_ON,
3310	.parent = &cam_cc_titan_top_gdsc.pd,
3311	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3312};
3313
3314static struct gdsc cam_cc_sfe_2_gdsc = {
3315	.gdscr = 0x130f8,
3316	.en_rest_wait_val = 0x2,
3317	.en_few_wait_val = 0x2,
3318	.clk_dis_wait_val = 0xf,
3319	.pd = {
3320		.name = "cam_cc_sfe_2_gdsc",
3321	},
3322	.pwrsts = PWRSTS_OFF_ON,
3323	.parent = &cam_cc_titan_top_gdsc.pd,
3324	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3325};
3326
3327static struct clk_regmap *cam_cc_sm8650_clocks[] = {
3328	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
3329	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
3330	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
3331	[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
3332	[CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr,
3333	[CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr,
3334	[CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr,
3335	[CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr,
3336	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
3337	[CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
3338	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
3339	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
3340	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
3341	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
3342	[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
3343	[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
3344	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
3345	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
3346	[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
3347	[CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
3348	[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
3349	[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
3350	[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
3351	[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
3352	[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
3353	[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
3354	[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
3355	[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
3356	[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
3357	[CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr,
3358	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
3359	[CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
3360	[CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
3361	[CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
3362	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
3363	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
3364	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
3365	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
3366	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
3367	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
3368	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
3369	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
3370	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
3371	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
3372	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
3373	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
3374	[CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
3375	[CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
3376	[CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
3377	[CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
3378	[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
3379	[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
3380	[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
3381	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
3382	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
3383	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
3384	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
3385	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
3386	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
3387	[CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
3388	[CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
3389	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
3390	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
3391	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
3392	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
3393	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
3394	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
3395	[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
3396	[CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr,
3397	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
3398	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
3399	[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
3400	[CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr,
3401	[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
3402	[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
3403	[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
3404	[CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr,
3405	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
3406	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
3407	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
3408	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
3409	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
3410	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
3411	[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
3412	[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
3413	[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
3414	[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
3415	[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
3416	[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
3417	[CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr,
3418	[CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
3419	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
3420	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
3421	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
3422	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
3423	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
3424	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
3425	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
3426	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
3427	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
3428	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
3429	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
3430	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
3431	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
3432	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
3433	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
3434	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
3435	[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
3436	[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
3437	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
3438	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
3439	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
3440	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
3441	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
3442	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
3443	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
3444	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
3445	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
3446	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
3447	[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
3448	[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
3449	[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
3450	[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
3451	[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
3452	[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
3453	[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
3454	[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
3455	[CAM_CC_PLL9] = &cam_cc_pll9.clkr,
3456	[CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
3457	[CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr,
3458	[CAM_CC_PLL10] = &cam_cc_pll10.clkr,
3459	[CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
3460	[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
3461	[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
3462	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
3463	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
3464	[CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
3465	[CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr,
3466	[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
3467	[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
3468	[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
3469	[CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr,
3470	[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
3471	[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
3472	[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
3473	[CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr,
3474	[CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr,
3475	[CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr,
3476	[CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr,
3477	[CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr,
3478	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
3479	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
3480	[CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr,
3481	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
3482};
3483
3484static struct gdsc *cam_cc_sm8650_gdscs[] = {
3485	[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
3486	[CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
3487	[CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
3488	[CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
3489	[CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
3490	[CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
3491	[CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
3492	[CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
3493	[CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
3494	[CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc,
3495};
3496
3497static const struct qcom_reset_map cam_cc_sm8650_resets[] = {
3498	[CAM_CC_BPS_BCR] = { 0x10000 },
3499	[CAM_CC_DRV_BCR] = { 0x13310 },
3500	[CAM_CC_ICP_BCR] = { 0x131a0 },
3501	[CAM_CC_IFE_0_BCR] = { 0x11000 },
3502	[CAM_CC_IFE_1_BCR] = { 0x12000 },
3503	[CAM_CC_IFE_2_BCR] = { 0x12050 },
3504	[CAM_CC_IPE_0_BCR] = { 0x1007c },
3505	[CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 },
3506	[CAM_CC_SBI_BCR] = { 0x100e0 },
3507	[CAM_CC_SFE_0_BCR] = { 0x13054 },
3508	[CAM_CC_SFE_1_BCR] = { 0x130a4 },
3509	[CAM_CC_SFE_2_BCR] = { 0x130f4 },
3510};
3511
3512static const struct regmap_config cam_cc_sm8650_regmap_config = {
3513	.reg_bits = 32,
3514	.reg_stride = 4,
3515	.val_bits = 32,
3516	.max_register = 0x1603c,
3517	.fast_io = true,
3518};
3519
3520static struct qcom_cc_desc cam_cc_sm8650_desc = {
3521	.config = &cam_cc_sm8650_regmap_config,
3522	.clks = cam_cc_sm8650_clocks,
3523	.num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks),
3524	.resets = cam_cc_sm8650_resets,
3525	.num_resets = ARRAY_SIZE(cam_cc_sm8650_resets),
3526	.gdscs = cam_cc_sm8650_gdscs,
3527	.num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs),
3528};
3529
3530static const struct of_device_id cam_cc_sm8650_match_table[] = {
3531	{ .compatible = "qcom,sm8650-camcc" },
3532	{ }
3533};
3534MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table);
3535
3536static int cam_cc_sm8650_probe(struct platform_device *pdev)
3537{
3538	struct regmap *regmap;
3539	int ret;
3540
3541	ret = devm_pm_runtime_enable(&pdev->dev);
3542	if (ret)
3543		return ret;
3544
3545	ret = pm_runtime_resume_and_get(&pdev->dev);
3546	if (ret)
3547		return ret;
3548
3549	regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc);
3550	if (IS_ERR(regmap)) {
3551		pm_runtime_put(&pdev->dev);
3552		return PTR_ERR(regmap);
3553	}
3554
3555	clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
3556	clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
3557	clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
3558	clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
3559	clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
3560	clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
3561	clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
3562	clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
3563	clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
3564	clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config);
3565	clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config);
3566
3567	/* Keep clocks always enabled */
3568	qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */
3569	qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */
3570	qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */
3571	qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */
3572
3573	ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap);
3574
3575	pm_runtime_put(&pdev->dev);
3576
3577	return ret;
3578}
3579
3580static struct platform_driver cam_cc_sm8650_driver = {
3581	.probe = cam_cc_sm8650_probe,
3582	.driver = {
3583		.name = "camcc-sm8650",
3584		.of_match_table = cam_cc_sm8650_match_table,
3585	},
3586};
3587
3588module_platform_driver(cam_cc_sm8650_driver);
3589
3590MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver");
3591MODULE_LICENSE("GPL");