1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,sm8450-camcc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-pll.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "clk-regmap.h"
  21#include "common.h"
  22#include "gdsc.h"
  23#include "reset.h"
  24
  25enum {
  26	DT_IFACE,
  27	DT_BI_TCXO,
  28	DT_BI_TCXO_AO,
  29	DT_SLEEP_CLK
  30};
  31
  32enum {
  33	P_BI_TCXO,
  34	P_CAM_CC_PLL0_OUT_EVEN,
  35	P_CAM_CC_PLL0_OUT_MAIN,
  36	P_CAM_CC_PLL0_OUT_ODD,
  37	P_CAM_CC_PLL1_OUT_EVEN,
  38	P_CAM_CC_PLL2_OUT_EVEN,
  39	P_CAM_CC_PLL2_OUT_MAIN,
  40	P_CAM_CC_PLL3_OUT_EVEN,
  41	P_CAM_CC_PLL4_OUT_EVEN,
  42	P_CAM_CC_PLL5_OUT_EVEN,
  43	P_CAM_CC_PLL6_OUT_EVEN,
  44	P_CAM_CC_PLL7_OUT_EVEN,
  45	P_CAM_CC_PLL8_OUT_EVEN,
  46	P_SLEEP_CLK,
  47};
  48
  49static const struct pll_vco lucid_evo_vco[] = {
  50	{ 249600000, 2000000000, 0 },
  51};
  52
  53static const struct pll_vco rivian_evo_vco[] = {
  54	{ 864000000, 1056000000, 0 },
  55};
  56
  57static const struct pll_vco rivian_ole_vco[] = {
  58	{ 864000000, 1075000000, 0 },
  59};
  60
  61static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
  62
  63static const struct alpha_pll_config cam_cc_pll0_config = {
  64	.l = 0x3e,
  65	.alpha = 0x8000,
  66	.config_ctl_val = 0x20485699,
  67	.config_ctl_hi_val = 0x00182261,
  68	.config_ctl_hi1_val = 0x32aa299c,
  69	.user_ctl_val = 0x00008400,
  70	.user_ctl_hi_val = 0x00000805,
  71};
  72
  73static const struct alpha_pll_config sm8475_cam_cc_pll0_config = {
  74	.l = 0x3e,
  75	.alpha = 0x8000,
  76	.config_ctl_val = 0x20485699,
  77	.config_ctl_hi_val = 0x00182261,
  78	.config_ctl_hi1_val = 0x82aa299c,
  79	.test_ctl_val = 0x00000000,
  80	.test_ctl_hi_val = 0x00000003,
  81	.test_ctl_hi1_val = 0x00009000,
  82	.test_ctl_hi2_val = 0x00000034,
  83	.user_ctl_val = 0x00008400,
  84	.user_ctl_hi_val = 0x00000005,
  85};
  86
  87static struct clk_alpha_pll cam_cc_pll0 = {
  88	.offset = 0x0,
  89	.vco_table = lucid_evo_vco,
  90	.num_vco = ARRAY_SIZE(lucid_evo_vco),
  91	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  92	.clkr = {
  93		.hw.init = &(const struct clk_init_data) {
  94			.name = "cam_cc_pll0",
  95			.parent_data = &pll_parent_data_tcxo,
  96			.num_parents = 1,
  97			.ops = &clk_alpha_pll_lucid_evo_ops,
  98		},
  99	},
 100};
 101
 102static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
 103	{ 0x1, 2 },
 104	{ }
 105};
 106
 107static struct clk_init_data sm8475_cam_cc_pll0_out_even_init = {
 108	.name = "cam_cc_pll0_out_even",
 109	.parent_hws = (const struct clk_hw*[]) {
 110		&cam_cc_pll0.clkr.hw,
 111	},
 112	.num_parents = 1,
 113	.flags = CLK_SET_RATE_PARENT,
 114	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 115};
 116
 117static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
 118	.offset = 0x0,
 119	.post_div_shift = 10,
 120	.post_div_table = post_div_table_cam_cc_pll0_out_even,
 121	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
 122	.width = 4,
 123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 124	.clkr.hw.init = &(const struct clk_init_data) {
 125		.name = "cam_cc_pll0_out_even",
 126		.parent_hws = (const struct clk_hw*[]) {
 127			&cam_cc_pll0.clkr.hw,
 128		},
 129		.num_parents = 1,
 130		.flags = CLK_SET_RATE_PARENT,
 131		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 132	},
 133};
 134
 135static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 136	{ 0x2, 3 },
 137	{ }
 138};
 139
 140static struct clk_init_data sm8475_cam_cc_pll0_out_odd_init = {
 141	.name = "cam_cc_pll0_out_odd",
 142	.parent_hws = (const struct clk_hw*[]) {
 143		&cam_cc_pll0.clkr.hw,
 144	},
 145	.num_parents = 1,
 146	.flags = CLK_SET_RATE_PARENT,
 147	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 148};
 149
 150static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 151	.offset = 0x0,
 152	.post_div_shift = 14,
 153	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
 154	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
 155	.width = 4,
 156	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 157	.clkr.hw.init = &(const struct clk_init_data) {
 158		.name = "cam_cc_pll0_out_odd",
 159		.parent_hws = (const struct clk_hw*[]) {
 160			&cam_cc_pll0.clkr.hw,
 161		},
 162		.num_parents = 1,
 163		.flags = CLK_SET_RATE_PARENT,
 164		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 165	},
 166};
 167
 168static const struct alpha_pll_config cam_cc_pll1_config = {
 169	.l = 0x25,
 170	.alpha = 0xeaaa,
 171	.config_ctl_val = 0x20485699,
 172	.config_ctl_hi_val = 0x00182261,
 173	.config_ctl_hi1_val = 0x32aa299c,
 174	.user_ctl_val = 0x00000400,
 175	.user_ctl_hi_val = 0x00000805,
 176};
 177
 178static const struct alpha_pll_config sm8475_cam_cc_pll1_config = {
 179	.l = 0x25,
 180	.alpha = 0xeaaa,
 181	.config_ctl_val = 0x20485699,
 182	.config_ctl_hi_val = 0x00182261,
 183	.config_ctl_hi1_val = 0x82aa299c,
 184	.test_ctl_val = 0x00000000,
 185	.test_ctl_hi_val = 0x00000003,
 186	.test_ctl_hi1_val = 0x00009000,
 187	.test_ctl_hi2_val = 0x00000034,
 188	.user_ctl_val = 0x00000400,
 189	.user_ctl_hi_val = 0x00000005,
 190};
 191
 192static struct clk_alpha_pll cam_cc_pll1 = {
 193	.offset = 0x1000,
 194	.vco_table = lucid_evo_vco,
 195	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 196	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 197	.clkr = {
 198		.hw.init = &(const struct clk_init_data) {
 199			.name = "cam_cc_pll1",
 200			.parent_data = &pll_parent_data_tcxo,
 201			.num_parents = 1,
 202			.ops = &clk_alpha_pll_lucid_evo_ops,
 203		},
 204	},
 205};
 206
 207static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 208	{ 0x1, 2 },
 209	{ }
 210};
 211
 212static struct clk_init_data sm8475_cam_cc_pll1_out_even_init = {
 213	.name = "cam_cc_pll1_out_even",
 214	.parent_hws = (const struct clk_hw*[]) {
 215		&cam_cc_pll1.clkr.hw,
 216	},
 217	.num_parents = 1,
 218	.flags = CLK_SET_RATE_PARENT,
 219	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 220};
 221
 222static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 223	.offset = 0x1000,
 224	.post_div_shift = 10,
 225	.post_div_table = post_div_table_cam_cc_pll1_out_even,
 226	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
 227	.width = 4,
 228	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 229	.clkr.hw.init = &(const struct clk_init_data) {
 230		.name = "cam_cc_pll1_out_even",
 231		.parent_hws = (const struct clk_hw*[]) {
 232			&cam_cc_pll1.clkr.hw,
 233		},
 234		.num_parents = 1,
 235		.flags = CLK_SET_RATE_PARENT,
 236		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 237	},
 238};
 239
 240static const struct alpha_pll_config cam_cc_pll2_config = {
 241	.l = 0x32,
 242	.alpha = 0x0,
 243	.config_ctl_val = 0x90008820,
 244	.config_ctl_hi_val = 0x00890263,
 245	.config_ctl_hi1_val = 0x00000217,
 246};
 247
 248static const struct alpha_pll_config sm8475_cam_cc_pll2_config = {
 249	.l = 0x32,
 250	.alpha = 0x0,
 251	.config_ctl_val = 0x10000030,
 252	.config_ctl_hi_val = 0x80890263,
 253	.config_ctl_hi1_val = 0x00000217,
 254	.user_ctl_val = 0x00000001,
 255	.user_ctl_hi_val = 0x00000000,
 256};
 257
 258static struct clk_alpha_pll cam_cc_pll2 = {
 259	.offset = 0x2000,
 260	.vco_table = rivian_evo_vco,
 261	.num_vco = ARRAY_SIZE(rivian_evo_vco),
 262	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
 263	.clkr = {
 264		.hw.init = &(const struct clk_init_data) {
 265			.name = "cam_cc_pll2",
 266			.parent_data = &pll_parent_data_tcxo,
 267			.num_parents = 1,
 268			.ops = &clk_alpha_pll_rivian_evo_ops,
 269		},
 270	},
 271};
 272
 273static const struct alpha_pll_config cam_cc_pll3_config = {
 274	.l = 0x2d,
 275	.alpha = 0x0,
 276	.config_ctl_val = 0x20485699,
 277	.config_ctl_hi_val = 0x00182261,
 278	.config_ctl_hi1_val = 0x32aa299c,
 279	.user_ctl_val = 0x00000400,
 280	.user_ctl_hi_val = 0x00000805,
 281};
 282
 283static const struct alpha_pll_config sm8475_cam_cc_pll3_config = {
 284	.l = 0x2d,
 285	.alpha = 0x0,
 286	.config_ctl_val = 0x20485699,
 287	.config_ctl_hi_val = 0x00182261,
 288	.config_ctl_hi1_val = 0x82aa299c,
 289	.test_ctl_val = 0x00000000,
 290	.test_ctl_hi_val = 0x00000003,
 291	.test_ctl_hi1_val = 0x00009000,
 292	.test_ctl_hi2_val = 0x00000034,
 293	.user_ctl_val = 0x00000400,
 294	.user_ctl_hi_val = 0x00000005,
 295};
 296
 297static struct clk_alpha_pll cam_cc_pll3 = {
 298	.offset = 0x3000,
 299	.vco_table = lucid_evo_vco,
 300	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 301	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 302	.clkr = {
 303		.hw.init = &(const struct clk_init_data) {
 304			.name = "cam_cc_pll3",
 305			.parent_data = &pll_parent_data_tcxo,
 306			.num_parents = 1,
 307			.ops = &clk_alpha_pll_lucid_evo_ops,
 308		},
 309	},
 310};
 311
 312static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 313	{ 0x1, 2 },
 314	{ }
 315};
 316
 317static struct clk_init_data sm8475_cam_cc_pll3_out_even_init = {
 318	.name = "cam_cc_pll3_out_even",
 319	.parent_hws = (const struct clk_hw*[]) {
 320		&cam_cc_pll3.clkr.hw,
 321	},
 322	.num_parents = 1,
 323	.flags = CLK_SET_RATE_PARENT,
 324	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 325};
 326
 327static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 328	.offset = 0x3000,
 329	.post_div_shift = 10,
 330	.post_div_table = post_div_table_cam_cc_pll3_out_even,
 331	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
 332	.width = 4,
 333	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 334	.clkr.hw.init = &(const struct clk_init_data) {
 335		.name = "cam_cc_pll3_out_even",
 336		.parent_hws = (const struct clk_hw*[]) {
 337			&cam_cc_pll3.clkr.hw,
 338		},
 339		.num_parents = 1,
 340		.flags = CLK_SET_RATE_PARENT,
 341		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 342	},
 343};
 344
 345static const struct alpha_pll_config cam_cc_pll4_config = {
 346	.l = 0x2d,
 347	.alpha = 0x0,
 348	.config_ctl_val = 0x20485699,
 349	.config_ctl_hi_val = 0x00182261,
 350	.config_ctl_hi1_val = 0x32aa299c,
 351	.user_ctl_val = 0x00000400,
 352	.user_ctl_hi_val = 0x00000805,
 353};
 354
 355static const struct alpha_pll_config sm8475_cam_cc_pll4_config = {
 356	.l = 0x2d,
 357	.alpha = 0x0,
 358	.config_ctl_val = 0x20485699,
 359	.config_ctl_hi_val = 0x00182261,
 360	.config_ctl_hi1_val = 0x82aa299c,
 361	.test_ctl_val = 0x00000000,
 362	.test_ctl_hi_val = 0x00000003,
 363	.test_ctl_hi1_val = 0x00009000,
 364	.test_ctl_hi2_val = 0x00000034,
 365	.user_ctl_val = 0x00000400,
 366	.user_ctl_hi_val = 0x00000005,
 367};
 368
 369static struct clk_alpha_pll cam_cc_pll4 = {
 370	.offset = 0x4000,
 371	.vco_table = lucid_evo_vco,
 372	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 373	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 374	.clkr = {
 375		.hw.init = &(const struct clk_init_data) {
 376			.name = "cam_cc_pll4",
 377			.parent_data = &pll_parent_data_tcxo,
 378			.num_parents = 1,
 379			.ops = &clk_alpha_pll_lucid_evo_ops,
 380		},
 381	},
 382};
 383
 384static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 385	{ 0x1, 2 },
 386	{ }
 387};
 388
 389static struct clk_init_data sm8475_cam_cc_pll4_out_even_init = {
 390	.name = "cam_cc_pll4_out_even",
 391	.parent_hws = (const struct clk_hw*[]) {
 392		&cam_cc_pll4.clkr.hw,
 393	},
 394	.num_parents = 1,
 395	.flags = CLK_SET_RATE_PARENT,
 396	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 397};
 398
 399static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 400	.offset = 0x4000,
 401	.post_div_shift = 10,
 402	.post_div_table = post_div_table_cam_cc_pll4_out_even,
 403	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
 404	.width = 4,
 405	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 406	.clkr.hw.init = &(const struct clk_init_data) {
 407		.name = "cam_cc_pll4_out_even",
 408		.parent_hws = (const struct clk_hw*[]) {
 409			&cam_cc_pll4.clkr.hw,
 410		},
 411		.num_parents = 1,
 412		.flags = CLK_SET_RATE_PARENT,
 413		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 414	},
 415};
 416
 417static const struct alpha_pll_config cam_cc_pll5_config = {
 418	.l = 0x2d,
 419	.alpha = 0x0,
 420	.config_ctl_val = 0x20485699,
 421	.config_ctl_hi_val = 0x00182261,
 422	.config_ctl_hi1_val = 0x32aa299c,
 423	.user_ctl_val = 0x00000400,
 424	.user_ctl_hi_val = 0x00000805,
 425};
 426
 427static const struct alpha_pll_config sm8475_cam_cc_pll5_config = {
 428	.l = 0x2d,
 429	.alpha = 0x0,
 430	.config_ctl_val = 0x20485699,
 431	.config_ctl_hi_val = 0x00182261,
 432	.config_ctl_hi1_val = 0x82aa299c,
 433	.test_ctl_val = 0x00000000,
 434	.test_ctl_hi_val = 0x00000003,
 435	.test_ctl_hi1_val = 0x00009000,
 436	.test_ctl_hi2_val = 0x00000034,
 437	.user_ctl_val = 0x00000400,
 438	.user_ctl_hi_val = 0x00000005,
 439};
 440
 441static struct clk_alpha_pll cam_cc_pll5 = {
 442	.offset = 0x5000,
 443	.vco_table = lucid_evo_vco,
 444	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 445	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 446	.clkr = {
 447		.hw.init = &(const struct clk_init_data) {
 448			.name = "cam_cc_pll5",
 449			.parent_data = &pll_parent_data_tcxo,
 450			.num_parents = 1,
 451			.ops = &clk_alpha_pll_lucid_evo_ops,
 452		},
 453	},
 454};
 455
 456static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
 457	{ 0x1, 2 },
 458	{ }
 459};
 460
 461static struct clk_init_data sm8475_cam_cc_pll5_out_even_init = {
 462	.name = "cam_cc_pll5_out_even",
 463	.parent_hws = (const struct clk_hw*[]) {
 464		&cam_cc_pll5.clkr.hw,
 465	},
 466	.num_parents = 1,
 467	.flags = CLK_SET_RATE_PARENT,
 468	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 469};
 470
 471static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 472	.offset = 0x5000,
 473	.post_div_shift = 10,
 474	.post_div_table = post_div_table_cam_cc_pll5_out_even,
 475	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
 476	.width = 4,
 477	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 478	.clkr.hw.init = &(const struct clk_init_data) {
 479		.name = "cam_cc_pll5_out_even",
 480		.parent_hws = (const struct clk_hw*[]) {
 481			&cam_cc_pll5.clkr.hw,
 482		},
 483		.num_parents = 1,
 484		.flags = CLK_SET_RATE_PARENT,
 485		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 486	},
 487};
 488
 489static const struct alpha_pll_config cam_cc_pll6_config = {
 490	.l = 0x2d,
 491	.alpha = 0x0,
 492	.config_ctl_val = 0x20485699,
 493	.config_ctl_hi_val = 0x00182261,
 494	.config_ctl_hi1_val = 0x32aa299c,
 495	.user_ctl_val = 0x00000400,
 496	.user_ctl_hi_val = 0x00000805,
 497};
 498
 499static const struct alpha_pll_config sm8475_cam_cc_pll6_config = {
 500	.l = 0x2d,
 501	.alpha = 0x0,
 502	.config_ctl_val = 0x20485699,
 503	.config_ctl_hi_val = 0x00182261,
 504	.config_ctl_hi1_val = 0x82aa299c,
 505	.test_ctl_val = 0x00000000,
 506	.test_ctl_hi_val = 0x00000003,
 507	.test_ctl_hi1_val = 0x00009000,
 508	.test_ctl_hi2_val = 0x00000034,
 509	.user_ctl_val = 0x00000400,
 510	.user_ctl_hi_val = 0x00000005,
 511};
 512
 513static struct clk_alpha_pll cam_cc_pll6 = {
 514	.offset = 0x6000,
 515	.vco_table = lucid_evo_vco,
 516	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 517	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 518	.clkr = {
 519		.hw.init = &(const struct clk_init_data) {
 520			.name = "cam_cc_pll6",
 521			.parent_data = &pll_parent_data_tcxo,
 522			.num_parents = 1,
 523			.ops = &clk_alpha_pll_lucid_evo_ops,
 524		},
 525	},
 526};
 527
 528static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
 529	{ 0x1, 2 },
 530	{ }
 531};
 532
 533static struct clk_init_data sm8475_cam_cc_pll6_out_even_init = {
 534	.name = "cam_cc_pll6_out_even",
 535	.parent_hws = (const struct clk_hw*[]) {
 536		&cam_cc_pll6.clkr.hw,
 537	},
 538	.num_parents = 1,
 539	.flags = CLK_SET_RATE_PARENT,
 540	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 541};
 542
 543static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 544	.offset = 0x6000,
 545	.post_div_shift = 10,
 546	.post_div_table = post_div_table_cam_cc_pll6_out_even,
 547	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
 548	.width = 4,
 549	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 550	.clkr.hw.init = &(const struct clk_init_data) {
 551		.name = "cam_cc_pll6_out_even",
 552		.parent_hws = (const struct clk_hw*[]) {
 553			&cam_cc_pll6.clkr.hw,
 554		},
 555		.num_parents = 1,
 556		.flags = CLK_SET_RATE_PARENT,
 557		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 558	},
 559};
 560
 561static const struct alpha_pll_config cam_cc_pll7_config = {
 562	.l = 0x2d,
 563	.alpha = 0x0,
 564	.config_ctl_val = 0x20485699,
 565	.config_ctl_hi_val = 0x00182261,
 566	.config_ctl_hi1_val = 0x32aa299c,
 567	.user_ctl_val = 0x00000400,
 568	.user_ctl_hi_val = 0x00000805,
 569};
 570
 571static const struct alpha_pll_config sm8475_cam_cc_pll7_config = {
 572	.l = 0x2d,
 573	.alpha = 0x0,
 574	.config_ctl_val = 0x20485699,
 575	.config_ctl_hi_val = 0x00182261,
 576	.config_ctl_hi1_val = 0x82aa299c,
 577	.test_ctl_val = 0x00000000,
 578	.test_ctl_hi_val = 0x00000003,
 579	.test_ctl_hi1_val = 0x00009000,
 580	.test_ctl_hi2_val = 0x00000034,
 581	.user_ctl_val = 0x00000400,
 582	.user_ctl_hi_val = 0x00000005,
 583};
 584
 585static struct clk_alpha_pll cam_cc_pll7 = {
 586	.offset = 0x7000,
 587	.vco_table = lucid_evo_vco,
 588	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 589	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 590	.clkr = {
 591		.hw.init = &(const struct clk_init_data) {
 592			.name = "cam_cc_pll7",
 593			.parent_data = &pll_parent_data_tcxo,
 594			.num_parents = 1,
 595			.ops = &clk_alpha_pll_lucid_evo_ops,
 596		},
 597	},
 598};
 599
 600static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
 601	{ 0x1, 2 },
 602	{ }
 603};
 604
 605static struct clk_init_data sm8475_cam_cc_pll7_out_even_init = {
 606	.name = "cam_cc_pll7_out_even",
 607	.parent_hws = (const struct clk_hw*[]) {
 608		&cam_cc_pll7.clkr.hw,
 609	},
 610	.num_parents = 1,
 611	.flags = CLK_SET_RATE_PARENT,
 612	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 613};
 614
 615static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 616	.offset = 0x7000,
 617	.post_div_shift = 10,
 618	.post_div_table = post_div_table_cam_cc_pll7_out_even,
 619	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
 620	.width = 4,
 621	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 622	.clkr.hw.init = &(const struct clk_init_data) {
 623		.name = "cam_cc_pll7_out_even",
 624		.parent_hws = (const struct clk_hw*[]) {
 625			&cam_cc_pll7.clkr.hw,
 626		},
 627		.num_parents = 1,
 628		.flags = CLK_SET_RATE_PARENT,
 629		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 630	},
 631};
 632
 633static const struct alpha_pll_config cam_cc_pll8_config = {
 634	.l = 0x32,
 635	.alpha = 0x0,
 636	.config_ctl_val = 0x20485699,
 637	.config_ctl_hi_val = 0x00182261,
 638	.config_ctl_hi1_val = 0x32aa299c,
 639	.user_ctl_val = 0x00000400,
 640	.user_ctl_hi_val = 0x00000805,
 641};
 642
 643static const struct alpha_pll_config sm8475_cam_cc_pll8_config = {
 644	.l = 0x32,
 645	.alpha = 0x0,
 646	.config_ctl_val = 0x20485699,
 647	.config_ctl_hi_val = 0x00182261,
 648	.config_ctl_hi1_val = 0x82aa299c,
 649	.test_ctl_val = 0x00000000,
 650	.test_ctl_hi_val = 0x00000003,
 651	.test_ctl_hi1_val = 0x00009000,
 652	.test_ctl_hi2_val = 0x00000034,
 653	.user_ctl_val = 0x00000400,
 654	.user_ctl_hi_val = 0x00000005,
 655};
 656
 657static struct clk_alpha_pll cam_cc_pll8 = {
 658	.offset = 0x8000,
 659	.vco_table = lucid_evo_vco,
 660	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 661	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 662	.clkr = {
 663		.hw.init = &(const struct clk_init_data) {
 664			.name = "cam_cc_pll8",
 665			.parent_data = &pll_parent_data_tcxo,
 666			.num_parents = 1,
 667			.ops = &clk_alpha_pll_lucid_evo_ops,
 668		},
 669	},
 670};
 671
 672static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
 673	{ 0x1, 2 },
 674	{ }
 675};
 676
 677static struct clk_init_data sm8475_cam_cc_pll8_out_even_init = {
 678	.name = "cam_cc_pll8_out_even",
 679	.parent_hws = (const struct clk_hw*[]) {
 680		&cam_cc_pll8.clkr.hw,
 681	},
 682	.num_parents = 1,
 683	.flags = CLK_SET_RATE_PARENT,
 684	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 685};
 686
 687static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
 688	.offset = 0x8000,
 689	.post_div_shift = 10,
 690	.post_div_table = post_div_table_cam_cc_pll8_out_even,
 691	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
 692	.width = 4,
 693	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 694	.clkr.hw.init = &(const struct clk_init_data) {
 695		.name = "cam_cc_pll8_out_even",
 696		.parent_hws = (const struct clk_hw*[]) {
 697			&cam_cc_pll8.clkr.hw,
 698		},
 699		.num_parents = 1,
 700		.flags = CLK_SET_RATE_PARENT,
 701		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 702	},
 703};
 704
 705static const struct parent_map cam_cc_parent_map_0[] = {
 706	{ P_BI_TCXO, 0 },
 707	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
 708	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
 709	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
 710	{ P_CAM_CC_PLL8_OUT_EVEN, 5 },
 711};
 712
 713static const struct clk_parent_data cam_cc_parent_data_0[] = {
 714	{ .index = DT_BI_TCXO },
 715	{ .hw = &cam_cc_pll0.clkr.hw },
 716	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
 717	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
 718	{ .hw = &cam_cc_pll8_out_even.clkr.hw },
 719};
 720
 721static const struct parent_map cam_cc_parent_map_1[] = {
 722	{ P_BI_TCXO, 0 },
 723	{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
 724	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
 725};
 726
 727static const struct clk_parent_data cam_cc_parent_data_1[] = {
 728	{ .index = DT_BI_TCXO },
 729	{ .hw = &cam_cc_pll2.clkr.hw },
 730	{ .hw = &cam_cc_pll2.clkr.hw },
 731};
 732
 733static const struct parent_map cam_cc_parent_map_2[] = {
 734	{ P_BI_TCXO, 0 },
 735	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
 736};
 737
 738static const struct clk_parent_data cam_cc_parent_data_2[] = {
 739	{ .index = DT_BI_TCXO },
 740	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
 741};
 742
 743static const struct parent_map cam_cc_parent_map_3[] = {
 744	{ P_BI_TCXO, 0 },
 745	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
 746};
 747
 748static const struct clk_parent_data cam_cc_parent_data_3[] = {
 749	{ .index = DT_BI_TCXO },
 750	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
 751};
 752
 753static const struct parent_map cam_cc_parent_map_4[] = {
 754	{ P_BI_TCXO, 0 },
 755	{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
 756};
 757
 758static const struct clk_parent_data cam_cc_parent_data_4[] = {
 759	{ .index = DT_BI_TCXO },
 760	{ .hw = &cam_cc_pll5_out_even.clkr.hw },
 761};
 762
 763static const struct parent_map cam_cc_parent_map_5[] = {
 764	{ P_BI_TCXO, 0 },
 765	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
 766};
 767
 768static const struct clk_parent_data cam_cc_parent_data_5[] = {
 769	{ .index = DT_BI_TCXO },
 770	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
 771};
 772
 773static const struct parent_map cam_cc_parent_map_6[] = {
 774	{ P_BI_TCXO, 0 },
 775	{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
 776};
 777
 778static const struct clk_parent_data cam_cc_parent_data_6[] = {
 779	{ .index = DT_BI_TCXO },
 780	{ .hw = &cam_cc_pll6_out_even.clkr.hw },
 781};
 782
 783static const struct parent_map cam_cc_parent_map_7[] = {
 784	{ P_BI_TCXO, 0 },
 785	{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
 786};
 787
 788static const struct clk_parent_data cam_cc_parent_data_7[] = {
 789	{ .index = DT_BI_TCXO },
 790	{ .hw = &cam_cc_pll7_out_even.clkr.hw },
 791};
 792
 793static const struct parent_map cam_cc_parent_map_8[] = {
 794	{ P_SLEEP_CLK, 0 },
 795};
 796
 797static const struct clk_parent_data cam_cc_parent_data_8[] = {
 798	{ .index = DT_SLEEP_CLK },
 799};
 800
 801static const struct parent_map cam_cc_parent_map_9[] = {
 802	{ P_BI_TCXO, 0 },
 803};
 804
 805static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
 806	{ .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" },
 807};
 808
 809static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 810	F(19200000, P_BI_TCXO, 1, 0, 0),
 811	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
 812	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 813	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 814	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 815	{ }
 816};
 817
 818static struct clk_rcg2 cam_cc_bps_clk_src = {
 819	.cmd_rcgr = 0x10050,
 820	.mnd_width = 0,
 821	.hid_width = 5,
 822	.parent_map = cam_cc_parent_map_0,
 823	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 824	.clkr.hw.init = &(const struct clk_init_data) {
 825		.name = "cam_cc_bps_clk_src",
 826		.parent_data = cam_cc_parent_data_0,
 827		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 828		.flags = CLK_SET_RATE_PARENT,
 829		.ops = &clk_rcg2_ops,
 830	},
 831};
 832
 833static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
 834	F(19200000, P_BI_TCXO, 1, 0, 0),
 835	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 836	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 837	{ }
 838};
 839
 840static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
 841	.cmd_rcgr = 0x13194,
 842	.mnd_width = 0,
 843	.hid_width = 5,
 844	.parent_map = cam_cc_parent_map_0,
 845	.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
 846	.clkr.hw.init = &(const struct clk_init_data) {
 847		.name = "cam_cc_camnoc_axi_clk_src",
 848		.parent_data = cam_cc_parent_data_0,
 849		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 850		.flags = CLK_SET_RATE_PARENT,
 851		.ops = &clk_rcg2_ops,
 852	},
 853};
 854
 855static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 856	F(19200000, P_BI_TCXO, 1, 0, 0),
 857	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 858	{ }
 859};
 860
 861static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 862	.cmd_rcgr = 0x1312c,
 863	.mnd_width = 8,
 864	.hid_width = 5,
 865	.parent_map = cam_cc_parent_map_0,
 866	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 867	.clkr.hw.init = &(const struct clk_init_data) {
 868		.name = "cam_cc_cci_0_clk_src",
 869		.parent_data = cam_cc_parent_data_0,
 870		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 871		.flags = CLK_SET_RATE_PARENT,
 872		.ops = &clk_rcg2_ops,
 873	},
 874};
 875
 876static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 877	.cmd_rcgr = 0x13148,
 878	.mnd_width = 8,
 879	.hid_width = 5,
 880	.parent_map = cam_cc_parent_map_0,
 881	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 882	.clkr.hw.init = &(const struct clk_init_data) {
 883		.name = "cam_cc_cci_1_clk_src",
 884		.parent_data = cam_cc_parent_data_0,
 885		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 886		.flags = CLK_SET_RATE_PARENT,
 887		.ops = &clk_rcg2_ops,
 888	},
 889};
 890
 891static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
 892	F(19200000, P_BI_TCXO, 1, 0, 0),
 893	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 894	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
 895	{ }
 896};
 897
 898static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 899	.cmd_rcgr = 0x1104c,
 900	.mnd_width = 0,
 901	.hid_width = 5,
 902	.parent_map = cam_cc_parent_map_0,
 903	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 904	.clkr.hw.init = &(const struct clk_init_data) {
 905		.name = "cam_cc_cphy_rx_clk_src",
 906		.parent_data = cam_cc_parent_data_0,
 907		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 908		.flags = CLK_SET_RATE_PARENT,
 909		.ops = &clk_rcg2_ops,
 910	},
 911};
 912
 913static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
 914	F(19200000, P_BI_TCXO, 1, 0, 0),
 915	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 916	{ }
 917};
 918
 919static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 920	.cmd_rcgr = 0x150e0,
 921	.mnd_width = 0,
 922	.hid_width = 5,
 923	.parent_map = cam_cc_parent_map_0,
 924	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 925	.clkr.hw.init = &(const struct clk_init_data) {
 926		.name = "cam_cc_csi0phytimer_clk_src",
 927		.parent_data = cam_cc_parent_data_0,
 928		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 929		.flags = CLK_SET_RATE_PARENT,
 930		.ops = &clk_rcg2_ops,
 931	},
 932};
 933
 934static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 935	.cmd_rcgr = 0x15104,
 936	.mnd_width = 0,
 937	.hid_width = 5,
 938	.parent_map = cam_cc_parent_map_0,
 939	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 940	.clkr.hw.init = &(const struct clk_init_data) {
 941		.name = "cam_cc_csi1phytimer_clk_src",
 942		.parent_data = cam_cc_parent_data_0,
 943		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 944		.flags = CLK_SET_RATE_PARENT,
 945		.ops = &clk_rcg2_ops,
 946	},
 947};
 948
 949static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 950	.cmd_rcgr = 0x15124,
 951	.mnd_width = 0,
 952	.hid_width = 5,
 953	.parent_map = cam_cc_parent_map_0,
 954	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 955	.clkr.hw.init = &(const struct clk_init_data) {
 956		.name = "cam_cc_csi2phytimer_clk_src",
 957		.parent_data = cam_cc_parent_data_0,
 958		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 959		.flags = CLK_SET_RATE_PARENT,
 960		.ops = &clk_rcg2_ops,
 961	},
 962};
 963
 964static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 965	.cmd_rcgr = 0x1514c,
 966	.mnd_width = 0,
 967	.hid_width = 5,
 968	.parent_map = cam_cc_parent_map_0,
 969	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 970	.clkr.hw.init = &(const struct clk_init_data) {
 971		.name = "cam_cc_csi3phytimer_clk_src",
 972		.parent_data = cam_cc_parent_data_0,
 973		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 974		.flags = CLK_SET_RATE_PARENT,
 975		.ops = &clk_rcg2_ops,
 976	},
 977};
 978
 979static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
 980	.cmd_rcgr = 0x1516c,
 981	.mnd_width = 0,
 982	.hid_width = 5,
 983	.parent_map = cam_cc_parent_map_0,
 984	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 985	.clkr.hw.init = &(const struct clk_init_data) {
 986		.name = "cam_cc_csi4phytimer_clk_src",
 987		.parent_data = cam_cc_parent_data_0,
 988		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 989		.flags = CLK_SET_RATE_PARENT,
 990		.ops = &clk_rcg2_ops,
 991	},
 992};
 993
 994static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
 995	.cmd_rcgr = 0x1518c,
 996	.mnd_width = 0,
 997	.hid_width = 5,
 998	.parent_map = cam_cc_parent_map_0,
 999	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1000	.clkr.hw.init = &(const struct clk_init_data) {
1001		.name = "cam_cc_csi5phytimer_clk_src",
1002		.parent_data = cam_cc_parent_data_0,
1003		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1004		.flags = CLK_SET_RATE_PARENT,
1005		.ops = &clk_rcg2_ops,
1006	},
1007};
1008
1009static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
1010	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1011	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1012	{ }
1013};
1014
1015static struct clk_rcg2 cam_cc_csid_clk_src = {
1016	.cmd_rcgr = 0x13174,
1017	.mnd_width = 0,
1018	.hid_width = 5,
1019	.parent_map = cam_cc_parent_map_0,
1020	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1021	.clkr.hw.init = &(const struct clk_init_data) {
1022		.name = "cam_cc_csid_clk_src",
1023		.parent_data = cam_cc_parent_data_0,
1024		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1025		.flags = CLK_SET_RATE_PARENT,
1026		.ops = &clk_rcg2_ops,
1027	},
1028};
1029
1030static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
1031	F(19200000, P_BI_TCXO, 1, 0, 0),
1032	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
1033	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
1034	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1035	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1036	{ }
1037};
1038
1039static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
1040	.cmd_rcgr = 0x10018,
1041	.mnd_width = 0,
1042	.hid_width = 5,
1043	.parent_map = cam_cc_parent_map_0,
1044	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
1045	.clkr.hw.init = &(const struct clk_init_data) {
1046		.name = "cam_cc_fast_ahb_clk_src",
1047		.parent_data = cam_cc_parent_data_0,
1048		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1049		.flags = CLK_SET_RATE_PARENT,
1050		.ops = &clk_rcg2_ops,
1051	},
1052};
1053
1054static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
1055	F(19200000, P_BI_TCXO, 1, 0, 0),
1056	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1057	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
1058	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
1059	{ }
1060};
1061
1062static struct clk_rcg2 cam_cc_icp_clk_src = {
1063	.cmd_rcgr = 0x13108,
1064	.mnd_width = 0,
1065	.hid_width = 5,
1066	.parent_map = cam_cc_parent_map_0,
1067	.freq_tbl = ftbl_cam_cc_icp_clk_src,
1068	.clkr.hw.init = &(const struct clk_init_data) {
1069		.name = "cam_cc_icp_clk_src",
1070		.parent_data = cam_cc_parent_data_0,
1071		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1072		.flags = CLK_SET_RATE_PARENT,
1073		.ops = &clk_rcg2_ops,
1074	},
1075};
1076
1077static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
1078	F(19200000, P_BI_TCXO, 1, 0, 0),
1079	F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1080	F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1081	F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1082	F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1083	{ }
1084};
1085
1086static struct clk_rcg2 cam_cc_ife_0_clk_src = {
1087	.cmd_rcgr = 0x11018,
1088	.mnd_width = 0,
1089	.hid_width = 5,
1090	.parent_map = cam_cc_parent_map_2,
1091	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
1092	.clkr.hw.init = &(const struct clk_init_data) {
1093		.name = "cam_cc_ife_0_clk_src",
1094		.parent_data = cam_cc_parent_data_2,
1095		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1096		.flags = CLK_SET_RATE_PARENT,
1097		.ops = &clk_rcg2_ops,
1098	},
1099};
1100
1101static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
1102	F(19200000, P_BI_TCXO, 1, 0, 0),
1103	F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1104	F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1105	F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1106	F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1107	{ }
1108};
1109
1110static struct clk_rcg2 cam_cc_ife_1_clk_src = {
1111	.cmd_rcgr = 0x12018,
1112	.mnd_width = 0,
1113	.hid_width = 5,
1114	.parent_map = cam_cc_parent_map_3,
1115	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
1116	.clkr.hw.init = &(const struct clk_init_data) {
1117		.name = "cam_cc_ife_1_clk_src",
1118		.parent_data = cam_cc_parent_data_3,
1119		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1120		.flags = CLK_SET_RATE_PARENT,
1121		.ops = &clk_rcg2_ops,
1122	},
1123};
1124
1125static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
1126	F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1127	F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1128	F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1129	F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1130	{ }
1131};
1132
1133static struct clk_rcg2 cam_cc_ife_2_clk_src = {
1134	.cmd_rcgr = 0x12064,
1135	.mnd_width = 0,
1136	.hid_width = 5,
1137	.parent_map = cam_cc_parent_map_4,
1138	.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
1139	.clkr.hw.init = &(const struct clk_init_data) {
1140		.name = "cam_cc_ife_2_clk_src",
1141		.parent_data = cam_cc_parent_data_4,
1142		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
1143		.flags = CLK_SET_RATE_PARENT,
1144		.ops = &clk_rcg2_ops,
1145	},
1146};
1147
1148static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
1149	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1150	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
1151	{ }
1152};
1153
1154static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
1155	.cmd_rcgr = 0x13000,
1156	.mnd_width = 0,
1157	.hid_width = 5,
1158	.parent_map = cam_cc_parent_map_0,
1159	.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
1160	.clkr.hw.init = &(const struct clk_init_data) {
1161		.name = "cam_cc_ife_lite_clk_src",
1162		.parent_data = cam_cc_parent_data_0,
1163		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1164		.flags = CLK_SET_RATE_PARENT,
1165		.ops = &clk_rcg2_ops,
1166	},
1167};
1168
1169static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
1170	.cmd_rcgr = 0x13024,
1171	.mnd_width = 0,
1172	.hid_width = 5,
1173	.parent_map = cam_cc_parent_map_0,
1174	.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
1175	.clkr.hw.init = &(const struct clk_init_data) {
1176		.name = "cam_cc_ife_lite_csid_clk_src",
1177		.parent_data = cam_cc_parent_data_0,
1178		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1179		.flags = CLK_SET_RATE_PARENT,
1180		.ops = &clk_rcg2_ops,
1181	},
1182};
1183
1184static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
1185	F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1186	F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1187	F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1188	F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1189	{ }
1190};
1191
1192static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
1193	.cmd_rcgr = 0x1008c,
1194	.mnd_width = 0,
1195	.hid_width = 5,
1196	.parent_map = cam_cc_parent_map_5,
1197	.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
1198	.clkr.hw.init = &(const struct clk_init_data) {
1199		.name = "cam_cc_ipe_nps_clk_src",
1200		.parent_data = cam_cc_parent_data_5,
1201		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
1202		.flags = CLK_SET_RATE_PARENT,
1203		.ops = &clk_rcg2_ops,
1204	},
1205};
1206
1207static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1208	.cmd_rcgr = 0x130dc,
1209	.mnd_width = 0,
1210	.hid_width = 5,
1211	.parent_map = cam_cc_parent_map_0,
1212	.freq_tbl = ftbl_cam_cc_bps_clk_src,
1213	.clkr.hw.init = &(const struct clk_init_data) {
1214		.name = "cam_cc_jpeg_clk_src",
1215		.parent_data = cam_cc_parent_data_0,
1216		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1217		.flags = CLK_SET_RATE_PARENT,
1218		.ops = &clk_rcg2_ops,
1219	},
1220};
1221
1222static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1223	F(19200000, P_BI_TCXO, 1, 0, 0),
1224	F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
1225	F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1226	{ }
1227};
1228
1229static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1230	.cmd_rcgr = 0x15000,
1231	.mnd_width = 8,
1232	.hid_width = 5,
1233	.parent_map = cam_cc_parent_map_1,
1234	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1235	.clkr.hw.init = &(const struct clk_init_data) {
1236		.name = "cam_cc_mclk0_clk_src",
1237		.parent_data = cam_cc_parent_data_1,
1238		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1239		.flags = CLK_SET_RATE_PARENT,
1240		.ops = &clk_rcg2_ops,
1241	},
1242};
1243
1244static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1245	.cmd_rcgr = 0x1501c,
1246	.mnd_width = 8,
1247	.hid_width = 5,
1248	.parent_map = cam_cc_parent_map_1,
1249	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1250	.clkr.hw.init = &(const struct clk_init_data) {
1251		.name = "cam_cc_mclk1_clk_src",
1252		.parent_data = cam_cc_parent_data_1,
1253		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1254		.flags = CLK_SET_RATE_PARENT,
1255		.ops = &clk_rcg2_ops,
1256	},
1257};
1258
1259static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1260	.cmd_rcgr = 0x15038,
1261	.mnd_width = 8,
1262	.hid_width = 5,
1263	.parent_map = cam_cc_parent_map_1,
1264	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1265	.clkr.hw.init = &(const struct clk_init_data) {
1266		.name = "cam_cc_mclk2_clk_src",
1267		.parent_data = cam_cc_parent_data_1,
1268		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1269		.flags = CLK_SET_RATE_PARENT,
1270		.ops = &clk_rcg2_ops,
1271	},
1272};
1273
1274static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1275	.cmd_rcgr = 0x15054,
1276	.mnd_width = 8,
1277	.hid_width = 5,
1278	.parent_map = cam_cc_parent_map_1,
1279	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1280	.clkr.hw.init = &(const struct clk_init_data) {
1281		.name = "cam_cc_mclk3_clk_src",
1282		.parent_data = cam_cc_parent_data_1,
1283		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1284		.flags = CLK_SET_RATE_PARENT,
1285		.ops = &clk_rcg2_ops,
1286	},
1287};
1288
1289static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1290	.cmd_rcgr = 0x15070,
1291	.mnd_width = 8,
1292	.hid_width = 5,
1293	.parent_map = cam_cc_parent_map_1,
1294	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1295	.clkr.hw.init = &(const struct clk_init_data) {
1296		.name = "cam_cc_mclk4_clk_src",
1297		.parent_data = cam_cc_parent_data_1,
1298		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1299		.flags = CLK_SET_RATE_PARENT,
1300		.ops = &clk_rcg2_ops,
1301	},
1302};
1303
1304static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1305	.cmd_rcgr = 0x1508c,
1306	.mnd_width = 8,
1307	.hid_width = 5,
1308	.parent_map = cam_cc_parent_map_1,
1309	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1310	.clkr.hw.init = &(const struct clk_init_data) {
1311		.name = "cam_cc_mclk5_clk_src",
1312		.parent_data = cam_cc_parent_data_1,
1313		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1314		.flags = CLK_SET_RATE_PARENT,
1315		.ops = &clk_rcg2_ops,
1316	},
1317};
1318
1319static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1320	.cmd_rcgr = 0x150a8,
1321	.mnd_width = 8,
1322	.hid_width = 5,
1323	.parent_map = cam_cc_parent_map_1,
1324	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1325	.clkr.hw.init = &(const struct clk_init_data) {
1326		.name = "cam_cc_mclk6_clk_src",
1327		.parent_data = cam_cc_parent_data_1,
1328		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1329		.flags = CLK_SET_RATE_PARENT,
1330		.ops = &clk_rcg2_ops,
1331	},
1332};
1333
1334static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1335	.cmd_rcgr = 0x150c4,
1336	.mnd_width = 8,
1337	.hid_width = 5,
1338	.parent_map = cam_cc_parent_map_1,
1339	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1340	.clkr.hw.init = &(const struct clk_init_data) {
1341		.name = "cam_cc_mclk7_clk_src",
1342		.parent_data = cam_cc_parent_data_1,
1343		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1344		.flags = CLK_SET_RATE_PARENT,
1345		.ops = &clk_rcg2_ops,
1346	},
1347};
1348
1349static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1350	F(19200000, P_BI_TCXO, 1, 0, 0),
1351	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1352	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1353	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1354	{ }
1355};
1356
1357static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1358	.cmd_rcgr = 0x131bc,
1359	.mnd_width = 0,
1360	.hid_width = 5,
1361	.parent_map = cam_cc_parent_map_0,
1362	.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1363	.clkr.hw.init = &(const struct clk_init_data) {
1364		.name = "cam_cc_qdss_debug_clk_src",
1365		.parent_data = cam_cc_parent_data_0,
1366		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1367		.flags = CLK_SET_RATE_PARENT,
1368		.ops = &clk_rcg2_ops,
1369	},
1370};
1371
1372static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1373	F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1374	F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1375	F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1376	F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1377	{ }
1378};
1379
1380static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1381	.cmd_rcgr = 0x13064,
1382	.mnd_width = 0,
1383	.hid_width = 5,
1384	.parent_map = cam_cc_parent_map_6,
1385	.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1386	.clkr.hw.init = &(const struct clk_init_data) {
1387		.name = "cam_cc_sfe_0_clk_src",
1388		.parent_data = cam_cc_parent_data_6,
1389		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1390		.flags = CLK_SET_RATE_PARENT,
1391		.ops = &clk_rcg2_ops,
1392	},
1393};
1394
1395static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1396	F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1397	F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1398	F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1399	F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1400	{ }
1401};
1402
1403static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1404	.cmd_rcgr = 0x130ac,
1405	.mnd_width = 0,
1406	.hid_width = 5,
1407	.parent_map = cam_cc_parent_map_7,
1408	.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1409	.clkr.hw.init = &(const struct clk_init_data) {
1410		.name = "cam_cc_sfe_1_clk_src",
1411		.parent_data = cam_cc_parent_data_7,
1412		.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1413		.flags = CLK_SET_RATE_PARENT,
1414		.ops = &clk_rcg2_ops,
1415	},
1416};
1417
1418static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1419	F(32000, P_SLEEP_CLK, 1, 0, 0),
1420	{ }
1421};
1422
1423static struct clk_rcg2 cam_cc_sleep_clk_src = {
1424	.cmd_rcgr = 0x13210,
1425	.mnd_width = 0,
1426	.hid_width = 5,
1427	.parent_map = cam_cc_parent_map_8,
1428	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1429	.clkr.hw.init = &(const struct clk_init_data) {
1430		.name = "cam_cc_sleep_clk_src",
1431		.parent_data = cam_cc_parent_data_8,
1432		.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1433		.flags = CLK_SET_RATE_PARENT,
1434		.ops = &clk_rcg2_ops,
1435	},
1436};
1437
1438static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1439	F(19200000, P_BI_TCXO, 1, 0, 0),
1440	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1441	{ }
1442};
1443
1444static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1445	.cmd_rcgr = 0x10034,
1446	.mnd_width = 8,
1447	.hid_width = 5,
1448	.parent_map = cam_cc_parent_map_0,
1449	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1450	.clkr.hw.init = &(const struct clk_init_data) {
1451		.name = "cam_cc_slow_ahb_clk_src",
1452		.parent_data = cam_cc_parent_data_0,
1453		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1454		.flags = CLK_SET_RATE_PARENT,
1455		.ops = &clk_rcg2_ops,
1456	},
1457};
1458
1459static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1460	F(19200000, P_BI_TCXO, 1, 0, 0),
1461	{ }
1462};
1463
1464static struct clk_rcg2 cam_cc_xo_clk_src = {
1465	.cmd_rcgr = 0x131f4,
1466	.mnd_width = 0,
1467	.hid_width = 5,
1468	.parent_map = cam_cc_parent_map_9,
1469	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1470	.clkr.hw.init = &(const struct clk_init_data) {
1471		.name = "cam_cc_xo_clk_src",
1472		.parent_data = cam_cc_parent_data_9_ao,
1473		.num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
1474		.flags = CLK_SET_RATE_PARENT,
1475		.ops = &clk_rcg2_ops,
1476	},
1477};
1478
1479static struct clk_branch cam_cc_gdsc_clk = {
1480	.halt_reg = 0x1320c,
1481	.halt_check = BRANCH_HALT,
1482	.clkr = {
1483		.enable_reg = 0x1320c,
1484		.enable_mask = BIT(0),
1485		.hw.init = &(const struct clk_init_data) {
1486			.name = "cam_cc_gdsc_clk",
1487			.parent_hws = (const struct clk_hw*[]) {
1488				&cam_cc_xo_clk_src.clkr.hw,
1489			},
1490			.num_parents = 1,
1491			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1492			.ops = &clk_branch2_ops,
1493		},
1494	},
1495};
1496
1497static struct clk_branch cam_cc_bps_ahb_clk = {
1498	.halt_reg = 0x1004c,
1499	.halt_check = BRANCH_HALT,
1500	.clkr = {
1501		.enable_reg = 0x1004c,
1502		.enable_mask = BIT(0),
1503		.hw.init = &(const struct clk_init_data) {
1504			.name = "cam_cc_bps_ahb_clk",
1505			.parent_hws = (const struct clk_hw*[]) {
1506				&cam_cc_slow_ahb_clk_src.clkr.hw,
1507			},
1508			.num_parents = 1,
1509			.flags = CLK_SET_RATE_PARENT,
1510			.ops = &clk_branch2_ops,
1511		},
1512	},
1513};
1514
1515static struct clk_branch cam_cc_bps_clk = {
1516	.halt_reg = 0x10068,
1517	.halt_check = BRANCH_HALT,
1518	.clkr = {
1519		.enable_reg = 0x10068,
1520		.enable_mask = BIT(0),
1521		.hw.init = &(const struct clk_init_data) {
1522			.name = "cam_cc_bps_clk",
1523			.parent_hws = (const struct clk_hw*[]) {
1524				&cam_cc_bps_clk_src.clkr.hw,
1525			},
1526			.num_parents = 1,
1527			.flags = CLK_SET_RATE_PARENT,
1528			.ops = &clk_branch2_ops,
1529		},
1530	},
1531};
1532
1533static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1534	.halt_reg = 0x10030,
1535	.halt_check = BRANCH_HALT,
1536	.clkr = {
1537		.enable_reg = 0x10030,
1538		.enable_mask = BIT(0),
1539		.hw.init = &(const struct clk_init_data) {
1540			.name = "cam_cc_bps_fast_ahb_clk",
1541			.parent_hws = (const struct clk_hw*[]) {
1542				&cam_cc_fast_ahb_clk_src.clkr.hw,
1543			},
1544			.num_parents = 1,
1545			.flags = CLK_SET_RATE_PARENT,
1546			.ops = &clk_branch2_ops,
1547		},
1548	},
1549};
1550
1551static struct clk_branch cam_cc_camnoc_axi_clk = {
1552	.halt_reg = 0x131ac,
1553	.halt_check = BRANCH_HALT,
1554	.clkr = {
1555		.enable_reg = 0x131ac,
1556		.enable_mask = BIT(0),
1557		.hw.init = &(const struct clk_init_data) {
1558			.name = "cam_cc_camnoc_axi_clk",
1559			.parent_hws = (const struct clk_hw*[]) {
1560				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1561			},
1562			.num_parents = 1,
1563			.flags = CLK_SET_RATE_PARENT,
1564			.ops = &clk_branch2_ops,
1565		},
1566	},
1567};
1568
1569static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1570	.halt_reg = 0x131b4,
1571	.halt_check = BRANCH_HALT,
1572	.clkr = {
1573		.enable_reg = 0x131b4,
1574		.enable_mask = BIT(0),
1575		.hw.init = &(const struct clk_init_data) {
1576			.name = "cam_cc_camnoc_dcd_xo_clk",
1577			.parent_hws = (const struct clk_hw*[]) {
1578				&cam_cc_xo_clk_src.clkr.hw,
1579			},
1580			.num_parents = 1,
1581			.flags = CLK_SET_RATE_PARENT,
1582			.ops = &clk_branch2_ops,
1583		},
1584	},
1585};
1586
1587static struct clk_branch cam_cc_cci_0_clk = {
1588	.halt_reg = 0x13144,
1589	.halt_check = BRANCH_HALT,
1590	.clkr = {
1591		.enable_reg = 0x13144,
1592		.enable_mask = BIT(0),
1593		.hw.init = &(const struct clk_init_data) {
1594			.name = "cam_cc_cci_0_clk",
1595			.parent_hws = (const struct clk_hw*[]) {
1596				&cam_cc_cci_0_clk_src.clkr.hw,
1597			},
1598			.num_parents = 1,
1599			.flags = CLK_SET_RATE_PARENT,
1600			.ops = &clk_branch2_ops,
1601		},
1602	},
1603};
1604
1605static struct clk_branch cam_cc_cci_1_clk = {
1606	.halt_reg = 0x13160,
1607	.halt_check = BRANCH_HALT,
1608	.clkr = {
1609		.enable_reg = 0x13160,
1610		.enable_mask = BIT(0),
1611		.hw.init = &(const struct clk_init_data) {
1612			.name = "cam_cc_cci_1_clk",
1613			.parent_hws = (const struct clk_hw*[]) {
1614				&cam_cc_cci_1_clk_src.clkr.hw,
1615			},
1616			.num_parents = 1,
1617			.flags = CLK_SET_RATE_PARENT,
1618			.ops = &clk_branch2_ops,
1619		},
1620	},
1621};
1622
1623static struct clk_branch cam_cc_core_ahb_clk = {
1624	.halt_reg = 0x131f0,
1625	.halt_check = BRANCH_HALT_DELAY,
1626	.clkr = {
1627		.enable_reg = 0x131f0,
1628		.enable_mask = BIT(0),
1629		.hw.init = &(const struct clk_init_data) {
1630			.name = "cam_cc_core_ahb_clk",
1631			.parent_hws = (const struct clk_hw*[]) {
1632				&cam_cc_slow_ahb_clk_src.clkr.hw,
1633			},
1634			.num_parents = 1,
1635			.flags = CLK_SET_RATE_PARENT,
1636			.ops = &clk_branch2_ops,
1637		},
1638	},
1639};
1640
1641static struct clk_branch cam_cc_cpas_ahb_clk = {
1642	.halt_reg = 0x13164,
1643	.halt_check = BRANCH_HALT,
1644	.clkr = {
1645		.enable_reg = 0x13164,
1646		.enable_mask = BIT(0),
1647		.hw.init = &(const struct clk_init_data) {
1648			.name = "cam_cc_cpas_ahb_clk",
1649			.parent_hws = (const struct clk_hw*[]) {
1650				&cam_cc_slow_ahb_clk_src.clkr.hw,
1651			},
1652			.num_parents = 1,
1653			.flags = CLK_SET_RATE_PARENT,
1654			.ops = &clk_branch2_ops,
1655		},
1656	},
1657};
1658
1659static struct clk_branch cam_cc_cpas_bps_clk = {
1660	.halt_reg = 0x10070,
1661	.halt_check = BRANCH_HALT,
1662	.clkr = {
1663		.enable_reg = 0x10070,
1664		.enable_mask = BIT(0),
1665		.hw.init = &(const struct clk_init_data) {
1666			.name = "cam_cc_cpas_bps_clk",
1667			.parent_hws = (const struct clk_hw*[]) {
1668				&cam_cc_bps_clk_src.clkr.hw,
1669			},
1670			.num_parents = 1,
1671			.flags = CLK_SET_RATE_PARENT,
1672			.ops = &clk_branch2_ops,
1673		},
1674	},
1675};
1676
1677static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1678	.halt_reg = 0x1316c,
1679	.halt_check = BRANCH_HALT,
1680	.clkr = {
1681		.enable_reg = 0x1316c,
1682		.enable_mask = BIT(0),
1683		.hw.init = &(const struct clk_init_data) {
1684			.name = "cam_cc_cpas_fast_ahb_clk",
1685			.parent_hws = (const struct clk_hw*[]) {
1686				&cam_cc_fast_ahb_clk_src.clkr.hw,
1687			},
1688			.num_parents = 1,
1689			.flags = CLK_SET_RATE_PARENT,
1690			.ops = &clk_branch2_ops,
1691		},
1692	},
1693};
1694
1695static struct clk_branch cam_cc_cpas_ife_0_clk = {
1696	.halt_reg = 0x11038,
1697	.halt_check = BRANCH_HALT,
1698	.clkr = {
1699		.enable_reg = 0x11038,
1700		.enable_mask = BIT(0),
1701		.hw.init = &(const struct clk_init_data) {
1702			.name = "cam_cc_cpas_ife_0_clk",
1703			.parent_hws = (const struct clk_hw*[]) {
1704				&cam_cc_ife_0_clk_src.clkr.hw,
1705			},
1706			.num_parents = 1,
1707			.flags = CLK_SET_RATE_PARENT,
1708			.ops = &clk_branch2_ops,
1709		},
1710	},
1711};
1712
1713static struct clk_branch cam_cc_cpas_ife_1_clk = {
1714	.halt_reg = 0x12038,
1715	.halt_check = BRANCH_HALT,
1716	.clkr = {
1717		.enable_reg = 0x12038,
1718		.enable_mask = BIT(0),
1719		.hw.init = &(const struct clk_init_data) {
1720			.name = "cam_cc_cpas_ife_1_clk",
1721			.parent_hws = (const struct clk_hw*[]) {
1722				&cam_cc_ife_1_clk_src.clkr.hw,
1723			},
1724			.num_parents = 1,
1725			.flags = CLK_SET_RATE_PARENT,
1726			.ops = &clk_branch2_ops,
1727		},
1728	},
1729};
1730
1731static struct clk_branch cam_cc_cpas_ife_2_clk = {
1732	.halt_reg = 0x12084,
1733	.halt_check = BRANCH_HALT,
1734	.clkr = {
1735		.enable_reg = 0x12084,
1736		.enable_mask = BIT(0),
1737		.hw.init = &(const struct clk_init_data) {
1738			.name = "cam_cc_cpas_ife_2_clk",
1739			.parent_hws = (const struct clk_hw*[]) {
1740				&cam_cc_ife_2_clk_src.clkr.hw,
1741			},
1742			.num_parents = 1,
1743			.flags = CLK_SET_RATE_PARENT,
1744			.ops = &clk_branch2_ops,
1745		},
1746	},
1747};
1748
1749static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1750	.halt_reg = 0x13020,
1751	.halt_check = BRANCH_HALT,
1752	.clkr = {
1753		.enable_reg = 0x13020,
1754		.enable_mask = BIT(0),
1755		.hw.init = &(const struct clk_init_data) {
1756			.name = "cam_cc_cpas_ife_lite_clk",
1757			.parent_hws = (const struct clk_hw*[]) {
1758				&cam_cc_ife_lite_clk_src.clkr.hw,
1759			},
1760			.num_parents = 1,
1761			.flags = CLK_SET_RATE_PARENT,
1762			.ops = &clk_branch2_ops,
1763		},
1764	},
1765};
1766
1767static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
1768	.halt_reg = 0x100ac,
1769	.halt_check = BRANCH_HALT,
1770	.clkr = {
1771		.enable_reg = 0x100ac,
1772		.enable_mask = BIT(0),
1773		.hw.init = &(const struct clk_init_data) {
1774			.name = "cam_cc_cpas_ipe_nps_clk",
1775			.parent_hws = (const struct clk_hw*[]) {
1776				&cam_cc_ipe_nps_clk_src.clkr.hw,
1777			},
1778			.num_parents = 1,
1779			.flags = CLK_SET_RATE_PARENT,
1780			.ops = &clk_branch2_ops,
1781		},
1782	},
1783};
1784
1785static struct clk_branch cam_cc_cpas_sbi_clk = {
1786	.halt_reg = 0x100ec,
1787	.halt_check = BRANCH_HALT,
1788	.clkr = {
1789		.enable_reg = 0x100ec,
1790		.enable_mask = BIT(0),
1791		.hw.init = &(const struct clk_init_data) {
1792			.name = "cam_cc_cpas_sbi_clk",
1793			.parent_hws = (const struct clk_hw*[]) {
1794				&cam_cc_ife_0_clk_src.clkr.hw,
1795			},
1796			.num_parents = 1,
1797			.flags = CLK_SET_RATE_PARENT,
1798			.ops = &clk_branch2_ops,
1799		},
1800	},
1801};
1802
1803static struct clk_branch cam_cc_cpas_sfe_0_clk = {
1804	.halt_reg = 0x13084,
1805	.halt_check = BRANCH_HALT,
1806	.clkr = {
1807		.enable_reg = 0x13084,
1808		.enable_mask = BIT(0),
1809		.hw.init = &(const struct clk_init_data) {
1810			.name = "cam_cc_cpas_sfe_0_clk",
1811			.parent_hws = (const struct clk_hw*[]) {
1812				&cam_cc_sfe_0_clk_src.clkr.hw,
1813			},
1814			.num_parents = 1,
1815			.flags = CLK_SET_RATE_PARENT,
1816			.ops = &clk_branch2_ops,
1817		},
1818	},
1819};
1820
1821static struct clk_branch cam_cc_cpas_sfe_1_clk = {
1822	.halt_reg = 0x130cc,
1823	.halt_check = BRANCH_HALT,
1824	.clkr = {
1825		.enable_reg = 0x130cc,
1826		.enable_mask = BIT(0),
1827		.hw.init = &(const struct clk_init_data) {
1828			.name = "cam_cc_cpas_sfe_1_clk",
1829			.parent_hws = (const struct clk_hw*[]) {
1830				&cam_cc_sfe_1_clk_src.clkr.hw,
1831			},
1832			.num_parents = 1,
1833			.flags = CLK_SET_RATE_PARENT,
1834			.ops = &clk_branch2_ops,
1835		},
1836	},
1837};
1838
1839static struct clk_branch cam_cc_csi0phytimer_clk = {
1840	.halt_reg = 0x150f8,
1841	.halt_check = BRANCH_HALT,
1842	.clkr = {
1843		.enable_reg = 0x150f8,
1844		.enable_mask = BIT(0),
1845		.hw.init = &(const struct clk_init_data) {
1846			.name = "cam_cc_csi0phytimer_clk",
1847			.parent_hws = (const struct clk_hw*[]) {
1848				&cam_cc_csi0phytimer_clk_src.clkr.hw,
1849			},
1850			.num_parents = 1,
1851			.flags = CLK_SET_RATE_PARENT,
1852			.ops = &clk_branch2_ops,
1853		},
1854	},
1855};
1856
1857static struct clk_branch cam_cc_csi1phytimer_clk = {
1858	.halt_reg = 0x1511c,
1859	.halt_check = BRANCH_HALT,
1860	.clkr = {
1861		.enable_reg = 0x1511c,
1862		.enable_mask = BIT(0),
1863		.hw.init = &(const struct clk_init_data) {
1864			.name = "cam_cc_csi1phytimer_clk",
1865			.parent_hws = (const struct clk_hw*[]) {
1866				&cam_cc_csi1phytimer_clk_src.clkr.hw,
1867			},
1868			.num_parents = 1,
1869			.flags = CLK_SET_RATE_PARENT,
1870			.ops = &clk_branch2_ops,
1871		},
1872	},
1873};
1874
1875static struct clk_branch cam_cc_csi2phytimer_clk = {
1876	.halt_reg = 0x1513c,
1877	.halt_check = BRANCH_HALT,
1878	.clkr = {
1879		.enable_reg = 0x1513c,
1880		.enable_mask = BIT(0),
1881		.hw.init = &(const struct clk_init_data) {
1882			.name = "cam_cc_csi2phytimer_clk",
1883			.parent_hws = (const struct clk_hw*[]) {
1884				&cam_cc_csi2phytimer_clk_src.clkr.hw,
1885			},
1886			.num_parents = 1,
1887			.flags = CLK_SET_RATE_PARENT,
1888			.ops = &clk_branch2_ops,
1889		},
1890	},
1891};
1892
1893static struct clk_branch cam_cc_csi3phytimer_clk = {
1894	.halt_reg = 0x15164,
1895	.halt_check = BRANCH_HALT,
1896	.clkr = {
1897		.enable_reg = 0x15164,
1898		.enable_mask = BIT(0),
1899		.hw.init = &(const struct clk_init_data) {
1900			.name = "cam_cc_csi3phytimer_clk",
1901			.parent_hws = (const struct clk_hw*[]) {
1902				&cam_cc_csi3phytimer_clk_src.clkr.hw,
1903			},
1904			.num_parents = 1,
1905			.flags = CLK_SET_RATE_PARENT,
1906			.ops = &clk_branch2_ops,
1907		},
1908	},
1909};
1910
1911static struct clk_branch cam_cc_csi4phytimer_clk = {
1912	.halt_reg = 0x15184,
1913	.halt_check = BRANCH_HALT,
1914	.clkr = {
1915		.enable_reg = 0x15184,
1916		.enable_mask = BIT(0),
1917		.hw.init = &(const struct clk_init_data) {
1918			.name = "cam_cc_csi4phytimer_clk",
1919			.parent_hws = (const struct clk_hw*[]) {
1920				&cam_cc_csi4phytimer_clk_src.clkr.hw,
1921			},
1922			.num_parents = 1,
1923			.flags = CLK_SET_RATE_PARENT,
1924			.ops = &clk_branch2_ops,
1925		},
1926	},
1927};
1928
1929static struct clk_branch cam_cc_csi5phytimer_clk = {
1930	.halt_reg = 0x151a4,
1931	.halt_check = BRANCH_HALT,
1932	.clkr = {
1933		.enable_reg = 0x151a4,
1934		.enable_mask = BIT(0),
1935		.hw.init = &(const struct clk_init_data) {
1936			.name = "cam_cc_csi5phytimer_clk",
1937			.parent_hws = (const struct clk_hw*[]) {
1938				&cam_cc_csi5phytimer_clk_src.clkr.hw,
1939			},
1940			.num_parents = 1,
1941			.flags = CLK_SET_RATE_PARENT,
1942			.ops = &clk_branch2_ops,
1943		},
1944	},
1945};
1946
1947static struct clk_branch cam_cc_csid_clk = {
1948	.halt_reg = 0x1318c,
1949	.halt_check = BRANCH_HALT,
1950	.clkr = {
1951		.enable_reg = 0x1318c,
1952		.enable_mask = BIT(0),
1953		.hw.init = &(const struct clk_init_data) {
1954			.name = "cam_cc_csid_clk",
1955			.parent_hws = (const struct clk_hw*[]) {
1956				&cam_cc_csid_clk_src.clkr.hw,
1957			},
1958			.num_parents = 1,
1959			.flags = CLK_SET_RATE_PARENT,
1960			.ops = &clk_branch2_ops,
1961		},
1962	},
1963};
1964
1965static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
1966	.halt_reg = 0x15100,
1967	.halt_check = BRANCH_HALT,
1968	.clkr = {
1969		.enable_reg = 0x15100,
1970		.enable_mask = BIT(0),
1971		.hw.init = &(const struct clk_init_data) {
1972			.name = "cam_cc_csid_csiphy_rx_clk",
1973			.parent_hws = (const struct clk_hw*[]) {
1974				&cam_cc_cphy_rx_clk_src.clkr.hw,
1975			},
1976			.num_parents = 1,
1977			.flags = CLK_SET_RATE_PARENT,
1978			.ops = &clk_branch2_ops,
1979		},
1980	},
1981};
1982
1983static struct clk_branch cam_cc_csiphy0_clk = {
1984	.halt_reg = 0x150fc,
1985	.halt_check = BRANCH_HALT,
1986	.clkr = {
1987		.enable_reg = 0x150fc,
1988		.enable_mask = BIT(0),
1989		.hw.init = &(const struct clk_init_data) {
1990			.name = "cam_cc_csiphy0_clk",
1991			.parent_hws = (const struct clk_hw*[]) {
1992				&cam_cc_cphy_rx_clk_src.clkr.hw,
1993			},
1994			.num_parents = 1,
1995			.flags = CLK_SET_RATE_PARENT,
1996			.ops = &clk_branch2_ops,
1997		},
1998	},
1999};
2000
2001static struct clk_branch cam_cc_csiphy1_clk = {
2002	.halt_reg = 0x15120,
2003	.halt_check = BRANCH_HALT,
2004	.clkr = {
2005		.enable_reg = 0x15120,
2006		.enable_mask = BIT(0),
2007		.hw.init = &(const struct clk_init_data) {
2008			.name = "cam_cc_csiphy1_clk",
2009			.parent_hws = (const struct clk_hw*[]) {
2010				&cam_cc_cphy_rx_clk_src.clkr.hw,
2011			},
2012			.num_parents = 1,
2013			.flags = CLK_SET_RATE_PARENT,
2014			.ops = &clk_branch2_ops,
2015		},
2016	},
2017};
2018
2019static struct clk_branch cam_cc_csiphy2_clk = {
2020	.halt_reg = 0x15140,
2021	.halt_check = BRANCH_HALT,
2022	.clkr = {
2023		.enable_reg = 0x15140,
2024		.enable_mask = BIT(0),
2025		.hw.init = &(const struct clk_init_data) {
2026			.name = "cam_cc_csiphy2_clk",
2027			.parent_hws = (const struct clk_hw*[]) {
2028				&cam_cc_cphy_rx_clk_src.clkr.hw,
2029			},
2030			.num_parents = 1,
2031			.flags = CLK_SET_RATE_PARENT,
2032			.ops = &clk_branch2_ops,
2033		},
2034	},
2035};
2036
2037static struct clk_branch cam_cc_csiphy3_clk = {
2038	.halt_reg = 0x15168,
2039	.halt_check = BRANCH_HALT,
2040	.clkr = {
2041		.enable_reg = 0x15168,
2042		.enable_mask = BIT(0),
2043		.hw.init = &(const struct clk_init_data) {
2044			.name = "cam_cc_csiphy3_clk",
2045			.parent_hws = (const struct clk_hw*[]) {
2046				&cam_cc_cphy_rx_clk_src.clkr.hw,
2047			},
2048			.num_parents = 1,
2049			.flags = CLK_SET_RATE_PARENT,
2050			.ops = &clk_branch2_ops,
2051		},
2052	},
2053};
2054
2055static struct clk_branch cam_cc_csiphy4_clk = {
2056	.halt_reg = 0x15188,
2057	.halt_check = BRANCH_HALT,
2058	.clkr = {
2059		.enable_reg = 0x15188,
2060		.enable_mask = BIT(0),
2061		.hw.init = &(const struct clk_init_data) {
2062			.name = "cam_cc_csiphy4_clk",
2063			.parent_hws = (const struct clk_hw*[]) {
2064				&cam_cc_cphy_rx_clk_src.clkr.hw,
2065			},
2066			.num_parents = 1,
2067			.flags = CLK_SET_RATE_PARENT,
2068			.ops = &clk_branch2_ops,
2069		},
2070	},
2071};
2072
2073static struct clk_branch cam_cc_csiphy5_clk = {
2074	.halt_reg = 0x151a8,
2075	.halt_check = BRANCH_HALT,
2076	.clkr = {
2077		.enable_reg = 0x151a8,
2078		.enable_mask = BIT(0),
2079		.hw.init = &(const struct clk_init_data) {
2080			.name = "cam_cc_csiphy5_clk",
2081			.parent_hws = (const struct clk_hw*[]) {
2082				&cam_cc_cphy_rx_clk_src.clkr.hw,
2083			},
2084			.num_parents = 1,
2085			.flags = CLK_SET_RATE_PARENT,
2086			.ops = &clk_branch2_ops,
2087		},
2088	},
2089};
2090
2091static struct clk_branch cam_cc_icp_ahb_clk = {
2092	.halt_reg = 0x13128,
2093	.halt_check = BRANCH_HALT,
2094	.clkr = {
2095		.enable_reg = 0x13128,
2096		.enable_mask = BIT(0),
2097		.hw.init = &(const struct clk_init_data) {
2098			.name = "cam_cc_icp_ahb_clk",
2099			.parent_hws = (const struct clk_hw*[]) {
2100				&cam_cc_slow_ahb_clk_src.clkr.hw,
2101			},
2102			.num_parents = 1,
2103			.flags = CLK_SET_RATE_PARENT,
2104			.ops = &clk_branch2_ops,
2105		},
2106	},
2107};
2108
2109static struct clk_branch cam_cc_icp_clk = {
2110	.halt_reg = 0x13120,
2111	.halt_check = BRANCH_HALT,
2112	.clkr = {
2113		.enable_reg = 0x13120,
2114		.enable_mask = BIT(0),
2115		.hw.init = &(const struct clk_init_data) {
2116			.name = "cam_cc_icp_clk",
2117			.parent_hws = (const struct clk_hw*[]) {
2118				&cam_cc_icp_clk_src.clkr.hw,
2119			},
2120			.num_parents = 1,
2121			.flags = CLK_SET_RATE_PARENT,
2122			.ops = &clk_branch2_ops,
2123		},
2124	},
2125};
2126
2127static struct clk_branch cam_cc_ife_0_clk = {
2128	.halt_reg = 0x11030,
2129	.halt_check = BRANCH_HALT,
2130	.clkr = {
2131		.enable_reg = 0x11030,
2132		.enable_mask = BIT(0),
2133		.hw.init = &(const struct clk_init_data) {
2134			.name = "cam_cc_ife_0_clk",
2135			.parent_hws = (const struct clk_hw*[]) {
2136				&cam_cc_ife_0_clk_src.clkr.hw,
2137			},
2138			.num_parents = 1,
2139			.flags = CLK_SET_RATE_PARENT,
2140			.ops = &clk_branch2_ops,
2141		},
2142	},
2143};
2144
2145static struct clk_branch cam_cc_ife_0_dsp_clk = {
2146	.halt_reg = 0x1103c,
2147	.halt_check = BRANCH_HALT,
2148	.clkr = {
2149		.enable_reg = 0x1103c,
2150		.enable_mask = BIT(0),
2151		.hw.init = &(const struct clk_init_data) {
2152			.name = "cam_cc_ife_0_dsp_clk",
2153			.parent_hws = (const struct clk_hw*[]) {
2154				&cam_cc_ife_0_clk_src.clkr.hw,
2155			},
2156			.num_parents = 1,
2157			.flags = CLK_SET_RATE_PARENT,
2158			.ops = &clk_branch2_ops,
2159		},
2160	},
2161};
2162
2163static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
2164	.halt_reg = 0x11048,
2165	.halt_check = BRANCH_HALT,
2166	.clkr = {
2167		.enable_reg = 0x11048,
2168		.enable_mask = BIT(0),
2169		.hw.init = &(const struct clk_init_data) {
2170			.name = "cam_cc_ife_0_fast_ahb_clk",
2171			.parent_hws = (const struct clk_hw*[]) {
2172				&cam_cc_fast_ahb_clk_src.clkr.hw,
2173			},
2174			.num_parents = 1,
2175			.flags = CLK_SET_RATE_PARENT,
2176			.ops = &clk_branch2_ops,
2177		},
2178	},
2179};
2180
2181static struct clk_branch cam_cc_ife_1_clk = {
2182	.halt_reg = 0x12030,
2183	.halt_check = BRANCH_HALT,
2184	.clkr = {
2185		.enable_reg = 0x12030,
2186		.enable_mask = BIT(0),
2187		.hw.init = &(const struct clk_init_data) {
2188			.name = "cam_cc_ife_1_clk",
2189			.parent_hws = (const struct clk_hw*[]) {
2190				&cam_cc_ife_1_clk_src.clkr.hw,
2191			},
2192			.num_parents = 1,
2193			.flags = CLK_SET_RATE_PARENT,
2194			.ops = &clk_branch2_ops,
2195		},
2196	},
2197};
2198
2199static struct clk_branch cam_cc_ife_1_dsp_clk = {
2200	.halt_reg = 0x1203c,
2201	.halt_check = BRANCH_HALT,
2202	.clkr = {
2203		.enable_reg = 0x1203c,
2204		.enable_mask = BIT(0),
2205		.hw.init = &(const struct clk_init_data) {
2206			.name = "cam_cc_ife_1_dsp_clk",
2207			.parent_hws = (const struct clk_hw*[]) {
2208				&cam_cc_ife_1_clk_src.clkr.hw,
2209			},
2210			.num_parents = 1,
2211			.flags = CLK_SET_RATE_PARENT,
2212			.ops = &clk_branch2_ops,
2213		},
2214	},
2215};
2216
2217static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2218	.halt_reg = 0x12048,
2219	.halt_check = BRANCH_HALT,
2220	.clkr = {
2221		.enable_reg = 0x12048,
2222		.enable_mask = BIT(0),
2223		.hw.init = &(const struct clk_init_data) {
2224			.name = "cam_cc_ife_1_fast_ahb_clk",
2225			.parent_hws = (const struct clk_hw*[]) {
2226				&cam_cc_fast_ahb_clk_src.clkr.hw,
2227			},
2228			.num_parents = 1,
2229			.flags = CLK_SET_RATE_PARENT,
2230			.ops = &clk_branch2_ops,
2231		},
2232	},
2233};
2234
2235static struct clk_branch cam_cc_ife_2_clk = {
2236	.halt_reg = 0x1207c,
2237	.halt_check = BRANCH_HALT,
2238	.clkr = {
2239		.enable_reg = 0x1207c,
2240		.enable_mask = BIT(0),
2241		.hw.init = &(const struct clk_init_data) {
2242			.name = "cam_cc_ife_2_clk",
2243			.parent_hws = (const struct clk_hw*[]) {
2244				&cam_cc_ife_2_clk_src.clkr.hw,
2245			},
2246			.num_parents = 1,
2247			.flags = CLK_SET_RATE_PARENT,
2248			.ops = &clk_branch2_ops,
2249		},
2250	},
2251};
2252
2253static struct clk_branch cam_cc_ife_2_dsp_clk = {
2254	.halt_reg = 0x12088,
2255	.halt_check = BRANCH_HALT,
2256	.clkr = {
2257		.enable_reg = 0x12088,
2258		.enable_mask = BIT(0),
2259		.hw.init = &(const struct clk_init_data) {
2260			.name = "cam_cc_ife_2_dsp_clk",
2261			.parent_hws = (const struct clk_hw*[]) {
2262				&cam_cc_ife_2_clk_src.clkr.hw,
2263			},
2264			.num_parents = 1,
2265			.flags = CLK_SET_RATE_PARENT,
2266			.ops = &clk_branch2_ops,
2267		},
2268	},
2269};
2270
2271static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2272	.halt_reg = 0x12094,
2273	.halt_check = BRANCH_HALT,
2274	.clkr = {
2275		.enable_reg = 0x12094,
2276		.enable_mask = BIT(0),
2277		.hw.init = &(const struct clk_init_data) {
2278			.name = "cam_cc_ife_2_fast_ahb_clk",
2279			.parent_hws = (const struct clk_hw*[]) {
2280				&cam_cc_fast_ahb_clk_src.clkr.hw,
2281			},
2282			.num_parents = 1,
2283			.flags = CLK_SET_RATE_PARENT,
2284			.ops = &clk_branch2_ops,
2285		},
2286	},
2287};
2288
2289static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2290	.halt_reg = 0x13048,
2291	.halt_check = BRANCH_HALT,
2292	.clkr = {
2293		.enable_reg = 0x13048,
2294		.enable_mask = BIT(0),
2295		.hw.init = &(const struct clk_init_data) {
2296			.name = "cam_cc_ife_lite_ahb_clk",
2297			.parent_hws = (const struct clk_hw*[]) {
2298				&cam_cc_slow_ahb_clk_src.clkr.hw,
2299			},
2300			.num_parents = 1,
2301			.flags = CLK_SET_RATE_PARENT,
2302			.ops = &clk_branch2_ops,
2303		},
2304	},
2305};
2306
2307static struct clk_branch cam_cc_ife_lite_clk = {
2308	.halt_reg = 0x13018,
2309	.halt_check = BRANCH_HALT,
2310	.clkr = {
2311		.enable_reg = 0x13018,
2312		.enable_mask = BIT(0),
2313		.hw.init = &(const struct clk_init_data) {
2314			.name = "cam_cc_ife_lite_clk",
2315			.parent_hws = (const struct clk_hw*[]) {
2316				&cam_cc_ife_lite_clk_src.clkr.hw,
2317			},
2318			.num_parents = 1,
2319			.flags = CLK_SET_RATE_PARENT,
2320			.ops = &clk_branch2_ops,
2321		},
2322	},
2323};
2324
2325static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2326	.halt_reg = 0x13044,
2327	.halt_check = BRANCH_HALT,
2328	.clkr = {
2329		.enable_reg = 0x13044,
2330		.enable_mask = BIT(0),
2331		.hw.init = &(const struct clk_init_data) {
2332			.name = "cam_cc_ife_lite_cphy_rx_clk",
2333			.parent_hws = (const struct clk_hw*[]) {
2334				&cam_cc_cphy_rx_clk_src.clkr.hw,
2335			},
2336			.num_parents = 1,
2337			.flags = CLK_SET_RATE_PARENT,
2338			.ops = &clk_branch2_ops,
2339		},
2340	},
2341};
2342
2343static struct clk_branch cam_cc_ife_lite_csid_clk = {
2344	.halt_reg = 0x1303c,
2345	.halt_check = BRANCH_HALT,
2346	.clkr = {
2347		.enable_reg = 0x1303c,
2348		.enable_mask = BIT(0),
2349		.hw.init = &(const struct clk_init_data) {
2350			.name = "cam_cc_ife_lite_csid_clk",
2351			.parent_hws = (const struct clk_hw*[]) {
2352				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
2353			},
2354			.num_parents = 1,
2355			.flags = CLK_SET_RATE_PARENT,
2356			.ops = &clk_branch2_ops,
2357		},
2358	},
2359};
2360
2361static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2362	.halt_reg = 0x100c0,
2363	.halt_check = BRANCH_HALT,
2364	.clkr = {
2365		.enable_reg = 0x100c0,
2366		.enable_mask = BIT(0),
2367		.hw.init = &(const struct clk_init_data) {
2368			.name = "cam_cc_ipe_nps_ahb_clk",
2369			.parent_hws = (const struct clk_hw*[]) {
2370				&cam_cc_slow_ahb_clk_src.clkr.hw,
2371			},
2372			.num_parents = 1,
2373			.flags = CLK_SET_RATE_PARENT,
2374			.ops = &clk_branch2_ops,
2375		},
2376	},
2377};
2378
2379static struct clk_branch cam_cc_ipe_nps_clk = {
2380	.halt_reg = 0x100a4,
2381	.halt_check = BRANCH_HALT,
2382	.clkr = {
2383		.enable_reg = 0x100a4,
2384		.enable_mask = BIT(0),
2385		.hw.init = &(const struct clk_init_data) {
2386			.name = "cam_cc_ipe_nps_clk",
2387			.parent_hws = (const struct clk_hw*[]) {
2388				&cam_cc_ipe_nps_clk_src.clkr.hw,
2389			},
2390			.num_parents = 1,
2391			.flags = CLK_SET_RATE_PARENT,
2392			.ops = &clk_branch2_ops,
2393		},
2394	},
2395};
2396
2397static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2398	.halt_reg = 0x100c4,
2399	.halt_check = BRANCH_HALT,
2400	.clkr = {
2401		.enable_reg = 0x100c4,
2402		.enable_mask = BIT(0),
2403		.hw.init = &(const struct clk_init_data) {
2404			.name = "cam_cc_ipe_nps_fast_ahb_clk",
2405			.parent_hws = (const struct clk_hw*[]) {
2406				&cam_cc_fast_ahb_clk_src.clkr.hw,
2407			},
2408			.num_parents = 1,
2409			.flags = CLK_SET_RATE_PARENT,
2410			.ops = &clk_branch2_ops,
2411		},
2412	},
2413};
2414
2415static struct clk_branch cam_cc_ipe_pps_clk = {
2416	.halt_reg = 0x100b0,
2417	.halt_check = BRANCH_HALT,
2418	.clkr = {
2419		.enable_reg = 0x100b0,
2420		.enable_mask = BIT(0),
2421		.hw.init = &(const struct clk_init_data) {
2422			.name = "cam_cc_ipe_pps_clk",
2423			.parent_hws = (const struct clk_hw*[]) {
2424				&cam_cc_ipe_nps_clk_src.clkr.hw,
2425			},
2426			.num_parents = 1,
2427			.flags = CLK_SET_RATE_PARENT,
2428			.ops = &clk_branch2_ops,
2429		},
2430	},
2431};
2432
2433static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2434	.halt_reg = 0x100c8,
2435	.halt_check = BRANCH_HALT,
2436	.clkr = {
2437		.enable_reg = 0x100c8,
2438		.enable_mask = BIT(0),
2439		.hw.init = &(const struct clk_init_data) {
2440			.name = "cam_cc_ipe_pps_fast_ahb_clk",
2441			.parent_hws = (const struct clk_hw*[]) {
2442				&cam_cc_fast_ahb_clk_src.clkr.hw,
2443			},
2444			.num_parents = 1,
2445			.flags = CLK_SET_RATE_PARENT,
2446			.ops = &clk_branch2_ops,
2447		},
2448	},
2449};
2450
2451static struct clk_branch cam_cc_jpeg_clk = {
2452	.halt_reg = 0x130f4,
2453	.halt_check = BRANCH_HALT,
2454	.clkr = {
2455		.enable_reg = 0x130f4,
2456		.enable_mask = BIT(0),
2457		.hw.init = &(const struct clk_init_data) {
2458			.name = "cam_cc_jpeg_clk",
2459			.parent_hws = (const struct clk_hw*[]) {
2460				&cam_cc_jpeg_clk_src.clkr.hw,
2461			},
2462			.num_parents = 1,
2463			.flags = CLK_SET_RATE_PARENT,
2464			.ops = &clk_branch2_ops,
2465		},
2466	},
2467};
2468
2469static struct clk_branch cam_cc_mclk0_clk = {
2470	.halt_reg = 0x15018,
2471	.halt_check = BRANCH_HALT,
2472	.clkr = {
2473		.enable_reg = 0x15018,
2474		.enable_mask = BIT(0),
2475		.hw.init = &(const struct clk_init_data) {
2476			.name = "cam_cc_mclk0_clk",
2477			.parent_hws = (const struct clk_hw*[]) {
2478				&cam_cc_mclk0_clk_src.clkr.hw,
2479			},
2480			.num_parents = 1,
2481			.flags = CLK_SET_RATE_PARENT,
2482			.ops = &clk_branch2_ops,
2483		},
2484	},
2485};
2486
2487static struct clk_branch cam_cc_mclk1_clk = {
2488	.halt_reg = 0x15034,
2489	.halt_check = BRANCH_HALT,
2490	.clkr = {
2491		.enable_reg = 0x15034,
2492		.enable_mask = BIT(0),
2493		.hw.init = &(const struct clk_init_data) {
2494			.name = "cam_cc_mclk1_clk",
2495			.parent_hws = (const struct clk_hw*[]) {
2496				&cam_cc_mclk1_clk_src.clkr.hw,
2497			},
2498			.num_parents = 1,
2499			.flags = CLK_SET_RATE_PARENT,
2500			.ops = &clk_branch2_ops,
2501		},
2502	},
2503};
2504
2505static struct clk_branch cam_cc_mclk2_clk = {
2506	.halt_reg = 0x15050,
2507	.halt_check = BRANCH_HALT,
2508	.clkr = {
2509		.enable_reg = 0x15050,
2510		.enable_mask = BIT(0),
2511		.hw.init = &(const struct clk_init_data) {
2512			.name = "cam_cc_mclk2_clk",
2513			.parent_hws = (const struct clk_hw*[]) {
2514				&cam_cc_mclk2_clk_src.clkr.hw,
2515			},
2516			.num_parents = 1,
2517			.flags = CLK_SET_RATE_PARENT,
2518			.ops = &clk_branch2_ops,
2519		},
2520	},
2521};
2522
2523static struct clk_branch cam_cc_mclk3_clk = {
2524	.halt_reg = 0x1506c,
2525	.halt_check = BRANCH_HALT,
2526	.clkr = {
2527		.enable_reg = 0x1506c,
2528		.enable_mask = BIT(0),
2529		.hw.init = &(const struct clk_init_data) {
2530			.name = "cam_cc_mclk3_clk",
2531			.parent_hws = (const struct clk_hw*[]) {
2532				&cam_cc_mclk3_clk_src.clkr.hw,
2533			},
2534			.num_parents = 1,
2535			.flags = CLK_SET_RATE_PARENT,
2536			.ops = &clk_branch2_ops,
2537		},
2538	},
2539};
2540
2541static struct clk_branch cam_cc_mclk4_clk = {
2542	.halt_reg = 0x15088,
2543	.halt_check = BRANCH_HALT,
2544	.clkr = {
2545		.enable_reg = 0x15088,
2546		.enable_mask = BIT(0),
2547		.hw.init = &(const struct clk_init_data) {
2548			.name = "cam_cc_mclk4_clk",
2549			.parent_hws = (const struct clk_hw*[]) {
2550				&cam_cc_mclk4_clk_src.clkr.hw,
2551			},
2552			.num_parents = 1,
2553			.flags = CLK_SET_RATE_PARENT,
2554			.ops = &clk_branch2_ops,
2555		},
2556	},
2557};
2558
2559static struct clk_branch cam_cc_mclk5_clk = {
2560	.halt_reg = 0x150a4,
2561	.halt_check = BRANCH_HALT,
2562	.clkr = {
2563		.enable_reg = 0x150a4,
2564		.enable_mask = BIT(0),
2565		.hw.init = &(const struct clk_init_data) {
2566			.name = "cam_cc_mclk5_clk",
2567			.parent_hws = (const struct clk_hw*[]) {
2568				&cam_cc_mclk5_clk_src.clkr.hw,
2569			},
2570			.num_parents = 1,
2571			.flags = CLK_SET_RATE_PARENT,
2572			.ops = &clk_branch2_ops,
2573		},
2574	},
2575};
2576
2577static struct clk_branch cam_cc_mclk6_clk = {
2578	.halt_reg = 0x150c0,
2579	.halt_check = BRANCH_HALT,
2580	.clkr = {
2581		.enable_reg = 0x150c0,
2582		.enable_mask = BIT(0),
2583		.hw.init = &(const struct clk_init_data) {
2584			.name = "cam_cc_mclk6_clk",
2585			.parent_hws = (const struct clk_hw*[]) {
2586				&cam_cc_mclk6_clk_src.clkr.hw,
2587			},
2588			.num_parents = 1,
2589			.flags = CLK_SET_RATE_PARENT,
2590			.ops = &clk_branch2_ops,
2591		},
2592	},
2593};
2594
2595static struct clk_branch cam_cc_mclk7_clk = {
2596	.halt_reg = 0x150dc,
2597	.halt_check = BRANCH_HALT,
2598	.clkr = {
2599		.enable_reg = 0x150dc,
2600		.enable_mask = BIT(0),
2601		.hw.init = &(const struct clk_init_data) {
2602			.name = "cam_cc_mclk7_clk",
2603			.parent_hws = (const struct clk_hw*[]) {
2604				&cam_cc_mclk7_clk_src.clkr.hw,
2605			},
2606			.num_parents = 1,
2607			.flags = CLK_SET_RATE_PARENT,
2608			.ops = &clk_branch2_ops,
2609		},
2610	},
2611};
2612
2613static struct clk_branch cam_cc_qdss_debug_clk = {
2614	.halt_reg = 0x131d4,
2615	.halt_check = BRANCH_HALT,
2616	.clkr = {
2617		.enable_reg = 0x131d4,
2618		.enable_mask = BIT(0),
2619		.hw.init = &(const struct clk_init_data) {
2620			.name = "cam_cc_qdss_debug_clk",
2621			.parent_hws = (const struct clk_hw*[]) {
2622				&cam_cc_qdss_debug_clk_src.clkr.hw,
2623			},
2624			.num_parents = 1,
2625			.flags = CLK_SET_RATE_PARENT,
2626			.ops = &clk_branch2_ops,
2627		},
2628	},
2629};
2630
2631static struct clk_branch cam_cc_qdss_debug_xo_clk = {
2632	.halt_reg = 0x131d8,
2633	.halt_check = BRANCH_HALT,
2634	.clkr = {
2635		.enable_reg = 0x131d8,
2636		.enable_mask = BIT(0),
2637		.hw.init = &(const struct clk_init_data) {
2638			.name = "cam_cc_qdss_debug_xo_clk",
2639			.parent_hws = (const struct clk_hw*[]) {
2640				&cam_cc_xo_clk_src.clkr.hw,
2641			},
2642			.num_parents = 1,
2643			.flags = CLK_SET_RATE_PARENT,
2644			.ops = &clk_branch2_ops,
2645		},
2646	},
2647};
2648
2649static struct clk_branch cam_cc_sbi_ahb_clk = {
2650	.halt_reg = 0x100f0,
2651	.halt_check = BRANCH_HALT,
2652	.clkr = {
2653		.enable_reg = 0x100f0,
2654		.enable_mask = BIT(0),
2655		.hw.init = &(const struct clk_init_data) {
2656			.name = "cam_cc_sbi_ahb_clk",
2657			.parent_hws = (const struct clk_hw*[]) {
2658				&cam_cc_slow_ahb_clk_src.clkr.hw,
2659			},
2660			.num_parents = 1,
2661			.flags = CLK_SET_RATE_PARENT,
2662			.ops = &clk_branch2_ops,
2663		},
2664	},
2665};
2666
2667static struct clk_branch cam_cc_sbi_clk = {
2668	.halt_reg = 0x100e4,
2669	.halt_check = BRANCH_HALT,
2670	.clkr = {
2671		.enable_reg = 0x100e4,
2672		.enable_mask = BIT(0),
2673		.hw.init = &(const struct clk_init_data) {
2674			.name = "cam_cc_sbi_clk",
2675			.parent_hws = (const struct clk_hw*[]) {
2676				&cam_cc_ife_0_clk_src.clkr.hw,
2677			},
2678			.num_parents = 1,
2679			.flags = CLK_SET_RATE_PARENT,
2680			.ops = &clk_branch2_ops,
2681		},
2682	},
2683};
2684
2685static struct clk_branch cam_cc_sfe_0_clk = {
2686	.halt_reg = 0x1307c,
2687	.halt_check = BRANCH_HALT,
2688	.clkr = {
2689		.enable_reg = 0x1307c,
2690		.enable_mask = BIT(0),
2691		.hw.init = &(const struct clk_init_data) {
2692			.name = "cam_cc_sfe_0_clk",
2693			.parent_hws = (const struct clk_hw*[]) {
2694				&cam_cc_sfe_0_clk_src.clkr.hw,
2695			},
2696			.num_parents = 1,
2697			.flags = CLK_SET_RATE_PARENT,
2698			.ops = &clk_branch2_ops,
2699		},
2700	},
2701};
2702
2703static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
2704	.halt_reg = 0x13090,
2705	.halt_check = BRANCH_HALT,
2706	.clkr = {
2707		.enable_reg = 0x13090,
2708		.enable_mask = BIT(0),
2709		.hw.init = &(const struct clk_init_data) {
2710			.name = "cam_cc_sfe_0_fast_ahb_clk",
2711			.parent_hws = (const struct clk_hw*[]) {
2712				&cam_cc_fast_ahb_clk_src.clkr.hw,
2713			},
2714			.num_parents = 1,
2715			.flags = CLK_SET_RATE_PARENT,
2716			.ops = &clk_branch2_ops,
2717		},
2718	},
2719};
2720
2721static struct clk_branch cam_cc_sfe_1_clk = {
2722	.halt_reg = 0x130c4,
2723	.halt_check = BRANCH_HALT,
2724	.clkr = {
2725		.enable_reg = 0x130c4,
2726		.enable_mask = BIT(0),
2727		.hw.init = &(const struct clk_init_data) {
2728			.name = "cam_cc_sfe_1_clk",
2729			.parent_hws = (const struct clk_hw*[]) {
2730				&cam_cc_sfe_1_clk_src.clkr.hw,
2731			},
2732			.num_parents = 1,
2733			.flags = CLK_SET_RATE_PARENT,
2734			.ops = &clk_branch2_ops,
2735		},
2736	},
2737};
2738
2739static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
2740	.halt_reg = 0x130d8,
2741	.halt_check = BRANCH_HALT,
2742	.clkr = {
2743		.enable_reg = 0x130d8,
2744		.enable_mask = BIT(0),
2745		.hw.init = &(const struct clk_init_data) {
2746			.name = "cam_cc_sfe_1_fast_ahb_clk",
2747			.parent_hws = (const struct clk_hw*[]) {
2748				&cam_cc_fast_ahb_clk_src.clkr.hw,
2749			},
2750			.num_parents = 1,
2751			.flags = CLK_SET_RATE_PARENT,
2752			.ops = &clk_branch2_ops,
2753		},
2754	},
2755};
2756
2757static struct clk_branch cam_cc_sleep_clk = {
2758	.halt_reg = 0x13228,
2759	.halt_check = BRANCH_HALT,
2760	.clkr = {
2761		.enable_reg = 0x13228,
2762		.enable_mask = BIT(0),
2763		.hw.init = &(const struct clk_init_data) {
2764			.name = "cam_cc_sleep_clk",
2765			.parent_hws = (const struct clk_hw*[]) {
2766				&cam_cc_sleep_clk_src.clkr.hw,
2767			},
2768			.num_parents = 1,
2769			.flags = CLK_SET_RATE_PARENT,
2770			.ops = &clk_branch2_ops,
2771		},
2772	},
2773};
2774
2775static struct clk_regmap *cam_cc_sm8450_clocks[] = {
2776	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2777	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2778	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2779	[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
2780	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2781	[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2782	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2783	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2784	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2785	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2786	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2787	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2788	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2789	[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
2790	[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
2791	[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
2792	[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
2793	[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
2794	[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
2795	[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
2796	[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
2797	[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
2798	[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
2799	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2800	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2801	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2802	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2803	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2804	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2805	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2806	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2807	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2808	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2809	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2810	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
2811	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
2812	[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
2813	[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
2814	[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
2815	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2816	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2817	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2818	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2819	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2820	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
2821	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2822	[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2823	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2824	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2825	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2826	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2827	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2828	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2829	[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
2830	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2831	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2832	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2833	[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
2834	[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2835	[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2836	[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2837	[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
2838	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
2839	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
2840	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
2841	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
2842	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
2843	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
2844	[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
2845	[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
2846	[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
2847	[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
2848	[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
2849	[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
2850	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2851	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2852	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2853	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2854	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2855	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2856	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2857	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2858	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2859	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2860	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2861	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2862	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2863	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2864	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2865	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2866	[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
2867	[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
2868	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2869	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2870	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2871	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2872	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2873	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2874	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2875	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2876	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2877	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2878	[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2879	[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
2880	[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2881	[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
2882	[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
2883	[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
2884	[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
2885	[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
2886	[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
2887	[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
2888	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
2889	[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
2890	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
2891	[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
2892	[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
2893	[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
2894	[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
2895	[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
2896	[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
2897	[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2898	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2899	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2900	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2901};
2902
2903static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
2904	[CAM_CC_BPS_BCR] = { 0x10000 },
2905	[CAM_CC_ICP_BCR] = { 0x13104 },
2906	[CAM_CC_IFE_0_BCR] = { 0x11000 },
2907	[CAM_CC_IFE_1_BCR] = { 0x12000 },
2908	[CAM_CC_IFE_2_BCR] = { 0x1204c },
2909	[CAM_CC_IPE_0_BCR] = { 0x10074 },
2910	[CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 },
2911	[CAM_CC_SBI_BCR] = { 0x100cc },
2912	[CAM_CC_SFE_0_BCR] = { 0x1304c },
2913	[CAM_CC_SFE_1_BCR] = { 0x13094 },
2914};
2915
2916static const struct regmap_config cam_cc_sm8450_regmap_config = {
2917	.reg_bits = 32,
2918	.reg_stride = 4,
2919	.val_bits = 32,
2920	.max_register = 0x1601c,
2921	.fast_io = true,
2922};
2923
2924static struct gdsc titan_top_gdsc;
2925
2926static struct gdsc bps_gdsc = {
2927	.gdscr = 0x10004,
2928	.pd = {
2929		.name = "bps_gdsc",
2930	},
2931	.flags = HW_CTRL | POLL_CFG_GDSCR,
2932	.pwrsts = PWRSTS_OFF_ON,
2933};
2934
2935static struct gdsc ipe_0_gdsc = {
2936	.gdscr = 0x10078,
2937	.pd = {
2938		.name = "ipe_0_gdsc",
2939	},
2940	.flags = HW_CTRL | POLL_CFG_GDSCR,
2941	.pwrsts = PWRSTS_OFF_ON,
2942};
2943
2944static struct gdsc sbi_gdsc = {
2945	.gdscr = 0x100d0,
2946	.pd = {
2947		.name = "sbi_gdsc",
2948	},
2949	.flags = POLL_CFG_GDSCR,
2950	.pwrsts = PWRSTS_OFF_ON,
2951};
2952
2953static struct gdsc ife_0_gdsc = {
2954	.gdscr = 0x11004,
2955	.pd = {
2956		.name = "ife_0_gdsc",
2957	},
2958	.flags = POLL_CFG_GDSCR,
2959	.parent = &titan_top_gdsc.pd,
2960	.pwrsts = PWRSTS_OFF_ON,
2961};
2962
2963static struct gdsc ife_1_gdsc = {
2964	.gdscr = 0x12004,
2965	.pd = {
2966		.name = "ife_1_gdsc",
2967	},
2968	.flags = POLL_CFG_GDSCR,
2969	.parent = &titan_top_gdsc.pd,
2970	.pwrsts = PWRSTS_OFF_ON,
2971};
2972
2973static struct gdsc ife_2_gdsc = {
2974	.gdscr = 0x12050,
2975	.pd = {
2976		.name = "ife_2_gdsc",
2977	},
2978	.flags = POLL_CFG_GDSCR,
2979	.parent = &titan_top_gdsc.pd,
2980	.pwrsts = PWRSTS_OFF_ON,
2981};
2982
2983static struct gdsc sfe_0_gdsc = {
2984	.gdscr = 0x13050,
2985	.pd = {
2986		.name = "sfe_0_gdsc",
2987	},
2988	.flags = POLL_CFG_GDSCR,
2989	.parent = &titan_top_gdsc.pd,
2990	.pwrsts = PWRSTS_OFF_ON,
2991};
2992
2993static struct gdsc sfe_1_gdsc = {
2994	.gdscr = 0x13098,
2995	.pd = {
2996		.name = "sfe_1_gdsc",
2997	},
2998	.flags = POLL_CFG_GDSCR,
2999	.parent = &titan_top_gdsc.pd,
3000	.pwrsts = PWRSTS_OFF_ON,
3001};
3002
3003static struct gdsc titan_top_gdsc = {
3004	.gdscr = 0x131dc,
3005	.pd = {
3006		.name = "titan_top_gdsc",
3007	},
3008	.flags = POLL_CFG_GDSCR,
3009	.pwrsts = PWRSTS_OFF_ON,
3010};
3011
3012static struct gdsc *cam_cc_sm8450_gdscs[] = {
3013	[BPS_GDSC] = &bps_gdsc,
3014	[IPE_0_GDSC] = &ipe_0_gdsc,
3015	[SBI_GDSC] = &sbi_gdsc,
3016	[IFE_0_GDSC] = &ife_0_gdsc,
3017	[IFE_1_GDSC] = &ife_1_gdsc,
3018	[IFE_2_GDSC] = &ife_2_gdsc,
3019	[SFE_0_GDSC] = &sfe_0_gdsc,
3020	[SFE_1_GDSC] = &sfe_1_gdsc,
3021	[TITAN_TOP_GDSC] = &titan_top_gdsc,
3022};
3023
3024static const struct qcom_cc_desc cam_cc_sm8450_desc = {
3025	.config = &cam_cc_sm8450_regmap_config,
3026	.clks = cam_cc_sm8450_clocks,
3027	.num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks),
3028	.resets = cam_cc_sm8450_resets,
3029	.num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
3030	.gdscs = cam_cc_sm8450_gdscs,
3031	.num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
3032};
3033
3034static const struct of_device_id cam_cc_sm8450_match_table[] = {
3035	{ .compatible = "qcom,sm8450-camcc" },
3036	{ .compatible = "qcom,sm8475-camcc" },
3037	{ }
3038};
3039MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
3040
3041static int cam_cc_sm8450_probe(struct platform_device *pdev)
3042{
3043	struct regmap *regmap;
3044
3045	regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc);
3046	if (IS_ERR(regmap))
3047		return PTR_ERR(regmap);
3048
3049	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) {
3050		/* Update CAMCC PLL0 */
3051		cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3052		cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3053		cam_cc_pll0_out_even.clkr.hw.init = &sm8475_cam_cc_pll0_out_even_init;
3054		cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3055		cam_cc_pll0_out_odd.clkr.hw.init = &sm8475_cam_cc_pll0_out_odd_init;
3056
3057		/* Update CAMCC PLL1 */
3058		cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3059		cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3060		cam_cc_pll1_out_even.clkr.hw.init = &sm8475_cam_cc_pll1_out_even_init;
3061
3062		/* Update CAMCC PLL2 */
3063		cam_cc_pll2.vco_table = rivian_ole_vco;
3064
3065		/* Update CAMCC PLL3 */
3066		cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3067		cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3068		cam_cc_pll3_out_even.clkr.hw.init = &sm8475_cam_cc_pll3_out_even_init;
3069
3070		/* Update CAMCC PLL4 */
3071		cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3072		cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3073		cam_cc_pll4_out_even.clkr.hw.init = &sm8475_cam_cc_pll4_out_even_init;
3074
3075		/* Update CAMCC PLL5 */
3076		cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3077		cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3078		cam_cc_pll5_out_even.clkr.hw.init = &sm8475_cam_cc_pll5_out_even_init;
3079
3080		/* Update CAMCC PLL6 */
3081		cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3082		cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3083		cam_cc_pll6_out_even.clkr.hw.init = &sm8475_cam_cc_pll6_out_even_init;
3084
3085		/* Update CAMCC PLL7 */
3086		cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3087		cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3088		cam_cc_pll7_out_even.clkr.hw.init = &sm8475_cam_cc_pll7_out_even_init;
3089
3090		/* Update CAMCC PLL8 */
3091		cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3092		cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3093		cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init;
3094
3095		clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config);
3096		clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config);
3097		clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config);
3098		clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config);
3099		clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config);
3100		clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config);
3101		clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config);
3102		clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config);
3103		clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config);
3104	} else {
3105		clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
3106		clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
3107		clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
3108		clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
3109		clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
3110		clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
3111		clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
3112		clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
3113		clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
3114	}
3115
3116	return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
3117}
3118
3119static struct platform_driver cam_cc_sm8450_driver = {
3120	.probe = cam_cc_sm8450_probe,
3121	.driver = {
3122		.name = "camcc-sm8450",
3123		.of_match_table = cam_cc_sm8450_match_table,
3124	},
3125};
3126
3127module_platform_driver(cam_cc_sm8450_driver);
3128
3129MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver");
3130MODULE_LICENSE("GPL");