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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/mod_devicetable.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13
14#include <dt-bindings/clock/qcom,sm7150-camcc.h>
15
16#include "clk-alpha-pll.h"
17#include "clk-branch.h"
18#include "clk-rcg.h"
19#include "clk-regmap.h"
20#include "common.h"
21#include "gdsc.h"
22
23enum {
24 DT_BI_TCXO,
25 DT_BI_TCXO_AO,
26 DT_CHIP_SLEEP_CLK,
27};
28
29enum {
30 P_BI_TCXO,
31 P_BI_TCXO_MX,
32 P_CAMCC_PLL0_OUT_EVEN,
33 P_CAMCC_PLL0_OUT_MAIN,
34 P_CAMCC_PLL0_OUT_ODD,
35 P_CAMCC_PLL1_OUT_EVEN,
36 P_CAMCC_PLL2_OUT_AUX,
37 P_CAMCC_PLL2_OUT_EARLY,
38 P_CAMCC_PLL2_OUT_MAIN,
39 P_CAMCC_PLL3_OUT_EVEN,
40 P_CAMCC_PLL4_OUT_EVEN,
41 P_CHIP_SLEEP_CLK,
42};
43
44static const struct pll_vco fabia_vco[] = {
45 { 249600000, 2000000000, 0 },
46};
47
48/* 1200MHz configuration */
49static const struct alpha_pll_config camcc_pll0_config = {
50 .l = 0x3e,
51 .alpha = 0x8000,
52 .post_div_mask = 0xff << 8,
53 .post_div_val = 0x31 << 8,
54 .test_ctl_val = 0x40000000,
55};
56
57static struct clk_alpha_pll camcc_pll0 = {
58 .offset = 0x0,
59 .vco_table = fabia_vco,
60 .num_vco = ARRAY_SIZE(fabia_vco),
61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
62 .clkr = {
63 .hw.init = &(const struct clk_init_data) {
64 .name = "camcc_pll0",
65 .parent_data = &(const struct clk_parent_data) {
66 .index = DT_BI_TCXO,
67 },
68 .num_parents = 1,
69 .ops = &clk_alpha_pll_fabia_ops,
70 },
71 },
72};
73
74static struct clk_fixed_factor camcc_pll0_out_even = {
75 .mult = 1,
76 .div = 2,
77 .hw.init = &(const struct clk_init_data) {
78 .name = "camcc_pll0_out_even",
79 .parent_hws = (const struct clk_hw*[]) {
80 &camcc_pll0.clkr.hw,
81 },
82 .num_parents = 1,
83 .ops = &clk_fixed_factor_ops,
84 },
85};
86
87static struct clk_fixed_factor camcc_pll0_out_odd = {
88 .mult = 1,
89 .div = 3,
90 .hw.init = &(const struct clk_init_data) {
91 .name = "camcc_pll0_out_odd",
92 .parent_hws = (const struct clk_hw*[]) {
93 &camcc_pll0.clkr.hw,
94 },
95 .num_parents = 1,
96 .ops = &clk_fixed_factor_ops,
97 },
98};
99
100/* 680MHz configuration */
101static const struct alpha_pll_config camcc_pll1_config = {
102 .l = 0x23,
103 .alpha = 0x6aaa,
104 .post_div_mask = 0xf << 8,
105 .post_div_val = 0x1 << 8,
106 .test_ctl_val = 0x40000000,
107};
108
109static struct clk_alpha_pll camcc_pll1 = {
110 .offset = 0x1000,
111 .vco_table = fabia_vco,
112 .num_vco = ARRAY_SIZE(fabia_vco),
113 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
114 .clkr = {
115 .hw.init = &(const struct clk_init_data) {
116 .name = "camcc_pll1",
117 .parent_data = &(const struct clk_parent_data) {
118 .index = DT_BI_TCXO,
119 },
120 .num_parents = 1,
121 .ops = &clk_alpha_pll_fabia_ops,
122 },
123 },
124};
125
126static struct clk_fixed_factor camcc_pll1_out_even = {
127 .mult = 1,
128 .div = 2,
129 .hw.init = &(const struct clk_init_data) {
130 .name = "camcc_pll1_out_even",
131 .parent_hws = (const struct clk_hw*[]) {
132 &camcc_pll1.clkr.hw,
133 },
134 .num_parents = 1,
135 .flags = CLK_SET_RATE_PARENT,
136 .ops = &clk_fixed_factor_ops,
137 },
138};
139
140/* 1920MHz configuration */
141static const struct alpha_pll_config camcc_pll2_config = {
142 .l = 0x64,
143 .post_div_val = 0x3 << 8,
144 .post_div_mask = 0x3 << 8,
145 .early_output_mask = BIT(3),
146 .aux_output_mask = BIT(1),
147 .main_output_mask = BIT(0),
148 .config_ctl_hi_val = 0x400003d6,
149 .config_ctl_val = 0x20000954,
150};
151
152static struct clk_alpha_pll camcc_pll2 = {
153 .offset = 0x2000,
154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
155 .clkr = {
156 .hw.init = &(const struct clk_init_data) {
157 .name = "camcc_pll2",
158 .parent_data = &(const struct clk_parent_data) {
159 .index = DT_BI_TCXO,
160 },
161 .num_parents = 1,
162 .ops = &clk_alpha_pll_agera_ops,
163 },
164 },
165};
166
167static struct clk_fixed_factor camcc_pll2_out_early = {
168 .mult = 1,
169 .div = 2,
170 .hw.init = &(const struct clk_init_data) {
171 .name = "camcc_pll2_out_early",
172 .parent_hws = (const struct clk_hw*[]) {
173 &camcc_pll2.clkr.hw,
174 },
175 .num_parents = 1,
176 .ops = &clk_fixed_factor_ops,
177 },
178};
179
180static struct clk_alpha_pll_postdiv camcc_pll2_out_aux = {
181 .offset = 0x2000,
182 .post_div_shift = 8,
183 .width = 2,
184 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
185 .clkr.hw.init = &(const struct clk_init_data) {
186 .name = "camcc_pll2_out_aux",
187 .parent_hws = (const struct clk_hw*[]) {
188 &camcc_pll2.clkr.hw,
189 },
190 .num_parents = 1,
191 .flags = CLK_SET_RATE_PARENT,
192 .ops = &clk_alpha_pll_postdiv_ops,
193 },
194};
195
196static struct clk_alpha_pll_postdiv camcc_pll2_out_main = {
197 .offset = 0x2000,
198 .post_div_shift = 8,
199 .width = 2,
200 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
201 .clkr.hw.init = &(const struct clk_init_data) {
202 .name = "camcc_pll2_out_main",
203 .parent_hws = (const struct clk_hw*[]) {
204 &camcc_pll2.clkr.hw,
205 },
206 .num_parents = 1,
207 .flags = CLK_SET_RATE_PARENT,
208 .ops = &clk_alpha_pll_postdiv_ops,
209 },
210};
211
212/* 760MHz configuration */
213static const struct alpha_pll_config camcc_pll3_config = {
214 .l = 0x27,
215 .alpha = 0x9555,
216 .post_div_mask = 0xf << 8,
217 .post_div_val = 0x1 << 8,
218 .test_ctl_val = 0x40000000,
219};
220
221static struct clk_alpha_pll camcc_pll3 = {
222 .offset = 0x3000,
223 .vco_table = fabia_vco,
224 .num_vco = ARRAY_SIZE(fabia_vco),
225 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
226 .clkr = {
227 .hw.init = &(const struct clk_init_data) {
228 .name = "camcc_pll3",
229 .parent_data = &(const struct clk_parent_data) {
230 .index = DT_BI_TCXO,
231 },
232 .num_parents = 1,
233 .ops = &clk_alpha_pll_fabia_ops,
234 },
235 },
236};
237
238static struct clk_fixed_factor camcc_pll3_out_even = {
239 .mult = 1,
240 .div = 2,
241 .hw.init = &(const struct clk_init_data) {
242 .name = "camcc_pll3_out_even",
243 .parent_hws = (const struct clk_hw*[]) {
244 &camcc_pll3.clkr.hw,
245 },
246 .num_parents = 1,
247 .flags = CLK_SET_RATE_PARENT,
248 .ops = &clk_fixed_factor_ops,
249 },
250};
251
252static struct clk_alpha_pll camcc_pll4 = {
253 .offset = 0x4000,
254 .vco_table = fabia_vco,
255 .num_vco = ARRAY_SIZE(fabia_vco),
256 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
257 .clkr = {
258 .hw.init = &(const struct clk_init_data) {
259 .name = "camcc_pll4",
260 .parent_data = &(const struct clk_parent_data) {
261 .index = DT_BI_TCXO,
262 },
263 .num_parents = 1,
264 .ops = &clk_alpha_pll_fabia_ops,
265 },
266 },
267};
268
269static struct clk_fixed_factor camcc_pll4_out_even = {
270 .mult = 1,
271 .div = 2,
272 .hw.init = &(const struct clk_init_data) {
273 .name = "camcc_pll4_out_even",
274 .parent_hws = (const struct clk_hw*[]) {
275 &camcc_pll4.clkr.hw,
276 },
277 .num_parents = 1,
278 .flags = CLK_SET_RATE_PARENT,
279 .ops = &clk_fixed_factor_ops,
280 },
281};
282
283static const struct parent_map camcc_parent_map_0[] = {
284 { P_BI_TCXO, 0 },
285 { P_CAMCC_PLL0_OUT_MAIN, 1 },
286 { P_CAMCC_PLL0_OUT_EVEN, 2 },
287 { P_CAMCC_PLL0_OUT_ODD, 3 },
288 { P_CAMCC_PLL2_OUT_MAIN, 5 },
289};
290
291static const struct clk_parent_data camcc_parent_data_0[] = {
292 { .index = DT_BI_TCXO },
293 { .hw = &camcc_pll0.clkr.hw },
294 { .hw = &camcc_pll0_out_even.hw },
295 { .hw = &camcc_pll0_out_odd.hw },
296 { .hw = &camcc_pll2_out_main.clkr.hw },
297};
298
299static const struct parent_map camcc_parent_map_1[] = {
300 { P_BI_TCXO, 0 },
301 { P_CAMCC_PLL0_OUT_MAIN, 1 },
302 { P_CAMCC_PLL0_OUT_EVEN, 2 },
303 { P_CAMCC_PLL0_OUT_ODD, 3 },
304 { P_CAMCC_PLL1_OUT_EVEN, 4 },
305 { P_CAMCC_PLL2_OUT_EARLY, 5 },
306};
307
308static const struct clk_parent_data camcc_parent_data_1[] = {
309 { .index = DT_BI_TCXO },
310 { .hw = &camcc_pll0.clkr.hw },
311 { .hw = &camcc_pll0_out_even.hw },
312 { .hw = &camcc_pll0_out_odd.hw },
313 { .hw = &camcc_pll1_out_even.hw },
314 { .hw = &camcc_pll2_out_early.hw },
315};
316
317static const struct parent_map camcc_parent_map_2[] = {
318 { P_BI_TCXO_MX, 0 },
319 { P_CAMCC_PLL2_OUT_AUX, 5 },
320};
321
322static const struct clk_parent_data camcc_parent_data_2[] = {
323 { .index = DT_BI_TCXO },
324 { .hw = &camcc_pll2_out_aux.clkr.hw },
325};
326
327static const struct parent_map camcc_parent_map_3[] = {
328 { P_BI_TCXO, 0 },
329 { P_CAMCC_PLL0_OUT_MAIN, 1 },
330 { P_CAMCC_PLL0_OUT_EVEN, 2 },
331 { P_CAMCC_PLL0_OUT_ODD, 3 },
332 { P_CAMCC_PLL2_OUT_EARLY, 5 },
333 { P_CAMCC_PLL4_OUT_EVEN, 6 },
334};
335
336static const struct clk_parent_data camcc_parent_data_3[] = {
337 { .index = DT_BI_TCXO },
338 { .hw = &camcc_pll0.clkr.hw },
339 { .hw = &camcc_pll0_out_even.hw },
340 { .hw = &camcc_pll0_out_odd.hw },
341 { .hw = &camcc_pll2_out_early.hw },
342 { .hw = &camcc_pll4_out_even.hw },
343};
344
345static const struct parent_map camcc_parent_map_4[] = {
346 { P_BI_TCXO, 0 },
347 { P_CAMCC_PLL3_OUT_EVEN, 6 },
348};
349
350static const struct clk_parent_data camcc_parent_data_4[] = {
351 { .index = DT_BI_TCXO },
352 { .hw = &camcc_pll3_out_even.hw },
353};
354
355static const struct parent_map camcc_parent_map_5[] = {
356 { P_BI_TCXO, 0 },
357 { P_CAMCC_PLL4_OUT_EVEN, 6 },
358};
359
360static const struct clk_parent_data camcc_parent_data_5[] = {
361 { .index = DT_BI_TCXO },
362 { .hw = &camcc_pll4_out_even.hw },
363};
364
365static const struct parent_map camcc_parent_map_6[] = {
366 { P_BI_TCXO, 0 },
367 { P_CAMCC_PLL1_OUT_EVEN, 4 },
368};
369
370static const struct clk_parent_data camcc_parent_data_6[] = {
371 { .index = DT_BI_TCXO },
372 { .hw = &camcc_pll1_out_even.hw },
373};
374
375static const struct parent_map camcc_parent_map_7[] = {
376 { P_CHIP_SLEEP_CLK, 0 },
377};
378
379static const struct clk_parent_data camcc_parent_data_7[] = {
380 { .index = DT_CHIP_SLEEP_CLK },
381};
382
383static const struct parent_map camcc_parent_map_8[] = {
384 { P_BI_TCXO, 0 },
385 { P_CAMCC_PLL0_OUT_ODD, 3 },
386};
387
388static const struct clk_parent_data camcc_parent_data_8[] = {
389 { .index = DT_BI_TCXO },
390 { .hw = &camcc_pll0_out_odd.hw },
391};
392
393static const struct parent_map camcc_parent_map_9[] = {
394 { P_BI_TCXO, 0 },
395};
396
397static const struct clk_parent_data camcc_parent_data_9[] = {
398 { .index = DT_BI_TCXO_AO },
399};
400
401static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
402 F(19200000, P_BI_TCXO, 1, 0, 0),
403 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
404 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
405 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
406 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
407 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
408 { }
409};
410
411static struct clk_rcg2 camcc_bps_clk_src = {
412 .cmd_rcgr = 0x7010,
413 .mnd_width = 0,
414 .hid_width = 5,
415 .parent_map = camcc_parent_map_0,
416 .freq_tbl = ftbl_camcc_bps_clk_src,
417 .clkr.hw.init = &(const struct clk_init_data) {
418 .name = "camcc_bps_clk_src",
419 .parent_data = camcc_parent_data_0,
420 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
421 .ops = &clk_rcg2_shared_ops,
422 },
423};
424
425static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = {
426 F(19200000, P_BI_TCXO, 1, 0, 0),
427 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
428 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
429 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
430 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
431 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
432 { }
433};
434
435static struct clk_rcg2 camcc_camnoc_axi_clk_src = {
436 .cmd_rcgr = 0xc12c,
437 .mnd_width = 0,
438 .hid_width = 5,
439 .parent_map = camcc_parent_map_0,
440 .freq_tbl = ftbl_camcc_camnoc_axi_clk_src,
441 .clkr.hw.init = &(const struct clk_init_data) {
442 .name = "camcc_camnoc_axi_clk_src",
443 .parent_data = camcc_parent_data_0,
444 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
445 .ops = &clk_rcg2_shared_ops,
446 },
447};
448
449static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
450 F(19200000, P_BI_TCXO, 1, 0, 0),
451 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
452 { }
453};
454
455static struct clk_rcg2 camcc_cci_0_clk_src = {
456 .cmd_rcgr = 0xc0c4,
457 .mnd_width = 8,
458 .hid_width = 5,
459 .parent_map = camcc_parent_map_0,
460 .freq_tbl = ftbl_camcc_cci_0_clk_src,
461 .clkr.hw.init = &(const struct clk_init_data) {
462 .name = "camcc_cci_0_clk_src",
463 .parent_data = camcc_parent_data_0,
464 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
465 .ops = &clk_rcg2_ops,
466 },
467};
468
469static struct clk_rcg2 camcc_cci_1_clk_src = {
470 .cmd_rcgr = 0xc0e0,
471 .mnd_width = 8,
472 .hid_width = 5,
473 .parent_map = camcc_parent_map_0,
474 .freq_tbl = ftbl_camcc_cci_0_clk_src,
475 .clkr.hw.init = &(const struct clk_init_data) {
476 .name = "camcc_cci_1_clk_src",
477 .parent_data = camcc_parent_data_0,
478 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
479 .ops = &clk_rcg2_ops,
480 },
481};
482
483static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
484 F(19200000, P_BI_TCXO, 1, 0, 0),
485 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
486 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
487 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
488 { }
489};
490
491static struct clk_rcg2 camcc_cphy_rx_clk_src = {
492 .cmd_rcgr = 0xa064,
493 .mnd_width = 0,
494 .hid_width = 5,
495 .parent_map = camcc_parent_map_1,
496 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
497 .clkr.hw.init = &(const struct clk_init_data) {
498 .name = "camcc_cphy_rx_clk_src",
499 .parent_data = camcc_parent_data_1,
500 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
501 .ops = &clk_rcg2_ops,
502 },
503};
504
505static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
506 F(19200000, P_BI_TCXO, 1, 0, 0),
507 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
508 { }
509};
510
511static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
512 .cmd_rcgr = 0x6004,
513 .mnd_width = 0,
514 .hid_width = 5,
515 .parent_map = camcc_parent_map_0,
516 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
517 .clkr.hw.init = &(const struct clk_init_data) {
518 .name = "camcc_csi0phytimer_clk_src",
519 .parent_data = camcc_parent_data_0,
520 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
521 .ops = &clk_rcg2_ops,
522 },
523};
524
525static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
526 .cmd_rcgr = 0x6028,
527 .mnd_width = 0,
528 .hid_width = 5,
529 .parent_map = camcc_parent_map_0,
530 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
531 .clkr.hw.init = &(const struct clk_init_data) {
532 .name = "camcc_csi1phytimer_clk_src",
533 .parent_data = camcc_parent_data_0,
534 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
535 .ops = &clk_rcg2_ops,
536 },
537};
538
539static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
540 .cmd_rcgr = 0x604c,
541 .mnd_width = 0,
542 .hid_width = 5,
543 .parent_map = camcc_parent_map_0,
544 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
545 .clkr.hw.init = &(const struct clk_init_data) {
546 .name = "camcc_csi2phytimer_clk_src",
547 .parent_data = camcc_parent_data_0,
548 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
549 .ops = &clk_rcg2_ops,
550 },
551};
552
553static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
554 .cmd_rcgr = 0x6070,
555 .mnd_width = 0,
556 .hid_width = 5,
557 .parent_map = camcc_parent_map_0,
558 .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
559 .clkr.hw.init = &(const struct clk_init_data) {
560 .name = "camcc_csi3phytimer_clk_src",
561 .parent_data = camcc_parent_data_0,
562 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
563 .ops = &clk_rcg2_ops,
564 },
565};
566
567static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
568 F(19200000, P_BI_TCXO, 1, 0, 0),
569 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0),
570 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
571 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
572 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
573 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
574 { }
575};
576
577static struct clk_rcg2 camcc_fast_ahb_clk_src = {
578 .cmd_rcgr = 0x703c,
579 .mnd_width = 0,
580 .hid_width = 5,
581 .parent_map = camcc_parent_map_0,
582 .freq_tbl = ftbl_camcc_fast_ahb_clk_src,
583 .clkr.hw.init = &(const struct clk_init_data) {
584 .name = "camcc_fast_ahb_clk_src",
585 .parent_data = camcc_parent_data_0,
586 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
587 .ops = &clk_rcg2_ops,
588 },
589};
590
591static const struct freq_tbl ftbl_camcc_fd_core_clk_src[] = {
592 F(19200000, P_BI_TCXO, 1, 0, 0),
593 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
594 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
595 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
596 F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0),
597 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
598 { }
599};
600
601static struct clk_rcg2 camcc_fd_core_clk_src = {
602 .cmd_rcgr = 0xc09c,
603 .mnd_width = 0,
604 .hid_width = 5,
605 .parent_map = camcc_parent_map_3,
606 .freq_tbl = ftbl_camcc_fd_core_clk_src,
607 .clkr.hw.init = &(const struct clk_init_data) {
608 .name = "camcc_fd_core_clk_src",
609 .parent_data = camcc_parent_data_3,
610 .num_parents = ARRAY_SIZE(camcc_parent_data_3),
611 .flags = CLK_SET_RATE_PARENT,
612 .ops = &clk_rcg2_shared_ops,
613 },
614};
615
616static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
617 F(19200000, P_BI_TCXO, 1, 0, 0),
618 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
619 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
620 { }
621};
622
623static struct clk_rcg2 camcc_icp_clk_src = {
624 .cmd_rcgr = 0xc074,
625 .mnd_width = 0,
626 .hid_width = 5,
627 .parent_map = camcc_parent_map_0,
628 .freq_tbl = ftbl_camcc_icp_clk_src,
629 .clkr.hw.init = &(const struct clk_init_data) {
630 .name = "camcc_icp_clk_src",
631 .parent_data = camcc_parent_data_0,
632 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
633 .ops = &clk_rcg2_shared_ops,
634 },
635};
636
637static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
638 F(19200000, P_BI_TCXO, 1, 0, 0),
639 F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
640 F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
641 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
642 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
643 { }
644};
645
646static struct clk_rcg2 camcc_ife_0_clk_src = {
647 .cmd_rcgr = 0xa010,
648 .mnd_width = 0,
649 .hid_width = 5,
650 .parent_map = camcc_parent_map_4,
651 .freq_tbl = ftbl_camcc_ife_0_clk_src,
652 .clkr.hw.init = &(const struct clk_init_data) {
653 .name = "camcc_ife_0_clk_src",
654 .parent_data = camcc_parent_data_4,
655 .num_parents = ARRAY_SIZE(camcc_parent_data_4),
656 .flags = CLK_SET_RATE_PARENT,
657 .ops = &clk_rcg2_shared_ops,
658 },
659};
660
661static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = {
662 F(19200000, P_BI_TCXO, 1, 0, 0),
663 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
664 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
665 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
666 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
667 { }
668};
669
670static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
671 .cmd_rcgr = 0xa03c,
672 .mnd_width = 0,
673 .hid_width = 5,
674 .parent_map = camcc_parent_map_1,
675 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
676 .clkr.hw.init = &(const struct clk_init_data) {
677 .name = "camcc_ife_0_csid_clk_src",
678 .parent_data = camcc_parent_data_1,
679 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
680 .ops = &clk_rcg2_shared_ops,
681 },
682};
683
684static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = {
685 F(19200000, P_BI_TCXO, 1, 0, 0),
686 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
687 F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
688 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
689 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
690 { }
691};
692
693static struct clk_rcg2 camcc_ife_1_clk_src = {
694 .cmd_rcgr = 0xb010,
695 .mnd_width = 0,
696 .hid_width = 5,
697 .parent_map = camcc_parent_map_5,
698 .freq_tbl = ftbl_camcc_ife_1_clk_src,
699 .clkr.hw.init = &(const struct clk_init_data) {
700 .name = "camcc_ife_1_clk_src",
701 .parent_data = camcc_parent_data_5,
702 .num_parents = ARRAY_SIZE(camcc_parent_data_5),
703 .flags = CLK_SET_RATE_PARENT,
704 .ops = &clk_rcg2_shared_ops,
705 },
706};
707
708static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
709 .cmd_rcgr = 0xb034,
710 .mnd_width = 0,
711 .hid_width = 5,
712 .parent_map = camcc_parent_map_1,
713 .freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
714 .clkr.hw.init = &(const struct clk_init_data) {
715 .name = "camcc_ife_1_csid_clk_src",
716 .parent_data = camcc_parent_data_1,
717 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
718 .ops = &clk_rcg2_shared_ops,
719 },
720};
721
722static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = {
723 F(19200000, P_BI_TCXO, 1, 0, 0),
724 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
725 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
726 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
727 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
728 { }
729};
730
731static struct clk_rcg2 camcc_ife_lite_clk_src = {
732 .cmd_rcgr = 0xc004,
733 .mnd_width = 0,
734 .hid_width = 5,
735 .parent_map = camcc_parent_map_0,
736 .freq_tbl = ftbl_camcc_ife_lite_clk_src,
737 .clkr.hw.init = &(const struct clk_init_data) {
738 .name = "camcc_ife_lite_clk_src",
739 .parent_data = camcc_parent_data_0,
740 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
741 .ops = &clk_rcg2_ops,
742 },
743};
744
745static struct clk_rcg2 camcc_ife_lite_csid_clk_src = {
746 .cmd_rcgr = 0xc020,
747 .mnd_width = 0,
748 .hid_width = 5,
749 .parent_map = camcc_parent_map_1,
750 .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
751 .clkr.hw.init = &(const struct clk_init_data) {
752 .name = "camcc_ife_lite_csid_clk_src",
753 .parent_data = camcc_parent_data_1,
754 .num_parents = ARRAY_SIZE(camcc_parent_data_1),
755 .ops = &clk_rcg2_shared_ops,
756 },
757};
758
759static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
760 F(19200000, P_BI_TCXO, 1, 0, 0),
761 F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
762 F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
763 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
764 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
765 { }
766};
767
768static struct clk_rcg2 camcc_ipe_0_clk_src = {
769 .cmd_rcgr = 0x8010,
770 .mnd_width = 0,
771 .hid_width = 5,
772 .parent_map = camcc_parent_map_6,
773 .freq_tbl = ftbl_camcc_ipe_0_clk_src,
774 .clkr.hw.init = &(const struct clk_init_data) {
775 .name = "camcc_ipe_0_clk_src",
776 .parent_data = camcc_parent_data_6,
777 .num_parents = ARRAY_SIZE(camcc_parent_data_6),
778 .flags = CLK_SET_RATE_PARENT,
779 .ops = &clk_rcg2_shared_ops,
780 },
781};
782
783static struct clk_rcg2 camcc_jpeg_clk_src = {
784 .cmd_rcgr = 0xc048,
785 .mnd_width = 0,
786 .hid_width = 5,
787 .parent_map = camcc_parent_map_0,
788 .freq_tbl = ftbl_camcc_bps_clk_src,
789 .clkr.hw.init = &(const struct clk_init_data) {
790 .name = "camcc_jpeg_clk_src",
791 .parent_data = camcc_parent_data_0,
792 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
793 .ops = &clk_rcg2_shared_ops,
794 },
795};
796
797static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
798 F(19200000, P_BI_TCXO, 1, 0, 0),
799 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
800 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
801 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
802 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
803 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
804 { }
805};
806
807static struct clk_rcg2 camcc_lrme_clk_src = {
808 .cmd_rcgr = 0xc100,
809 .mnd_width = 0,
810 .hid_width = 5,
811 .parent_map = camcc_parent_map_0,
812 .freq_tbl = ftbl_camcc_lrme_clk_src,
813 .clkr.hw.init = &(const struct clk_init_data) {
814 .name = "camcc_lrme_clk_src",
815 .parent_data = camcc_parent_data_0,
816 .num_parents = ARRAY_SIZE(camcc_parent_data_0),
817 .ops = &clk_rcg2_shared_ops,
818 },
819};
820
821static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
822 F(19200000, P_BI_TCXO_MX, 1, 0, 0),
823 F(24000000, P_CAMCC_PLL2_OUT_AUX, 1, 1, 20),
824 F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0),
825 { }
826};
827
828static struct clk_rcg2 camcc_mclk0_clk_src = {
829 .cmd_rcgr = 0x5004,
830 .mnd_width = 8,
831 .hid_width = 5,
832 .parent_map = camcc_parent_map_2,
833 .freq_tbl = ftbl_camcc_mclk0_clk_src,
834 .clkr.hw.init = &(const struct clk_init_data) {
835 .name = "camcc_mclk0_clk_src",
836 .parent_data = camcc_parent_data_2,
837 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
838 .ops = &clk_rcg2_ops,
839 },
840};
841
842static struct clk_rcg2 camcc_mclk1_clk_src = {
843 .cmd_rcgr = 0x5024,
844 .mnd_width = 8,
845 .hid_width = 5,
846 .parent_map = camcc_parent_map_2,
847 .freq_tbl = ftbl_camcc_mclk0_clk_src,
848 .clkr.hw.init = &(const struct clk_init_data) {
849 .name = "camcc_mclk1_clk_src",
850 .parent_data = camcc_parent_data_2,
851 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
852 .ops = &clk_rcg2_ops,
853 },
854};
855
856static struct clk_rcg2 camcc_mclk2_clk_src = {
857 .cmd_rcgr = 0x5044,
858 .mnd_width = 8,
859 .hid_width = 5,
860 .parent_map = camcc_parent_map_2,
861 .freq_tbl = ftbl_camcc_mclk0_clk_src,
862 .clkr.hw.init = &(const struct clk_init_data) {
863 .name = "camcc_mclk2_clk_src",
864 .parent_data = camcc_parent_data_2,
865 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
866 .ops = &clk_rcg2_ops,
867 },
868};
869
870static struct clk_rcg2 camcc_mclk3_clk_src = {
871 .cmd_rcgr = 0x5064,
872 .mnd_width = 8,
873 .hid_width = 5,
874 .parent_map = camcc_parent_map_2,
875 .freq_tbl = ftbl_camcc_mclk0_clk_src,
876 .clkr.hw.init = &(const struct clk_init_data) {
877 .name = "camcc_mclk3_clk_src",
878 .parent_data = camcc_parent_data_2,
879 .num_parents = ARRAY_SIZE(camcc_parent_data_2),
880 .ops = &clk_rcg2_ops,
881 },
882};
883
884static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = {
885 F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
886 { }
887};
888
889static struct clk_rcg2 camcc_sleep_clk_src = {
890 .cmd_rcgr = 0xc1a4,
891 .mnd_width = 0,
892 .hid_width = 5,
893 .parent_map = camcc_parent_map_7,
894 .freq_tbl = ftbl_camcc_sleep_clk_src,
895 .clkr.hw.init = &(const struct clk_init_data) {
896 .name = "camcc_sleep_clk_src",
897 .parent_data = camcc_parent_data_7,
898 .num_parents = ARRAY_SIZE(camcc_parent_data_7),
899 .ops = &clk_rcg2_ops,
900 },
901};
902
903static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
904 F(19200000, P_BI_TCXO, 1, 0, 0),
905 F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0),
906 { }
907};
908
909static struct clk_rcg2 camcc_slow_ahb_clk_src = {
910 .cmd_rcgr = 0x7058,
911 .mnd_width = 0,
912 .hid_width = 5,
913 .parent_map = camcc_parent_map_8,
914 .freq_tbl = ftbl_camcc_slow_ahb_clk_src,
915 .clkr.hw.init = &(const struct clk_init_data) {
916 .name = "camcc_slow_ahb_clk_src",
917 .parent_data = camcc_parent_data_8,
918 .num_parents = ARRAY_SIZE(camcc_parent_data_8),
919 .ops = &clk_rcg2_shared_ops,
920 },
921};
922
923static const struct freq_tbl ftbl_camcc_xo_clk_src[] = {
924 F(19200000, P_BI_TCXO, 1, 0, 0),
925 { }
926};
927
928static struct clk_rcg2 camcc_xo_clk_src = {
929 .cmd_rcgr = 0xc188,
930 .mnd_width = 0,
931 .hid_width = 5,
932 .parent_map = camcc_parent_map_9,
933 .freq_tbl = ftbl_camcc_xo_clk_src,
934 .clkr.hw.init = &(const struct clk_init_data) {
935 .name = "camcc_xo_clk_src",
936 .parent_data = camcc_parent_data_9,
937 .num_parents = ARRAY_SIZE(camcc_parent_data_9),
938 .ops = &clk_rcg2_ops,
939 },
940};
941
942static struct clk_branch camcc_bps_ahb_clk = {
943 .halt_reg = 0x7070,
944 .halt_check = BRANCH_HALT,
945 .clkr = {
946 .enable_reg = 0x7070,
947 .enable_mask = BIT(0),
948 .hw.init = &(const struct clk_init_data) {
949 .name = "camcc_bps_ahb_clk",
950 .parent_hws = (const struct clk_hw*[]) {
951 &camcc_slow_ahb_clk_src.clkr.hw,
952 },
953 .num_parents = 1,
954 .flags = CLK_SET_RATE_PARENT,
955 .ops = &clk_branch2_ops,
956 },
957 },
958};
959
960static struct clk_branch camcc_bps_areg_clk = {
961 .halt_reg = 0x7054,
962 .halt_check = BRANCH_HALT,
963 .clkr = {
964 .enable_reg = 0x7054,
965 .enable_mask = BIT(0),
966 .hw.init = &(const struct clk_init_data) {
967 .name = "camcc_bps_areg_clk",
968 .parent_hws = (const struct clk_hw*[]) {
969 &camcc_fast_ahb_clk_src.clkr.hw,
970 },
971 .num_parents = 1,
972 .flags = CLK_SET_RATE_PARENT,
973 .ops = &clk_branch2_ops,
974 },
975 },
976};
977
978static struct clk_branch camcc_bps_axi_clk = {
979 .halt_reg = 0x7038,
980 .halt_check = BRANCH_HALT,
981 .clkr = {
982 .enable_reg = 0x7038,
983 .enable_mask = BIT(0),
984 .hw.init = &(const struct clk_init_data) {
985 .name = "camcc_bps_axi_clk",
986 .parent_hws = (const struct clk_hw*[]) {
987 &camcc_camnoc_axi_clk_src.clkr.hw,
988 },
989 .num_parents = 1,
990 .flags = CLK_SET_RATE_PARENT,
991 .ops = &clk_branch2_ops,
992 },
993 },
994};
995
996static struct clk_branch camcc_bps_clk = {
997 .halt_reg = 0x7028,
998 .halt_check = BRANCH_HALT,
999 .clkr = {
1000 .enable_reg = 0x7028,
1001 .enable_mask = BIT(0),
1002 .hw.init = &(const struct clk_init_data) {
1003 .name = "camcc_bps_clk",
1004 .parent_hws = (const struct clk_hw*[]) {
1005 &camcc_bps_clk_src.clkr.hw,
1006 },
1007 .num_parents = 1,
1008 .flags = CLK_SET_RATE_PARENT,
1009 .ops = &clk_branch2_ops,
1010 },
1011 },
1012};
1013
1014static struct clk_branch camcc_camnoc_axi_clk = {
1015 .halt_reg = 0xc148,
1016 .halt_check = BRANCH_HALT,
1017 .clkr = {
1018 .enable_reg = 0xc148,
1019 .enable_mask = BIT(0),
1020 .hw.init = &(const struct clk_init_data) {
1021 .name = "camcc_camnoc_axi_clk",
1022 .parent_hws = (const struct clk_hw*[]) {
1023 &camcc_camnoc_axi_clk_src.clkr.hw,
1024 },
1025 .num_parents = 1,
1026 .flags = CLK_SET_RATE_PARENT,
1027 .ops = &clk_branch2_ops,
1028 },
1029 },
1030};
1031
1032static struct clk_branch camcc_camnoc_dcd_xo_clk = {
1033 .halt_reg = 0xc150,
1034 .halt_check = BRANCH_HALT,
1035 .clkr = {
1036 .enable_reg = 0xc150,
1037 .enable_mask = BIT(0),
1038 .hw.init = &(const struct clk_init_data) {
1039 .name = "camcc_camnoc_dcd_xo_clk",
1040 .parent_hws = (const struct clk_hw*[]) {
1041 &camcc_xo_clk_src.clkr.hw,
1042 },
1043 .num_parents = 1,
1044 .flags = CLK_SET_RATE_PARENT,
1045 .ops = &clk_branch2_ops,
1046 },
1047 },
1048};
1049
1050static struct clk_branch camcc_cci_0_clk = {
1051 .halt_reg = 0xc0dc,
1052 .halt_check = BRANCH_HALT,
1053 .clkr = {
1054 .enable_reg = 0xc0dc,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(const struct clk_init_data) {
1057 .name = "camcc_cci_0_clk",
1058 .parent_hws = (const struct clk_hw*[]) {
1059 &camcc_cci_0_clk_src.clkr.hw,
1060 },
1061 .num_parents = 1,
1062 .flags = CLK_SET_RATE_PARENT,
1063 .ops = &clk_branch2_ops,
1064 },
1065 },
1066};
1067
1068static struct clk_branch camcc_cci_1_clk = {
1069 .halt_reg = 0xc0f8,
1070 .halt_check = BRANCH_HALT,
1071 .clkr = {
1072 .enable_reg = 0xc0f8,
1073 .enable_mask = BIT(0),
1074 .hw.init = &(const struct clk_init_data) {
1075 .name = "camcc_cci_1_clk",
1076 .parent_hws = (const struct clk_hw*[]) {
1077 &camcc_cci_1_clk_src.clkr.hw,
1078 },
1079 .num_parents = 1,
1080 .flags = CLK_SET_RATE_PARENT,
1081 .ops = &clk_branch2_ops,
1082 },
1083 },
1084};
1085
1086static struct clk_branch camcc_core_ahb_clk = {
1087 .halt_reg = 0xc184,
1088 .halt_check = BRANCH_HALT_DELAY,
1089 .clkr = {
1090 .enable_reg = 0xc184,
1091 .enable_mask = BIT(0),
1092 .hw.init = &(const struct clk_init_data) {
1093 .name = "camcc_core_ahb_clk",
1094 .parent_hws = (const struct clk_hw*[]) {
1095 &camcc_slow_ahb_clk_src.clkr.hw,
1096 },
1097 .num_parents = 1,
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_branch2_ops,
1100 },
1101 },
1102};
1103
1104static struct clk_branch camcc_cpas_ahb_clk = {
1105 .halt_reg = 0xc124,
1106 .halt_check = BRANCH_HALT,
1107 .clkr = {
1108 .enable_reg = 0xc124,
1109 .enable_mask = BIT(0),
1110 .hw.init = &(const struct clk_init_data) {
1111 .name = "camcc_cpas_ahb_clk",
1112 .parent_hws = (const struct clk_hw*[]) {
1113 &camcc_slow_ahb_clk_src.clkr.hw,
1114 },
1115 .num_parents = 1,
1116 .flags = CLK_SET_RATE_PARENT,
1117 .ops = &clk_branch2_ops,
1118 },
1119 },
1120};
1121
1122static struct clk_branch camcc_csi0phytimer_clk = {
1123 .halt_reg = 0x601c,
1124 .halt_check = BRANCH_HALT,
1125 .clkr = {
1126 .enable_reg = 0x601c,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(const struct clk_init_data) {
1129 .name = "camcc_csi0phytimer_clk",
1130 .parent_hws = (const struct clk_hw*[]) {
1131 &camcc_csi0phytimer_clk_src.clkr.hw,
1132 },
1133 .num_parents = 1,
1134 .flags = CLK_SET_RATE_PARENT,
1135 .ops = &clk_branch2_ops,
1136 },
1137 },
1138};
1139
1140static struct clk_branch camcc_csi1phytimer_clk = {
1141 .halt_reg = 0x6040,
1142 .halt_check = BRANCH_HALT,
1143 .clkr = {
1144 .enable_reg = 0x6040,
1145 .enable_mask = BIT(0),
1146 .hw.init = &(const struct clk_init_data) {
1147 .name = "camcc_csi1phytimer_clk",
1148 .parent_hws = (const struct clk_hw*[]) {
1149 &camcc_csi1phytimer_clk_src.clkr.hw,
1150 },
1151 .num_parents = 1,
1152 .flags = CLK_SET_RATE_PARENT,
1153 .ops = &clk_branch2_ops,
1154 },
1155 },
1156};
1157
1158static struct clk_branch camcc_csi2phytimer_clk = {
1159 .halt_reg = 0x6064,
1160 .halt_check = BRANCH_HALT,
1161 .clkr = {
1162 .enable_reg = 0x6064,
1163 .enable_mask = BIT(0),
1164 .hw.init = &(const struct clk_init_data) {
1165 .name = "camcc_csi2phytimer_clk",
1166 .parent_hws = (const struct clk_hw*[]) {
1167 &camcc_csi2phytimer_clk_src.clkr.hw,
1168 },
1169 .num_parents = 1,
1170 .flags = CLK_SET_RATE_PARENT,
1171 .ops = &clk_branch2_ops,
1172 },
1173 },
1174};
1175
1176static struct clk_branch camcc_csi3phytimer_clk = {
1177 .halt_reg = 0x6088,
1178 .halt_check = BRANCH_HALT,
1179 .clkr = {
1180 .enable_reg = 0x6088,
1181 .enable_mask = BIT(0),
1182 .hw.init = &(const struct clk_init_data) {
1183 .name = "camcc_csi3phytimer_clk",
1184 .parent_hws = (const struct clk_hw*[]) {
1185 &camcc_csi3phytimer_clk_src.clkr.hw,
1186 },
1187 .num_parents = 1,
1188 .flags = CLK_SET_RATE_PARENT,
1189 .ops = &clk_branch2_ops,
1190 },
1191 },
1192};
1193
1194static struct clk_branch camcc_csiphy0_clk = {
1195 .halt_reg = 0x6020,
1196 .halt_check = BRANCH_HALT,
1197 .clkr = {
1198 .enable_reg = 0x6020,
1199 .enable_mask = BIT(0),
1200 .hw.init = &(const struct clk_init_data) {
1201 .name = "camcc_csiphy0_clk",
1202 .parent_hws = (const struct clk_hw*[]) {
1203 &camcc_cphy_rx_clk_src.clkr.hw,
1204 },
1205 .num_parents = 1,
1206 .flags = CLK_SET_RATE_PARENT,
1207 .ops = &clk_branch2_ops,
1208 },
1209 },
1210};
1211
1212static struct clk_branch camcc_csiphy1_clk = {
1213 .halt_reg = 0x6044,
1214 .halt_check = BRANCH_HALT,
1215 .clkr = {
1216 .enable_reg = 0x6044,
1217 .enable_mask = BIT(0),
1218 .hw.init = &(const struct clk_init_data) {
1219 .name = "camcc_csiphy1_clk",
1220 .parent_hws = (const struct clk_hw*[]) {
1221 &camcc_cphy_rx_clk_src.clkr.hw,
1222 },
1223 .num_parents = 1,
1224 .flags = CLK_SET_RATE_PARENT,
1225 .ops = &clk_branch2_ops,
1226 },
1227 },
1228};
1229
1230static struct clk_branch camcc_csiphy2_clk = {
1231 .halt_reg = 0x6068,
1232 .halt_check = BRANCH_HALT,
1233 .clkr = {
1234 .enable_reg = 0x6068,
1235 .enable_mask = BIT(0),
1236 .hw.init = &(const struct clk_init_data) {
1237 .name = "camcc_csiphy2_clk",
1238 .parent_hws = (const struct clk_hw*[]) {
1239 &camcc_cphy_rx_clk_src.clkr.hw,
1240 },
1241 .num_parents = 1,
1242 .flags = CLK_SET_RATE_PARENT,
1243 .ops = &clk_branch2_ops,
1244 },
1245 },
1246};
1247
1248static struct clk_branch camcc_csiphy3_clk = {
1249 .halt_reg = 0x608c,
1250 .halt_check = BRANCH_HALT,
1251 .clkr = {
1252 .enable_reg = 0x608c,
1253 .enable_mask = BIT(0),
1254 .hw.init = &(const struct clk_init_data) {
1255 .name = "camcc_csiphy3_clk",
1256 .parent_hws = (const struct clk_hw*[]) {
1257 &camcc_cphy_rx_clk_src.clkr.hw,
1258 },
1259 .num_parents = 1,
1260 .flags = CLK_SET_RATE_PARENT,
1261 .ops = &clk_branch2_ops,
1262 },
1263 },
1264};
1265
1266static struct clk_branch camcc_fd_core_clk = {
1267 .halt_reg = 0xc0b4,
1268 .halt_check = BRANCH_HALT,
1269 .clkr = {
1270 .enable_reg = 0xc0b4,
1271 .enable_mask = BIT(0),
1272 .hw.init = &(const struct clk_init_data) {
1273 .name = "camcc_fd_core_clk",
1274 .parent_hws = (const struct clk_hw*[]) {
1275 &camcc_fd_core_clk_src.clkr.hw,
1276 },
1277 .num_parents = 1,
1278 .flags = CLK_SET_RATE_PARENT,
1279 .ops = &clk_branch2_ops,
1280 },
1281 },
1282};
1283
1284static struct clk_branch camcc_fd_core_uar_clk = {
1285 .halt_reg = 0xc0bc,
1286 .halt_check = BRANCH_HALT,
1287 .clkr = {
1288 .enable_reg = 0xc0bc,
1289 .enable_mask = BIT(0),
1290 .hw.init = &(const struct clk_init_data) {
1291 .name = "camcc_fd_core_uar_clk",
1292 .parent_hws = (const struct clk_hw*[]) {
1293 &camcc_fd_core_clk_src.clkr.hw,
1294 },
1295 .num_parents = 1,
1296 .flags = CLK_SET_RATE_PARENT,
1297 .ops = &clk_branch2_ops,
1298 },
1299 },
1300};
1301
1302static struct clk_branch camcc_icp_ahb_clk = {
1303 .halt_reg = 0xc094,
1304 .halt_check = BRANCH_HALT,
1305 .clkr = {
1306 .enable_reg = 0xc094,
1307 .enable_mask = BIT(0),
1308 .hw.init = &(const struct clk_init_data) {
1309 .name = "camcc_icp_ahb_clk",
1310 .parent_hws = (const struct clk_hw*[]) {
1311 &camcc_slow_ahb_clk_src.clkr.hw,
1312 },
1313 .num_parents = 1,
1314 .flags = CLK_SET_RATE_PARENT,
1315 .ops = &clk_branch2_ops,
1316 },
1317 },
1318};
1319
1320static struct clk_branch camcc_icp_clk = {
1321 .halt_reg = 0xc08c,
1322 .halt_check = BRANCH_HALT,
1323 .clkr = {
1324 .enable_reg = 0xc08c,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(const struct clk_init_data) {
1327 .name = "camcc_icp_clk",
1328 .parent_hws = (const struct clk_hw*[]) {
1329 &camcc_icp_clk_src.clkr.hw,
1330 },
1331 .num_parents = 1,
1332 .flags = CLK_SET_RATE_PARENT,
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336};
1337
1338static struct clk_branch camcc_ife_0_axi_clk = {
1339 .halt_reg = 0xa080,
1340 .halt_check = BRANCH_HALT,
1341 .clkr = {
1342 .enable_reg = 0xa080,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(const struct clk_init_data) {
1345 .name = "camcc_ife_0_axi_clk",
1346 .parent_hws = (const struct clk_hw*[]) {
1347 &camcc_camnoc_axi_clk_src.clkr.hw,
1348 },
1349 .num_parents = 1,
1350 .flags = CLK_SET_RATE_PARENT,
1351 .ops = &clk_branch2_ops,
1352 },
1353 },
1354};
1355
1356static struct clk_branch camcc_ife_0_clk = {
1357 .halt_reg = 0xa028,
1358 .halt_check = BRANCH_HALT,
1359 .clkr = {
1360 .enable_reg = 0xa028,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(const struct clk_init_data) {
1363 .name = "camcc_ife_0_clk",
1364 .parent_hws = (const struct clk_hw*[]) {
1365 &camcc_ife_0_clk_src.clkr.hw,
1366 },
1367 .num_parents = 1,
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1370 },
1371 },
1372};
1373
1374static struct clk_branch camcc_ife_0_cphy_rx_clk = {
1375 .halt_reg = 0xa07c,
1376 .halt_check = BRANCH_HALT,
1377 .clkr = {
1378 .enable_reg = 0xa07c,
1379 .enable_mask = BIT(0),
1380 .hw.init = &(const struct clk_init_data) {
1381 .name = "camcc_ife_0_cphy_rx_clk",
1382 .parent_hws = (const struct clk_hw*[]) {
1383 &camcc_cphy_rx_clk_src.clkr.hw,
1384 },
1385 .num_parents = 1,
1386 .flags = CLK_SET_RATE_PARENT,
1387 .ops = &clk_branch2_ops,
1388 },
1389 },
1390};
1391
1392static struct clk_branch camcc_ife_0_csid_clk = {
1393 .halt_reg = 0xa054,
1394 .halt_check = BRANCH_HALT,
1395 .clkr = {
1396 .enable_reg = 0xa054,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(const struct clk_init_data) {
1399 .name = "camcc_ife_0_csid_clk",
1400 .parent_hws = (const struct clk_hw*[]) {
1401 &camcc_ife_0_csid_clk_src.clkr.hw,
1402 },
1403 .num_parents = 1,
1404 .flags = CLK_SET_RATE_PARENT,
1405 .ops = &clk_branch2_ops,
1406 },
1407 },
1408};
1409
1410static struct clk_branch camcc_ife_0_dsp_clk = {
1411 .halt_reg = 0xa038,
1412 .halt_check = BRANCH_HALT,
1413 .clkr = {
1414 .enable_reg = 0xa038,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(const struct clk_init_data) {
1417 .name = "camcc_ife_0_dsp_clk",
1418 .parent_hws = (const struct clk_hw*[]) {
1419 &camcc_ife_0_clk_src.clkr.hw,
1420 },
1421 .num_parents = 1,
1422 .flags = CLK_SET_RATE_PARENT,
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428static struct clk_branch camcc_ife_1_axi_clk = {
1429 .halt_reg = 0xb058,
1430 .halt_check = BRANCH_HALT,
1431 .clkr = {
1432 .enable_reg = 0xb058,
1433 .enable_mask = BIT(0),
1434 .hw.init = &(const struct clk_init_data) {
1435 .name = "camcc_ife_1_axi_clk",
1436 .parent_hws = (const struct clk_hw*[]) {
1437 &camcc_camnoc_axi_clk_src.clkr.hw,
1438 },
1439 .num_parents = 1,
1440 .flags = CLK_SET_RATE_PARENT,
1441 .ops = &clk_branch2_ops,
1442 },
1443 },
1444};
1445
1446static struct clk_branch camcc_ife_1_clk = {
1447 .halt_reg = 0xb028,
1448 .halt_check = BRANCH_HALT,
1449 .clkr = {
1450 .enable_reg = 0xb028,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(const struct clk_init_data) {
1453 .name = "camcc_ife_1_clk",
1454 .parent_hws = (const struct clk_hw*[]) {
1455 &camcc_ife_1_clk_src.clkr.hw,
1456 },
1457 .num_parents = 1,
1458 .flags = CLK_SET_RATE_PARENT,
1459 .ops = &clk_branch2_ops,
1460 },
1461 },
1462};
1463
1464static struct clk_branch camcc_ife_1_cphy_rx_clk = {
1465 .halt_reg = 0xb054,
1466 .halt_check = BRANCH_HALT,
1467 .clkr = {
1468 .enable_reg = 0xb054,
1469 .enable_mask = BIT(0),
1470 .hw.init = &(const struct clk_init_data) {
1471 .name = "camcc_ife_1_cphy_rx_clk",
1472 .parent_hws = (const struct clk_hw*[]) {
1473 &camcc_cphy_rx_clk_src.clkr.hw,
1474 },
1475 .num_parents = 1,
1476 .flags = CLK_SET_RATE_PARENT,
1477 .ops = &clk_branch2_ops,
1478 },
1479 },
1480};
1481
1482static struct clk_branch camcc_ife_1_csid_clk = {
1483 .halt_reg = 0xb04c,
1484 .halt_check = BRANCH_HALT,
1485 .clkr = {
1486 .enable_reg = 0xb04c,
1487 .enable_mask = BIT(0),
1488 .hw.init = &(const struct clk_init_data) {
1489 .name = "camcc_ife_1_csid_clk",
1490 .parent_hws = (const struct clk_hw*[]) {
1491 &camcc_ife_1_csid_clk_src.clkr.hw,
1492 },
1493 .num_parents = 1,
1494 .flags = CLK_SET_RATE_PARENT,
1495 .ops = &clk_branch2_ops,
1496 },
1497 },
1498};
1499
1500static struct clk_branch camcc_ife_1_dsp_clk = {
1501 .halt_reg = 0xb030,
1502 .halt_check = BRANCH_HALT,
1503 .clkr = {
1504 .enable_reg = 0xb030,
1505 .enable_mask = BIT(0),
1506 .hw.init = &(const struct clk_init_data) {
1507 .name = "camcc_ife_1_dsp_clk",
1508 .parent_hws = (const struct clk_hw*[]) {
1509 &camcc_ife_1_clk_src.clkr.hw,
1510 },
1511 .num_parents = 1,
1512 .flags = CLK_SET_RATE_PARENT,
1513 .ops = &clk_branch2_ops,
1514 },
1515 },
1516};
1517
1518static struct clk_branch camcc_ife_lite_clk = {
1519 .halt_reg = 0xc01c,
1520 .halt_check = BRANCH_HALT,
1521 .clkr = {
1522 .enable_reg = 0xc01c,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(const struct clk_init_data) {
1525 .name = "camcc_ife_lite_clk",
1526 .parent_hws = (const struct clk_hw*[]) {
1527 &camcc_ife_lite_clk_src.clkr.hw,
1528 },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch camcc_ife_lite_cphy_rx_clk = {
1537 .halt_reg = 0xc040,
1538 .halt_check = BRANCH_HALT,
1539 .clkr = {
1540 .enable_reg = 0xc040,
1541 .enable_mask = BIT(0),
1542 .hw.init = &(const struct clk_init_data) {
1543 .name = "camcc_ife_lite_cphy_rx_clk",
1544 .parent_hws = (const struct clk_hw*[]) {
1545 &camcc_cphy_rx_clk_src.clkr.hw,
1546 },
1547 .num_parents = 1,
1548 .flags = CLK_SET_RATE_PARENT,
1549 .ops = &clk_branch2_ops,
1550 },
1551 },
1552};
1553
1554static struct clk_branch camcc_ife_lite_csid_clk = {
1555 .halt_reg = 0xc038,
1556 .halt_check = BRANCH_HALT,
1557 .clkr = {
1558 .enable_reg = 0xc038,
1559 .enable_mask = BIT(0),
1560 .hw.init = &(const struct clk_init_data) {
1561 .name = "camcc_ife_lite_csid_clk",
1562 .parent_hws = (const struct clk_hw*[]) {
1563 &camcc_ife_lite_csid_clk_src.clkr.hw,
1564 },
1565 .num_parents = 1,
1566 .flags = CLK_SET_RATE_PARENT,
1567 .ops = &clk_branch2_ops,
1568 },
1569 },
1570};
1571
1572static struct clk_branch camcc_ipe_0_ahb_clk = {
1573 .halt_reg = 0x8040,
1574 .halt_check = BRANCH_HALT,
1575 .clkr = {
1576 .enable_reg = 0x8040,
1577 .enable_mask = BIT(0),
1578 .hw.init = &(const struct clk_init_data) {
1579 .name = "camcc_ipe_0_ahb_clk",
1580 .parent_hws = (const struct clk_hw*[]) {
1581 &camcc_slow_ahb_clk_src.clkr.hw,
1582 },
1583 .num_parents = 1,
1584 .flags = CLK_SET_RATE_PARENT,
1585 .ops = &clk_branch2_ops,
1586 },
1587 },
1588};
1589
1590static struct clk_branch camcc_ipe_0_areg_clk = {
1591 .halt_reg = 0x803c,
1592 .halt_check = BRANCH_HALT,
1593 .clkr = {
1594 .enable_reg = 0x803c,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(const struct clk_init_data) {
1597 .name = "camcc_ipe_0_areg_clk",
1598 .parent_hws = (const struct clk_hw*[]) {
1599 &camcc_fast_ahb_clk_src.clkr.hw,
1600 },
1601 .num_parents = 1,
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1604 },
1605 },
1606};
1607
1608static struct clk_branch camcc_ipe_0_axi_clk = {
1609 .halt_reg = 0x8038,
1610 .halt_check = BRANCH_HALT,
1611 .clkr = {
1612 .enable_reg = 0x8038,
1613 .enable_mask = BIT(0),
1614 .hw.init = &(const struct clk_init_data) {
1615 .name = "camcc_ipe_0_axi_clk",
1616 .parent_hws = (const struct clk_hw*[]) {
1617 &camcc_camnoc_axi_clk_src.clkr.hw,
1618 },
1619 .num_parents = 1,
1620 .flags = CLK_SET_RATE_PARENT,
1621 .ops = &clk_branch2_ops,
1622 },
1623 },
1624};
1625
1626static struct clk_branch camcc_ipe_0_clk = {
1627 .halt_reg = 0x8028,
1628 .halt_check = BRANCH_HALT,
1629 .clkr = {
1630 .enable_reg = 0x8028,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(const struct clk_init_data) {
1633 .name = "camcc_ipe_0_clk",
1634 .parent_hws = (const struct clk_hw*[]) {
1635 &camcc_ipe_0_clk_src.clkr.hw,
1636 },
1637 .num_parents = 1,
1638 .flags = CLK_SET_RATE_PARENT,
1639 .ops = &clk_branch2_ops,
1640 },
1641 },
1642};
1643
1644static struct clk_branch camcc_ipe_1_ahb_clk = {
1645 .halt_reg = 0x9028,
1646 .halt_check = BRANCH_HALT,
1647 .clkr = {
1648 .enable_reg = 0x9028,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(const struct clk_init_data) {
1651 .name = "camcc_ipe_1_ahb_clk",
1652 .parent_hws = (const struct clk_hw*[]) {
1653 &camcc_slow_ahb_clk_src.clkr.hw,
1654 },
1655 .num_parents = 1,
1656 .flags = CLK_SET_RATE_PARENT,
1657 .ops = &clk_branch2_ops,
1658 },
1659 },
1660};
1661
1662static struct clk_branch camcc_ipe_1_areg_clk = {
1663 .halt_reg = 0x9024,
1664 .halt_check = BRANCH_HALT,
1665 .clkr = {
1666 .enable_reg = 0x9024,
1667 .enable_mask = BIT(0),
1668 .hw.init = &(const struct clk_init_data) {
1669 .name = "camcc_ipe_1_areg_clk",
1670 .parent_hws = (const struct clk_hw*[]) {
1671 &camcc_fast_ahb_clk_src.clkr.hw,
1672 },
1673 .num_parents = 1,
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1676 },
1677 },
1678};
1679
1680static struct clk_branch camcc_ipe_1_axi_clk = {
1681 .halt_reg = 0x9020,
1682 .halt_check = BRANCH_HALT,
1683 .clkr = {
1684 .enable_reg = 0x9020,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(const struct clk_init_data) {
1687 .name = "camcc_ipe_1_axi_clk",
1688 .parent_hws = (const struct clk_hw*[]) {
1689 &camcc_camnoc_axi_clk_src.clkr.hw,
1690 },
1691 .num_parents = 1,
1692 .flags = CLK_SET_RATE_PARENT,
1693 .ops = &clk_branch2_ops,
1694 },
1695 },
1696};
1697
1698static struct clk_branch camcc_ipe_1_clk = {
1699 .halt_reg = 0x9010,
1700 .halt_check = BRANCH_HALT,
1701 .clkr = {
1702 .enable_reg = 0x9010,
1703 .enable_mask = BIT(0),
1704 .hw.init = &(const struct clk_init_data) {
1705 .name = "camcc_ipe_1_clk",
1706 .parent_hws = (const struct clk_hw*[]) {
1707 &camcc_ipe_0_clk_src.clkr.hw,
1708 },
1709 .num_parents = 1,
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch camcc_jpeg_clk = {
1717 .halt_reg = 0xc060,
1718 .halt_check = BRANCH_HALT,
1719 .clkr = {
1720 .enable_reg = 0xc060,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(const struct clk_init_data) {
1723 .name = "camcc_jpeg_clk",
1724 .parent_hws = (const struct clk_hw*[]) {
1725 &camcc_jpeg_clk_src.clkr.hw,
1726 },
1727 .num_parents = 1,
1728 .flags = CLK_SET_RATE_PARENT,
1729 .ops = &clk_branch2_ops,
1730 },
1731 },
1732};
1733
1734static struct clk_branch camcc_lrme_clk = {
1735 .halt_reg = 0xc118,
1736 .halt_check = BRANCH_HALT,
1737 .clkr = {
1738 .enable_reg = 0xc118,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(const struct clk_init_data) {
1741 .name = "camcc_lrme_clk",
1742 .parent_hws = (const struct clk_hw*[]) {
1743 &camcc_lrme_clk_src.clkr.hw,
1744 },
1745 .num_parents = 1,
1746 .flags = CLK_SET_RATE_PARENT,
1747 .ops = &clk_branch2_ops,
1748 },
1749 },
1750};
1751
1752static struct clk_branch camcc_mclk0_clk = {
1753 .halt_reg = 0x501c,
1754 .halt_check = BRANCH_HALT,
1755 .clkr = {
1756 .enable_reg = 0x501c,
1757 .enable_mask = BIT(0),
1758 .hw.init = &(const struct clk_init_data) {
1759 .name = "camcc_mclk0_clk",
1760 .parent_hws = (const struct clk_hw*[]) {
1761 &camcc_mclk0_clk_src.clkr.hw,
1762 },
1763 .num_parents = 1,
1764 .flags = CLK_SET_RATE_PARENT,
1765 .ops = &clk_branch2_ops,
1766 },
1767 },
1768};
1769
1770static struct clk_branch camcc_mclk1_clk = {
1771 .halt_reg = 0x503c,
1772 .halt_check = BRANCH_HALT,
1773 .clkr = {
1774 .enable_reg = 0x503c,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(const struct clk_init_data) {
1777 .name = "camcc_mclk1_clk",
1778 .parent_hws = (const struct clk_hw*[]) {
1779 &camcc_mclk1_clk_src.clkr.hw,
1780 },
1781 .num_parents = 1,
1782 .flags = CLK_SET_RATE_PARENT,
1783 .ops = &clk_branch2_ops,
1784 },
1785 },
1786};
1787
1788static struct clk_branch camcc_mclk2_clk = {
1789 .halt_reg = 0x505c,
1790 .halt_check = BRANCH_HALT,
1791 .clkr = {
1792 .enable_reg = 0x505c,
1793 .enable_mask = BIT(0),
1794 .hw.init = &(const struct clk_init_data) {
1795 .name = "camcc_mclk2_clk",
1796 .parent_hws = (const struct clk_hw*[]) {
1797 &camcc_mclk2_clk_src.clkr.hw,
1798 },
1799 .num_parents = 1,
1800 .flags = CLK_SET_RATE_PARENT,
1801 .ops = &clk_branch2_ops,
1802 },
1803 },
1804};
1805
1806static struct clk_branch camcc_mclk3_clk = {
1807 .halt_reg = 0x507c,
1808 .halt_check = BRANCH_HALT,
1809 .clkr = {
1810 .enable_reg = 0x507c,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(const struct clk_init_data) {
1813 .name = "camcc_mclk3_clk",
1814 .parent_hws = (const struct clk_hw*[]) {
1815 &camcc_mclk3_clk_src.clkr.hw,
1816 },
1817 .num_parents = 1,
1818 .flags = CLK_SET_RATE_PARENT,
1819 .ops = &clk_branch2_ops,
1820 },
1821 },
1822};
1823
1824static struct clk_branch camcc_sleep_clk = {
1825 .halt_reg = 0xc1bc,
1826 .halt_check = BRANCH_HALT,
1827 .clkr = {
1828 .enable_reg = 0xc1bc,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(const struct clk_init_data) {
1831 .name = "camcc_sleep_clk",
1832 .parent_hws = (const struct clk_hw*[]) {
1833 &camcc_sleep_clk_src.clkr.hw,
1834 },
1835 .num_parents = 1,
1836 .flags = CLK_SET_RATE_PARENT,
1837 .ops = &clk_branch2_ops,
1838 },
1839 },
1840};
1841
1842static struct gdsc camcc_titan_top_gdsc;
1843
1844static struct gdsc camcc_bps_gdsc = {
1845 .gdscr = 0x7004,
1846 .pd = {
1847 .name = "camcc_bps_gdsc",
1848 },
1849 .flags = HW_CTRL | POLL_CFG_GDSCR,
1850 .pwrsts = PWRSTS_OFF_ON,
1851};
1852
1853static struct gdsc camcc_ife_0_gdsc = {
1854 .gdscr = 0xa004,
1855 .pd = {
1856 .name = "camcc_ife_0_gdsc",
1857 },
1858 .flags = POLL_CFG_GDSCR,
1859 .parent = &camcc_titan_top_gdsc.pd,
1860 .pwrsts = PWRSTS_OFF_ON,
1861};
1862
1863static struct gdsc camcc_ife_1_gdsc = {
1864 .gdscr = 0xb004,
1865 .pd = {
1866 .name = "camcc_ife_1_gdsc",
1867 },
1868 .flags = POLL_CFG_GDSCR,
1869 .parent = &camcc_titan_top_gdsc.pd,
1870 .pwrsts = PWRSTS_OFF_ON,
1871};
1872
1873static struct gdsc camcc_ipe_0_gdsc = {
1874 .gdscr = 0x8004,
1875 .pd = {
1876 .name = "camcc_ipe_0_gdsc",
1877 },
1878 .flags = HW_CTRL | POLL_CFG_GDSCR,
1879 .pwrsts = PWRSTS_OFF_ON,
1880};
1881
1882static struct gdsc camcc_ipe_1_gdsc = {
1883 .gdscr = 0x9004,
1884 .pd = {
1885 .name = "camcc_ipe_1_gdsc",
1886 },
1887 .flags = HW_CTRL | POLL_CFG_GDSCR,
1888 .pwrsts = PWRSTS_OFF_ON,
1889};
1890
1891static struct gdsc camcc_titan_top_gdsc = {
1892 .gdscr = 0xc1c4,
1893 .pd = {
1894 .name = "camcc_titan_top_gdsc",
1895 },
1896 .flags = POLL_CFG_GDSCR,
1897 .pwrsts = PWRSTS_OFF_ON,
1898};
1899
1900struct clk_hw *camcc_sm7150_hws[] = {
1901 [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw,
1902 [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw,
1903 [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw,
1904 [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw,
1905 [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.hw,
1906 [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.hw,
1907};
1908
1909static struct clk_regmap *camcc_sm7150_clocks[] = {
1910 [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
1911 [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
1912 [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
1913 [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
1914 [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
1915 [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
1916 [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr,
1917 [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr,
1918 [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
1919 [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
1920 [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
1921 [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
1922 [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
1923 [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
1924 [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
1925 [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
1926 [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
1927 [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
1928 [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
1929 [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
1930 [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
1931 [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
1932 [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
1933 [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
1934 [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
1935 [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
1936 [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
1937 [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
1938 [CAMCC_FD_CORE_CLK] = &camcc_fd_core_clk.clkr,
1939 [CAMCC_FD_CORE_CLK_SRC] = &camcc_fd_core_clk_src.clkr,
1940 [CAMCC_FD_CORE_UAR_CLK] = &camcc_fd_core_uar_clk.clkr,
1941 [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr,
1942 [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
1943 [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
1944 [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
1945 [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
1946 [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
1947 [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
1948 [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
1949 [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
1950 [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
1951 [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
1952 [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
1953 [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
1954 [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
1955 [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
1956 [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
1957 [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
1958 [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr,
1959 [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr,
1960 [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr,
1961 [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr,
1962 [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr,
1963 [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
1964 [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
1965 [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
1966 [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
1967 [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
1968 [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr,
1969 [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr,
1970 [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr,
1971 [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr,
1972 [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
1973 [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
1974 [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
1975 [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
1976 [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
1977 [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
1978 [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
1979 [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
1980 [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
1981 [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
1982 [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
1983 [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
1984 [CAMCC_PLL0] = &camcc_pll0.clkr,
1985 [CAMCC_PLL1] = &camcc_pll1.clkr,
1986 [CAMCC_PLL2] = &camcc_pll2.clkr,
1987 [CAMCC_PLL2_OUT_AUX] = &camcc_pll2_out_aux.clkr,
1988 [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr,
1989 [CAMCC_PLL3] = &camcc_pll3.clkr,
1990 [CAMCC_PLL4] = &camcc_pll4.clkr,
1991 [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr,
1992 [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr,
1993 [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
1994 [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr,
1995};
1996
1997static struct gdsc *camcc_sm7150_gdscs[] = {
1998 [BPS_GDSC] = &camcc_bps_gdsc,
1999 [IFE_0_GDSC] = &camcc_ife_0_gdsc,
2000 [IFE_1_GDSC] = &camcc_ife_1_gdsc,
2001 [IPE_0_GDSC] = &camcc_ipe_0_gdsc,
2002 [IPE_1_GDSC] = &camcc_ipe_1_gdsc,
2003 [TITAN_TOP_GDSC] = &camcc_titan_top_gdsc,
2004};
2005
2006static const struct regmap_config camcc_sm7150_regmap_config = {
2007 .reg_bits = 32,
2008 .reg_stride = 4,
2009 .val_bits = 32,
2010 .max_register = 0xd024,
2011 .fast_io = true,
2012};
2013
2014static const struct qcom_cc_desc camcc_sm7150_desc = {
2015 .config = &camcc_sm7150_regmap_config,
2016 .clk_hws = camcc_sm7150_hws,
2017 .num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws),
2018 .clks = camcc_sm7150_clocks,
2019 .num_clks = ARRAY_SIZE(camcc_sm7150_clocks),
2020 .gdscs = camcc_sm7150_gdscs,
2021 .num_gdscs = ARRAY_SIZE(camcc_sm7150_gdscs),
2022};
2023
2024static const struct of_device_id camcc_sm7150_match_table[] = {
2025 { .compatible = "qcom,sm7150-camcc" },
2026 { }
2027};
2028MODULE_DEVICE_TABLE(of, camcc_sm7150_match_table);
2029
2030static int camcc_sm7150_probe(struct platform_device *pdev)
2031{
2032 struct regmap *regmap;
2033
2034 regmap = qcom_cc_map(pdev, &camcc_sm7150_desc);
2035 if (IS_ERR(regmap))
2036 return PTR_ERR(regmap);
2037
2038 clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
2039 clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
2040 clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
2041 clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
2042 clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config);
2043
2044 /* Keep some clocks always-on */
2045 qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */
2046
2047 return qcom_cc_really_probe(&pdev->dev, &camcc_sm7150_desc, regmap);
2048}
2049
2050static struct platform_driver camcc_sm7150_driver = {
2051 .probe = camcc_sm7150_probe,
2052 .driver = {
2053 .name = "camcc-sm7150",
2054 .of_match_table = camcc_sm7150_match_table,
2055 },
2056};
2057
2058module_platform_driver(camcc_sm7150_driver);
2059
2060MODULE_DESCRIPTION("Qualcomm SM7150 Camera Clock Controller");
2061MODULE_LICENSE("GPL");