Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/clk-provider.h>
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/reset.h>
15#include <linux/reset-controller.h>
16#include <linux/slab.h>
17
18#include "meson-clkc-utils.h"
19#include "axg-audio.h"
20#include "clk-regmap.h"
21#include "clk-phase.h"
22#include "sclk-div.h"
23
24#include <dt-bindings/clock/axg-audio-clkc.h>
25
26#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
27 .data = &(struct clk_regmap_gate_data){ \
28 .offset = (_reg), \
29 .bit_idx = (_bit), \
30 }, \
31 .hw.init = &(struct clk_init_data) { \
32 .name = "aud_"#_name, \
33 .ops = &clk_regmap_gate_ops, \
34 .parent_names = (const char *[]){ #_pname }, \
35 .num_parents = 1, \
36 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
37 }, \
38}
39
40#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \
41 .data = &(struct clk_regmap_mux_data){ \
42 .offset = (_reg), \
43 .mask = (_mask), \
44 .shift = (_shift), \
45 .flags = (_dflags), \
46 }, \
47 .hw.init = &(struct clk_init_data){ \
48 .name = "aud_"#_name, \
49 .ops = &clk_regmap_mux_ops, \
50 .parent_data = _pdata, \
51 .num_parents = ARRAY_SIZE(_pdata), \
52 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
53 }, \
54}
55
56#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
57 .data = &(struct clk_regmap_div_data){ \
58 .offset = (_reg), \
59 .shift = (_shift), \
60 .width = (_width), \
61 .flags = (_dflags), \
62 }, \
63 .hw.init = &(struct clk_init_data){ \
64 .name = "aud_"#_name, \
65 .ops = &clk_regmap_divider_ops, \
66 .parent_names = (const char *[]){ #_pname }, \
67 .num_parents = 1, \
68 .flags = (_iflags), \
69 }, \
70}
71
72#define AUD_PCLK_GATE(_name, _reg, _bit) { \
73 .data = &(struct clk_regmap_gate_data){ \
74 .offset = (_reg), \
75 .bit_idx = (_bit), \
76 }, \
77 .hw.init = &(struct clk_init_data) { \
78 .name = "aud_"#_name, \
79 .ops = &clk_regmap_gate_ops, \
80 .parent_names = (const char *[]){ "aud_top" }, \
81 .num_parents = 1, \
82 }, \
83}
84
85#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
86 _hi_shift, _hi_width, _pname, _iflags) { \
87 .data = &(struct meson_sclk_div_data) { \
88 .div = { \
89 .reg_off = (_reg), \
90 .shift = (_div_shift), \
91 .width = (_div_width), \
92 }, \
93 .hi = { \
94 .reg_off = (_reg), \
95 .shift = (_hi_shift), \
96 .width = (_hi_width), \
97 }, \
98 }, \
99 .hw.init = &(struct clk_init_data) { \
100 .name = "aud_"#_name, \
101 .ops = &meson_sclk_div_ops, \
102 .parent_names = (const char *[]){ #_pname }, \
103 .num_parents = 1, \
104 .flags = (_iflags), \
105 }, \
106}
107
108#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
109 _pname, _iflags) { \
110 .data = &(struct meson_clk_triphase_data) { \
111 .ph0 = { \
112 .reg_off = (_reg), \
113 .shift = (_shift0), \
114 .width = (_width), \
115 }, \
116 .ph1 = { \
117 .reg_off = (_reg), \
118 .shift = (_shift1), \
119 .width = (_width), \
120 }, \
121 .ph2 = { \
122 .reg_off = (_reg), \
123 .shift = (_shift2), \
124 .width = (_width), \
125 }, \
126 }, \
127 .hw.init = &(struct clk_init_data) { \
128 .name = "aud_"#_name, \
129 .ops = &meson_clk_triphase_ops, \
130 .parent_names = (const char *[]){ #_pname }, \
131 .num_parents = 1, \
132 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
133 }, \
134}
135
136#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \
137 .data = &(struct meson_clk_phase_data) { \
138 .ph = { \
139 .reg_off = (_reg), \
140 .shift = (_shift), \
141 .width = (_width), \
142 }, \
143 }, \
144 .hw.init = &(struct clk_init_data) { \
145 .name = "aud_"#_name, \
146 .ops = &meson_clk_phase_ops, \
147 .parent_names = (const char *[]){ #_pname }, \
148 .num_parents = 1, \
149 .flags = (_iflags), \
150 }, \
151}
152
153#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \
154 _iflags) { \
155 .data = &(struct meson_sclk_ws_inv_data) { \
156 .ph = { \
157 .reg_off = (_reg), \
158 .shift = (_shift_ph), \
159 .width = (_width), \
160 }, \
161 .ws = { \
162 .reg_off = (_reg), \
163 .shift = (_shift_ws), \
164 .width = (_width), \
165 }, \
166 }, \
167 .hw.init = &(struct clk_init_data) { \
168 .name = "aud_"#_name, \
169 .ops = &meson_clk_phase_ops, \
170 .parent_names = (const char *[]){ #_pname }, \
171 .num_parents = 1, \
172 .flags = (_iflags), \
173 }, \
174}
175
176/* Audio Master Clocks */
177static const struct clk_parent_data mst_mux_parent_data[] = {
178 { .fw_name = "mst_in0", },
179 { .fw_name = "mst_in1", },
180 { .fw_name = "mst_in2", },
181 { .fw_name = "mst_in3", },
182 { .fw_name = "mst_in4", },
183 { .fw_name = "mst_in5", },
184 { .fw_name = "mst_in6", },
185 { .fw_name = "mst_in7", },
186};
187
188#define AUD_MST_MUX(_name, _reg, _flag) \
189 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
190 mst_mux_parent_data, 0)
191#define AUD_MST_DIV(_name, _reg, _flag) \
192 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
193 aud_##_name##_sel, CLK_SET_RATE_PARENT)
194#define AUD_MST_MCLK_GATE(_name, _reg) \
195 AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
196 CLK_SET_RATE_PARENT)
197
198#define AUD_MST_MCLK_MUX(_name, _reg) \
199 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
200#define AUD_MST_MCLK_DIV(_name, _reg) \
201 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
202
203#define AUD_MST_SYS_MUX(_name, _reg) \
204 AUD_MST_MUX(_name, _reg, 0)
205#define AUD_MST_SYS_DIV(_name, _reg) \
206 AUD_MST_DIV(_name, _reg, 0)
207
208/* Sample Clocks */
209#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
210 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
211 aud_mst_##_name##_mclk, 0)
212#define AUD_MST_SCLK_DIV(_name, _reg) \
213 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
214 aud_mst_##_name##_sclk_pre_en, \
215 CLK_SET_RATE_PARENT)
216#define AUD_MST_SCLK_POST_EN(_name, _reg) \
217 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
218 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
219#define AUD_MST_SCLK(_name, _reg) \
220 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
221 aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
222
223#define AUD_MST_LRCLK_DIV(_name, _reg) \
224 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
225 aud_mst_##_name##_sclk_post_en, 0)
226#define AUD_MST_LRCLK(_name, _reg) \
227 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
228 aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
229
230/* TDM bit clock sources */
231static const struct clk_parent_data tdm_sclk_parent_data[] = {
232 { .name = "aud_mst_a_sclk", .index = -1, },
233 { .name = "aud_mst_b_sclk", .index = -1, },
234 { .name = "aud_mst_c_sclk", .index = -1, },
235 { .name = "aud_mst_d_sclk", .index = -1, },
236 { .name = "aud_mst_e_sclk", .index = -1, },
237 { .name = "aud_mst_f_sclk", .index = -1, },
238 { .fw_name = "slv_sclk0", },
239 { .fw_name = "slv_sclk1", },
240 { .fw_name = "slv_sclk2", },
241 { .fw_name = "slv_sclk3", },
242 { .fw_name = "slv_sclk4", },
243 { .fw_name = "slv_sclk5", },
244 { .fw_name = "slv_sclk6", },
245 { .fw_name = "slv_sclk7", },
246 { .fw_name = "slv_sclk8", },
247 { .fw_name = "slv_sclk9", },
248};
249
250/* TDM sample clock sources */
251static const struct clk_parent_data tdm_lrclk_parent_data[] = {
252 { .name = "aud_mst_a_lrclk", .index = -1, },
253 { .name = "aud_mst_b_lrclk", .index = -1, },
254 { .name = "aud_mst_c_lrclk", .index = -1, },
255 { .name = "aud_mst_d_lrclk", .index = -1, },
256 { .name = "aud_mst_e_lrclk", .index = -1, },
257 { .name = "aud_mst_f_lrclk", .index = -1, },
258 { .fw_name = "slv_lrclk0", },
259 { .fw_name = "slv_lrclk1", },
260 { .fw_name = "slv_lrclk2", },
261 { .fw_name = "slv_lrclk3", },
262 { .fw_name = "slv_lrclk4", },
263 { .fw_name = "slv_lrclk5", },
264 { .fw_name = "slv_lrclk6", },
265 { .fw_name = "slv_lrclk7", },
266 { .fw_name = "slv_lrclk8", },
267 { .fw_name = "slv_lrclk9", },
268};
269
270#define AUD_TDM_SCLK_MUX(_name, _reg) \
271 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
272 CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
273#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
274 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
275 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
276#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
277 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
278 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
279#define AUD_TDM_SCLK(_name, _reg) \
280 AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \
281 aud_tdm##_name##_sclk_post_en, \
282 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
283#define AUD_TDM_SCLK_WS(_name, _reg) \
284 AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \
285 aud_tdm##_name##_sclk_post_en, \
286 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
287
288#define AUD_TDM_LRLCK(_name, _reg) \
289 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
290 CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
291
292/* Pad master clock sources */
293static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
294 { .name = "aud_mst_a_mclk", .index = -1, },
295 { .name = "aud_mst_b_mclk", .index = -1, },
296 { .name = "aud_mst_c_mclk", .index = -1, },
297 { .name = "aud_mst_d_mclk", .index = -1, },
298 { .name = "aud_mst_e_mclk", .index = -1, },
299 { .name = "aud_mst_f_mclk", .index = -1, },
300};
301
302/* Pad bit clock sources */
303static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
304 { .name = "aud_mst_a_sclk", .index = -1, },
305 { .name = "aud_mst_b_sclk", .index = -1, },
306 { .name = "aud_mst_c_sclk", .index = -1, },
307 { .name = "aud_mst_d_sclk", .index = -1, },
308 { .name = "aud_mst_e_sclk", .index = -1, },
309 { .name = "aud_mst_f_sclk", .index = -1, },
310};
311
312/* Pad sample clock sources */
313static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
314 { .name = "aud_mst_a_lrclk", .index = -1, },
315 { .name = "aud_mst_b_lrclk", .index = -1, },
316 { .name = "aud_mst_c_lrclk", .index = -1, },
317 { .name = "aud_mst_d_lrclk", .index = -1, },
318 { .name = "aud_mst_e_lrclk", .index = -1, },
319 { .name = "aud_mst_f_lrclk", .index = -1, },
320};
321
322#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
323 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \
324 CLK_SET_RATE_NO_REPARENT)
325
326/* Common Clocks */
327static struct clk_regmap ddr_arb =
328 AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
329static struct clk_regmap pdm =
330 AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
331static struct clk_regmap tdmin_a =
332 AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
333static struct clk_regmap tdmin_b =
334 AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
335static struct clk_regmap tdmin_c =
336 AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
337static struct clk_regmap tdmin_lb =
338 AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
339static struct clk_regmap tdmout_a =
340 AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
341static struct clk_regmap tdmout_b =
342 AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
343static struct clk_regmap tdmout_c =
344 AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
345static struct clk_regmap frddr_a =
346 AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
347static struct clk_regmap frddr_b =
348 AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
349static struct clk_regmap frddr_c =
350 AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
351static struct clk_regmap toddr_a =
352 AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
353static struct clk_regmap toddr_b =
354 AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
355static struct clk_regmap toddr_c =
356 AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
357static struct clk_regmap loopback =
358 AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
359static struct clk_regmap spdifin =
360 AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
361static struct clk_regmap spdifout =
362 AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
363static struct clk_regmap resample =
364 AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
365static struct clk_regmap power_detect =
366 AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
367
368static struct clk_regmap spdifout_clk_sel =
369 AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
370static struct clk_regmap pdm_dclk_sel =
371 AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
372static struct clk_regmap spdifin_clk_sel =
373 AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
374static struct clk_regmap pdm_sysclk_sel =
375 AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
376static struct clk_regmap spdifout_b_clk_sel =
377 AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
378
379static struct clk_regmap spdifout_clk_div =
380 AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
381static struct clk_regmap pdm_dclk_div =
382 AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
383static struct clk_regmap spdifin_clk_div =
384 AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
385static struct clk_regmap pdm_sysclk_div =
386 AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
387static struct clk_regmap spdifout_b_clk_div =
388 AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
389
390static struct clk_regmap spdifout_clk =
391 AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
392static struct clk_regmap spdifin_clk =
393 AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
394static struct clk_regmap pdm_dclk =
395 AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
396static struct clk_regmap pdm_sysclk =
397 AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
398static struct clk_regmap spdifout_b_clk =
399 AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
400
401static struct clk_regmap mst_a_sclk_pre_en =
402 AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
403static struct clk_regmap mst_b_sclk_pre_en =
404 AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
405static struct clk_regmap mst_c_sclk_pre_en =
406 AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
407static struct clk_regmap mst_d_sclk_pre_en =
408 AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
409static struct clk_regmap mst_e_sclk_pre_en =
410 AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
411static struct clk_regmap mst_f_sclk_pre_en =
412 AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
413
414static struct clk_regmap mst_a_sclk_div =
415 AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
416static struct clk_regmap mst_b_sclk_div =
417 AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
418static struct clk_regmap mst_c_sclk_div =
419 AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
420static struct clk_regmap mst_d_sclk_div =
421 AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
422static struct clk_regmap mst_e_sclk_div =
423 AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
424static struct clk_regmap mst_f_sclk_div =
425 AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
426
427static struct clk_regmap mst_a_sclk_post_en =
428 AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
429static struct clk_regmap mst_b_sclk_post_en =
430 AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
431static struct clk_regmap mst_c_sclk_post_en =
432 AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
433static struct clk_regmap mst_d_sclk_post_en =
434 AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
435static struct clk_regmap mst_e_sclk_post_en =
436 AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
437static struct clk_regmap mst_f_sclk_post_en =
438 AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
439
440static struct clk_regmap mst_a_sclk =
441 AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
442static struct clk_regmap mst_b_sclk =
443 AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
444static struct clk_regmap mst_c_sclk =
445 AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
446static struct clk_regmap mst_d_sclk =
447 AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
448static struct clk_regmap mst_e_sclk =
449 AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
450static struct clk_regmap mst_f_sclk =
451 AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
452
453static struct clk_regmap mst_a_lrclk_div =
454 AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
455static struct clk_regmap mst_b_lrclk_div =
456 AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
457static struct clk_regmap mst_c_lrclk_div =
458 AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
459static struct clk_regmap mst_d_lrclk_div =
460 AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
461static struct clk_regmap mst_e_lrclk_div =
462 AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
463static struct clk_regmap mst_f_lrclk_div =
464 AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
465
466static struct clk_regmap mst_a_lrclk =
467 AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
468static struct clk_regmap mst_b_lrclk =
469 AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
470static struct clk_regmap mst_c_lrclk =
471 AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
472static struct clk_regmap mst_d_lrclk =
473 AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
474static struct clk_regmap mst_e_lrclk =
475 AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
476static struct clk_regmap mst_f_lrclk =
477 AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
478
479static struct clk_regmap tdmin_a_sclk_sel =
480 AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
481static struct clk_regmap tdmin_b_sclk_sel =
482 AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
483static struct clk_regmap tdmin_c_sclk_sel =
484 AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
485static struct clk_regmap tdmin_lb_sclk_sel =
486 AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
487static struct clk_regmap tdmout_a_sclk_sel =
488 AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
489static struct clk_regmap tdmout_b_sclk_sel =
490 AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
491static struct clk_regmap tdmout_c_sclk_sel =
492 AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
493
494static struct clk_regmap tdmin_a_sclk_pre_en =
495 AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
496static struct clk_regmap tdmin_b_sclk_pre_en =
497 AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
498static struct clk_regmap tdmin_c_sclk_pre_en =
499 AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
500static struct clk_regmap tdmin_lb_sclk_pre_en =
501 AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
502static struct clk_regmap tdmout_a_sclk_pre_en =
503 AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
504static struct clk_regmap tdmout_b_sclk_pre_en =
505 AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
506static struct clk_regmap tdmout_c_sclk_pre_en =
507 AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
508
509static struct clk_regmap tdmin_a_sclk_post_en =
510 AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
511static struct clk_regmap tdmin_b_sclk_post_en =
512 AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
513static struct clk_regmap tdmin_c_sclk_post_en =
514 AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
515static struct clk_regmap tdmin_lb_sclk_post_en =
516 AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
517static struct clk_regmap tdmout_a_sclk_post_en =
518 AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
519static struct clk_regmap tdmout_b_sclk_post_en =
520 AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
521static struct clk_regmap tdmout_c_sclk_post_en =
522 AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
523
524static struct clk_regmap tdmin_a_sclk =
525 AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
526static struct clk_regmap tdmin_b_sclk =
527 AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
528static struct clk_regmap tdmin_c_sclk =
529 AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
530static struct clk_regmap tdmin_lb_sclk =
531 AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
532
533static struct clk_regmap tdmin_a_lrclk =
534 AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
535static struct clk_regmap tdmin_b_lrclk =
536 AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
537static struct clk_regmap tdmin_c_lrclk =
538 AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
539static struct clk_regmap tdmin_lb_lrclk =
540 AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
541static struct clk_regmap tdmout_a_lrclk =
542 AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
543static struct clk_regmap tdmout_b_lrclk =
544 AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
545static struct clk_regmap tdmout_c_lrclk =
546 AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
547
548/* AXG Clocks */
549static struct clk_regmap axg_tdmout_a_sclk =
550 AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
551static struct clk_regmap axg_tdmout_b_sclk =
552 AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
553static struct clk_regmap axg_tdmout_c_sclk =
554 AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
555
556/* AXG/G12A Clocks */
557static struct clk_hw axg_aud_top = {
558 .init = &(struct clk_init_data) {
559 /* Provide aud_top signal name on axg and g12a */
560 .name = "aud_top",
561 .ops = &(const struct clk_ops) {},
562 .parent_data = &(const struct clk_parent_data) {
563 .fw_name = "pclk",
564 },
565 .num_parents = 1,
566 },
567};
568
569static struct clk_regmap mst_a_mclk_sel =
570 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
571static struct clk_regmap mst_b_mclk_sel =
572 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
573static struct clk_regmap mst_c_mclk_sel =
574 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
575static struct clk_regmap mst_d_mclk_sel =
576 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
577static struct clk_regmap mst_e_mclk_sel =
578 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
579static struct clk_regmap mst_f_mclk_sel =
580 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
581
582static struct clk_regmap mst_a_mclk_div =
583 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
584static struct clk_regmap mst_b_mclk_div =
585 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
586static struct clk_regmap mst_c_mclk_div =
587 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
588static struct clk_regmap mst_d_mclk_div =
589 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
590static struct clk_regmap mst_e_mclk_div =
591 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
592static struct clk_regmap mst_f_mclk_div =
593 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
594
595static struct clk_regmap mst_a_mclk =
596 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
597static struct clk_regmap mst_b_mclk =
598 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
599static struct clk_regmap mst_c_mclk =
600 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
601static struct clk_regmap mst_d_mclk =
602 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
603static struct clk_regmap mst_e_mclk =
604 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
605static struct clk_regmap mst_f_mclk =
606 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
607
608/* G12a clocks */
609static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
610 mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
611static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
612 mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
613static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
614 lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
615static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
616 lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
617static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
618 lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
619static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
620 sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
621static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
622 sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
623static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
624 sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
625
626static struct clk_regmap g12a_tdmout_a_sclk =
627 AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
628static struct clk_regmap g12a_tdmout_b_sclk =
629 AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
630static struct clk_regmap g12a_tdmout_c_sclk =
631 AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
632
633static struct clk_regmap toram =
634 AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
635static struct clk_regmap spdifout_b =
636 AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
637static struct clk_regmap eqdrc =
638 AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
639
640/* SM1 Clocks */
641static struct clk_regmap sm1_clk81_en = {
642 .data = &(struct clk_regmap_gate_data){
643 .offset = AUDIO_CLK81_EN,
644 .bit_idx = 31,
645 },
646 .hw.init = &(struct clk_init_data) {
647 .name = "aud_clk81_en",
648 .ops = &clk_regmap_gate_ops,
649 .parent_data = &(const struct clk_parent_data) {
650 .fw_name = "pclk",
651 },
652 .num_parents = 1,
653 },
654};
655
656static struct clk_regmap sm1_sysclk_a_div = {
657 .data = &(struct clk_regmap_div_data){
658 .offset = AUDIO_CLK81_CTRL,
659 .shift = 0,
660 .width = 8,
661 },
662 .hw.init = &(struct clk_init_data) {
663 .name = "aud_sysclk_a_div",
664 .ops = &clk_regmap_divider_ops,
665 .parent_hws = (const struct clk_hw *[]) {
666 &sm1_clk81_en.hw,
667 },
668 .num_parents = 1,
669 .flags = CLK_SET_RATE_PARENT,
670 },
671};
672
673static struct clk_regmap sm1_sysclk_a_en = {
674 .data = &(struct clk_regmap_gate_data){
675 .offset = AUDIO_CLK81_CTRL,
676 .bit_idx = 8,
677 },
678 .hw.init = &(struct clk_init_data) {
679 .name = "aud_sysclk_a_en",
680 .ops = &clk_regmap_gate_ops,
681 .parent_hws = (const struct clk_hw *[]) {
682 &sm1_sysclk_a_div.hw,
683 },
684 .num_parents = 1,
685 .flags = CLK_SET_RATE_PARENT,
686 },
687};
688
689static struct clk_regmap sm1_sysclk_b_div = {
690 .data = &(struct clk_regmap_div_data){
691 .offset = AUDIO_CLK81_CTRL,
692 .shift = 16,
693 .width = 8,
694 },
695 .hw.init = &(struct clk_init_data) {
696 .name = "aud_sysclk_b_div",
697 .ops = &clk_regmap_divider_ops,
698 .parent_hws = (const struct clk_hw *[]) {
699 &sm1_clk81_en.hw,
700 },
701 .num_parents = 1,
702 .flags = CLK_SET_RATE_PARENT,
703 },
704};
705
706static struct clk_regmap sm1_sysclk_b_en = {
707 .data = &(struct clk_regmap_gate_data){
708 .offset = AUDIO_CLK81_CTRL,
709 .bit_idx = 24,
710 },
711 .hw.init = &(struct clk_init_data) {
712 .name = "aud_sysclk_b_en",
713 .ops = &clk_regmap_gate_ops,
714 .parent_hws = (const struct clk_hw *[]) {
715 &sm1_sysclk_b_div.hw,
716 },
717 .num_parents = 1,
718 .flags = CLK_SET_RATE_PARENT,
719 },
720};
721
722static const struct clk_hw *sm1_aud_top_parents[] = {
723 &sm1_sysclk_a_en.hw,
724 &sm1_sysclk_b_en.hw,
725};
726
727static struct clk_regmap sm1_aud_top = {
728 .data = &(struct clk_regmap_mux_data){
729 .offset = AUDIO_CLK81_CTRL,
730 .mask = 0x1,
731 .shift = 31,
732 },
733 .hw.init = &(struct clk_init_data){
734 .name = "aud_top",
735 .ops = &clk_regmap_mux_ops,
736 .parent_hws = sm1_aud_top_parents,
737 .num_parents = ARRAY_SIZE(sm1_aud_top_parents),
738 .flags = CLK_SET_RATE_NO_REPARENT,
739 },
740};
741
742static struct clk_regmap resample_b =
743 AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
744static struct clk_regmap tovad =
745 AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
746static struct clk_regmap locker =
747 AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
748static struct clk_regmap spdifin_lb =
749 AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
750static struct clk_regmap frddr_d =
751 AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
752static struct clk_regmap toddr_d =
753 AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
754static struct clk_regmap loopback_b =
755 AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
756static struct clk_regmap earcrx =
757 AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6);
758
759
760static struct clk_regmap sm1_mst_a_mclk_sel =
761 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
762static struct clk_regmap sm1_mst_b_mclk_sel =
763 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
764static struct clk_regmap sm1_mst_c_mclk_sel =
765 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
766static struct clk_regmap sm1_mst_d_mclk_sel =
767 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
768static struct clk_regmap sm1_mst_e_mclk_sel =
769 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
770static struct clk_regmap sm1_mst_f_mclk_sel =
771 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
772static struct clk_regmap sm1_earcrx_cmdc_clk_sel =
773 AUD_MST_MCLK_MUX(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL);
774static struct clk_regmap sm1_earcrx_dmac_clk_sel =
775 AUD_MST_MCLK_MUX(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL);
776
777static struct clk_regmap sm1_mst_a_mclk_div =
778 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
779static struct clk_regmap sm1_mst_b_mclk_div =
780 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
781static struct clk_regmap sm1_mst_c_mclk_div =
782 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
783static struct clk_regmap sm1_mst_d_mclk_div =
784 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
785static struct clk_regmap sm1_mst_e_mclk_div =
786 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
787static struct clk_regmap sm1_mst_f_mclk_div =
788 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
789static struct clk_regmap sm1_earcrx_cmdc_clk_div =
790 AUD_MST_MCLK_DIV(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL);
791static struct clk_regmap sm1_earcrx_dmac_clk_div =
792 AUD_MST_MCLK_DIV(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL);
793
794
795static struct clk_regmap sm1_mst_a_mclk =
796 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
797static struct clk_regmap sm1_mst_b_mclk =
798 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
799static struct clk_regmap sm1_mst_c_mclk =
800 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
801static struct clk_regmap sm1_mst_d_mclk =
802 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
803static struct clk_regmap sm1_mst_e_mclk =
804 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
805static struct clk_regmap sm1_mst_f_mclk =
806 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
807static struct clk_regmap sm1_earcrx_cmdc_clk =
808 AUD_MST_MCLK_GATE(earcrx_cmdc_clk, AUDIO_EARCRX_CMDC_CLK_CTRL);
809static struct clk_regmap sm1_earcrx_dmac_clk =
810 AUD_MST_MCLK_GATE(earcrx_dmac_clk, AUDIO_EARCRX_DMAC_CLK_CTRL);
811
812static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
813 tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
814static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
815 tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
816static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
817 tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
818static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
819 tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
820static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
821 tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
822static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
823 tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
824static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
825 tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
826static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
827 tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
828
829/*
830 * Array of all clocks provided by this provider
831 * The input clocks of the controller will be populated at runtime
832 */
833static struct clk_hw *axg_audio_hw_clks[] = {
834 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
835 [AUD_CLKID_PDM] = &pdm.hw,
836 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
837 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
838 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
839 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
840 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
841 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
842 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
843 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
844 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
845 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
846 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
847 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
848 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
849 [AUD_CLKID_LOOPBACK] = &loopback.hw,
850 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
851 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
852 [AUD_CLKID_RESAMPLE] = &resample.hw,
853 [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
854 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
855 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
856 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
857 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
858 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
859 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
860 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
861 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
862 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
863 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
864 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
865 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
866 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
867 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
868 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
869 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
870 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
871 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
872 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
873 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
874 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
875 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
876 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
877 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
878 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
879 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
880 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
881 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
882 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
883 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
884 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
885 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
886 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
887 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
888 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
889 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
890 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
891 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
892 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
893 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
894 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
895 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
896 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
897 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
898 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
899 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
900 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
901 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
902 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
903 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
904 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
905 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
906 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
907 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
908 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
909 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
910 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
911 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
912 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
913 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
914 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
915 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
916 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
917 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
918 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
919 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
920 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
921 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
922 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
923 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
924 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
925 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
926 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
927 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
928 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
929 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
930 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
931 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
932 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
933 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
934 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
935 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
936 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
937 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
938 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
939 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
940 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
941 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
942 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
943 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
944 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
945 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
946 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
947 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
948 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
949 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
950 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
951 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
952 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
953 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
954 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
955 [AUD_CLKID_TOP] = &axg_aud_top,
956};
957
958/*
959 * Array of all G12A clocks provided by this provider
960 * The input clocks of the controller will be populated at runtime
961 */
962static struct clk_hw *g12a_audio_hw_clks[] = {
963 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
964 [AUD_CLKID_PDM] = &pdm.hw,
965 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
966 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
967 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
968 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
969 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
970 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
971 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
972 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
973 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
974 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
975 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
976 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
977 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
978 [AUD_CLKID_LOOPBACK] = &loopback.hw,
979 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
980 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
981 [AUD_CLKID_RESAMPLE] = &resample.hw,
982 [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
983 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
984 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
985 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
986 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
987 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
988 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
989 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
990 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
991 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
992 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
993 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
994 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
995 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
996 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
997 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
998 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
999 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
1000 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
1001 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
1002 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1003 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1004 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1005 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1006 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1007 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1008 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1009 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1010 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1011 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1012 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1013 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1014 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1015 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1016 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1017 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1018 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1019 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1020 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1021 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1022 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1023 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1024 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1025 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1026 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1027 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1028 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1029 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1030 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1031 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1032 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1033 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1034 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1035 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1036 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1037 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1038 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1039 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1040 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1041 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1042 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1043 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1044 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1045 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1046 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1047 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1048 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1049 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1050 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1051 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1052 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1053 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1054 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1055 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1056 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1057 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1058 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1059 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1060 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1061 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1062 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1063 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1064 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1065 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1066 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1067 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1068 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1069 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1070 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1071 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1072 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1073 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1074 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1075 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1076 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1077 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1078 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1079 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1080 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1081 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1082 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1083 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1084 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1085 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1086 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1087 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1088 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
1089 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
1090 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
1091 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
1092 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
1093 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
1094 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
1095 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
1096 [AUD_CLKID_TOP] = &axg_aud_top,
1097};
1098
1099/*
1100 * Array of all SM1 clocks provided by this provider
1101 * The input clocks of the controller will be populated at runtime
1102 */
1103static struct clk_hw *sm1_audio_hw_clks[] = {
1104 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
1105 [AUD_CLKID_PDM] = &pdm.hw,
1106 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
1107 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
1108 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
1109 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
1110 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
1111 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
1112 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
1113 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
1114 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
1115 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
1116 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
1117 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
1118 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
1119 [AUD_CLKID_LOOPBACK] = &loopback.hw,
1120 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
1121 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
1122 [AUD_CLKID_RESAMPLE] = &resample.hw,
1123 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
1124 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
1125 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
1126 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
1127 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
1128 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
1129 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
1130 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
1131 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
1132 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
1133 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
1134 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
1135 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
1136 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
1137 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
1138 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
1139 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
1140 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
1141 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
1142 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1143 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1144 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1145 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1146 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1147 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1148 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1149 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1150 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1151 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1152 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1153 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1154 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1155 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1156 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1157 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1158 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1159 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1160 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1161 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1162 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1163 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1164 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1165 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1166 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1167 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1168 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1169 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1170 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1171 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1172 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1173 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1174 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1175 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1176 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1177 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1178 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1179 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1180 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1181 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1182 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1183 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1184 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1185 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1186 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1187 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1188 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1189 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1190 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1191 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1192 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1193 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1194 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1195 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1196 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1197 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1198 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1199 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1200 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1201 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1202 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1203 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1204 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1205 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1206 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1207 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1208 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1209 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1210 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1211 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1212 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1213 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1214 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1215 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1216 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1217 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1218 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1219 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1220 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1221 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1222 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1223 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1224 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1225 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1226 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1227 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1228 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
1229 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
1230 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
1231 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
1232 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
1233 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
1234 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
1235 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
1236 [AUD_CLKID_TOP] = &sm1_aud_top.hw,
1237 [AUD_CLKID_TORAM] = &toram.hw,
1238 [AUD_CLKID_EQDRC] = &eqdrc.hw,
1239 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
1240 [AUD_CLKID_TOVAD] = &tovad.hw,
1241 [AUD_CLKID_LOCKER] = &locker.hw,
1242 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
1243 [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
1244 [AUD_CLKID_TODDR_D] = &toddr_d.hw,
1245 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
1246 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
1247 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
1248 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
1249 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
1250 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
1251 [AUD_CLKID_EARCRX] = &earcrx.hw,
1252 [AUD_CLKID_EARCRX_CMDC_SEL] = &sm1_earcrx_cmdc_clk_sel.hw,
1253 [AUD_CLKID_EARCRX_CMDC_DIV] = &sm1_earcrx_cmdc_clk_div.hw,
1254 [AUD_CLKID_EARCRX_CMDC] = &sm1_earcrx_cmdc_clk.hw,
1255 [AUD_CLKID_EARCRX_DMAC_SEL] = &sm1_earcrx_dmac_clk_sel.hw,
1256 [AUD_CLKID_EARCRX_DMAC_DIV] = &sm1_earcrx_dmac_clk_div.hw,
1257 [AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw,
1258};
1259
1260
1261/* Convenience table to populate regmap in .probe(). */
1262static struct clk_regmap *const axg_clk_regmaps[] = {
1263 &ddr_arb,
1264 &pdm,
1265 &tdmin_a,
1266 &tdmin_b,
1267 &tdmin_c,
1268 &tdmin_lb,
1269 &tdmout_a,
1270 &tdmout_b,
1271 &tdmout_c,
1272 &frddr_a,
1273 &frddr_b,
1274 &frddr_c,
1275 &toddr_a,
1276 &toddr_b,
1277 &toddr_c,
1278 &loopback,
1279 &spdifin,
1280 &spdifout,
1281 &resample,
1282 &power_detect,
1283 &mst_a_mclk_sel,
1284 &mst_b_mclk_sel,
1285 &mst_c_mclk_sel,
1286 &mst_d_mclk_sel,
1287 &mst_e_mclk_sel,
1288 &mst_f_mclk_sel,
1289 &mst_a_mclk_div,
1290 &mst_b_mclk_div,
1291 &mst_c_mclk_div,
1292 &mst_d_mclk_div,
1293 &mst_e_mclk_div,
1294 &mst_f_mclk_div,
1295 &mst_a_mclk,
1296 &mst_b_mclk,
1297 &mst_c_mclk,
1298 &mst_d_mclk,
1299 &mst_e_mclk,
1300 &mst_f_mclk,
1301 &spdifout_clk_sel,
1302 &spdifout_clk_div,
1303 &spdifout_clk,
1304 &spdifin_clk_sel,
1305 &spdifin_clk_div,
1306 &spdifin_clk,
1307 &pdm_dclk_sel,
1308 &pdm_dclk_div,
1309 &pdm_dclk,
1310 &pdm_sysclk_sel,
1311 &pdm_sysclk_div,
1312 &pdm_sysclk,
1313 &mst_a_sclk_pre_en,
1314 &mst_b_sclk_pre_en,
1315 &mst_c_sclk_pre_en,
1316 &mst_d_sclk_pre_en,
1317 &mst_e_sclk_pre_en,
1318 &mst_f_sclk_pre_en,
1319 &mst_a_sclk_div,
1320 &mst_b_sclk_div,
1321 &mst_c_sclk_div,
1322 &mst_d_sclk_div,
1323 &mst_e_sclk_div,
1324 &mst_f_sclk_div,
1325 &mst_a_sclk_post_en,
1326 &mst_b_sclk_post_en,
1327 &mst_c_sclk_post_en,
1328 &mst_d_sclk_post_en,
1329 &mst_e_sclk_post_en,
1330 &mst_f_sclk_post_en,
1331 &mst_a_sclk,
1332 &mst_b_sclk,
1333 &mst_c_sclk,
1334 &mst_d_sclk,
1335 &mst_e_sclk,
1336 &mst_f_sclk,
1337 &mst_a_lrclk_div,
1338 &mst_b_lrclk_div,
1339 &mst_c_lrclk_div,
1340 &mst_d_lrclk_div,
1341 &mst_e_lrclk_div,
1342 &mst_f_lrclk_div,
1343 &mst_a_lrclk,
1344 &mst_b_lrclk,
1345 &mst_c_lrclk,
1346 &mst_d_lrclk,
1347 &mst_e_lrclk,
1348 &mst_f_lrclk,
1349 &tdmin_a_sclk_sel,
1350 &tdmin_b_sclk_sel,
1351 &tdmin_c_sclk_sel,
1352 &tdmin_lb_sclk_sel,
1353 &tdmout_a_sclk_sel,
1354 &tdmout_b_sclk_sel,
1355 &tdmout_c_sclk_sel,
1356 &tdmin_a_sclk_pre_en,
1357 &tdmin_b_sclk_pre_en,
1358 &tdmin_c_sclk_pre_en,
1359 &tdmin_lb_sclk_pre_en,
1360 &tdmout_a_sclk_pre_en,
1361 &tdmout_b_sclk_pre_en,
1362 &tdmout_c_sclk_pre_en,
1363 &tdmin_a_sclk_post_en,
1364 &tdmin_b_sclk_post_en,
1365 &tdmin_c_sclk_post_en,
1366 &tdmin_lb_sclk_post_en,
1367 &tdmout_a_sclk_post_en,
1368 &tdmout_b_sclk_post_en,
1369 &tdmout_c_sclk_post_en,
1370 &tdmin_a_sclk,
1371 &tdmin_b_sclk,
1372 &tdmin_c_sclk,
1373 &tdmin_lb_sclk,
1374 &axg_tdmout_a_sclk,
1375 &axg_tdmout_b_sclk,
1376 &axg_tdmout_c_sclk,
1377 &tdmin_a_lrclk,
1378 &tdmin_b_lrclk,
1379 &tdmin_c_lrclk,
1380 &tdmin_lb_lrclk,
1381 &tdmout_a_lrclk,
1382 &tdmout_b_lrclk,
1383 &tdmout_c_lrclk,
1384};
1385
1386static struct clk_regmap *const g12a_clk_regmaps[] = {
1387 &ddr_arb,
1388 &pdm,
1389 &tdmin_a,
1390 &tdmin_b,
1391 &tdmin_c,
1392 &tdmin_lb,
1393 &tdmout_a,
1394 &tdmout_b,
1395 &tdmout_c,
1396 &frddr_a,
1397 &frddr_b,
1398 &frddr_c,
1399 &toddr_a,
1400 &toddr_b,
1401 &toddr_c,
1402 &loopback,
1403 &spdifin,
1404 &spdifout,
1405 &resample,
1406 &power_detect,
1407 &spdifout_b,
1408 &mst_a_mclk_sel,
1409 &mst_b_mclk_sel,
1410 &mst_c_mclk_sel,
1411 &mst_d_mclk_sel,
1412 &mst_e_mclk_sel,
1413 &mst_f_mclk_sel,
1414 &mst_a_mclk_div,
1415 &mst_b_mclk_div,
1416 &mst_c_mclk_div,
1417 &mst_d_mclk_div,
1418 &mst_e_mclk_div,
1419 &mst_f_mclk_div,
1420 &mst_a_mclk,
1421 &mst_b_mclk,
1422 &mst_c_mclk,
1423 &mst_d_mclk,
1424 &mst_e_mclk,
1425 &mst_f_mclk,
1426 &spdifout_clk_sel,
1427 &spdifout_clk_div,
1428 &spdifout_clk,
1429 &spdifin_clk_sel,
1430 &spdifin_clk_div,
1431 &spdifin_clk,
1432 &pdm_dclk_sel,
1433 &pdm_dclk_div,
1434 &pdm_dclk,
1435 &pdm_sysclk_sel,
1436 &pdm_sysclk_div,
1437 &pdm_sysclk,
1438 &mst_a_sclk_pre_en,
1439 &mst_b_sclk_pre_en,
1440 &mst_c_sclk_pre_en,
1441 &mst_d_sclk_pre_en,
1442 &mst_e_sclk_pre_en,
1443 &mst_f_sclk_pre_en,
1444 &mst_a_sclk_div,
1445 &mst_b_sclk_div,
1446 &mst_c_sclk_div,
1447 &mst_d_sclk_div,
1448 &mst_e_sclk_div,
1449 &mst_f_sclk_div,
1450 &mst_a_sclk_post_en,
1451 &mst_b_sclk_post_en,
1452 &mst_c_sclk_post_en,
1453 &mst_d_sclk_post_en,
1454 &mst_e_sclk_post_en,
1455 &mst_f_sclk_post_en,
1456 &mst_a_sclk,
1457 &mst_b_sclk,
1458 &mst_c_sclk,
1459 &mst_d_sclk,
1460 &mst_e_sclk,
1461 &mst_f_sclk,
1462 &mst_a_lrclk_div,
1463 &mst_b_lrclk_div,
1464 &mst_c_lrclk_div,
1465 &mst_d_lrclk_div,
1466 &mst_e_lrclk_div,
1467 &mst_f_lrclk_div,
1468 &mst_a_lrclk,
1469 &mst_b_lrclk,
1470 &mst_c_lrclk,
1471 &mst_d_lrclk,
1472 &mst_e_lrclk,
1473 &mst_f_lrclk,
1474 &tdmin_a_sclk_sel,
1475 &tdmin_b_sclk_sel,
1476 &tdmin_c_sclk_sel,
1477 &tdmin_lb_sclk_sel,
1478 &tdmout_a_sclk_sel,
1479 &tdmout_b_sclk_sel,
1480 &tdmout_c_sclk_sel,
1481 &tdmin_a_sclk_pre_en,
1482 &tdmin_b_sclk_pre_en,
1483 &tdmin_c_sclk_pre_en,
1484 &tdmin_lb_sclk_pre_en,
1485 &tdmout_a_sclk_pre_en,
1486 &tdmout_b_sclk_pre_en,
1487 &tdmout_c_sclk_pre_en,
1488 &tdmin_a_sclk_post_en,
1489 &tdmin_b_sclk_post_en,
1490 &tdmin_c_sclk_post_en,
1491 &tdmin_lb_sclk_post_en,
1492 &tdmout_a_sclk_post_en,
1493 &tdmout_b_sclk_post_en,
1494 &tdmout_c_sclk_post_en,
1495 &tdmin_a_sclk,
1496 &tdmin_b_sclk,
1497 &tdmin_c_sclk,
1498 &tdmin_lb_sclk,
1499 &g12a_tdmout_a_sclk,
1500 &g12a_tdmout_b_sclk,
1501 &g12a_tdmout_c_sclk,
1502 &tdmin_a_lrclk,
1503 &tdmin_b_lrclk,
1504 &tdmin_c_lrclk,
1505 &tdmin_lb_lrclk,
1506 &tdmout_a_lrclk,
1507 &tdmout_b_lrclk,
1508 &tdmout_c_lrclk,
1509 &spdifout_b_clk_sel,
1510 &spdifout_b_clk_div,
1511 &spdifout_b_clk,
1512 &g12a_tdm_mclk_pad_0,
1513 &g12a_tdm_mclk_pad_1,
1514 &g12a_tdm_lrclk_pad_0,
1515 &g12a_tdm_lrclk_pad_1,
1516 &g12a_tdm_lrclk_pad_2,
1517 &g12a_tdm_sclk_pad_0,
1518 &g12a_tdm_sclk_pad_1,
1519 &g12a_tdm_sclk_pad_2,
1520 &toram,
1521 &eqdrc,
1522};
1523
1524static struct clk_regmap *const sm1_clk_regmaps[] = {
1525 &ddr_arb,
1526 &pdm,
1527 &tdmin_a,
1528 &tdmin_b,
1529 &tdmin_c,
1530 &tdmin_lb,
1531 &tdmout_a,
1532 &tdmout_b,
1533 &tdmout_c,
1534 &frddr_a,
1535 &frddr_b,
1536 &frddr_c,
1537 &toddr_a,
1538 &toddr_b,
1539 &toddr_c,
1540 &loopback,
1541 &spdifin,
1542 &spdifout,
1543 &resample,
1544 &spdifout_b,
1545 &sm1_mst_a_mclk_sel,
1546 &sm1_mst_b_mclk_sel,
1547 &sm1_mst_c_mclk_sel,
1548 &sm1_mst_d_mclk_sel,
1549 &sm1_mst_e_mclk_sel,
1550 &sm1_mst_f_mclk_sel,
1551 &sm1_mst_a_mclk_div,
1552 &sm1_mst_b_mclk_div,
1553 &sm1_mst_c_mclk_div,
1554 &sm1_mst_d_mclk_div,
1555 &sm1_mst_e_mclk_div,
1556 &sm1_mst_f_mclk_div,
1557 &sm1_mst_a_mclk,
1558 &sm1_mst_b_mclk,
1559 &sm1_mst_c_mclk,
1560 &sm1_mst_d_mclk,
1561 &sm1_mst_e_mclk,
1562 &sm1_mst_f_mclk,
1563 &spdifout_clk_sel,
1564 &spdifout_clk_div,
1565 &spdifout_clk,
1566 &spdifin_clk_sel,
1567 &spdifin_clk_div,
1568 &spdifin_clk,
1569 &pdm_dclk_sel,
1570 &pdm_dclk_div,
1571 &pdm_dclk,
1572 &pdm_sysclk_sel,
1573 &pdm_sysclk_div,
1574 &pdm_sysclk,
1575 &mst_a_sclk_pre_en,
1576 &mst_b_sclk_pre_en,
1577 &mst_c_sclk_pre_en,
1578 &mst_d_sclk_pre_en,
1579 &mst_e_sclk_pre_en,
1580 &mst_f_sclk_pre_en,
1581 &mst_a_sclk_div,
1582 &mst_b_sclk_div,
1583 &mst_c_sclk_div,
1584 &mst_d_sclk_div,
1585 &mst_e_sclk_div,
1586 &mst_f_sclk_div,
1587 &mst_a_sclk_post_en,
1588 &mst_b_sclk_post_en,
1589 &mst_c_sclk_post_en,
1590 &mst_d_sclk_post_en,
1591 &mst_e_sclk_post_en,
1592 &mst_f_sclk_post_en,
1593 &mst_a_sclk,
1594 &mst_b_sclk,
1595 &mst_c_sclk,
1596 &mst_d_sclk,
1597 &mst_e_sclk,
1598 &mst_f_sclk,
1599 &mst_a_lrclk_div,
1600 &mst_b_lrclk_div,
1601 &mst_c_lrclk_div,
1602 &mst_d_lrclk_div,
1603 &mst_e_lrclk_div,
1604 &mst_f_lrclk_div,
1605 &mst_a_lrclk,
1606 &mst_b_lrclk,
1607 &mst_c_lrclk,
1608 &mst_d_lrclk,
1609 &mst_e_lrclk,
1610 &mst_f_lrclk,
1611 &tdmin_a_sclk_sel,
1612 &tdmin_b_sclk_sel,
1613 &tdmin_c_sclk_sel,
1614 &tdmin_lb_sclk_sel,
1615 &tdmout_a_sclk_sel,
1616 &tdmout_b_sclk_sel,
1617 &tdmout_c_sclk_sel,
1618 &tdmin_a_sclk_pre_en,
1619 &tdmin_b_sclk_pre_en,
1620 &tdmin_c_sclk_pre_en,
1621 &tdmin_lb_sclk_pre_en,
1622 &tdmout_a_sclk_pre_en,
1623 &tdmout_b_sclk_pre_en,
1624 &tdmout_c_sclk_pre_en,
1625 &tdmin_a_sclk_post_en,
1626 &tdmin_b_sclk_post_en,
1627 &tdmin_c_sclk_post_en,
1628 &tdmin_lb_sclk_post_en,
1629 &tdmout_a_sclk_post_en,
1630 &tdmout_b_sclk_post_en,
1631 &tdmout_c_sclk_post_en,
1632 &tdmin_a_sclk,
1633 &tdmin_b_sclk,
1634 &tdmin_c_sclk,
1635 &tdmin_lb_sclk,
1636 &g12a_tdmout_a_sclk,
1637 &g12a_tdmout_b_sclk,
1638 &g12a_tdmout_c_sclk,
1639 &tdmin_a_lrclk,
1640 &tdmin_b_lrclk,
1641 &tdmin_c_lrclk,
1642 &tdmin_lb_lrclk,
1643 &tdmout_a_lrclk,
1644 &tdmout_b_lrclk,
1645 &tdmout_c_lrclk,
1646 &spdifout_b_clk_sel,
1647 &spdifout_b_clk_div,
1648 &spdifout_b_clk,
1649 &sm1_tdm_mclk_pad_0,
1650 &sm1_tdm_mclk_pad_1,
1651 &sm1_tdm_lrclk_pad_0,
1652 &sm1_tdm_lrclk_pad_1,
1653 &sm1_tdm_lrclk_pad_2,
1654 &sm1_tdm_sclk_pad_0,
1655 &sm1_tdm_sclk_pad_1,
1656 &sm1_tdm_sclk_pad_2,
1657 &sm1_aud_top,
1658 &toram,
1659 &eqdrc,
1660 &resample_b,
1661 &tovad,
1662 &locker,
1663 &spdifin_lb,
1664 &frddr_d,
1665 &toddr_d,
1666 &loopback_b,
1667 &sm1_clk81_en,
1668 &sm1_sysclk_a_div,
1669 &sm1_sysclk_a_en,
1670 &sm1_sysclk_b_div,
1671 &sm1_sysclk_b_en,
1672 &earcrx,
1673 &sm1_earcrx_cmdc_clk_sel,
1674 &sm1_earcrx_cmdc_clk_div,
1675 &sm1_earcrx_cmdc_clk,
1676 &sm1_earcrx_dmac_clk_sel,
1677 &sm1_earcrx_dmac_clk_div,
1678 &sm1_earcrx_dmac_clk,
1679};
1680
1681struct axg_audio_reset_data {
1682 struct reset_controller_dev rstc;
1683 struct regmap *map;
1684 unsigned int offset;
1685};
1686
1687static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
1688 unsigned long id,
1689 unsigned int *reg,
1690 unsigned int *bit)
1691{
1692 unsigned int stride = regmap_get_reg_stride(rst->map);
1693
1694 *reg = (id / (stride * BITS_PER_BYTE)) * stride;
1695 *reg += rst->offset;
1696 *bit = id % (stride * BITS_PER_BYTE);
1697}
1698
1699static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
1700 unsigned long id, bool assert)
1701{
1702 struct axg_audio_reset_data *rst =
1703 container_of(rcdev, struct axg_audio_reset_data, rstc);
1704 unsigned int offset, bit;
1705
1706 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1707
1708 regmap_update_bits(rst->map, offset, BIT(bit),
1709 assert ? BIT(bit) : 0);
1710
1711 return 0;
1712}
1713
1714static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
1715 unsigned long id)
1716{
1717 struct axg_audio_reset_data *rst =
1718 container_of(rcdev, struct axg_audio_reset_data, rstc);
1719 unsigned int val, offset, bit;
1720
1721 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1722
1723 regmap_read(rst->map, offset, &val);
1724
1725 return !!(val & BIT(bit));
1726}
1727
1728static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
1729 unsigned long id)
1730{
1731 return axg_audio_reset_update(rcdev, id, true);
1732}
1733
1734static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
1735 unsigned long id)
1736{
1737 return axg_audio_reset_update(rcdev, id, false);
1738}
1739
1740static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
1741 unsigned long id)
1742{
1743 int ret;
1744
1745 ret = axg_audio_reset_assert(rcdev, id);
1746 if (ret)
1747 return ret;
1748
1749 return axg_audio_reset_deassert(rcdev, id);
1750}
1751
1752static const struct reset_control_ops axg_audio_rstc_ops = {
1753 .assert = axg_audio_reset_assert,
1754 .deassert = axg_audio_reset_deassert,
1755 .reset = axg_audio_reset_toggle,
1756 .status = axg_audio_reset_status,
1757};
1758
1759static struct regmap_config axg_audio_regmap_cfg = {
1760 .reg_bits = 32,
1761 .val_bits = 32,
1762 .reg_stride = 4,
1763};
1764
1765struct audioclk_data {
1766 struct clk_regmap *const *regmap_clks;
1767 unsigned int regmap_clk_num;
1768 struct meson_clk_hw_data hw_clks;
1769 unsigned int reset_offset;
1770 unsigned int reset_num;
1771 unsigned int max_register;
1772};
1773
1774static int axg_audio_clkc_probe(struct platform_device *pdev)
1775{
1776 struct device *dev = &pdev->dev;
1777 const struct audioclk_data *data;
1778 struct axg_audio_reset_data *rst;
1779 struct regmap *map;
1780 void __iomem *regs;
1781 struct clk_hw *hw;
1782 struct clk *clk;
1783 int ret, i;
1784
1785 data = of_device_get_match_data(dev);
1786 if (!data)
1787 return -EINVAL;
1788
1789 regs = devm_platform_ioremap_resource(pdev, 0);
1790 if (IS_ERR(regs))
1791 return PTR_ERR(regs);
1792
1793 axg_audio_regmap_cfg.max_register = data->max_register;
1794 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
1795 if (IS_ERR(map)) {
1796 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
1797 return PTR_ERR(map);
1798 }
1799
1800 /* Get the mandatory peripheral clock */
1801 clk = devm_clk_get_enabled(dev, "pclk");
1802 if (IS_ERR(clk))
1803 return PTR_ERR(clk);
1804
1805 ret = device_reset(dev);
1806 if (ret) {
1807 dev_err_probe(dev, ret, "failed to reset device\n");
1808 return ret;
1809 }
1810
1811 /* Populate regmap for the regmap backed clocks */
1812 for (i = 0; i < data->regmap_clk_num; i++)
1813 data->regmap_clks[i]->map = map;
1814
1815 /* Take care to skip the registered input clocks */
1816 for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
1817 const char *name;
1818
1819 hw = data->hw_clks.hws[i];
1820 /* array might be sparse */
1821 if (!hw)
1822 continue;
1823
1824 name = hw->init->name;
1825
1826 ret = devm_clk_hw_register(dev, hw);
1827 if (ret) {
1828 dev_err(dev, "failed to register clock %s\n", name);
1829 return ret;
1830 }
1831 }
1832
1833 ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
1834 if (ret)
1835 return ret;
1836
1837 /* Stop here if there is no reset */
1838 if (!data->reset_num)
1839 return 0;
1840
1841 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1842 if (!rst)
1843 return -ENOMEM;
1844
1845 rst->map = map;
1846 rst->offset = data->reset_offset;
1847 rst->rstc.nr_resets = data->reset_num;
1848 rst->rstc.ops = &axg_audio_rstc_ops;
1849 rst->rstc.of_node = dev->of_node;
1850 rst->rstc.owner = THIS_MODULE;
1851
1852 return devm_reset_controller_register(dev, &rst->rstc);
1853}
1854
1855static const struct audioclk_data axg_audioclk_data = {
1856 .regmap_clks = axg_clk_regmaps,
1857 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1858 .hw_clks = {
1859 .hws = axg_audio_hw_clks,
1860 .num = ARRAY_SIZE(axg_audio_hw_clks),
1861 },
1862 .max_register = AUDIO_CLK_PDMIN_CTRL1,
1863};
1864
1865static const struct audioclk_data g12a_audioclk_data = {
1866 .regmap_clks = g12a_clk_regmaps,
1867 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
1868 .hw_clks = {
1869 .hws = g12a_audio_hw_clks,
1870 .num = ARRAY_SIZE(g12a_audio_hw_clks),
1871 },
1872 .reset_offset = AUDIO_SW_RESET,
1873 .reset_num = 26,
1874 .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
1875};
1876
1877static const struct audioclk_data sm1_audioclk_data = {
1878 .regmap_clks = sm1_clk_regmaps,
1879 .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1880 .hw_clks = {
1881 .hws = sm1_audio_hw_clks,
1882 .num = ARRAY_SIZE(sm1_audio_hw_clks),
1883 },
1884 .reset_offset = AUDIO_SM1_SW_RESET0,
1885 .reset_num = 39,
1886 .max_register = AUDIO_EARCRX_DMAC_CLK_CTRL,
1887};
1888
1889static const struct of_device_id clkc_match_table[] = {
1890 {
1891 .compatible = "amlogic,axg-audio-clkc",
1892 .data = &axg_audioclk_data
1893 }, {
1894 .compatible = "amlogic,g12a-audio-clkc",
1895 .data = &g12a_audioclk_data
1896 }, {
1897 .compatible = "amlogic,sm1-audio-clkc",
1898 .data = &sm1_audioclk_data
1899 }, {}
1900};
1901MODULE_DEVICE_TABLE(of, clkc_match_table);
1902
1903static struct platform_driver axg_audio_driver = {
1904 .probe = axg_audio_clkc_probe,
1905 .driver = {
1906 .name = "axg-audio-clkc",
1907 .of_match_table = clkc_match_table,
1908 },
1909};
1910module_platform_driver(axg_audio_driver);
1911
1912MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
1913MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
1914MODULE_LICENSE("GPL");
1915MODULE_IMPORT_NS("CLK_MESON");