Loading...
1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/pci.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/syscore_ops.h>
34#include <linux/msi.h>
35#include <linux/htirq.h>
36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
39#include <linux/slab.h>
40#ifdef CONFIG_ACPI
41#include <acpi/acpi_bus.h>
42#endif
43#include <linux/bootmem.h>
44#include <linux/dmar.h>
45#include <linux/hpet.h>
46
47#include <asm/idle.h>
48#include <asm/io.h>
49#include <asm/smp.h>
50#include <asm/cpu.h>
51#include <asm/desc.h>
52#include <asm/proto.h>
53#include <asm/acpi.h>
54#include <asm/dma.h>
55#include <asm/timer.h>
56#include <asm/i8259.h>
57#include <asm/msidef.h>
58#include <asm/hypertransport.h>
59#include <asm/setup.h>
60#include <asm/irq_remapping.h>
61#include <asm/hpet.h>
62#include <asm/hw_irq.h>
63
64#include <asm/apic.h>
65
66#define __apicdebuginit(type) static type __init
67
68#define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
70
71#ifdef CONFIG_IRQ_REMAP
72static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
73static inline bool irq_remapped(struct irq_cfg *cfg)
74{
75 return cfg->irq_2_iommu.iommu != NULL;
76}
77#else
78static inline bool irq_remapped(struct irq_cfg *cfg)
79{
80 return false;
81}
82static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
83{
84}
85#endif
86
87/*
88 * Is the SiS APIC rmw bug present ?
89 * -1 = don't know, 0 = no, 1 = yes
90 */
91int sis_apic_bug = -1;
92
93static DEFINE_RAW_SPINLOCK(ioapic_lock);
94static DEFINE_RAW_SPINLOCK(vector_lock);
95
96static struct ioapic {
97 /*
98 * # of IRQ routing registers
99 */
100 int nr_registers;
101 /*
102 * Saved state during suspend/resume, or while enabling intr-remap.
103 */
104 struct IO_APIC_route_entry *saved_registers;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config;
109 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
110} ioapics[MAX_IO_APICS];
111
112#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
113
114int mpc_ioapic_id(int ioapic_idx)
115{
116 return ioapics[ioapic_idx].mp_config.apicid;
117}
118
119unsigned int mpc_ioapic_addr(int ioapic_idx)
120{
121 return ioapics[ioapic_idx].mp_config.apicaddr;
122}
123
124struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
125{
126 return &ioapics[ioapic_idx].gsi_config;
127}
128
129int nr_ioapics;
130
131/* The one past the highest gsi number used */
132u32 gsi_top;
133
134/* MP IRQ source entries */
135struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
136
137/* # of MP IRQ source entries */
138int mp_irq_entries;
139
140/* GSI interrupts */
141static int nr_irqs_gsi = NR_IRQS_LEGACY;
142
143#ifdef CONFIG_EISA
144int mp_bus_id_to_type[MAX_MP_BUSSES];
145#endif
146
147DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
148
149int skip_ioapic_setup;
150
151/**
152 * disable_ioapic_support() - disables ioapic support at runtime
153 */
154void disable_ioapic_support(void)
155{
156#ifdef CONFIG_PCI
157 noioapicquirk = 1;
158 noioapicreroute = -1;
159#endif
160 skip_ioapic_setup = 1;
161}
162
163static int __init parse_noapic(char *str)
164{
165 /* disable IO-APIC */
166 disable_ioapic_support();
167 return 0;
168}
169early_param("noapic", parse_noapic);
170
171static int io_apic_setup_irq_pin(unsigned int irq, int node,
172 struct io_apic_irq_attr *attr);
173
174/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
175void mp_save_irq(struct mpc_intsrc *m)
176{
177 int i;
178
179 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
180 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
181 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
182 m->srcbusirq, m->dstapic, m->dstirq);
183
184 for (i = 0; i < mp_irq_entries; i++) {
185 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
186 return;
187 }
188
189 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
190 if (++mp_irq_entries == MAX_IRQ_SOURCES)
191 panic("Max # of irq sources exceeded!!\n");
192}
193
194struct irq_pin_list {
195 int apic, pin;
196 struct irq_pin_list *next;
197};
198
199static struct irq_pin_list *alloc_irq_pin_list(int node)
200{
201 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
202}
203
204
205/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
206static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
207
208int __init arch_early_irq_init(void)
209{
210 struct irq_cfg *cfg;
211 int count, node, i;
212
213 if (!legacy_pic->nr_legacy_irqs)
214 io_apic_irqs = ~0UL;
215
216 for (i = 0; i < nr_ioapics; i++) {
217 ioapics[i].saved_registers =
218 kzalloc(sizeof(struct IO_APIC_route_entry) *
219 ioapics[i].nr_registers, GFP_KERNEL);
220 if (!ioapics[i].saved_registers)
221 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
222 }
223
224 cfg = irq_cfgx;
225 count = ARRAY_SIZE(irq_cfgx);
226 node = cpu_to_node(0);
227
228 /* Make sure the legacy interrupts are marked in the bitmap */
229 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
230
231 for (i = 0; i < count; i++) {
232 irq_set_chip_data(i, &cfg[i]);
233 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
234 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
235 /*
236 * For legacy IRQ's, start with assigning irq0 to irq15 to
237 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
238 */
239 if (i < legacy_pic->nr_legacy_irqs) {
240 cfg[i].vector = IRQ0_VECTOR + i;
241 cpumask_set_cpu(0, cfg[i].domain);
242 }
243 }
244
245 return 0;
246}
247
248static struct irq_cfg *irq_cfg(unsigned int irq)
249{
250 return irq_get_chip_data(irq);
251}
252
253static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
254{
255 struct irq_cfg *cfg;
256
257 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
258 if (!cfg)
259 return NULL;
260 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
261 goto out_cfg;
262 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
263 goto out_domain;
264 return cfg;
265out_domain:
266 free_cpumask_var(cfg->domain);
267out_cfg:
268 kfree(cfg);
269 return NULL;
270}
271
272static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
273{
274 if (!cfg)
275 return;
276 irq_set_chip_data(at, NULL);
277 free_cpumask_var(cfg->domain);
278 free_cpumask_var(cfg->old_domain);
279 kfree(cfg);
280}
281
282static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
283{
284 int res = irq_alloc_desc_at(at, node);
285 struct irq_cfg *cfg;
286
287 if (res < 0) {
288 if (res != -EEXIST)
289 return NULL;
290 cfg = irq_get_chip_data(at);
291 if (cfg)
292 return cfg;
293 }
294
295 cfg = alloc_irq_cfg(at, node);
296 if (cfg)
297 irq_set_chip_data(at, cfg);
298 else
299 irq_free_desc(at);
300 return cfg;
301}
302
303static int alloc_irq_from(unsigned int from, int node)
304{
305 return irq_alloc_desc_from(from, node);
306}
307
308static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
309{
310 free_irq_cfg(at, cfg);
311 irq_free_desc(at);
312}
313
314
315struct io_apic {
316 unsigned int index;
317 unsigned int unused[3];
318 unsigned int data;
319 unsigned int unused2[11];
320 unsigned int eoi;
321};
322
323static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
324{
325 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
326 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
327}
328
329static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
330{
331 struct io_apic __iomem *io_apic = io_apic_base(apic);
332 writel(vector, &io_apic->eoi);
333}
334
335unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
336{
337 struct io_apic __iomem *io_apic = io_apic_base(apic);
338 writel(reg, &io_apic->index);
339 return readl(&io_apic->data);
340}
341
342void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
343{
344 struct io_apic __iomem *io_apic = io_apic_base(apic);
345
346 writel(reg, &io_apic->index);
347 writel(value, &io_apic->data);
348}
349
350/*
351 * Re-write a value: to be used for read-modify-write
352 * cycles where the read already set up the index register.
353 *
354 * Older SiS APIC requires we rewrite the index register
355 */
356void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
357{
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
359
360 if (sis_apic_bug)
361 writel(reg, &io_apic->index);
362 writel(value, &io_apic->data);
363}
364
365union entry_union {
366 struct { u32 w1, w2; };
367 struct IO_APIC_route_entry entry;
368};
369
370static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
371{
372 union entry_union eu;
373
374 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
375 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
376
377 return eu.entry;
378}
379
380static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
381{
382 union entry_union eu;
383 unsigned long flags;
384
385 raw_spin_lock_irqsave(&ioapic_lock, flags);
386 eu.entry = __ioapic_read_entry(apic, pin);
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
388
389 return eu.entry;
390}
391
392/*
393 * When we write a new IO APIC routing entry, we need to write the high
394 * word first! If the mask bit in the low word is clear, we will enable
395 * the interrupt, and we need to make sure the entry is fully populated
396 * before that happens.
397 */
398static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
399{
400 union entry_union eu = {{0, 0}};
401
402 eu.entry = e;
403 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
404 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
405}
406
407static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
408{
409 unsigned long flags;
410
411 raw_spin_lock_irqsave(&ioapic_lock, flags);
412 __ioapic_write_entry(apic, pin, e);
413 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
414}
415
416/*
417 * When we mask an IO APIC routing entry, we need to write the low
418 * word first, in order to set the mask bit before we change the
419 * high bits!
420 */
421static void ioapic_mask_entry(int apic, int pin)
422{
423 unsigned long flags;
424 union entry_union eu = { .entry.mask = 1 };
425
426 raw_spin_lock_irqsave(&ioapic_lock, flags);
427 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
428 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
430}
431
432/*
433 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
434 * shared ISA-space IRQs, so we have to support them. We are super
435 * fast in the common case, and fast for shared ISA-space IRQs.
436 */
437static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
438{
439 struct irq_pin_list **last, *entry;
440
441 /* don't allow duplicates */
442 last = &cfg->irq_2_pin;
443 for_each_irq_pin(entry, cfg->irq_2_pin) {
444 if (entry->apic == apic && entry->pin == pin)
445 return 0;
446 last = &entry->next;
447 }
448
449 entry = alloc_irq_pin_list(node);
450 if (!entry) {
451 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
452 node, apic, pin);
453 return -ENOMEM;
454 }
455 entry->apic = apic;
456 entry->pin = pin;
457
458 *last = entry;
459 return 0;
460}
461
462static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
463{
464 if (__add_pin_to_irq_node(cfg, node, apic, pin))
465 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
466}
467
468/*
469 * Reroute an IRQ to a different pin.
470 */
471static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
472 int oldapic, int oldpin,
473 int newapic, int newpin)
474{
475 struct irq_pin_list *entry;
476
477 for_each_irq_pin(entry, cfg->irq_2_pin) {
478 if (entry->apic == oldapic && entry->pin == oldpin) {
479 entry->apic = newapic;
480 entry->pin = newpin;
481 /* every one is different, right? */
482 return;
483 }
484 }
485
486 /* old apic/pin didn't exist, so just add new ones */
487 add_pin_to_irq_node(cfg, node, newapic, newpin);
488}
489
490static void __io_apic_modify_irq(struct irq_pin_list *entry,
491 int mask_and, int mask_or,
492 void (*final)(struct irq_pin_list *entry))
493{
494 unsigned int reg, pin;
495
496 pin = entry->pin;
497 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
498 reg &= mask_and;
499 reg |= mask_or;
500 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
501 if (final)
502 final(entry);
503}
504
505static void io_apic_modify_irq(struct irq_cfg *cfg,
506 int mask_and, int mask_or,
507 void (*final)(struct irq_pin_list *entry))
508{
509 struct irq_pin_list *entry;
510
511 for_each_irq_pin(entry, cfg->irq_2_pin)
512 __io_apic_modify_irq(entry, mask_and, mask_or, final);
513}
514
515static void io_apic_sync(struct irq_pin_list *entry)
516{
517 /*
518 * Synchronize the IO-APIC and the CPU by doing
519 * a dummy read from the IO-APIC
520 */
521 struct io_apic __iomem *io_apic;
522
523 io_apic = io_apic_base(entry->apic);
524 readl(&io_apic->data);
525}
526
527static void mask_ioapic(struct irq_cfg *cfg)
528{
529 unsigned long flags;
530
531 raw_spin_lock_irqsave(&ioapic_lock, flags);
532 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
533 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
534}
535
536static void mask_ioapic_irq(struct irq_data *data)
537{
538 mask_ioapic(data->chip_data);
539}
540
541static void __unmask_ioapic(struct irq_cfg *cfg)
542{
543 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
544}
545
546static void unmask_ioapic(struct irq_cfg *cfg)
547{
548 unsigned long flags;
549
550 raw_spin_lock_irqsave(&ioapic_lock, flags);
551 __unmask_ioapic(cfg);
552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
553}
554
555static void unmask_ioapic_irq(struct irq_data *data)
556{
557 unmask_ioapic(data->chip_data);
558}
559
560/*
561 * IO-APIC versions below 0x20 don't support EOI register.
562 * For the record, here is the information about various versions:
563 * 0Xh 82489DX
564 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
565 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
566 * 30h-FFh Reserved
567 *
568 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
569 * version as 0x2. This is an error with documentation and these ICH chips
570 * use io-apic's of version 0x20.
571 *
572 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
573 * Otherwise, we simulate the EOI message manually by changing the trigger
574 * mode to edge and then back to level, with RTE being masked during this.
575 */
576static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
577{
578 if (mpc_ioapic_ver(apic) >= 0x20) {
579 /*
580 * Intr-remapping uses pin number as the virtual vector
581 * in the RTE. Actual vector is programmed in
582 * intr-remapping table entry. Hence for the io-apic
583 * EOI we use the pin number.
584 */
585 if (cfg && irq_remapped(cfg))
586 io_apic_eoi(apic, pin);
587 else
588 io_apic_eoi(apic, vector);
589 } else {
590 struct IO_APIC_route_entry entry, entry1;
591
592 entry = entry1 = __ioapic_read_entry(apic, pin);
593
594 /*
595 * Mask the entry and change the trigger mode to edge.
596 */
597 entry1.mask = 1;
598 entry1.trigger = IOAPIC_EDGE;
599
600 __ioapic_write_entry(apic, pin, entry1);
601
602 /*
603 * Restore the previous level triggered entry.
604 */
605 __ioapic_write_entry(apic, pin, entry);
606 }
607}
608
609static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
610{
611 struct irq_pin_list *entry;
612 unsigned long flags;
613
614 raw_spin_lock_irqsave(&ioapic_lock, flags);
615 for_each_irq_pin(entry, cfg->irq_2_pin)
616 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
617 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
618}
619
620static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
621{
622 struct IO_APIC_route_entry entry;
623
624 /* Check delivery_mode to be sure we're not clearing an SMI pin */
625 entry = ioapic_read_entry(apic, pin);
626 if (entry.delivery_mode == dest_SMI)
627 return;
628
629 /*
630 * Make sure the entry is masked and re-read the contents to check
631 * if it is a level triggered pin and if the remote-IRR is set.
632 */
633 if (!entry.mask) {
634 entry.mask = 1;
635 ioapic_write_entry(apic, pin, entry);
636 entry = ioapic_read_entry(apic, pin);
637 }
638
639 if (entry.irr) {
640 unsigned long flags;
641
642 /*
643 * Make sure the trigger mode is set to level. Explicit EOI
644 * doesn't clear the remote-IRR if the trigger mode is not
645 * set to level.
646 */
647 if (!entry.trigger) {
648 entry.trigger = IOAPIC_LEVEL;
649 ioapic_write_entry(apic, pin, entry);
650 }
651
652 raw_spin_lock_irqsave(&ioapic_lock, flags);
653 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
654 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
655 }
656
657 /*
658 * Clear the rest of the bits in the IO-APIC RTE except for the mask
659 * bit.
660 */
661 ioapic_mask_entry(apic, pin);
662 entry = ioapic_read_entry(apic, pin);
663 if (entry.irr)
664 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
665 mpc_ioapic_id(apic), pin);
666}
667
668static void clear_IO_APIC (void)
669{
670 int apic, pin;
671
672 for (apic = 0; apic < nr_ioapics; apic++)
673 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
674 clear_IO_APIC_pin(apic, pin);
675}
676
677#ifdef CONFIG_X86_32
678/*
679 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680 * specific CPU-side IRQs.
681 */
682
683#define MAX_PIRQS 8
684static int pirq_entries[MAX_PIRQS] = {
685 [0 ... MAX_PIRQS - 1] = -1
686};
687
688static int __init ioapic_pirq_setup(char *str)
689{
690 int i, max;
691 int ints[MAX_PIRQS+1];
692
693 get_options(str, ARRAY_SIZE(ints), ints);
694
695 apic_printk(APIC_VERBOSE, KERN_INFO
696 "PIRQ redirection, working around broken MP-BIOS.\n");
697 max = MAX_PIRQS;
698 if (ints[0] < MAX_PIRQS)
699 max = ints[0];
700
701 for (i = 0; i < max; i++) {
702 apic_printk(APIC_VERBOSE, KERN_DEBUG
703 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
704 /*
705 * PIRQs are mapped upside down, usually.
706 */
707 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
708 }
709 return 1;
710}
711
712__setup("pirq=", ioapic_pirq_setup);
713#endif /* CONFIG_X86_32 */
714
715/*
716 * Saves all the IO-APIC RTE's
717 */
718int save_ioapic_entries(void)
719{
720 int apic, pin;
721 int err = 0;
722
723 for (apic = 0; apic < nr_ioapics; apic++) {
724 if (!ioapics[apic].saved_registers) {
725 err = -ENOMEM;
726 continue;
727 }
728
729 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
730 ioapics[apic].saved_registers[pin] =
731 ioapic_read_entry(apic, pin);
732 }
733
734 return err;
735}
736
737/*
738 * Mask all IO APIC entries.
739 */
740void mask_ioapic_entries(void)
741{
742 int apic, pin;
743
744 for (apic = 0; apic < nr_ioapics; apic++) {
745 if (!ioapics[apic].saved_registers)
746 continue;
747
748 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
749 struct IO_APIC_route_entry entry;
750
751 entry = ioapics[apic].saved_registers[pin];
752 if (!entry.mask) {
753 entry.mask = 1;
754 ioapic_write_entry(apic, pin, entry);
755 }
756 }
757 }
758}
759
760/*
761 * Restore IO APIC entries which was saved in the ioapic structure.
762 */
763int restore_ioapic_entries(void)
764{
765 int apic, pin;
766
767 for (apic = 0; apic < nr_ioapics; apic++) {
768 if (!ioapics[apic].saved_registers)
769 continue;
770
771 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
772 ioapic_write_entry(apic, pin,
773 ioapics[apic].saved_registers[pin]);
774 }
775 return 0;
776}
777
778/*
779 * Find the IRQ entry number of a certain pin.
780 */
781static int find_irq_entry(int ioapic_idx, int pin, int type)
782{
783 int i;
784
785 for (i = 0; i < mp_irq_entries; i++)
786 if (mp_irqs[i].irqtype == type &&
787 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
788 mp_irqs[i].dstapic == MP_APIC_ALL) &&
789 mp_irqs[i].dstirq == pin)
790 return i;
791
792 return -1;
793}
794
795/*
796 * Find the pin to which IRQ[irq] (ISA) is connected
797 */
798static int __init find_isa_irq_pin(int irq, int type)
799{
800 int i;
801
802 for (i = 0; i < mp_irq_entries; i++) {
803 int lbus = mp_irqs[i].srcbus;
804
805 if (test_bit(lbus, mp_bus_not_pci) &&
806 (mp_irqs[i].irqtype == type) &&
807 (mp_irqs[i].srcbusirq == irq))
808
809 return mp_irqs[i].dstirq;
810 }
811 return -1;
812}
813
814static int __init find_isa_irq_apic(int irq, int type)
815{
816 int i;
817
818 for (i = 0; i < mp_irq_entries; i++) {
819 int lbus = mp_irqs[i].srcbus;
820
821 if (test_bit(lbus, mp_bus_not_pci) &&
822 (mp_irqs[i].irqtype == type) &&
823 (mp_irqs[i].srcbusirq == irq))
824 break;
825 }
826
827 if (i < mp_irq_entries) {
828 int ioapic_idx;
829
830 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
831 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
832 return ioapic_idx;
833 }
834
835 return -1;
836}
837
838#ifdef CONFIG_EISA
839/*
840 * EISA Edge/Level control register, ELCR
841 */
842static int EISA_ELCR(unsigned int irq)
843{
844 if (irq < legacy_pic->nr_legacy_irqs) {
845 unsigned int port = 0x4d0 + (irq >> 3);
846 return (inb(port) >> (irq & 7)) & 1;
847 }
848 apic_printk(APIC_VERBOSE, KERN_INFO
849 "Broken MPtable reports ISA irq %d\n", irq);
850 return 0;
851}
852
853#endif
854
855/* ISA interrupts are always polarity zero edge triggered,
856 * when listed as conforming in the MP table. */
857
858#define default_ISA_trigger(idx) (0)
859#define default_ISA_polarity(idx) (0)
860
861/* EISA interrupts are always polarity zero and can be edge or level
862 * trigger depending on the ELCR value. If an interrupt is listed as
863 * EISA conforming in the MP table, that means its trigger type must
864 * be read in from the ELCR */
865
866#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
867#define default_EISA_polarity(idx) default_ISA_polarity(idx)
868
869/* PCI interrupts are always polarity one level triggered,
870 * when listed as conforming in the MP table. */
871
872#define default_PCI_trigger(idx) (1)
873#define default_PCI_polarity(idx) (1)
874
875static int irq_polarity(int idx)
876{
877 int bus = mp_irqs[idx].srcbus;
878 int polarity;
879
880 /*
881 * Determine IRQ line polarity (high active or low active):
882 */
883 switch (mp_irqs[idx].irqflag & 3)
884 {
885 case 0: /* conforms, ie. bus-type dependent polarity */
886 if (test_bit(bus, mp_bus_not_pci))
887 polarity = default_ISA_polarity(idx);
888 else
889 polarity = default_PCI_polarity(idx);
890 break;
891 case 1: /* high active */
892 {
893 polarity = 0;
894 break;
895 }
896 case 2: /* reserved */
897 {
898 printk(KERN_WARNING "broken BIOS!!\n");
899 polarity = 1;
900 break;
901 }
902 case 3: /* low active */
903 {
904 polarity = 1;
905 break;
906 }
907 default: /* invalid */
908 {
909 printk(KERN_WARNING "broken BIOS!!\n");
910 polarity = 1;
911 break;
912 }
913 }
914 return polarity;
915}
916
917static int irq_trigger(int idx)
918{
919 int bus = mp_irqs[idx].srcbus;
920 int trigger;
921
922 /*
923 * Determine IRQ trigger mode (edge or level sensitive):
924 */
925 switch ((mp_irqs[idx].irqflag>>2) & 3)
926 {
927 case 0: /* conforms, ie. bus-type dependent */
928 if (test_bit(bus, mp_bus_not_pci))
929 trigger = default_ISA_trigger(idx);
930 else
931 trigger = default_PCI_trigger(idx);
932#ifdef CONFIG_EISA
933 switch (mp_bus_id_to_type[bus]) {
934 case MP_BUS_ISA: /* ISA pin */
935 {
936 /* set before the switch */
937 break;
938 }
939 case MP_BUS_EISA: /* EISA pin */
940 {
941 trigger = default_EISA_trigger(idx);
942 break;
943 }
944 case MP_BUS_PCI: /* PCI pin */
945 {
946 /* set before the switch */
947 break;
948 }
949 default:
950 {
951 printk(KERN_WARNING "broken BIOS!!\n");
952 trigger = 1;
953 break;
954 }
955 }
956#endif
957 break;
958 case 1: /* edge */
959 {
960 trigger = 0;
961 break;
962 }
963 case 2: /* reserved */
964 {
965 printk(KERN_WARNING "broken BIOS!!\n");
966 trigger = 1;
967 break;
968 }
969 case 3: /* level */
970 {
971 trigger = 1;
972 break;
973 }
974 default: /* invalid */
975 {
976 printk(KERN_WARNING "broken BIOS!!\n");
977 trigger = 0;
978 break;
979 }
980 }
981 return trigger;
982}
983
984static int pin_2_irq(int idx, int apic, int pin)
985{
986 int irq;
987 int bus = mp_irqs[idx].srcbus;
988 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
989
990 /*
991 * Debugging check, we are in big trouble if this message pops up!
992 */
993 if (mp_irqs[idx].dstirq != pin)
994 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
995
996 if (test_bit(bus, mp_bus_not_pci)) {
997 irq = mp_irqs[idx].srcbusirq;
998 } else {
999 u32 gsi = gsi_cfg->gsi_base + pin;
1000
1001 if (gsi >= NR_IRQS_LEGACY)
1002 irq = gsi;
1003 else
1004 irq = gsi_top + gsi;
1005 }
1006
1007#ifdef CONFIG_X86_32
1008 /*
1009 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1010 */
1011 if ((pin >= 16) && (pin <= 23)) {
1012 if (pirq_entries[pin-16] != -1) {
1013 if (!pirq_entries[pin-16]) {
1014 apic_printk(APIC_VERBOSE, KERN_DEBUG
1015 "disabling PIRQ%d\n", pin-16);
1016 } else {
1017 irq = pirq_entries[pin-16];
1018 apic_printk(APIC_VERBOSE, KERN_DEBUG
1019 "using PIRQ%d -> IRQ %d\n",
1020 pin-16, irq);
1021 }
1022 }
1023 }
1024#endif
1025
1026 return irq;
1027}
1028
1029/*
1030 * Find a specific PCI IRQ entry.
1031 * Not an __init, possibly needed by modules
1032 */
1033int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1034 struct io_apic_irq_attr *irq_attr)
1035{
1036 int ioapic_idx, i, best_guess = -1;
1037
1038 apic_printk(APIC_DEBUG,
1039 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1040 bus, slot, pin);
1041 if (test_bit(bus, mp_bus_not_pci)) {
1042 apic_printk(APIC_VERBOSE,
1043 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1044 return -1;
1045 }
1046 for (i = 0; i < mp_irq_entries; i++) {
1047 int lbus = mp_irqs[i].srcbus;
1048
1049 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1050 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1051 mp_irqs[i].dstapic == MP_APIC_ALL)
1052 break;
1053
1054 if (!test_bit(lbus, mp_bus_not_pci) &&
1055 !mp_irqs[i].irqtype &&
1056 (bus == lbus) &&
1057 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1058 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1059
1060 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1061 continue;
1062
1063 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1064 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1065 mp_irqs[i].dstirq,
1066 irq_trigger(i),
1067 irq_polarity(i));
1068 return irq;
1069 }
1070 /*
1071 * Use the first all-but-pin matching entry as a
1072 * best-guess fuzzy result for broken mptables.
1073 */
1074 if (best_guess < 0) {
1075 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1076 mp_irqs[i].dstirq,
1077 irq_trigger(i),
1078 irq_polarity(i));
1079 best_guess = irq;
1080 }
1081 }
1082 }
1083 return best_guess;
1084}
1085EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1086
1087void lock_vector_lock(void)
1088{
1089 /* Used to the online set of cpus does not change
1090 * during assign_irq_vector.
1091 */
1092 raw_spin_lock(&vector_lock);
1093}
1094
1095void unlock_vector_lock(void)
1096{
1097 raw_spin_unlock(&vector_lock);
1098}
1099
1100static int
1101__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1102{
1103 /*
1104 * NOTE! The local APIC isn't very good at handling
1105 * multiple interrupts at the same interrupt level.
1106 * As the interrupt level is determined by taking the
1107 * vector number and shifting that right by 4, we
1108 * want to spread these out a bit so that they don't
1109 * all fall in the same interrupt level.
1110 *
1111 * Also, we've got to be careful not to trash gate
1112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1113 */
1114 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1115 static int current_offset = VECTOR_OFFSET_START % 8;
1116 unsigned int old_vector;
1117 int cpu, err;
1118 cpumask_var_t tmp_mask;
1119
1120 if (cfg->move_in_progress)
1121 return -EBUSY;
1122
1123 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1124 return -ENOMEM;
1125
1126 old_vector = cfg->vector;
1127 if (old_vector) {
1128 cpumask_and(tmp_mask, mask, cpu_online_mask);
1129 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1130 if (!cpumask_empty(tmp_mask)) {
1131 free_cpumask_var(tmp_mask);
1132 return 0;
1133 }
1134 }
1135
1136 /* Only try and allocate irqs on cpus that are present */
1137 err = -ENOSPC;
1138 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1139 int new_cpu;
1140 int vector, offset;
1141
1142 apic->vector_allocation_domain(cpu, tmp_mask);
1143
1144 vector = current_vector;
1145 offset = current_offset;
1146next:
1147 vector += 8;
1148 if (vector >= first_system_vector) {
1149 /* If out of vectors on large boxen, must share them. */
1150 offset = (offset + 1) % 8;
1151 vector = FIRST_EXTERNAL_VECTOR + offset;
1152 }
1153 if (unlikely(current_vector == vector))
1154 continue;
1155
1156 if (test_bit(vector, used_vectors))
1157 goto next;
1158
1159 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1160 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1161 goto next;
1162 /* Found one! */
1163 current_vector = vector;
1164 current_offset = offset;
1165 if (old_vector) {
1166 cfg->move_in_progress = 1;
1167 cpumask_copy(cfg->old_domain, cfg->domain);
1168 }
1169 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1170 per_cpu(vector_irq, new_cpu)[vector] = irq;
1171 cfg->vector = vector;
1172 cpumask_copy(cfg->domain, tmp_mask);
1173 err = 0;
1174 break;
1175 }
1176 free_cpumask_var(tmp_mask);
1177 return err;
1178}
1179
1180int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1181{
1182 int err;
1183 unsigned long flags;
1184
1185 raw_spin_lock_irqsave(&vector_lock, flags);
1186 err = __assign_irq_vector(irq, cfg, mask);
1187 raw_spin_unlock_irqrestore(&vector_lock, flags);
1188 return err;
1189}
1190
1191static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1192{
1193 int cpu, vector;
1194
1195 BUG_ON(!cfg->vector);
1196
1197 vector = cfg->vector;
1198 for_each_cpu(cpu, cfg->domain)
1199 per_cpu(vector_irq, cpu)[vector] = -1;
1200
1201 cfg->vector = 0;
1202 cpumask_clear(cfg->domain);
1203
1204 if (likely(!cfg->move_in_progress))
1205 return;
1206 for_each_cpu(cpu, cfg->old_domain) {
1207 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1208 vector++) {
1209 if (per_cpu(vector_irq, cpu)[vector] != irq)
1210 continue;
1211 per_cpu(vector_irq, cpu)[vector] = -1;
1212 break;
1213 }
1214 }
1215 cfg->move_in_progress = 0;
1216}
1217
1218void __setup_vector_irq(int cpu)
1219{
1220 /* Initialize vector_irq on a new cpu */
1221 int irq, vector;
1222 struct irq_cfg *cfg;
1223
1224 /*
1225 * vector_lock will make sure that we don't run into irq vector
1226 * assignments that might be happening on another cpu in parallel,
1227 * while we setup our initial vector to irq mappings.
1228 */
1229 raw_spin_lock(&vector_lock);
1230 /* Mark the inuse vectors */
1231 for_each_active_irq(irq) {
1232 cfg = irq_get_chip_data(irq);
1233 if (!cfg)
1234 continue;
1235 /*
1236 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1237 * will be part of the irq_cfg's domain.
1238 */
1239 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1240 cpumask_set_cpu(cpu, cfg->domain);
1241
1242 if (!cpumask_test_cpu(cpu, cfg->domain))
1243 continue;
1244 vector = cfg->vector;
1245 per_cpu(vector_irq, cpu)[vector] = irq;
1246 }
1247 /* Mark the free vectors */
1248 for (vector = 0; vector < NR_VECTORS; ++vector) {
1249 irq = per_cpu(vector_irq, cpu)[vector];
1250 if (irq < 0)
1251 continue;
1252
1253 cfg = irq_cfg(irq);
1254 if (!cpumask_test_cpu(cpu, cfg->domain))
1255 per_cpu(vector_irq, cpu)[vector] = -1;
1256 }
1257 raw_spin_unlock(&vector_lock);
1258}
1259
1260static struct irq_chip ioapic_chip;
1261
1262#ifdef CONFIG_X86_32
1263static inline int IO_APIC_irq_trigger(int irq)
1264{
1265 int apic, idx, pin;
1266
1267 for (apic = 0; apic < nr_ioapics; apic++) {
1268 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1269 idx = find_irq_entry(apic, pin, mp_INT);
1270 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1271 return irq_trigger(idx);
1272 }
1273 }
1274 /*
1275 * nonexistent IRQs are edge default
1276 */
1277 return 0;
1278}
1279#else
1280static inline int IO_APIC_irq_trigger(int irq)
1281{
1282 return 1;
1283}
1284#endif
1285
1286static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1287 unsigned long trigger)
1288{
1289 struct irq_chip *chip = &ioapic_chip;
1290 irq_flow_handler_t hdl;
1291 bool fasteoi;
1292
1293 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1294 trigger == IOAPIC_LEVEL) {
1295 irq_set_status_flags(irq, IRQ_LEVEL);
1296 fasteoi = true;
1297 } else {
1298 irq_clear_status_flags(irq, IRQ_LEVEL);
1299 fasteoi = false;
1300 }
1301
1302 if (irq_remapped(cfg)) {
1303 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1304 irq_remap_modify_chip_defaults(chip);
1305 fasteoi = trigger != 0;
1306 }
1307
1308 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1309 irq_set_chip_and_handler_name(irq, chip, hdl,
1310 fasteoi ? "fasteoi" : "edge");
1311}
1312
1313static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1314 unsigned int destination, int vector,
1315 struct io_apic_irq_attr *attr)
1316{
1317 if (irq_remapping_enabled)
1318 return setup_ioapic_remapped_entry(irq, entry, destination,
1319 vector, attr);
1320
1321 memset(entry, 0, sizeof(*entry));
1322
1323 entry->delivery_mode = apic->irq_delivery_mode;
1324 entry->dest_mode = apic->irq_dest_mode;
1325 entry->dest = destination;
1326 entry->vector = vector;
1327 entry->mask = 0; /* enable IRQ */
1328 entry->trigger = attr->trigger;
1329 entry->polarity = attr->polarity;
1330
1331 /*
1332 * Mask level triggered irqs.
1333 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1334 */
1335 if (attr->trigger)
1336 entry->mask = 1;
1337
1338 return 0;
1339}
1340
1341static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1342 struct io_apic_irq_attr *attr)
1343{
1344 struct IO_APIC_route_entry entry;
1345 unsigned int dest;
1346
1347 if (!IO_APIC_IRQ(irq))
1348 return;
1349 /*
1350 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1351 * controllers like 8259. Now that IO-APIC can handle this irq, update
1352 * the cfg->domain.
1353 */
1354 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1355 apic->vector_allocation_domain(0, cfg->domain);
1356
1357 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1358 return;
1359
1360 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1361
1362 apic_printk(APIC_VERBOSE,KERN_DEBUG
1363 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1364 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1365 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1366 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1367
1368 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1369 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1370 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1371 __clear_irq_vector(irq, cfg);
1372
1373 return;
1374 }
1375
1376 ioapic_register_intr(irq, cfg, attr->trigger);
1377 if (irq < legacy_pic->nr_legacy_irqs)
1378 legacy_pic->mask(irq);
1379
1380 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1381}
1382
1383static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1384{
1385 if (idx != -1)
1386 return false;
1387
1388 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1389 mpc_ioapic_id(ioapic_idx), pin);
1390 return true;
1391}
1392
1393static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1394{
1395 int idx, node = cpu_to_node(0);
1396 struct io_apic_irq_attr attr;
1397 unsigned int pin, irq;
1398
1399 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1400 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1401 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1402 continue;
1403
1404 irq = pin_2_irq(idx, ioapic_idx, pin);
1405
1406 if ((ioapic_idx > 0) && (irq > 16))
1407 continue;
1408
1409 /*
1410 * Skip the timer IRQ if there's a quirk handler
1411 * installed and if it returns 1:
1412 */
1413 if (apic->multi_timer_check &&
1414 apic->multi_timer_check(ioapic_idx, irq))
1415 continue;
1416
1417 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1418 irq_polarity(idx));
1419
1420 io_apic_setup_irq_pin(irq, node, &attr);
1421 }
1422}
1423
1424static void __init setup_IO_APIC_irqs(void)
1425{
1426 unsigned int ioapic_idx;
1427
1428 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1429
1430 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1431 __io_apic_setup_irqs(ioapic_idx);
1432}
1433
1434/*
1435 * for the gsit that is not in first ioapic
1436 * but could not use acpi_register_gsi()
1437 * like some special sci in IBM x3330
1438 */
1439void setup_IO_APIC_irq_extra(u32 gsi)
1440{
1441 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1442 struct io_apic_irq_attr attr;
1443
1444 /*
1445 * Convert 'gsi' to 'ioapic.pin'.
1446 */
1447 ioapic_idx = mp_find_ioapic(gsi);
1448 if (ioapic_idx < 0)
1449 return;
1450
1451 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1452 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1453 if (idx == -1)
1454 return;
1455
1456 irq = pin_2_irq(idx, ioapic_idx, pin);
1457
1458 /* Only handle the non legacy irqs on secondary ioapics */
1459 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1460 return;
1461
1462 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1463 irq_polarity(idx));
1464
1465 io_apic_setup_irq_pin_once(irq, node, &attr);
1466}
1467
1468/*
1469 * Set up the timer pin, possibly with the 8259A-master behind.
1470 */
1471static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1472 unsigned int pin, int vector)
1473{
1474 struct IO_APIC_route_entry entry;
1475
1476 if (irq_remapping_enabled)
1477 return;
1478
1479 memset(&entry, 0, sizeof(entry));
1480
1481 /*
1482 * We use logical delivery to get the timer IRQ
1483 * to the first CPU.
1484 */
1485 entry.dest_mode = apic->irq_dest_mode;
1486 entry.mask = 0; /* don't mask IRQ for edge */
1487 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1488 entry.delivery_mode = apic->irq_delivery_mode;
1489 entry.polarity = 0;
1490 entry.trigger = 0;
1491 entry.vector = vector;
1492
1493 /*
1494 * The timer IRQ doesn't have to know that behind the
1495 * scene we may have a 8259A-master in AEOI mode ...
1496 */
1497 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1498 "edge");
1499
1500 /*
1501 * Add it to the IO-APIC irq-routing table:
1502 */
1503 ioapic_write_entry(ioapic_idx, pin, entry);
1504}
1505
1506__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1507{
1508 int i;
1509 union IO_APIC_reg_00 reg_00;
1510 union IO_APIC_reg_01 reg_01;
1511 union IO_APIC_reg_02 reg_02;
1512 union IO_APIC_reg_03 reg_03;
1513 unsigned long flags;
1514
1515 raw_spin_lock_irqsave(&ioapic_lock, flags);
1516 reg_00.raw = io_apic_read(ioapic_idx, 0);
1517 reg_01.raw = io_apic_read(ioapic_idx, 1);
1518 if (reg_01.bits.version >= 0x10)
1519 reg_02.raw = io_apic_read(ioapic_idx, 2);
1520 if (reg_01.bits.version >= 0x20)
1521 reg_03.raw = io_apic_read(ioapic_idx, 3);
1522 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1523
1524 printk("\n");
1525 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1526 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1527 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1528 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1529 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1530
1531 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1532 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1533 reg_01.bits.entries);
1534
1535 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1536 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1537 reg_01.bits.version);
1538
1539 /*
1540 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1541 * but the value of reg_02 is read as the previous read register
1542 * value, so ignore it if reg_02 == reg_01.
1543 */
1544 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1545 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1546 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1547 }
1548
1549 /*
1550 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1551 * or reg_03, but the value of reg_0[23] is read as the previous read
1552 * register value, so ignore it if reg_03 == reg_0[12].
1553 */
1554 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1555 reg_03.raw != reg_01.raw) {
1556 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1557 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1558 }
1559
1560 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1561
1562 if (irq_remapping_enabled) {
1563 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1564 " Pol Stat Indx2 Zero Vect:\n");
1565 } else {
1566 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1567 " Stat Dmod Deli Vect:\n");
1568 }
1569
1570 for (i = 0; i <= reg_01.bits.entries; i++) {
1571 if (irq_remapping_enabled) {
1572 struct IO_APIC_route_entry entry;
1573 struct IR_IO_APIC_route_entry *ir_entry;
1574
1575 entry = ioapic_read_entry(ioapic_idx, i);
1576 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1577 printk(KERN_DEBUG " %02x %04X ",
1578 i,
1579 ir_entry->index
1580 );
1581 printk("%1d %1d %1d %1d %1d "
1582 "%1d %1d %X %02X\n",
1583 ir_entry->format,
1584 ir_entry->mask,
1585 ir_entry->trigger,
1586 ir_entry->irr,
1587 ir_entry->polarity,
1588 ir_entry->delivery_status,
1589 ir_entry->index2,
1590 ir_entry->zero,
1591 ir_entry->vector
1592 );
1593 } else {
1594 struct IO_APIC_route_entry entry;
1595
1596 entry = ioapic_read_entry(ioapic_idx, i);
1597 printk(KERN_DEBUG " %02x %02X ",
1598 i,
1599 entry.dest
1600 );
1601 printk("%1d %1d %1d %1d %1d "
1602 "%1d %1d %02X\n",
1603 entry.mask,
1604 entry.trigger,
1605 entry.irr,
1606 entry.polarity,
1607 entry.delivery_status,
1608 entry.dest_mode,
1609 entry.delivery_mode,
1610 entry.vector
1611 );
1612 }
1613 }
1614}
1615
1616__apicdebuginit(void) print_IO_APICs(void)
1617{
1618 int ioapic_idx;
1619 struct irq_cfg *cfg;
1620 unsigned int irq;
1621 struct irq_chip *chip;
1622
1623 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1624 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1625 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1626 mpc_ioapic_id(ioapic_idx),
1627 ioapics[ioapic_idx].nr_registers);
1628
1629 /*
1630 * We are a bit conservative about what we expect. We have to
1631 * know about every hardware change ASAP.
1632 */
1633 printk(KERN_INFO "testing the IO APIC.......................\n");
1634
1635 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1636 print_IO_APIC(ioapic_idx);
1637
1638 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1639 for_each_active_irq(irq) {
1640 struct irq_pin_list *entry;
1641
1642 chip = irq_get_chip(irq);
1643 if (chip != &ioapic_chip)
1644 continue;
1645
1646 cfg = irq_get_chip_data(irq);
1647 if (!cfg)
1648 continue;
1649 entry = cfg->irq_2_pin;
1650 if (!entry)
1651 continue;
1652 printk(KERN_DEBUG "IRQ%d ", irq);
1653 for_each_irq_pin(entry, cfg->irq_2_pin)
1654 printk("-> %d:%d", entry->apic, entry->pin);
1655 printk("\n");
1656 }
1657
1658 printk(KERN_INFO ".................................... done.\n");
1659}
1660
1661__apicdebuginit(void) print_APIC_field(int base)
1662{
1663 int i;
1664
1665 printk(KERN_DEBUG);
1666
1667 for (i = 0; i < 8; i++)
1668 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1669
1670 printk(KERN_CONT "\n");
1671}
1672
1673__apicdebuginit(void) print_local_APIC(void *dummy)
1674{
1675 unsigned int i, v, ver, maxlvt;
1676 u64 icr;
1677
1678 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1679 smp_processor_id(), hard_smp_processor_id());
1680 v = apic_read(APIC_ID);
1681 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1682 v = apic_read(APIC_LVR);
1683 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1684 ver = GET_APIC_VERSION(v);
1685 maxlvt = lapic_get_maxlvt();
1686
1687 v = apic_read(APIC_TASKPRI);
1688 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1689
1690 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1691 if (!APIC_XAPIC(ver)) {
1692 v = apic_read(APIC_ARBPRI);
1693 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1694 v & APIC_ARBPRI_MASK);
1695 }
1696 v = apic_read(APIC_PROCPRI);
1697 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1698 }
1699
1700 /*
1701 * Remote read supported only in the 82489DX and local APIC for
1702 * Pentium processors.
1703 */
1704 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1705 v = apic_read(APIC_RRR);
1706 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1707 }
1708
1709 v = apic_read(APIC_LDR);
1710 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1711 if (!x2apic_enabled()) {
1712 v = apic_read(APIC_DFR);
1713 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1714 }
1715 v = apic_read(APIC_SPIV);
1716 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1717
1718 printk(KERN_DEBUG "... APIC ISR field:\n");
1719 print_APIC_field(APIC_ISR);
1720 printk(KERN_DEBUG "... APIC TMR field:\n");
1721 print_APIC_field(APIC_TMR);
1722 printk(KERN_DEBUG "... APIC IRR field:\n");
1723 print_APIC_field(APIC_IRR);
1724
1725 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1726 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1727 apic_write(APIC_ESR, 0);
1728
1729 v = apic_read(APIC_ESR);
1730 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1731 }
1732
1733 icr = apic_icr_read();
1734 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1735 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1736
1737 v = apic_read(APIC_LVTT);
1738 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1739
1740 if (maxlvt > 3) { /* PC is LVT#4. */
1741 v = apic_read(APIC_LVTPC);
1742 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1743 }
1744 v = apic_read(APIC_LVT0);
1745 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1746 v = apic_read(APIC_LVT1);
1747 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1748
1749 if (maxlvt > 2) { /* ERR is LVT#3. */
1750 v = apic_read(APIC_LVTERR);
1751 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1752 }
1753
1754 v = apic_read(APIC_TMICT);
1755 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1756 v = apic_read(APIC_TMCCT);
1757 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1758 v = apic_read(APIC_TDCR);
1759 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1760
1761 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1762 v = apic_read(APIC_EFEAT);
1763 maxlvt = (v >> 16) & 0xff;
1764 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1765 v = apic_read(APIC_ECTRL);
1766 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1767 for (i = 0; i < maxlvt; i++) {
1768 v = apic_read(APIC_EILVTn(i));
1769 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1770 }
1771 }
1772 printk("\n");
1773}
1774
1775__apicdebuginit(void) print_local_APICs(int maxcpu)
1776{
1777 int cpu;
1778
1779 if (!maxcpu)
1780 return;
1781
1782 preempt_disable();
1783 for_each_online_cpu(cpu) {
1784 if (cpu >= maxcpu)
1785 break;
1786 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1787 }
1788 preempt_enable();
1789}
1790
1791__apicdebuginit(void) print_PIC(void)
1792{
1793 unsigned int v;
1794 unsigned long flags;
1795
1796 if (!legacy_pic->nr_legacy_irqs)
1797 return;
1798
1799 printk(KERN_DEBUG "\nprinting PIC contents\n");
1800
1801 raw_spin_lock_irqsave(&i8259A_lock, flags);
1802
1803 v = inb(0xa1) << 8 | inb(0x21);
1804 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1805
1806 v = inb(0xa0) << 8 | inb(0x20);
1807 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1808
1809 outb(0x0b,0xa0);
1810 outb(0x0b,0x20);
1811 v = inb(0xa0) << 8 | inb(0x20);
1812 outb(0x0a,0xa0);
1813 outb(0x0a,0x20);
1814
1815 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1816
1817 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1818
1819 v = inb(0x4d1) << 8 | inb(0x4d0);
1820 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1821}
1822
1823static int __initdata show_lapic = 1;
1824static __init int setup_show_lapic(char *arg)
1825{
1826 int num = -1;
1827
1828 if (strcmp(arg, "all") == 0) {
1829 show_lapic = CONFIG_NR_CPUS;
1830 } else {
1831 get_option(&arg, &num);
1832 if (num >= 0)
1833 show_lapic = num;
1834 }
1835
1836 return 1;
1837}
1838__setup("show_lapic=", setup_show_lapic);
1839
1840__apicdebuginit(int) print_ICs(void)
1841{
1842 if (apic_verbosity == APIC_QUIET)
1843 return 0;
1844
1845 print_PIC();
1846
1847 /* don't print out if apic is not there */
1848 if (!cpu_has_apic && !apic_from_smp_config())
1849 return 0;
1850
1851 print_local_APICs(show_lapic);
1852 print_IO_APICs();
1853
1854 return 0;
1855}
1856
1857late_initcall(print_ICs);
1858
1859
1860/* Where if anywhere is the i8259 connect in external int mode */
1861static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1862
1863void __init enable_IO_APIC(void)
1864{
1865 int i8259_apic, i8259_pin;
1866 int apic;
1867
1868 if (!legacy_pic->nr_legacy_irqs)
1869 return;
1870
1871 for(apic = 0; apic < nr_ioapics; apic++) {
1872 int pin;
1873 /* See if any of the pins is in ExtINT mode */
1874 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1875 struct IO_APIC_route_entry entry;
1876 entry = ioapic_read_entry(apic, pin);
1877
1878 /* If the interrupt line is enabled and in ExtInt mode
1879 * I have found the pin where the i8259 is connected.
1880 */
1881 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1882 ioapic_i8259.apic = apic;
1883 ioapic_i8259.pin = pin;
1884 goto found_i8259;
1885 }
1886 }
1887 }
1888 found_i8259:
1889 /* Look to see what if the MP table has reported the ExtINT */
1890 /* If we could not find the appropriate pin by looking at the ioapic
1891 * the i8259 probably is not connected the ioapic but give the
1892 * mptable a chance anyway.
1893 */
1894 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1895 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1896 /* Trust the MP table if nothing is setup in the hardware */
1897 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1898 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1899 ioapic_i8259.pin = i8259_pin;
1900 ioapic_i8259.apic = i8259_apic;
1901 }
1902 /* Complain if the MP table and the hardware disagree */
1903 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1904 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1905 {
1906 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1907 }
1908
1909 /*
1910 * Do not trust the IO-APIC being empty at bootup
1911 */
1912 clear_IO_APIC();
1913}
1914
1915/*
1916 * Not an __init, needed by the reboot code
1917 */
1918void disable_IO_APIC(void)
1919{
1920 /*
1921 * Clear the IO-APIC before rebooting:
1922 */
1923 clear_IO_APIC();
1924
1925 if (!legacy_pic->nr_legacy_irqs)
1926 return;
1927
1928 /*
1929 * If the i8259 is routed through an IOAPIC
1930 * Put that IOAPIC in virtual wire mode
1931 * so legacy interrupts can be delivered.
1932 *
1933 * With interrupt-remapping, for now we will use virtual wire A mode,
1934 * as virtual wire B is little complex (need to configure both
1935 * IOAPIC RTE as well as interrupt-remapping table entry).
1936 * As this gets called during crash dump, keep this simple for now.
1937 */
1938 if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) {
1939 struct IO_APIC_route_entry entry;
1940
1941 memset(&entry, 0, sizeof(entry));
1942 entry.mask = 0; /* Enabled */
1943 entry.trigger = 0; /* Edge */
1944 entry.irr = 0;
1945 entry.polarity = 0; /* High */
1946 entry.delivery_status = 0;
1947 entry.dest_mode = 0; /* Physical */
1948 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1949 entry.vector = 0;
1950 entry.dest = read_apic_id();
1951
1952 /*
1953 * Add it to the IO-APIC irq-routing table:
1954 */
1955 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1956 }
1957
1958 /*
1959 * Use virtual wire A mode when interrupt remapping is enabled.
1960 */
1961 if (cpu_has_apic || apic_from_smp_config())
1962 disconnect_bsp_APIC(!irq_remapping_enabled &&
1963 ioapic_i8259.pin != -1);
1964}
1965
1966#ifdef CONFIG_X86_32
1967/*
1968 * function to set the IO-APIC physical IDs based on the
1969 * values stored in the MPC table.
1970 *
1971 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1972 */
1973void __init setup_ioapic_ids_from_mpc_nocheck(void)
1974{
1975 union IO_APIC_reg_00 reg_00;
1976 physid_mask_t phys_id_present_map;
1977 int ioapic_idx;
1978 int i;
1979 unsigned char old_id;
1980 unsigned long flags;
1981
1982 /*
1983 * This is broken; anything with a real cpu count has to
1984 * circumvent this idiocy regardless.
1985 */
1986 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1987
1988 /*
1989 * Set the IOAPIC ID to the value stored in the MPC table.
1990 */
1991 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1992 /* Read the register 0 value */
1993 raw_spin_lock_irqsave(&ioapic_lock, flags);
1994 reg_00.raw = io_apic_read(ioapic_idx, 0);
1995 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1996
1997 old_id = mpc_ioapic_id(ioapic_idx);
1998
1999 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2000 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2001 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2002 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2003 reg_00.bits.ID);
2004 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2005 }
2006
2007 /*
2008 * Sanity check, is the ID really free? Every APIC in a
2009 * system must have a unique ID or we get lots of nice
2010 * 'stuck on smp_invalidate_needed IPI wait' messages.
2011 */
2012 if (apic->check_apicid_used(&phys_id_present_map,
2013 mpc_ioapic_id(ioapic_idx))) {
2014 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2015 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2016 for (i = 0; i < get_physical_broadcast(); i++)
2017 if (!physid_isset(i, phys_id_present_map))
2018 break;
2019 if (i >= get_physical_broadcast())
2020 panic("Max APIC ID exceeded!\n");
2021 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2022 i);
2023 physid_set(i, phys_id_present_map);
2024 ioapics[ioapic_idx].mp_config.apicid = i;
2025 } else {
2026 physid_mask_t tmp;
2027 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2028 &tmp);
2029 apic_printk(APIC_VERBOSE, "Setting %d in the "
2030 "phys_id_present_map\n",
2031 mpc_ioapic_id(ioapic_idx));
2032 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2033 }
2034
2035 /*
2036 * We need to adjust the IRQ routing table
2037 * if the ID changed.
2038 */
2039 if (old_id != mpc_ioapic_id(ioapic_idx))
2040 for (i = 0; i < mp_irq_entries; i++)
2041 if (mp_irqs[i].dstapic == old_id)
2042 mp_irqs[i].dstapic
2043 = mpc_ioapic_id(ioapic_idx);
2044
2045 /*
2046 * Update the ID register according to the right value
2047 * from the MPC table if they are different.
2048 */
2049 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2050 continue;
2051
2052 apic_printk(APIC_VERBOSE, KERN_INFO
2053 "...changing IO-APIC physical APIC ID to %d ...",
2054 mpc_ioapic_id(ioapic_idx));
2055
2056 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2057 raw_spin_lock_irqsave(&ioapic_lock, flags);
2058 io_apic_write(ioapic_idx, 0, reg_00.raw);
2059 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2060
2061 /*
2062 * Sanity check
2063 */
2064 raw_spin_lock_irqsave(&ioapic_lock, flags);
2065 reg_00.raw = io_apic_read(ioapic_idx, 0);
2066 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2067 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2068 printk("could not set ID!\n");
2069 else
2070 apic_printk(APIC_VERBOSE, " ok.\n");
2071 }
2072}
2073
2074void __init setup_ioapic_ids_from_mpc(void)
2075{
2076
2077 if (acpi_ioapic)
2078 return;
2079 /*
2080 * Don't check I/O APIC IDs for xAPIC systems. They have
2081 * no meaning without the serial APIC bus.
2082 */
2083 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2084 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2085 return;
2086 setup_ioapic_ids_from_mpc_nocheck();
2087}
2088#endif
2089
2090int no_timer_check __initdata;
2091
2092static int __init notimercheck(char *s)
2093{
2094 no_timer_check = 1;
2095 return 1;
2096}
2097__setup("no_timer_check", notimercheck);
2098
2099/*
2100 * There is a nasty bug in some older SMP boards, their mptable lies
2101 * about the timer IRQ. We do the following to work around the situation:
2102 *
2103 * - timer IRQ defaults to IO-APIC IRQ
2104 * - if this function detects that timer IRQs are defunct, then we fall
2105 * back to ISA timer IRQs
2106 */
2107static int __init timer_irq_works(void)
2108{
2109 unsigned long t1 = jiffies;
2110 unsigned long flags;
2111
2112 if (no_timer_check)
2113 return 1;
2114
2115 local_save_flags(flags);
2116 local_irq_enable();
2117 /* Let ten ticks pass... */
2118 mdelay((10 * 1000) / HZ);
2119 local_irq_restore(flags);
2120
2121 /*
2122 * Expect a few ticks at least, to be sure some possible
2123 * glue logic does not lock up after one or two first
2124 * ticks in a non-ExtINT mode. Also the local APIC
2125 * might have cached one ExtINT interrupt. Finally, at
2126 * least one tick may be lost due to delays.
2127 */
2128
2129 /* jiffies wrap? */
2130 if (time_after(jiffies, t1 + 4))
2131 return 1;
2132 return 0;
2133}
2134
2135/*
2136 * In the SMP+IOAPIC case it might happen that there are an unspecified
2137 * number of pending IRQ events unhandled. These cases are very rare,
2138 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2139 * better to do it this way as thus we do not have to be aware of
2140 * 'pending' interrupts in the IRQ path, except at this point.
2141 */
2142/*
2143 * Edge triggered needs to resend any interrupt
2144 * that was delayed but this is now handled in the device
2145 * independent code.
2146 */
2147
2148/*
2149 * Starting up a edge-triggered IO-APIC interrupt is
2150 * nasty - we need to make sure that we get the edge.
2151 * If it is already asserted for some reason, we need
2152 * return 1 to indicate that is was pending.
2153 *
2154 * This is not complete - we should be able to fake
2155 * an edge even if it isn't on the 8259A...
2156 */
2157
2158static unsigned int startup_ioapic_irq(struct irq_data *data)
2159{
2160 int was_pending = 0, irq = data->irq;
2161 unsigned long flags;
2162
2163 raw_spin_lock_irqsave(&ioapic_lock, flags);
2164 if (irq < legacy_pic->nr_legacy_irqs) {
2165 legacy_pic->mask(irq);
2166 if (legacy_pic->irq_pending(irq))
2167 was_pending = 1;
2168 }
2169 __unmask_ioapic(data->chip_data);
2170 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2171
2172 return was_pending;
2173}
2174
2175static int ioapic_retrigger_irq(struct irq_data *data)
2176{
2177 struct irq_cfg *cfg = data->chip_data;
2178 unsigned long flags;
2179
2180 raw_spin_lock_irqsave(&vector_lock, flags);
2181 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2182 raw_spin_unlock_irqrestore(&vector_lock, flags);
2183
2184 return 1;
2185}
2186
2187/*
2188 * Level and edge triggered IO-APIC interrupts need different handling,
2189 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2190 * handled with the level-triggered descriptor, but that one has slightly
2191 * more overhead. Level-triggered interrupts cannot be handled with the
2192 * edge-triggered handler, without risking IRQ storms and other ugly
2193 * races.
2194 */
2195
2196#ifdef CONFIG_SMP
2197void send_cleanup_vector(struct irq_cfg *cfg)
2198{
2199 cpumask_var_t cleanup_mask;
2200
2201 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2202 unsigned int i;
2203 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2204 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2205 } else {
2206 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2207 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2208 free_cpumask_var(cleanup_mask);
2209 }
2210 cfg->move_in_progress = 0;
2211}
2212
2213static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2214{
2215 int apic, pin;
2216 struct irq_pin_list *entry;
2217 u8 vector = cfg->vector;
2218
2219 for_each_irq_pin(entry, cfg->irq_2_pin) {
2220 unsigned int reg;
2221
2222 apic = entry->apic;
2223 pin = entry->pin;
2224 /*
2225 * With interrupt-remapping, destination information comes
2226 * from interrupt-remapping table entry.
2227 */
2228 if (!irq_remapped(cfg))
2229 io_apic_write(apic, 0x11 + pin*2, dest);
2230 reg = io_apic_read(apic, 0x10 + pin*2);
2231 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2232 reg |= vector;
2233 io_apic_modify(apic, 0x10 + pin*2, reg);
2234 }
2235}
2236
2237/*
2238 * Either sets data->affinity to a valid value, and returns
2239 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2240 * leaves data->affinity untouched.
2241 */
2242int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2243 unsigned int *dest_id)
2244{
2245 struct irq_cfg *cfg = data->chip_data;
2246
2247 if (!cpumask_intersects(mask, cpu_online_mask))
2248 return -1;
2249
2250 if (assign_irq_vector(data->irq, data->chip_data, mask))
2251 return -1;
2252
2253 cpumask_copy(data->affinity, mask);
2254
2255 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2256 return 0;
2257}
2258
2259static int
2260ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2261 bool force)
2262{
2263 unsigned int dest, irq = data->irq;
2264 unsigned long flags;
2265 int ret;
2266
2267 raw_spin_lock_irqsave(&ioapic_lock, flags);
2268 ret = __ioapic_set_affinity(data, mask, &dest);
2269 if (!ret) {
2270 /* Only the high 8 bits are valid. */
2271 dest = SET_APIC_LOGICAL_ID(dest);
2272 __target_IO_APIC_irq(irq, dest, data->chip_data);
2273 }
2274 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2275 return ret;
2276}
2277
2278asmlinkage void smp_irq_move_cleanup_interrupt(void)
2279{
2280 unsigned vector, me;
2281
2282 ack_APIC_irq();
2283 irq_enter();
2284 exit_idle();
2285
2286 me = smp_processor_id();
2287 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2288 unsigned int irq;
2289 unsigned int irr;
2290 struct irq_desc *desc;
2291 struct irq_cfg *cfg;
2292 irq = __this_cpu_read(vector_irq[vector]);
2293
2294 if (irq == -1)
2295 continue;
2296
2297 desc = irq_to_desc(irq);
2298 if (!desc)
2299 continue;
2300
2301 cfg = irq_cfg(irq);
2302 raw_spin_lock(&desc->lock);
2303
2304 /*
2305 * Check if the irq migration is in progress. If so, we
2306 * haven't received the cleanup request yet for this irq.
2307 */
2308 if (cfg->move_in_progress)
2309 goto unlock;
2310
2311 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2312 goto unlock;
2313
2314 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2315 /*
2316 * Check if the vector that needs to be cleanedup is
2317 * registered at the cpu's IRR. If so, then this is not
2318 * the best time to clean it up. Lets clean it up in the
2319 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2320 * to myself.
2321 */
2322 if (irr & (1 << (vector % 32))) {
2323 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2324 goto unlock;
2325 }
2326 __this_cpu_write(vector_irq[vector], -1);
2327unlock:
2328 raw_spin_unlock(&desc->lock);
2329 }
2330
2331 irq_exit();
2332}
2333
2334static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2335{
2336 unsigned me;
2337
2338 if (likely(!cfg->move_in_progress))
2339 return;
2340
2341 me = smp_processor_id();
2342
2343 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2344 send_cleanup_vector(cfg);
2345}
2346
2347static void irq_complete_move(struct irq_cfg *cfg)
2348{
2349 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2350}
2351
2352void irq_force_complete_move(int irq)
2353{
2354 struct irq_cfg *cfg = irq_get_chip_data(irq);
2355
2356 if (!cfg)
2357 return;
2358
2359 __irq_complete_move(cfg, cfg->vector);
2360}
2361#else
2362static inline void irq_complete_move(struct irq_cfg *cfg) { }
2363#endif
2364
2365static void ack_apic_edge(struct irq_data *data)
2366{
2367 irq_complete_move(data->chip_data);
2368 irq_move_irq(data);
2369 ack_APIC_irq();
2370}
2371
2372atomic_t irq_mis_count;
2373
2374#ifdef CONFIG_GENERIC_PENDING_IRQ
2375static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2376{
2377 struct irq_pin_list *entry;
2378 unsigned long flags;
2379
2380 raw_spin_lock_irqsave(&ioapic_lock, flags);
2381 for_each_irq_pin(entry, cfg->irq_2_pin) {
2382 unsigned int reg;
2383 int pin;
2384
2385 pin = entry->pin;
2386 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2387 /* Is the remote IRR bit set? */
2388 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2389 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2390 return true;
2391 }
2392 }
2393 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2394
2395 return false;
2396}
2397
2398static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2399{
2400 /* If we are moving the irq we need to mask it */
2401 if (unlikely(irqd_is_setaffinity_pending(data))) {
2402 mask_ioapic(cfg);
2403 return true;
2404 }
2405 return false;
2406}
2407
2408static inline void ioapic_irqd_unmask(struct irq_data *data,
2409 struct irq_cfg *cfg, bool masked)
2410{
2411 if (unlikely(masked)) {
2412 /* Only migrate the irq if the ack has been received.
2413 *
2414 * On rare occasions the broadcast level triggered ack gets
2415 * delayed going to ioapics, and if we reprogram the
2416 * vector while Remote IRR is still set the irq will never
2417 * fire again.
2418 *
2419 * To prevent this scenario we read the Remote IRR bit
2420 * of the ioapic. This has two effects.
2421 * - On any sane system the read of the ioapic will
2422 * flush writes (and acks) going to the ioapic from
2423 * this cpu.
2424 * - We get to see if the ACK has actually been delivered.
2425 *
2426 * Based on failed experiments of reprogramming the
2427 * ioapic entry from outside of irq context starting
2428 * with masking the ioapic entry and then polling until
2429 * Remote IRR was clear before reprogramming the
2430 * ioapic I don't trust the Remote IRR bit to be
2431 * completey accurate.
2432 *
2433 * However there appears to be no other way to plug
2434 * this race, so if the Remote IRR bit is not
2435 * accurate and is causing problems then it is a hardware bug
2436 * and you can go talk to the chipset vendor about it.
2437 */
2438 if (!io_apic_level_ack_pending(cfg))
2439 irq_move_masked_irq(data);
2440 unmask_ioapic(cfg);
2441 }
2442}
2443#else
2444static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2445{
2446 return false;
2447}
2448static inline void ioapic_irqd_unmask(struct irq_data *data,
2449 struct irq_cfg *cfg, bool masked)
2450{
2451}
2452#endif
2453
2454static void ack_apic_level(struct irq_data *data)
2455{
2456 struct irq_cfg *cfg = data->chip_data;
2457 int i, irq = data->irq;
2458 unsigned long v;
2459 bool masked;
2460
2461 irq_complete_move(cfg);
2462 masked = ioapic_irqd_mask(data, cfg);
2463
2464 /*
2465 * It appears there is an erratum which affects at least version 0x11
2466 * of I/O APIC (that's the 82093AA and cores integrated into various
2467 * chipsets). Under certain conditions a level-triggered interrupt is
2468 * erroneously delivered as edge-triggered one but the respective IRR
2469 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2470 * message but it will never arrive and further interrupts are blocked
2471 * from the source. The exact reason is so far unknown, but the
2472 * phenomenon was observed when two consecutive interrupt requests
2473 * from a given source get delivered to the same CPU and the source is
2474 * temporarily disabled in between.
2475 *
2476 * A workaround is to simulate an EOI message manually. We achieve it
2477 * by setting the trigger mode to edge and then to level when the edge
2478 * trigger mode gets detected in the TMR of a local APIC for a
2479 * level-triggered interrupt. We mask the source for the time of the
2480 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2481 * The idea is from Manfred Spraul. --macro
2482 *
2483 * Also in the case when cpu goes offline, fixup_irqs() will forward
2484 * any unhandled interrupt on the offlined cpu to the new cpu
2485 * destination that is handling the corresponding interrupt. This
2486 * interrupt forwarding is done via IPI's. Hence, in this case also
2487 * level-triggered io-apic interrupt will be seen as an edge
2488 * interrupt in the IRR. And we can't rely on the cpu's EOI
2489 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2490 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2491 * supporting EOI register, we do an explicit EOI to clear the
2492 * remote IRR and on IO-APIC's which don't have an EOI register,
2493 * we use the above logic (mask+edge followed by unmask+level) from
2494 * Manfred Spraul to clear the remote IRR.
2495 */
2496 i = cfg->vector;
2497 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2498
2499 /*
2500 * We must acknowledge the irq before we move it or the acknowledge will
2501 * not propagate properly.
2502 */
2503 ack_APIC_irq();
2504
2505 /*
2506 * Tail end of clearing remote IRR bit (either by delivering the EOI
2507 * message via io-apic EOI register write or simulating it using
2508 * mask+edge followed by unnask+level logic) manually when the
2509 * level triggered interrupt is seen as the edge triggered interrupt
2510 * at the cpu.
2511 */
2512 if (!(v & (1 << (i & 0x1f)))) {
2513 atomic_inc(&irq_mis_count);
2514
2515 eoi_ioapic_irq(irq, cfg);
2516 }
2517
2518 ioapic_irqd_unmask(data, cfg, masked);
2519}
2520
2521#ifdef CONFIG_IRQ_REMAP
2522static void ir_ack_apic_edge(struct irq_data *data)
2523{
2524 ack_APIC_irq();
2525}
2526
2527static void ir_ack_apic_level(struct irq_data *data)
2528{
2529 ack_APIC_irq();
2530 eoi_ioapic_irq(data->irq, data->chip_data);
2531}
2532
2533static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2534{
2535 seq_printf(p, " IR-%s", data->chip->name);
2536}
2537
2538static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2539{
2540 chip->irq_print_chip = ir_print_prefix;
2541 chip->irq_ack = ir_ack_apic_edge;
2542 chip->irq_eoi = ir_ack_apic_level;
2543
2544#ifdef CONFIG_SMP
2545 chip->irq_set_affinity = set_remapped_irq_affinity;
2546#endif
2547}
2548#endif /* CONFIG_IRQ_REMAP */
2549
2550static struct irq_chip ioapic_chip __read_mostly = {
2551 .name = "IO-APIC",
2552 .irq_startup = startup_ioapic_irq,
2553 .irq_mask = mask_ioapic_irq,
2554 .irq_unmask = unmask_ioapic_irq,
2555 .irq_ack = ack_apic_edge,
2556 .irq_eoi = ack_apic_level,
2557#ifdef CONFIG_SMP
2558 .irq_set_affinity = ioapic_set_affinity,
2559#endif
2560 .irq_retrigger = ioapic_retrigger_irq,
2561};
2562
2563static inline void init_IO_APIC_traps(void)
2564{
2565 struct irq_cfg *cfg;
2566 unsigned int irq;
2567
2568 /*
2569 * NOTE! The local APIC isn't very good at handling
2570 * multiple interrupts at the same interrupt level.
2571 * As the interrupt level is determined by taking the
2572 * vector number and shifting that right by 4, we
2573 * want to spread these out a bit so that they don't
2574 * all fall in the same interrupt level.
2575 *
2576 * Also, we've got to be careful not to trash gate
2577 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2578 */
2579 for_each_active_irq(irq) {
2580 cfg = irq_get_chip_data(irq);
2581 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2582 /*
2583 * Hmm.. We don't have an entry for this,
2584 * so default to an old-fashioned 8259
2585 * interrupt if we can..
2586 */
2587 if (irq < legacy_pic->nr_legacy_irqs)
2588 legacy_pic->make_irq(irq);
2589 else
2590 /* Strange. Oh, well.. */
2591 irq_set_chip(irq, &no_irq_chip);
2592 }
2593 }
2594}
2595
2596/*
2597 * The local APIC irq-chip implementation:
2598 */
2599
2600static void mask_lapic_irq(struct irq_data *data)
2601{
2602 unsigned long v;
2603
2604 v = apic_read(APIC_LVT0);
2605 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2606}
2607
2608static void unmask_lapic_irq(struct irq_data *data)
2609{
2610 unsigned long v;
2611
2612 v = apic_read(APIC_LVT0);
2613 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2614}
2615
2616static void ack_lapic_irq(struct irq_data *data)
2617{
2618 ack_APIC_irq();
2619}
2620
2621static struct irq_chip lapic_chip __read_mostly = {
2622 .name = "local-APIC",
2623 .irq_mask = mask_lapic_irq,
2624 .irq_unmask = unmask_lapic_irq,
2625 .irq_ack = ack_lapic_irq,
2626};
2627
2628static void lapic_register_intr(int irq)
2629{
2630 irq_clear_status_flags(irq, IRQ_LEVEL);
2631 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2632 "edge");
2633}
2634
2635/*
2636 * This looks a bit hackish but it's about the only one way of sending
2637 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2638 * not support the ExtINT mode, unfortunately. We need to send these
2639 * cycles as some i82489DX-based boards have glue logic that keeps the
2640 * 8259A interrupt line asserted until INTA. --macro
2641 */
2642static inline void __init unlock_ExtINT_logic(void)
2643{
2644 int apic, pin, i;
2645 struct IO_APIC_route_entry entry0, entry1;
2646 unsigned char save_control, save_freq_select;
2647
2648 pin = find_isa_irq_pin(8, mp_INT);
2649 if (pin == -1) {
2650 WARN_ON_ONCE(1);
2651 return;
2652 }
2653 apic = find_isa_irq_apic(8, mp_INT);
2654 if (apic == -1) {
2655 WARN_ON_ONCE(1);
2656 return;
2657 }
2658
2659 entry0 = ioapic_read_entry(apic, pin);
2660 clear_IO_APIC_pin(apic, pin);
2661
2662 memset(&entry1, 0, sizeof(entry1));
2663
2664 entry1.dest_mode = 0; /* physical delivery */
2665 entry1.mask = 0; /* unmask IRQ now */
2666 entry1.dest = hard_smp_processor_id();
2667 entry1.delivery_mode = dest_ExtINT;
2668 entry1.polarity = entry0.polarity;
2669 entry1.trigger = 0;
2670 entry1.vector = 0;
2671
2672 ioapic_write_entry(apic, pin, entry1);
2673
2674 save_control = CMOS_READ(RTC_CONTROL);
2675 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2676 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2677 RTC_FREQ_SELECT);
2678 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2679
2680 i = 100;
2681 while (i-- > 0) {
2682 mdelay(10);
2683 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2684 i -= 10;
2685 }
2686
2687 CMOS_WRITE(save_control, RTC_CONTROL);
2688 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2689 clear_IO_APIC_pin(apic, pin);
2690
2691 ioapic_write_entry(apic, pin, entry0);
2692}
2693
2694static int disable_timer_pin_1 __initdata;
2695/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2696static int __init disable_timer_pin_setup(char *arg)
2697{
2698 disable_timer_pin_1 = 1;
2699 return 0;
2700}
2701early_param("disable_timer_pin_1", disable_timer_pin_setup);
2702
2703int timer_through_8259 __initdata;
2704
2705/*
2706 * This code may look a bit paranoid, but it's supposed to cooperate with
2707 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2708 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2709 * fanatically on his truly buggy board.
2710 *
2711 * FIXME: really need to revamp this for all platforms.
2712 */
2713static inline void __init check_timer(void)
2714{
2715 struct irq_cfg *cfg = irq_get_chip_data(0);
2716 int node = cpu_to_node(0);
2717 int apic1, pin1, apic2, pin2;
2718 unsigned long flags;
2719 int no_pin1 = 0;
2720
2721 local_irq_save(flags);
2722
2723 /*
2724 * get/set the timer IRQ vector:
2725 */
2726 legacy_pic->mask(0);
2727 assign_irq_vector(0, cfg, apic->target_cpus());
2728
2729 /*
2730 * As IRQ0 is to be enabled in the 8259A, the virtual
2731 * wire has to be disabled in the local APIC. Also
2732 * timer interrupts need to be acknowledged manually in
2733 * the 8259A for the i82489DX when using the NMI
2734 * watchdog as that APIC treats NMIs as level-triggered.
2735 * The AEOI mode will finish them in the 8259A
2736 * automatically.
2737 */
2738 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2739 legacy_pic->init(1);
2740
2741 pin1 = find_isa_irq_pin(0, mp_INT);
2742 apic1 = find_isa_irq_apic(0, mp_INT);
2743 pin2 = ioapic_i8259.pin;
2744 apic2 = ioapic_i8259.apic;
2745
2746 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2747 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2748 cfg->vector, apic1, pin1, apic2, pin2);
2749
2750 /*
2751 * Some BIOS writers are clueless and report the ExtINTA
2752 * I/O APIC input from the cascaded 8259A as the timer
2753 * interrupt input. So just in case, if only one pin
2754 * was found above, try it both directly and through the
2755 * 8259A.
2756 */
2757 if (pin1 == -1) {
2758 if (irq_remapping_enabled)
2759 panic("BIOS bug: timer not connected to IO-APIC");
2760 pin1 = pin2;
2761 apic1 = apic2;
2762 no_pin1 = 1;
2763 } else if (pin2 == -1) {
2764 pin2 = pin1;
2765 apic2 = apic1;
2766 }
2767
2768 if (pin1 != -1) {
2769 /*
2770 * Ok, does IRQ0 through the IOAPIC work?
2771 */
2772 if (no_pin1) {
2773 add_pin_to_irq_node(cfg, node, apic1, pin1);
2774 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2775 } else {
2776 /* for edge trigger, setup_ioapic_irq already
2777 * leave it unmasked.
2778 * so only need to unmask if it is level-trigger
2779 * do we really have level trigger timer?
2780 */
2781 int idx;
2782 idx = find_irq_entry(apic1, pin1, mp_INT);
2783 if (idx != -1 && irq_trigger(idx))
2784 unmask_ioapic(cfg);
2785 }
2786 if (timer_irq_works()) {
2787 if (disable_timer_pin_1 > 0)
2788 clear_IO_APIC_pin(0, pin1);
2789 goto out;
2790 }
2791 if (irq_remapping_enabled)
2792 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2793 local_irq_disable();
2794 clear_IO_APIC_pin(apic1, pin1);
2795 if (!no_pin1)
2796 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2797 "8254 timer not connected to IO-APIC\n");
2798
2799 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2800 "(IRQ0) through the 8259A ...\n");
2801 apic_printk(APIC_QUIET, KERN_INFO
2802 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2803 /*
2804 * legacy devices should be connected to IO APIC #0
2805 */
2806 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2807 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2808 legacy_pic->unmask(0);
2809 if (timer_irq_works()) {
2810 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2811 timer_through_8259 = 1;
2812 goto out;
2813 }
2814 /*
2815 * Cleanup, just in case ...
2816 */
2817 local_irq_disable();
2818 legacy_pic->mask(0);
2819 clear_IO_APIC_pin(apic2, pin2);
2820 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2821 }
2822
2823 apic_printk(APIC_QUIET, KERN_INFO
2824 "...trying to set up timer as Virtual Wire IRQ...\n");
2825
2826 lapic_register_intr(0);
2827 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2828 legacy_pic->unmask(0);
2829
2830 if (timer_irq_works()) {
2831 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2832 goto out;
2833 }
2834 local_irq_disable();
2835 legacy_pic->mask(0);
2836 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2837 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2838
2839 apic_printk(APIC_QUIET, KERN_INFO
2840 "...trying to set up timer as ExtINT IRQ...\n");
2841
2842 legacy_pic->init(0);
2843 legacy_pic->make_irq(0);
2844 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2845
2846 unlock_ExtINT_logic();
2847
2848 if (timer_irq_works()) {
2849 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2850 goto out;
2851 }
2852 local_irq_disable();
2853 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2854 if (x2apic_preenabled)
2855 apic_printk(APIC_QUIET, KERN_INFO
2856 "Perhaps problem with the pre-enabled x2apic mode\n"
2857 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2858 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2859 "report. Then try booting with the 'noapic' option.\n");
2860out:
2861 local_irq_restore(flags);
2862}
2863
2864/*
2865 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2866 * to devices. However there may be an I/O APIC pin available for
2867 * this interrupt regardless. The pin may be left unconnected, but
2868 * typically it will be reused as an ExtINT cascade interrupt for
2869 * the master 8259A. In the MPS case such a pin will normally be
2870 * reported as an ExtINT interrupt in the MP table. With ACPI
2871 * there is no provision for ExtINT interrupts, and in the absence
2872 * of an override it would be treated as an ordinary ISA I/O APIC
2873 * interrupt, that is edge-triggered and unmasked by default. We
2874 * used to do this, but it caused problems on some systems because
2875 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2876 * the same ExtINT cascade interrupt to drive the local APIC of the
2877 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2878 * the I/O APIC in all cases now. No actual device should request
2879 * it anyway. --macro
2880 */
2881#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2882
2883void __init setup_IO_APIC(void)
2884{
2885
2886 /*
2887 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2888 */
2889 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2890
2891 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2892 /*
2893 * Set up IO-APIC IRQ routing.
2894 */
2895 x86_init.mpparse.setup_ioapic_ids();
2896
2897 sync_Arb_IDs();
2898 setup_IO_APIC_irqs();
2899 init_IO_APIC_traps();
2900 if (legacy_pic->nr_legacy_irqs)
2901 check_timer();
2902}
2903
2904/*
2905 * Called after all the initialization is done. If we didn't find any
2906 * APIC bugs then we can allow the modify fast path
2907 */
2908
2909static int __init io_apic_bug_finalize(void)
2910{
2911 if (sis_apic_bug == -1)
2912 sis_apic_bug = 0;
2913 return 0;
2914}
2915
2916late_initcall(io_apic_bug_finalize);
2917
2918static void resume_ioapic_id(int ioapic_idx)
2919{
2920 unsigned long flags;
2921 union IO_APIC_reg_00 reg_00;
2922
2923 raw_spin_lock_irqsave(&ioapic_lock, flags);
2924 reg_00.raw = io_apic_read(ioapic_idx, 0);
2925 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2926 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2927 io_apic_write(ioapic_idx, 0, reg_00.raw);
2928 }
2929 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2930}
2931
2932static void ioapic_resume(void)
2933{
2934 int ioapic_idx;
2935
2936 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2937 resume_ioapic_id(ioapic_idx);
2938
2939 restore_ioapic_entries();
2940}
2941
2942static struct syscore_ops ioapic_syscore_ops = {
2943 .suspend = save_ioapic_entries,
2944 .resume = ioapic_resume,
2945};
2946
2947static int __init ioapic_init_ops(void)
2948{
2949 register_syscore_ops(&ioapic_syscore_ops);
2950
2951 return 0;
2952}
2953
2954device_initcall(ioapic_init_ops);
2955
2956/*
2957 * Dynamic irq allocate and deallocation
2958 */
2959unsigned int create_irq_nr(unsigned int from, int node)
2960{
2961 struct irq_cfg *cfg;
2962 unsigned long flags;
2963 unsigned int ret = 0;
2964 int irq;
2965
2966 if (from < nr_irqs_gsi)
2967 from = nr_irqs_gsi;
2968
2969 irq = alloc_irq_from(from, node);
2970 if (irq < 0)
2971 return 0;
2972 cfg = alloc_irq_cfg(irq, node);
2973 if (!cfg) {
2974 free_irq_at(irq, NULL);
2975 return 0;
2976 }
2977
2978 raw_spin_lock_irqsave(&vector_lock, flags);
2979 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
2980 ret = irq;
2981 raw_spin_unlock_irqrestore(&vector_lock, flags);
2982
2983 if (ret) {
2984 irq_set_chip_data(irq, cfg);
2985 irq_clear_status_flags(irq, IRQ_NOREQUEST);
2986 } else {
2987 free_irq_at(irq, cfg);
2988 }
2989 return ret;
2990}
2991
2992int create_irq(void)
2993{
2994 int node = cpu_to_node(0);
2995 unsigned int irq_want;
2996 int irq;
2997
2998 irq_want = nr_irqs_gsi;
2999 irq = create_irq_nr(irq_want, node);
3000
3001 if (irq == 0)
3002 irq = -1;
3003
3004 return irq;
3005}
3006
3007void destroy_irq(unsigned int irq)
3008{
3009 struct irq_cfg *cfg = irq_get_chip_data(irq);
3010 unsigned long flags;
3011
3012 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3013
3014 if (irq_remapped(cfg))
3015 free_remapped_irq(irq);
3016 raw_spin_lock_irqsave(&vector_lock, flags);
3017 __clear_irq_vector(irq, cfg);
3018 raw_spin_unlock_irqrestore(&vector_lock, flags);
3019 free_irq_at(irq, cfg);
3020}
3021
3022/*
3023 * MSI message composition
3024 */
3025#ifdef CONFIG_PCI_MSI
3026static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3027 struct msi_msg *msg, u8 hpet_id)
3028{
3029 struct irq_cfg *cfg;
3030 int err;
3031 unsigned dest;
3032
3033 if (disable_apic)
3034 return -ENXIO;
3035
3036 cfg = irq_cfg(irq);
3037 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3038 if (err)
3039 return err;
3040
3041 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3042
3043 if (irq_remapped(cfg)) {
3044 compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
3045 return err;
3046 }
3047
3048 if (x2apic_enabled())
3049 msg->address_hi = MSI_ADDR_BASE_HI |
3050 MSI_ADDR_EXT_DEST_ID(dest);
3051 else
3052 msg->address_hi = MSI_ADDR_BASE_HI;
3053
3054 msg->address_lo =
3055 MSI_ADDR_BASE_LO |
3056 ((apic->irq_dest_mode == 0) ?
3057 MSI_ADDR_DEST_MODE_PHYSICAL:
3058 MSI_ADDR_DEST_MODE_LOGICAL) |
3059 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3060 MSI_ADDR_REDIRECTION_CPU:
3061 MSI_ADDR_REDIRECTION_LOWPRI) |
3062 MSI_ADDR_DEST_ID(dest);
3063
3064 msg->data =
3065 MSI_DATA_TRIGGER_EDGE |
3066 MSI_DATA_LEVEL_ASSERT |
3067 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3068 MSI_DATA_DELIVERY_FIXED:
3069 MSI_DATA_DELIVERY_LOWPRI) |
3070 MSI_DATA_VECTOR(cfg->vector);
3071
3072 return err;
3073}
3074
3075#ifdef CONFIG_SMP
3076static int
3077msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3078{
3079 struct irq_cfg *cfg = data->chip_data;
3080 struct msi_msg msg;
3081 unsigned int dest;
3082
3083 if (__ioapic_set_affinity(data, mask, &dest))
3084 return -1;
3085
3086 __get_cached_msi_msg(data->msi_desc, &msg);
3087
3088 msg.data &= ~MSI_DATA_VECTOR_MASK;
3089 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3090 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3091 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3092
3093 __write_msi_msg(data->msi_desc, &msg);
3094
3095 return 0;
3096}
3097#endif /* CONFIG_SMP */
3098
3099/*
3100 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3101 * which implement the MSI or MSI-X Capability Structure.
3102 */
3103static struct irq_chip msi_chip = {
3104 .name = "PCI-MSI",
3105 .irq_unmask = unmask_msi_irq,
3106 .irq_mask = mask_msi_irq,
3107 .irq_ack = ack_apic_edge,
3108#ifdef CONFIG_SMP
3109 .irq_set_affinity = msi_set_affinity,
3110#endif
3111 .irq_retrigger = ioapic_retrigger_irq,
3112};
3113
3114static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3115{
3116 struct irq_chip *chip = &msi_chip;
3117 struct msi_msg msg;
3118 int ret;
3119
3120 ret = msi_compose_msg(dev, irq, &msg, -1);
3121 if (ret < 0)
3122 return ret;
3123
3124 irq_set_msi_desc(irq, msidesc);
3125 write_msi_msg(irq, &msg);
3126
3127 if (irq_remapped(irq_get_chip_data(irq))) {
3128 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3129 irq_remap_modify_chip_defaults(chip);
3130 }
3131
3132 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3133
3134 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3135
3136 return 0;
3137}
3138
3139int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3140{
3141 int node, ret, sub_handle, index = 0;
3142 unsigned int irq, irq_want;
3143 struct msi_desc *msidesc;
3144
3145 /* x86 doesn't support multiple MSI yet */
3146 if (type == PCI_CAP_ID_MSI && nvec > 1)
3147 return 1;
3148
3149 node = dev_to_node(&dev->dev);
3150 irq_want = nr_irqs_gsi;
3151 sub_handle = 0;
3152 list_for_each_entry(msidesc, &dev->msi_list, list) {
3153 irq = create_irq_nr(irq_want, node);
3154 if (irq == 0)
3155 return -1;
3156 irq_want = irq + 1;
3157 if (!irq_remapping_enabled)
3158 goto no_ir;
3159
3160 if (!sub_handle) {
3161 /*
3162 * allocate the consecutive block of IRTE's
3163 * for 'nvec'
3164 */
3165 index = msi_alloc_remapped_irq(dev, irq, nvec);
3166 if (index < 0) {
3167 ret = index;
3168 goto error;
3169 }
3170 } else {
3171 ret = msi_setup_remapped_irq(dev, irq, index,
3172 sub_handle);
3173 if (ret < 0)
3174 goto error;
3175 }
3176no_ir:
3177 ret = setup_msi_irq(dev, msidesc, irq);
3178 if (ret < 0)
3179 goto error;
3180 sub_handle++;
3181 }
3182 return 0;
3183
3184error:
3185 destroy_irq(irq);
3186 return ret;
3187}
3188
3189void native_teardown_msi_irq(unsigned int irq)
3190{
3191 destroy_irq(irq);
3192}
3193
3194#ifdef CONFIG_DMAR_TABLE
3195#ifdef CONFIG_SMP
3196static int
3197dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3198 bool force)
3199{
3200 struct irq_cfg *cfg = data->chip_data;
3201 unsigned int dest, irq = data->irq;
3202 struct msi_msg msg;
3203
3204 if (__ioapic_set_affinity(data, mask, &dest))
3205 return -1;
3206
3207 dmar_msi_read(irq, &msg);
3208
3209 msg.data &= ~MSI_DATA_VECTOR_MASK;
3210 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3211 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3212 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3213 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3214
3215 dmar_msi_write(irq, &msg);
3216
3217 return 0;
3218}
3219
3220#endif /* CONFIG_SMP */
3221
3222static struct irq_chip dmar_msi_type = {
3223 .name = "DMAR_MSI",
3224 .irq_unmask = dmar_msi_unmask,
3225 .irq_mask = dmar_msi_mask,
3226 .irq_ack = ack_apic_edge,
3227#ifdef CONFIG_SMP
3228 .irq_set_affinity = dmar_msi_set_affinity,
3229#endif
3230 .irq_retrigger = ioapic_retrigger_irq,
3231};
3232
3233int arch_setup_dmar_msi(unsigned int irq)
3234{
3235 int ret;
3236 struct msi_msg msg;
3237
3238 ret = msi_compose_msg(NULL, irq, &msg, -1);
3239 if (ret < 0)
3240 return ret;
3241 dmar_msi_write(irq, &msg);
3242 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3243 "edge");
3244 return 0;
3245}
3246#endif
3247
3248#ifdef CONFIG_HPET_TIMER
3249
3250#ifdef CONFIG_SMP
3251static int hpet_msi_set_affinity(struct irq_data *data,
3252 const struct cpumask *mask, bool force)
3253{
3254 struct irq_cfg *cfg = data->chip_data;
3255 struct msi_msg msg;
3256 unsigned int dest;
3257
3258 if (__ioapic_set_affinity(data, mask, &dest))
3259 return -1;
3260
3261 hpet_msi_read(data->handler_data, &msg);
3262
3263 msg.data &= ~MSI_DATA_VECTOR_MASK;
3264 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3265 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3266 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3267
3268 hpet_msi_write(data->handler_data, &msg);
3269
3270 return 0;
3271}
3272
3273#endif /* CONFIG_SMP */
3274
3275static struct irq_chip hpet_msi_type = {
3276 .name = "HPET_MSI",
3277 .irq_unmask = hpet_msi_unmask,
3278 .irq_mask = hpet_msi_mask,
3279 .irq_ack = ack_apic_edge,
3280#ifdef CONFIG_SMP
3281 .irq_set_affinity = hpet_msi_set_affinity,
3282#endif
3283 .irq_retrigger = ioapic_retrigger_irq,
3284};
3285
3286int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3287{
3288 struct irq_chip *chip = &hpet_msi_type;
3289 struct msi_msg msg;
3290 int ret;
3291
3292 if (irq_remapping_enabled) {
3293 if (!setup_hpet_msi_remapped(irq, id))
3294 return -1;
3295 }
3296
3297 ret = msi_compose_msg(NULL, irq, &msg, id);
3298 if (ret < 0)
3299 return ret;
3300
3301 hpet_msi_write(irq_get_handler_data(irq), &msg);
3302 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3303 if (irq_remapped(irq_get_chip_data(irq)))
3304 irq_remap_modify_chip_defaults(chip);
3305
3306 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3307 return 0;
3308}
3309#endif
3310
3311#endif /* CONFIG_PCI_MSI */
3312/*
3313 * Hypertransport interrupt support
3314 */
3315#ifdef CONFIG_HT_IRQ
3316
3317#ifdef CONFIG_SMP
3318
3319static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3320{
3321 struct ht_irq_msg msg;
3322 fetch_ht_irq_msg(irq, &msg);
3323
3324 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3325 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3326
3327 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3328 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3329
3330 write_ht_irq_msg(irq, &msg);
3331}
3332
3333static int
3334ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3335{
3336 struct irq_cfg *cfg = data->chip_data;
3337 unsigned int dest;
3338
3339 if (__ioapic_set_affinity(data, mask, &dest))
3340 return -1;
3341
3342 target_ht_irq(data->irq, dest, cfg->vector);
3343 return 0;
3344}
3345
3346#endif
3347
3348static struct irq_chip ht_irq_chip = {
3349 .name = "PCI-HT",
3350 .irq_mask = mask_ht_irq,
3351 .irq_unmask = unmask_ht_irq,
3352 .irq_ack = ack_apic_edge,
3353#ifdef CONFIG_SMP
3354 .irq_set_affinity = ht_set_affinity,
3355#endif
3356 .irq_retrigger = ioapic_retrigger_irq,
3357};
3358
3359int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3360{
3361 struct irq_cfg *cfg;
3362 int err;
3363
3364 if (disable_apic)
3365 return -ENXIO;
3366
3367 cfg = irq_cfg(irq);
3368 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3369 if (!err) {
3370 struct ht_irq_msg msg;
3371 unsigned dest;
3372
3373 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3374 apic->target_cpus());
3375
3376 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3377
3378 msg.address_lo =
3379 HT_IRQ_LOW_BASE |
3380 HT_IRQ_LOW_DEST_ID(dest) |
3381 HT_IRQ_LOW_VECTOR(cfg->vector) |
3382 ((apic->irq_dest_mode == 0) ?
3383 HT_IRQ_LOW_DM_PHYSICAL :
3384 HT_IRQ_LOW_DM_LOGICAL) |
3385 HT_IRQ_LOW_RQEOI_EDGE |
3386 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3387 HT_IRQ_LOW_MT_FIXED :
3388 HT_IRQ_LOW_MT_ARBITRATED) |
3389 HT_IRQ_LOW_IRQ_MASKED;
3390
3391 write_ht_irq_msg(irq, &msg);
3392
3393 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3394 handle_edge_irq, "edge");
3395
3396 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3397 }
3398 return err;
3399}
3400#endif /* CONFIG_HT_IRQ */
3401
3402static int
3403io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3404{
3405 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3406 int ret;
3407
3408 if (!cfg)
3409 return -EINVAL;
3410 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3411 if (!ret)
3412 setup_ioapic_irq(irq, cfg, attr);
3413 return ret;
3414}
3415
3416int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3417 struct io_apic_irq_attr *attr)
3418{
3419 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3420 int ret;
3421
3422 /* Avoid redundant programming */
3423 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3424 pr_debug("Pin %d-%d already programmed\n",
3425 mpc_ioapic_id(ioapic_idx), pin);
3426 return 0;
3427 }
3428 ret = io_apic_setup_irq_pin(irq, node, attr);
3429 if (!ret)
3430 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3431 return ret;
3432}
3433
3434static int __init io_apic_get_redir_entries(int ioapic)
3435{
3436 union IO_APIC_reg_01 reg_01;
3437 unsigned long flags;
3438
3439 raw_spin_lock_irqsave(&ioapic_lock, flags);
3440 reg_01.raw = io_apic_read(ioapic, 1);
3441 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3442
3443 /* The register returns the maximum index redir index
3444 * supported, which is one less than the total number of redir
3445 * entries.
3446 */
3447 return reg_01.bits.entries + 1;
3448}
3449
3450static void __init probe_nr_irqs_gsi(void)
3451{
3452 int nr;
3453
3454 nr = gsi_top + NR_IRQS_LEGACY;
3455 if (nr > nr_irqs_gsi)
3456 nr_irqs_gsi = nr;
3457
3458 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3459}
3460
3461int get_nr_irqs_gsi(void)
3462{
3463 return nr_irqs_gsi;
3464}
3465
3466int __init arch_probe_nr_irqs(void)
3467{
3468 int nr;
3469
3470 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3471 nr_irqs = NR_VECTORS * nr_cpu_ids;
3472
3473 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3474#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3475 /*
3476 * for MSI and HT dyn irq
3477 */
3478 nr += nr_irqs_gsi * 16;
3479#endif
3480 if (nr < nr_irqs)
3481 nr_irqs = nr;
3482
3483 return NR_IRQS_LEGACY;
3484}
3485
3486int io_apic_set_pci_routing(struct device *dev, int irq,
3487 struct io_apic_irq_attr *irq_attr)
3488{
3489 int node;
3490
3491 if (!IO_APIC_IRQ(irq)) {
3492 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3493 irq_attr->ioapic);
3494 return -EINVAL;
3495 }
3496
3497 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3498
3499 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3500}
3501
3502#ifdef CONFIG_X86_32
3503static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3504{
3505 union IO_APIC_reg_00 reg_00;
3506 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3507 physid_mask_t tmp;
3508 unsigned long flags;
3509 int i = 0;
3510
3511 /*
3512 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3513 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3514 * supports up to 16 on one shared APIC bus.
3515 *
3516 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3517 * advantage of new APIC bus architecture.
3518 */
3519
3520 if (physids_empty(apic_id_map))
3521 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3522
3523 raw_spin_lock_irqsave(&ioapic_lock, flags);
3524 reg_00.raw = io_apic_read(ioapic, 0);
3525 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3526
3527 if (apic_id >= get_physical_broadcast()) {
3528 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3529 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3530 apic_id = reg_00.bits.ID;
3531 }
3532
3533 /*
3534 * Every APIC in a system must have a unique ID or we get lots of nice
3535 * 'stuck on smp_invalidate_needed IPI wait' messages.
3536 */
3537 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3538
3539 for (i = 0; i < get_physical_broadcast(); i++) {
3540 if (!apic->check_apicid_used(&apic_id_map, i))
3541 break;
3542 }
3543
3544 if (i == get_physical_broadcast())
3545 panic("Max apic_id exceeded!\n");
3546
3547 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3548 "trying %d\n", ioapic, apic_id, i);
3549
3550 apic_id = i;
3551 }
3552
3553 apic->apicid_to_cpu_present(apic_id, &tmp);
3554 physids_or(apic_id_map, apic_id_map, tmp);
3555
3556 if (reg_00.bits.ID != apic_id) {
3557 reg_00.bits.ID = apic_id;
3558
3559 raw_spin_lock_irqsave(&ioapic_lock, flags);
3560 io_apic_write(ioapic, 0, reg_00.raw);
3561 reg_00.raw = io_apic_read(ioapic, 0);
3562 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3563
3564 /* Sanity check */
3565 if (reg_00.bits.ID != apic_id) {
3566 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3567 return -1;
3568 }
3569 }
3570
3571 apic_printk(APIC_VERBOSE, KERN_INFO
3572 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3573
3574 return apic_id;
3575}
3576
3577static u8 __init io_apic_unique_id(u8 id)
3578{
3579 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3580 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3581 return io_apic_get_unique_id(nr_ioapics, id);
3582 else
3583 return id;
3584}
3585#else
3586static u8 __init io_apic_unique_id(u8 id)
3587{
3588 int i;
3589 DECLARE_BITMAP(used, 256);
3590
3591 bitmap_zero(used, 256);
3592 for (i = 0; i < nr_ioapics; i++) {
3593 __set_bit(mpc_ioapic_id(i), used);
3594 }
3595 if (!test_bit(id, used))
3596 return id;
3597 return find_first_zero_bit(used, 256);
3598}
3599#endif
3600
3601static int __init io_apic_get_version(int ioapic)
3602{
3603 union IO_APIC_reg_01 reg_01;
3604 unsigned long flags;
3605
3606 raw_spin_lock_irqsave(&ioapic_lock, flags);
3607 reg_01.raw = io_apic_read(ioapic, 1);
3608 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3609
3610 return reg_01.bits.version;
3611}
3612
3613int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3614{
3615 int ioapic, pin, idx;
3616
3617 if (skip_ioapic_setup)
3618 return -1;
3619
3620 ioapic = mp_find_ioapic(gsi);
3621 if (ioapic < 0)
3622 return -1;
3623
3624 pin = mp_find_ioapic_pin(ioapic, gsi);
3625 if (pin < 0)
3626 return -1;
3627
3628 idx = find_irq_entry(ioapic, pin, mp_INT);
3629 if (idx < 0)
3630 return -1;
3631
3632 *trigger = irq_trigger(idx);
3633 *polarity = irq_polarity(idx);
3634 return 0;
3635}
3636
3637/*
3638 * This function currently is only a helper for the i386 smp boot process where
3639 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3640 * so mask in all cases should simply be apic->target_cpus()
3641 */
3642#ifdef CONFIG_SMP
3643void __init setup_ioapic_dest(void)
3644{
3645 int pin, ioapic, irq, irq_entry;
3646 const struct cpumask *mask;
3647 struct irq_data *idata;
3648
3649 if (skip_ioapic_setup == 1)
3650 return;
3651
3652 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3653 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3654 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3655 if (irq_entry == -1)
3656 continue;
3657 irq = pin_2_irq(irq_entry, ioapic, pin);
3658
3659 if ((ioapic > 0) && (irq > 16))
3660 continue;
3661
3662 idata = irq_get_irq_data(irq);
3663
3664 /*
3665 * Honour affinities which have been set in early boot
3666 */
3667 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3668 mask = idata->affinity;
3669 else
3670 mask = apic->target_cpus();
3671
3672 if (irq_remapping_enabled)
3673 set_remapped_irq_affinity(idata, mask, false);
3674 else
3675 ioapic_set_affinity(idata, mask, false);
3676 }
3677
3678}
3679#endif
3680
3681#define IOAPIC_RESOURCE_NAME_SIZE 11
3682
3683static struct resource *ioapic_resources;
3684
3685static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3686{
3687 unsigned long n;
3688 struct resource *res;
3689 char *mem;
3690 int i;
3691
3692 if (nr_ioapics <= 0)
3693 return NULL;
3694
3695 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3696 n *= nr_ioapics;
3697
3698 mem = alloc_bootmem(n);
3699 res = (void *)mem;
3700
3701 mem += sizeof(struct resource) * nr_ioapics;
3702
3703 for (i = 0; i < nr_ioapics; i++) {
3704 res[i].name = mem;
3705 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3706 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3707 mem += IOAPIC_RESOURCE_NAME_SIZE;
3708 }
3709
3710 ioapic_resources = res;
3711
3712 return res;
3713}
3714
3715void __init native_io_apic_init_mappings(void)
3716{
3717 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3718 struct resource *ioapic_res;
3719 int i;
3720
3721 ioapic_res = ioapic_setup_resources(nr_ioapics);
3722 for (i = 0; i < nr_ioapics; i++) {
3723 if (smp_found_config) {
3724 ioapic_phys = mpc_ioapic_addr(i);
3725#ifdef CONFIG_X86_32
3726 if (!ioapic_phys) {
3727 printk(KERN_ERR
3728 "WARNING: bogus zero IO-APIC "
3729 "address found in MPTABLE, "
3730 "disabling IO/APIC support!\n");
3731 smp_found_config = 0;
3732 skip_ioapic_setup = 1;
3733 goto fake_ioapic_page;
3734 }
3735#endif
3736 } else {
3737#ifdef CONFIG_X86_32
3738fake_ioapic_page:
3739#endif
3740 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3741 ioapic_phys = __pa(ioapic_phys);
3742 }
3743 set_fixmap_nocache(idx, ioapic_phys);
3744 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3745 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3746 ioapic_phys);
3747 idx++;
3748
3749 ioapic_res->start = ioapic_phys;
3750 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3751 ioapic_res++;
3752 }
3753
3754 probe_nr_irqs_gsi();
3755}
3756
3757void __init ioapic_insert_resources(void)
3758{
3759 int i;
3760 struct resource *r = ioapic_resources;
3761
3762 if (!r) {
3763 if (nr_ioapics > 0)
3764 printk(KERN_ERR
3765 "IO APIC resources couldn't be allocated.\n");
3766 return;
3767 }
3768
3769 for (i = 0; i < nr_ioapics; i++) {
3770 insert_resource(&iomem_resource, r);
3771 r++;
3772 }
3773}
3774
3775int mp_find_ioapic(u32 gsi)
3776{
3777 int i = 0;
3778
3779 if (nr_ioapics == 0)
3780 return -1;
3781
3782 /* Find the IOAPIC that manages this GSI. */
3783 for (i = 0; i < nr_ioapics; i++) {
3784 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3785 if ((gsi >= gsi_cfg->gsi_base)
3786 && (gsi <= gsi_cfg->gsi_end))
3787 return i;
3788 }
3789
3790 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3791 return -1;
3792}
3793
3794int mp_find_ioapic_pin(int ioapic, u32 gsi)
3795{
3796 struct mp_ioapic_gsi *gsi_cfg;
3797
3798 if (WARN_ON(ioapic == -1))
3799 return -1;
3800
3801 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3802 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3803 return -1;
3804
3805 return gsi - gsi_cfg->gsi_base;
3806}
3807
3808static __init int bad_ioapic(unsigned long address)
3809{
3810 if (nr_ioapics >= MAX_IO_APICS) {
3811 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3812 MAX_IO_APICS, nr_ioapics);
3813 return 1;
3814 }
3815 if (!address) {
3816 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3817 return 1;
3818 }
3819 return 0;
3820}
3821
3822static __init int bad_ioapic_register(int idx)
3823{
3824 union IO_APIC_reg_00 reg_00;
3825 union IO_APIC_reg_01 reg_01;
3826 union IO_APIC_reg_02 reg_02;
3827
3828 reg_00.raw = io_apic_read(idx, 0);
3829 reg_01.raw = io_apic_read(idx, 1);
3830 reg_02.raw = io_apic_read(idx, 2);
3831
3832 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3833 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3834 mpc_ioapic_addr(idx));
3835 return 1;
3836 }
3837
3838 return 0;
3839}
3840
3841void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3842{
3843 int idx = 0;
3844 int entries;
3845 struct mp_ioapic_gsi *gsi_cfg;
3846
3847 if (bad_ioapic(address))
3848 return;
3849
3850 idx = nr_ioapics;
3851
3852 ioapics[idx].mp_config.type = MP_IOAPIC;
3853 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3854 ioapics[idx].mp_config.apicaddr = address;
3855
3856 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3857
3858 if (bad_ioapic_register(idx)) {
3859 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3860 return;
3861 }
3862
3863 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3864 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3865
3866 /*
3867 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3868 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3869 */
3870 entries = io_apic_get_redir_entries(idx);
3871 gsi_cfg = mp_ioapic_gsi_routing(idx);
3872 gsi_cfg->gsi_base = gsi_base;
3873 gsi_cfg->gsi_end = gsi_base + entries - 1;
3874
3875 /*
3876 * The number of IO-APIC IRQ registers (== #pins):
3877 */
3878 ioapics[idx].nr_registers = entries;
3879
3880 if (gsi_cfg->gsi_end >= gsi_top)
3881 gsi_top = gsi_cfg->gsi_end + 1;
3882
3883 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3884 idx, mpc_ioapic_id(idx),
3885 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3886 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3887
3888 nr_ioapics++;
3889}
3890
3891/* Enable IOAPIC early just for system timer */
3892void __init pre_init_apic_IRQ0(void)
3893{
3894 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3895
3896 printk(KERN_INFO "Early APIC setup for system timer0\n");
3897#ifndef CONFIG_SMP
3898 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3899 &phys_cpu_present_map);
3900#endif
3901 setup_local_APIC();
3902
3903 io_apic_setup_irq_pin(0, 0, &attr);
3904 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
3905 "edge");
3906}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51#include <linux/msi.h>
52
53#include <asm/irqdomain.h>
54#include <asm/io.h>
55#include <asm/smp.h>
56#include <asm/cpu.h>
57#include <asm/desc.h>
58#include <asm/proto.h>
59#include <asm/acpi.h>
60#include <asm/dma.h>
61#include <asm/timer.h>
62#include <asm/time.h>
63#include <asm/i8259.h>
64#include <asm/setup.h>
65#include <asm/irq_remapping.h>
66#include <asm/hw_irq.h>
67#include <asm/apic.h>
68#include <asm/pgtable.h>
69#include <asm/x86_init.h>
70
71#define for_each_ioapic(idx) \
72 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
73#define for_each_ioapic_reverse(idx) \
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75#define for_each_pin(idx, pin) \
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77#define for_each_ioapic_pin(idx, pin) \
78 for_each_ioapic((idx)) \
79 for_each_pin((idx), (pin))
80#define for_each_irq_pin(entry, head) \
81 list_for_each_entry(entry, &head, list)
82
83static DEFINE_RAW_SPINLOCK(ioapic_lock);
84static DEFINE_MUTEX(ioapic_mutex);
85static unsigned int ioapic_dynirq_base;
86static int ioapic_initialized;
87
88struct irq_pin_list {
89 struct list_head list;
90 int apic, pin;
91};
92
93struct mp_chip_data {
94 struct list_head irq_2_pin;
95 struct IO_APIC_route_entry entry;
96 bool is_level;
97 bool active_low;
98 bool isa_irq;
99 u32 count;
100};
101
102struct mp_ioapic_gsi {
103 u32 gsi_base;
104 u32 gsi_end;
105};
106
107static struct ioapic {
108 /* # of IRQ routing registers */
109 int nr_registers;
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
111 struct IO_APIC_route_entry *saved_registers;
112 /* I/O APIC config */
113 struct mpc_ioapic mp_config;
114 /* IO APIC gsi routing info */
115 struct mp_ioapic_gsi gsi_config;
116 struct ioapic_domain_cfg irqdomain_cfg;
117 struct irq_domain *irqdomain;
118 struct resource *iomem_res;
119} ioapics[MAX_IO_APICS];
120
121#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
122
123int mpc_ioapic_id(int ioapic_idx)
124{
125 return ioapics[ioapic_idx].mp_config.apicid;
126}
127
128unsigned int mpc_ioapic_addr(int ioapic_idx)
129{
130 return ioapics[ioapic_idx].mp_config.apicaddr;
131}
132
133static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134{
135 return &ioapics[ioapic_idx].gsi_config;
136}
137
138static inline int mp_ioapic_pin_count(int ioapic)
139{
140 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
143}
144
145static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146{
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
148}
149
150static inline bool mp_is_legacy_irq(int irq)
151{
152 return irq >= 0 && irq < nr_legacy_irqs();
153}
154
155static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
156{
157 return ioapics[ioapic].irqdomain;
158}
159
160int nr_ioapics;
161
162/* The one past the highest gsi number used */
163u32 gsi_top;
164
165/* MP IRQ source entries */
166struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
167
168/* # of MP IRQ source entries */
169int mp_irq_entries;
170
171#ifdef CONFIG_EISA
172int mp_bus_id_to_type[MAX_MP_BUSSES];
173#endif
174
175DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
176
177bool ioapic_is_disabled __ro_after_init;
178
179/**
180 * disable_ioapic_support() - disables ioapic support at runtime
181 */
182void disable_ioapic_support(void)
183{
184#ifdef CONFIG_PCI
185 noioapicquirk = 1;
186 noioapicreroute = -1;
187#endif
188 ioapic_is_disabled = true;
189}
190
191static int __init parse_noapic(char *str)
192{
193 /* disable IO-APIC */
194 disable_ioapic_support();
195 return 0;
196}
197early_param("noapic", parse_noapic);
198
199/* Will be called in mpparse/ACPI codes for saving IRQ info */
200void mp_save_irq(struct mpc_intsrc *m)
201{
202 int i;
203
204 apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n",
205 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
206 m->srcbusirq, m->dstapic, m->dstirq);
207
208 for (i = 0; i < mp_irq_entries; i++) {
209 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
210 return;
211 }
212
213 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
214 if (++mp_irq_entries == MAX_IRQ_SOURCES)
215 panic("Max # of irq sources exceeded!!\n");
216}
217
218static void alloc_ioapic_saved_registers(int idx)
219{
220 size_t size;
221
222 if (ioapics[idx].saved_registers)
223 return;
224
225 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
226 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
227 if (!ioapics[idx].saved_registers)
228 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
229}
230
231static void free_ioapic_saved_registers(int idx)
232{
233 kfree(ioapics[idx].saved_registers);
234 ioapics[idx].saved_registers = NULL;
235}
236
237int __init arch_early_ioapic_init(void)
238{
239 int i;
240
241 if (!nr_legacy_irqs())
242 io_apic_irqs = ~0UL;
243
244 for_each_ioapic(i)
245 alloc_ioapic_saved_registers(i);
246
247 return 0;
248}
249
250struct io_apic {
251 unsigned int index;
252 unsigned int unused[3];
253 unsigned int data;
254 unsigned int unused2[11];
255 unsigned int eoi;
256};
257
258static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
259{
260 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
261 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
262}
263
264static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
265{
266 struct io_apic __iomem *io_apic = io_apic_base(apic);
267
268 writel(vector, &io_apic->eoi);
269}
270
271unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
272{
273 struct io_apic __iomem *io_apic = io_apic_base(apic);
274
275 writel(reg, &io_apic->index);
276 return readl(&io_apic->data);
277}
278
279static void io_apic_write(unsigned int apic, unsigned int reg,
280 unsigned int value)
281{
282 struct io_apic __iomem *io_apic = io_apic_base(apic);
283
284 writel(reg, &io_apic->index);
285 writel(value, &io_apic->data);
286}
287
288static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
289{
290 struct IO_APIC_route_entry entry;
291
292 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
293 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
294
295 return entry;
296}
297
298static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
299{
300 guard(raw_spinlock_irqsave)(&ioapic_lock);
301 return __ioapic_read_entry(apic, pin);
302}
303
304/*
305 * When we write a new IO APIC routing entry, we need to write the high
306 * word first! If the mask bit in the low word is clear, we will enable
307 * the interrupt, and we need to make sure the entry is fully populated
308 * before that happens.
309 */
310static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
311{
312 io_apic_write(apic, 0x11 + 2*pin, e.w2);
313 io_apic_write(apic, 0x10 + 2*pin, e.w1);
314}
315
316static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
317{
318 guard(raw_spinlock_irqsave)(&ioapic_lock);
319 __ioapic_write_entry(apic, pin, e);
320}
321
322/*
323 * When we mask an IO APIC routing entry, we need to write the low
324 * word first, in order to set the mask bit before we change the
325 * high bits!
326 */
327static void ioapic_mask_entry(int apic, int pin)
328{
329 struct IO_APIC_route_entry e = { .masked = true };
330
331 guard(raw_spinlock_irqsave)(&ioapic_lock);
332 io_apic_write(apic, 0x10 + 2*pin, e.w1);
333 io_apic_write(apic, 0x11 + 2*pin, e.w2);
334}
335
336/*
337 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
338 * shared ISA-space IRQs, so we have to support them. We are super
339 * fast in the common case, and fast for shared ISA-space IRQs.
340 */
341static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin)
342{
343 struct irq_pin_list *entry;
344
345 /* Don't allow duplicates */
346 for_each_irq_pin(entry, data->irq_2_pin) {
347 if (entry->apic == apic && entry->pin == pin)
348 return true;
349 }
350
351 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
352 if (!entry) {
353 pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin);
354 return false;
355 }
356
357 entry->apic = apic;
358 entry->pin = pin;
359 list_add_tail(&entry->list, &data->irq_2_pin);
360 return true;
361}
362
363static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
364{
365 struct irq_pin_list *tmp, *entry;
366
367 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) {
368 if (entry->apic == apic && entry->pin == pin) {
369 list_del(&entry->list);
370 kfree(entry);
371 return;
372 }
373 }
374}
375
376static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
377 void (*final)(struct irq_pin_list *entry))
378{
379 struct irq_pin_list *entry;
380
381 data->entry.masked = masked;
382
383 for_each_irq_pin(entry, data->irq_2_pin) {
384 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
385 if (final)
386 final(entry);
387 }
388}
389
390/*
391 * Synchronize the IO-APIC and the CPU by doing a dummy read from the
392 * IO-APIC
393 */
394static void io_apic_sync(struct irq_pin_list *entry)
395{
396 struct io_apic __iomem *io_apic;
397
398 io_apic = io_apic_base(entry->apic);
399 readl(&io_apic->data);
400}
401
402static void mask_ioapic_irq(struct irq_data *irq_data)
403{
404 struct mp_chip_data *data = irq_data->chip_data;
405
406 guard(raw_spinlock_irqsave)(&ioapic_lock);
407 io_apic_modify_irq(data, true, &io_apic_sync);
408}
409
410static void __unmask_ioapic(struct mp_chip_data *data)
411{
412 io_apic_modify_irq(data, false, NULL);
413}
414
415static void unmask_ioapic_irq(struct irq_data *irq_data)
416{
417 struct mp_chip_data *data = irq_data->chip_data;
418
419 guard(raw_spinlock_irqsave)(&ioapic_lock);
420 __unmask_ioapic(data);
421}
422
423/*
424 * IO-APIC versions below 0x20 don't support EOI register.
425 * For the record, here is the information about various versions:
426 * 0Xh 82489DX
427 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
428 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
429 * 30h-FFh Reserved
430 *
431 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
432 * version as 0x2. This is an error with documentation and these ICH chips
433 * use io-apic's of version 0x20.
434 *
435 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
436 * Otherwise, we simulate the EOI message manually by changing the trigger
437 * mode to edge and then back to level, with RTE being masked during this.
438 */
439static void __eoi_ioapic_pin(int apic, int pin, int vector)
440{
441 if (mpc_ioapic_ver(apic) >= 0x20) {
442 io_apic_eoi(apic, vector);
443 } else {
444 struct IO_APIC_route_entry entry, entry1;
445
446 entry = entry1 = __ioapic_read_entry(apic, pin);
447
448 /* Mask the entry and change the trigger mode to edge. */
449 entry1.masked = true;
450 entry1.is_level = false;
451
452 __ioapic_write_entry(apic, pin, entry1);
453
454 /* Restore the previous level triggered entry. */
455 __ioapic_write_entry(apic, pin, entry);
456 }
457}
458
459static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
460{
461 struct irq_pin_list *entry;
462
463 guard(raw_spinlock_irqsave)(&ioapic_lock);
464 for_each_irq_pin(entry, data->irq_2_pin)
465 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
466}
467
468static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
469{
470 struct IO_APIC_route_entry entry;
471
472 /* Check delivery_mode to be sure we're not clearing an SMI pin */
473 entry = ioapic_read_entry(apic, pin);
474 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
475 return;
476
477 /*
478 * Make sure the entry is masked and re-read the contents to check
479 * if it is a level triggered pin and if the remote-IRR is set.
480 */
481 if (!entry.masked) {
482 entry.masked = true;
483 ioapic_write_entry(apic, pin, entry);
484 entry = ioapic_read_entry(apic, pin);
485 }
486
487 if (entry.irr) {
488 /*
489 * Make sure the trigger mode is set to level. Explicit EOI
490 * doesn't clear the remote-IRR if the trigger mode is not
491 * set to level.
492 */
493 if (!entry.is_level) {
494 entry.is_level = true;
495 ioapic_write_entry(apic, pin, entry);
496 }
497 guard(raw_spinlock_irqsave)(&ioapic_lock);
498 __eoi_ioapic_pin(apic, pin, entry.vector);
499 }
500
501 /*
502 * Clear the rest of the bits in the IO-APIC RTE except for the mask
503 * bit.
504 */
505 ioapic_mask_entry(apic, pin);
506 entry = ioapic_read_entry(apic, pin);
507 if (entry.irr)
508 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
509 mpc_ioapic_id(apic), pin);
510}
511
512void clear_IO_APIC (void)
513{
514 int apic, pin;
515
516 for_each_ioapic_pin(apic, pin)
517 clear_IO_APIC_pin(apic, pin);
518}
519
520#ifdef CONFIG_X86_32
521/*
522 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
523 * specific CPU-side IRQs.
524 */
525
526#define MAX_PIRQS 8
527static int pirq_entries[MAX_PIRQS] = {
528 [0 ... MAX_PIRQS - 1] = -1
529};
530
531static int __init ioapic_pirq_setup(char *str)
532{
533 int i, max, ints[MAX_PIRQS+1];
534
535 get_options(str, ARRAY_SIZE(ints), ints);
536
537 apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n");
538
539 max = MAX_PIRQS;
540 if (ints[0] < MAX_PIRQS)
541 max = ints[0];
542
543 for (i = 0; i < max; i++) {
544 apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]);
545 /* PIRQs are mapped upside down, usually */
546 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
547 }
548 return 1;
549}
550__setup("pirq=", ioapic_pirq_setup);
551#endif /* CONFIG_X86_32 */
552
553/*
554 * Saves all the IO-APIC RTE's
555 */
556int save_ioapic_entries(void)
557{
558 int apic, pin;
559 int err = 0;
560
561 for_each_ioapic(apic) {
562 if (!ioapics[apic].saved_registers) {
563 err = -ENOMEM;
564 continue;
565 }
566
567 for_each_pin(apic, pin)
568 ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin);
569 }
570
571 return err;
572}
573
574/*
575 * Mask all IO APIC entries.
576 */
577void mask_ioapic_entries(void)
578{
579 int apic, pin;
580
581 for_each_ioapic(apic) {
582 if (!ioapics[apic].saved_registers)
583 continue;
584
585 for_each_pin(apic, pin) {
586 struct IO_APIC_route_entry entry;
587
588 entry = ioapics[apic].saved_registers[pin];
589 if (!entry.masked) {
590 entry.masked = true;
591 ioapic_write_entry(apic, pin, entry);
592 }
593 }
594 }
595}
596
597/*
598 * Restore IO APIC entries which was saved in the ioapic structure.
599 */
600int restore_ioapic_entries(void)
601{
602 int apic, pin;
603
604 for_each_ioapic(apic) {
605 if (!ioapics[apic].saved_registers)
606 continue;
607
608 for_each_pin(apic, pin)
609 ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]);
610 }
611 return 0;
612}
613
614/*
615 * Find the IRQ entry number of a certain pin.
616 */
617static int find_irq_entry(int ioapic_idx, int pin, int type)
618{
619 int i;
620
621 for (i = 0; i < mp_irq_entries; i++) {
622 if (mp_irqs[i].irqtype == type &&
623 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
624 mp_irqs[i].dstapic == MP_APIC_ALL) &&
625 mp_irqs[i].dstirq == pin)
626 return i;
627 }
628
629 return -1;
630}
631
632/*
633 * Find the pin to which IRQ[irq] (ISA) is connected
634 */
635static int __init find_isa_irq_pin(int irq, int type)
636{
637 int i;
638
639 for (i = 0; i < mp_irq_entries; i++) {
640 int lbus = mp_irqs[i].srcbus;
641
642 if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) &&
643 (mp_irqs[i].srcbusirq == irq))
644 return mp_irqs[i].dstirq;
645 }
646 return -1;
647}
648
649static int __init find_isa_irq_apic(int irq, int type)
650{
651 int i;
652
653 for (i = 0; i < mp_irq_entries; i++) {
654 int lbus = mp_irqs[i].srcbus;
655
656 if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) &&
657 (mp_irqs[i].srcbusirq == irq))
658 break;
659 }
660
661 if (i < mp_irq_entries) {
662 int ioapic_idx;
663
664 for_each_ioapic(ioapic_idx) {
665 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
666 return ioapic_idx;
667 }
668 }
669
670 return -1;
671}
672
673static bool irq_active_low(int idx)
674{
675 int bus = mp_irqs[idx].srcbus;
676
677 /*
678 * Determine IRQ line polarity (high active or low active):
679 */
680 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
681 case MP_IRQPOL_DEFAULT:
682 /*
683 * Conforms to spec, ie. bus-type dependent polarity. PCI
684 * defaults to low active. [E]ISA defaults to high active.
685 */
686 return !test_bit(bus, mp_bus_not_pci);
687 case MP_IRQPOL_ACTIVE_HIGH:
688 return false;
689 case MP_IRQPOL_RESERVED:
690 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
691 fallthrough;
692 case MP_IRQPOL_ACTIVE_LOW:
693 default: /* Pointless default required due to do gcc stupidity */
694 return true;
695 }
696}
697
698#ifdef CONFIG_EISA
699/*
700 * EISA Edge/Level control register, ELCR
701 */
702static bool EISA_ELCR(unsigned int irq)
703{
704 if (irq < nr_legacy_irqs()) {
705 unsigned int port = PIC_ELCR1 + (irq >> 3);
706 return (inb(port) >> (irq & 7)) & 1;
707 }
708 apic_pr_verbose("Broken MPtable reports ISA irq %d\n", irq);
709 return false;
710}
711
712/*
713 * EISA interrupts are always active high and can be edge or level
714 * triggered depending on the ELCR value. If an interrupt is listed as
715 * EISA conforming in the MP table, that means its trigger type must be
716 * read in from the ELCR.
717 */
718static bool eisa_irq_is_level(int idx, int bus, bool level)
719{
720 switch (mp_bus_id_to_type[bus]) {
721 case MP_BUS_PCI:
722 case MP_BUS_ISA:
723 return level;
724 case MP_BUS_EISA:
725 return EISA_ELCR(mp_irqs[idx].srcbusirq);
726 }
727 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
728 return true;
729}
730#else
731static inline int eisa_irq_is_level(int idx, int bus, bool level)
732{
733 return level;
734}
735#endif
736
737static bool irq_is_level(int idx)
738{
739 int bus = mp_irqs[idx].srcbus;
740 bool level;
741
742 /*
743 * Determine IRQ trigger mode (edge or level sensitive):
744 */
745 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
746 case MP_IRQTRIG_DEFAULT:
747 /*
748 * Conforms to spec, ie. bus-type dependent trigger
749 * mode. PCI defaults to level, ISA to edge.
750 */
751 level = !test_bit(bus, mp_bus_not_pci);
752 /* Take EISA into account */
753 return eisa_irq_is_level(idx, bus, level);
754 case MP_IRQTRIG_EDGE:
755 return false;
756 case MP_IRQTRIG_RESERVED:
757 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
758 fallthrough;
759 case MP_IRQTRIG_LEVEL:
760 default: /* Pointless default required due to do gcc stupidity */
761 return true;
762 }
763}
764
765static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
766{
767 int ioapic, pin, idx;
768
769 if (ioapic_is_disabled)
770 return -1;
771
772 ioapic = mp_find_ioapic(gsi);
773 if (ioapic < 0)
774 return -1;
775
776 pin = mp_find_ioapic_pin(ioapic, gsi);
777 if (pin < 0)
778 return -1;
779
780 idx = find_irq_entry(ioapic, pin, mp_INT);
781 if (idx < 0)
782 return -1;
783
784 *trigger = irq_is_level(idx);
785 *polarity = irq_active_low(idx);
786 return 0;
787}
788
789#ifdef CONFIG_ACPI
790int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
791{
792 *is_level = *active_low = 0;
793 return __acpi_get_override_irq(gsi, (bool *)is_level,
794 (bool *)active_low);
795}
796#endif
797
798void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
799 int trigger, int polarity)
800{
801 init_irq_alloc_info(info, NULL);
802 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
803 info->ioapic.node = node;
804 info->ioapic.is_level = trigger;
805 info->ioapic.active_low = polarity;
806 info->ioapic.valid = 1;
807}
808
809static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
810 struct irq_alloc_info *src,
811 u32 gsi, int ioapic_idx, int pin)
812{
813 bool level, pol_low;
814
815 copy_irq_alloc_info(dst, src);
816 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
817 dst->devid = mpc_ioapic_id(ioapic_idx);
818 dst->ioapic.pin = pin;
819 dst->ioapic.valid = 1;
820 if (src && src->ioapic.valid) {
821 dst->ioapic.node = src->ioapic.node;
822 dst->ioapic.is_level = src->ioapic.is_level;
823 dst->ioapic.active_low = src->ioapic.active_low;
824 } else {
825 dst->ioapic.node = NUMA_NO_NODE;
826 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
827 dst->ioapic.is_level = level;
828 dst->ioapic.active_low = pol_low;
829 } else {
830 /*
831 * PCI interrupts are always active low level
832 * triggered.
833 */
834 dst->ioapic.is_level = true;
835 dst->ioapic.active_low = true;
836 }
837 }
838}
839
840static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
841{
842 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
843}
844
845static void mp_register_handler(unsigned int irq, bool level)
846{
847 irq_flow_handler_t hdl;
848 bool fasteoi;
849
850 if (level) {
851 irq_set_status_flags(irq, IRQ_LEVEL);
852 fasteoi = true;
853 } else {
854 irq_clear_status_flags(irq, IRQ_LEVEL);
855 fasteoi = false;
856 }
857
858 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
859 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
860}
861
862static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
863{
864 struct mp_chip_data *data = irq_get_chip_data(irq);
865
866 /*
867 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
868 * and polarity attributes. So allow the first user to reprogram the
869 * pin with real trigger and polarity attributes.
870 */
871 if (irq < nr_legacy_irqs() && data->count == 1) {
872 if (info->ioapic.is_level != data->is_level)
873 mp_register_handler(irq, info->ioapic.is_level);
874 data->entry.is_level = data->is_level = info->ioapic.is_level;
875 data->entry.active_low = data->active_low = info->ioapic.active_low;
876 }
877
878 return data->is_level == info->ioapic.is_level &&
879 data->active_low == info->ioapic.active_low;
880}
881
882static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
883 struct irq_alloc_info *info)
884{
885 int type = ioapics[ioapic].irqdomain_cfg.type;
886 bool legacy = false;
887 int irq = -1;
888
889 switch (type) {
890 case IOAPIC_DOMAIN_LEGACY:
891 /*
892 * Dynamically allocate IRQ number for non-ISA IRQs in the first
893 * 16 GSIs on some weird platforms.
894 */
895 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
896 irq = gsi;
897 legacy = mp_is_legacy_irq(irq);
898 break;
899 case IOAPIC_DOMAIN_STRICT:
900 irq = gsi;
901 break;
902 case IOAPIC_DOMAIN_DYNAMIC:
903 break;
904 default:
905 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
906 return -1;
907 }
908
909 return __irq_domain_alloc_irqs(domain, irq, 1, ioapic_alloc_attr_node(info),
910 info, legacy, NULL);
911}
912
913/*
914 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
915 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
916 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
917 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
918 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
919 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
920 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
921 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
922 */
923static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int ioapic, int pin,
924 struct irq_alloc_info *info)
925{
926 struct irq_data *irq_data = irq_get_irq_data(irq);
927 int node = ioapic_alloc_attr_node(info);
928 struct mp_chip_data *data;
929
930 /*
931 * Legacy ISA IRQ has already been allocated, just add pin to
932 * the pin list associated with this IRQ and program the IOAPIC
933 * entry.
934 */
935 if (irq_data && irq_data->parent_data) {
936 if (!mp_check_pin_attr(irq, info))
937 return -EBUSY;
938 if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic.pin))
939 return -ENOMEM;
940 } else {
941 info->flags |= X86_IRQ_ALLOC_LEGACY;
942 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, NULL);
943 if (irq >= 0) {
944 irq_data = irq_domain_get_irq_data(domain, irq);
945 data = irq_data->chip_data;
946 data->isa_irq = true;
947 }
948 }
949
950 return irq;
951}
952
953static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
954 unsigned int flags, struct irq_alloc_info *info)
955{
956 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
957 struct irq_alloc_info tmp;
958 struct mp_chip_data *data;
959 bool legacy = false;
960 int irq;
961
962 if (!domain)
963 return -ENOSYS;
964
965 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
966 irq = mp_irqs[idx].srcbusirq;
967 legacy = mp_is_legacy_irq(irq);
968 /*
969 * IRQ2 is unusable for historical reasons on systems which
970 * have a legacy PIC. See the comment vs. IRQ2 further down.
971 *
972 * If this gets removed at some point then the related code
973 * in lapic_assign_system_vectors() needs to be adjusted as
974 * well.
975 */
976 if (legacy && irq == PIC_CASCADE_IR)
977 return -EINVAL;
978 }
979
980 guard(mutex)(&ioapic_mutex);
981 if (!(flags & IOAPIC_MAP_ALLOC)) {
982 if (!legacy) {
983 irq = irq_find_mapping(domain, pin);
984 if (irq == 0)
985 irq = -ENOENT;
986 }
987 } else {
988 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
989 if (legacy)
990 irq = alloc_isa_irq_from_domain(domain, irq,
991 ioapic, pin, &tmp);
992 else if ((irq = irq_find_mapping(domain, pin)) == 0)
993 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
994 else if (!mp_check_pin_attr(irq, &tmp))
995 irq = -EBUSY;
996 if (irq >= 0) {
997 data = irq_get_chip_data(irq);
998 data->count++;
999 }
1000 }
1001 return irq;
1002}
1003
1004static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1005{
1006 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1007
1008 /* Debugging check, we are in big trouble if this message pops up! */
1009 if (mp_irqs[idx].dstirq != pin)
1010 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1011
1012#ifdef CONFIG_X86_32
1013 /* PCI IRQ command line redirection. Yes, limits are hardcoded. */
1014 if ((pin >= 16) && (pin <= 23)) {
1015 if (pirq_entries[pin - 16] != -1) {
1016 if (!pirq_entries[pin - 16]) {
1017 apic_pr_verbose("Disabling PIRQ%d\n", pin - 16);
1018 } else {
1019 int irq = pirq_entries[pin-16];
1020
1021 apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq);
1022 return irq;
1023 }
1024 }
1025 }
1026#endif
1027
1028 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1029}
1030
1031int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1032{
1033 int ioapic, pin, idx;
1034
1035 ioapic = mp_find_ioapic(gsi);
1036 if (ioapic < 0)
1037 return -ENODEV;
1038
1039 pin = mp_find_ioapic_pin(ioapic, gsi);
1040 idx = find_irq_entry(ioapic, pin, mp_INT);
1041 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1042 return -ENODEV;
1043
1044 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1045}
1046
1047void mp_unmap_irq(int irq)
1048{
1049 struct irq_data *irq_data = irq_get_irq_data(irq);
1050 struct mp_chip_data *data;
1051
1052 if (!irq_data || !irq_data->domain)
1053 return;
1054
1055 data = irq_data->chip_data;
1056 if (!data || data->isa_irq)
1057 return;
1058
1059 guard(mutex)(&ioapic_mutex);
1060 if (--data->count == 0)
1061 irq_domain_free_irqs(irq, 1);
1062}
1063
1064/*
1065 * Find a specific PCI IRQ entry.
1066 * Not an __init, possibly needed by modules
1067 */
1068int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1069{
1070 int irq, i, best_ioapic = -1, best_idx = -1;
1071
1072 apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1073 bus, slot, pin);
1074 if (test_bit(bus, mp_bus_not_pci)) {
1075 apic_pr_verbose("PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1076 return -1;
1077 }
1078
1079 for (i = 0; i < mp_irq_entries; i++) {
1080 int lbus = mp_irqs[i].srcbus;
1081 int ioapic_idx, found = 0;
1082
1083 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1084 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1085 continue;
1086
1087 for_each_ioapic(ioapic_idx)
1088 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1089 mp_irqs[i].dstapic == MP_APIC_ALL) {
1090 found = 1;
1091 break;
1092 }
1093 if (!found)
1094 continue;
1095
1096 /* Skip ISA IRQs */
1097 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1098 if (irq > 0 && !IO_APIC_IRQ(irq))
1099 continue;
1100
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1102 best_idx = i;
1103 best_ioapic = ioapic_idx;
1104 goto out;
1105 }
1106
1107 /*
1108 * Use the first all-but-pin matching entry as a
1109 * best-guess fuzzy result for broken mptables.
1110 */
1111 if (best_idx < 0) {
1112 best_idx = i;
1113 best_ioapic = ioapic_idx;
1114 }
1115 }
1116 if (best_idx < 0)
1117 return -1;
1118
1119out:
1120 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, IOAPIC_MAP_ALLOC);
1121}
1122EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1123
1124static struct irq_chip ioapic_chip, ioapic_ir_chip;
1125
1126static void __init setup_IO_APIC_irqs(void)
1127{
1128 unsigned int ioapic, pin;
1129 int idx;
1130
1131 apic_pr_verbose("Init IO_APIC IRQs\n");
1132
1133 for_each_ioapic_pin(ioapic, pin) {
1134 idx = find_irq_entry(ioapic, pin, mp_INT);
1135 if (idx < 0) {
1136 apic_pr_verbose("apic %d pin %d not connected\n",
1137 mpc_ioapic_id(ioapic), pin);
1138 } else {
1139 pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC);
1140 }
1141 }
1142}
1143
1144void ioapic_zap_locks(void)
1145{
1146 raw_spin_lock_init(&ioapic_lock);
1147}
1148
1149static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1150{
1151 struct IO_APIC_route_entry entry;
1152 char buf[256];
1153 int i;
1154
1155 apic_dbg("IOAPIC %d:\n", apic);
1156 for (i = 0; i <= nr_entries; i++) {
1157 entry = ioapic_read_entry(apic, i);
1158 snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1159 i, entry.masked ? "disabled" : "enabled ",
1160 entry.is_level ? "level" : "edge ",
1161 entry.active_low ? "low " : "high",
1162 entry.vector, entry.irr, entry.delivery_status);
1163 if (entry.ir_format) {
1164 apic_dbg("%s, remapped, I(%04X), Z(%X)\n", buf,
1165 (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero);
1166 } else {
1167 apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf,
1168 entry.dest_mode_logical ? "logical " : "physic al",
1169 entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode);
1170 }
1171 }
1172}
1173
1174static void __init print_IO_APIC(int ioapic_idx)
1175{
1176 union IO_APIC_reg_00 reg_00;
1177 union IO_APIC_reg_01 reg_01;
1178 union IO_APIC_reg_02 reg_02;
1179 union IO_APIC_reg_03 reg_03;
1180
1181 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
1182 reg_00.raw = io_apic_read(ioapic_idx, 0);
1183 reg_01.raw = io_apic_read(ioapic_idx, 1);
1184 if (reg_01.bits.version >= 0x10)
1185 reg_02.raw = io_apic_read(ioapic_idx, 2);
1186 if (reg_01.bits.version >= 0x20)
1187 reg_03.raw = io_apic_read(ioapic_idx, 3);
1188 }
1189
1190 apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1191 apic_dbg(".... register #00: %08X\n", reg_00.raw);
1192 apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID);
1193 apic_dbg("....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1194 apic_dbg("....... : LTS : %X\n", reg_00.bits.LTS);
1195 apic_dbg(".... register #01: %08X\n", *(int *)®_01);
1196 apic_dbg("....... : max redirection entries: %02X\n", reg_01.bits.entries);
1197 apic_dbg("....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1198 apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version);
1199
1200 /*
1201 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1202 * but the value of reg_02 is read as the previous read register
1203 * value, so ignore it if reg_02 == reg_01.
1204 */
1205 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1206 apic_dbg(".... register #02: %08X\n", reg_02.raw);
1207 apic_dbg("....... : arbitration: %02X\n", reg_02.bits.arbitration);
1208 }
1209
1210 /*
1211 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1212 * or reg_03, but the value of reg_0[23] is read as the previous read
1213 * register value, so ignore it if reg_03 == reg_0[12].
1214 */
1215 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1216 reg_03.raw != reg_01.raw) {
1217 apic_dbg(".... register #03: %08X\n", reg_03.raw);
1218 apic_dbg("....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1219 }
1220
1221 apic_dbg(".... IRQ redirection table:\n");
1222 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1223}
1224
1225void __init print_IO_APICs(void)
1226{
1227 int ioapic_idx;
1228 unsigned int irq;
1229
1230 apic_dbg("number of MP IRQ sources: %d.\n", mp_irq_entries);
1231 for_each_ioapic(ioapic_idx) {
1232 apic_dbg("number of IO-APIC #%d registers: %d.\n",
1233 mpc_ioapic_id(ioapic_idx), ioapics[ioapic_idx].nr_registers);
1234 }
1235
1236 /*
1237 * We are a bit conservative about what we expect. We have to
1238 * know about every hardware change ASAP.
1239 */
1240 printk(KERN_INFO "testing the IO APIC.......................\n");
1241
1242 for_each_ioapic(ioapic_idx)
1243 print_IO_APIC(ioapic_idx);
1244
1245 apic_dbg("IRQ to pin mappings:\n");
1246 for_each_active_irq(irq) {
1247 struct irq_pin_list *entry;
1248 struct irq_chip *chip;
1249 struct mp_chip_data *data;
1250
1251 chip = irq_get_chip(irq);
1252 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1253 continue;
1254 data = irq_get_chip_data(irq);
1255 if (!data)
1256 continue;
1257 if (list_empty(&data->irq_2_pin))
1258 continue;
1259
1260 apic_dbg("IRQ%d ", irq);
1261 for_each_irq_pin(entry, data->irq_2_pin)
1262 pr_cont("-> %d:%d", entry->apic, entry->pin);
1263 pr_cont("\n");
1264 }
1265
1266 printk(KERN_INFO ".................................... done.\n");
1267}
1268
1269/* Where if anywhere is the i8259 connect in external int mode */
1270static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1271
1272void __init enable_IO_APIC(void)
1273{
1274 int i8259_apic, i8259_pin, apic, pin;
1275
1276 if (ioapic_is_disabled)
1277 nr_ioapics = 0;
1278
1279 if (!nr_legacy_irqs() || !nr_ioapics)
1280 return;
1281
1282 for_each_ioapic_pin(apic, pin) {
1283 /* See if any of the pins is in ExtINT mode */
1284 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1285
1286 /*
1287 * If the interrupt line is enabled and in ExtInt mode I
1288 * have found the pin where the i8259 is connected.
1289 */
1290 if (!entry.masked && entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1291 ioapic_i8259.apic = apic;
1292 ioapic_i8259.pin = pin;
1293 break;
1294 }
1295 }
1296
1297 /*
1298 * Look to see what if the MP table has reported the ExtINT
1299 *
1300 * If we could not find the appropriate pin by looking at the ioapic
1301 * the i8259 probably is not connected the ioapic but give the
1302 * mptable a chance anyway.
1303 */
1304 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1305 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1306 /* Trust the MP table if nothing is setup in the hardware */
1307 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1308 pr_warn("ExtINT not setup in hardware but reported by MP table\n");
1309 ioapic_i8259.pin = i8259_pin;
1310 ioapic_i8259.apic = i8259_apic;
1311 }
1312 /* Complain if the MP table and the hardware disagree */
1313 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1314 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1315 pr_warn("ExtINT in hardware and MP table differ\n");
1316
1317 /* Do not trust the IO-APIC being empty at bootup */
1318 clear_IO_APIC();
1319}
1320
1321void native_restore_boot_irq_mode(void)
1322{
1323 /*
1324 * If the i8259 is routed through an IOAPIC Put that IOAPIC in
1325 * virtual wire mode so legacy interrupts can be delivered.
1326 */
1327 if (ioapic_i8259.pin != -1) {
1328 struct IO_APIC_route_entry entry;
1329 u32 apic_id = read_apic_id();
1330
1331 memset(&entry, 0, sizeof(entry));
1332 entry.masked = false;
1333 entry.is_level = false;
1334 entry.active_low = false;
1335 entry.dest_mode_logical = false;
1336 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1337 entry.destid_0_7 = apic_id & 0xFF;
1338 entry.virt_destid_8_14 = apic_id >> 8;
1339
1340 /* Add it to the IO-APIC irq-routing table */
1341 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1342 }
1343
1344 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1345 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1346}
1347
1348void restore_boot_irq_mode(void)
1349{
1350 if (!nr_legacy_irqs())
1351 return;
1352
1353 x86_apic_ops.restore();
1354}
1355
1356#ifdef CONFIG_X86_32
1357/*
1358 * function to set the IO-APIC physical IDs based on the
1359 * values stored in the MPC table.
1360 *
1361 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1362 */
1363static void __init setup_ioapic_ids_from_mpc_nocheck(void)
1364{
1365 DECLARE_BITMAP(phys_id_present_map, MAX_LOCAL_APIC);
1366 const u32 broadcast_id = 0xF;
1367 union IO_APIC_reg_00 reg_00;
1368 unsigned char old_id;
1369 int ioapic_idx, i;
1370
1371 /*
1372 * This is broken; anything with a real cpu count has to
1373 * circumvent this idiocy regardless.
1374 */
1375 copy_phys_cpu_present_map(phys_id_present_map);
1376
1377 /*
1378 * Set the IOAPIC ID to the value stored in the MPC table.
1379 */
1380 for_each_ioapic(ioapic_idx) {
1381 /* Read the register 0 value */
1382 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
1383 reg_00.raw = io_apic_read(ioapic_idx, 0);
1384
1385 old_id = mpc_ioapic_id(ioapic_idx);
1386
1387 if (mpc_ioapic_id(ioapic_idx) >= broadcast_id) {
1388 pr_err(FW_BUG "IO-APIC#%d ID is %d in the MPC table!...\n",
1389 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1390 pr_err("... fixing up to %d. (tell your hw vendor)\n", reg_00.bits.ID);
1391 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1392 }
1393
1394 /*
1395 * Sanity check, is the ID really free? Every APIC in a
1396 * system must have a unique ID or we get lots of nice
1397 * 'stuck on smp_invalidate_needed IPI wait' messages.
1398 */
1399 if (test_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) {
1400 pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n",
1401 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1402 for (i = 0; i < broadcast_id; i++)
1403 if (!test_bit(i, phys_id_present_map))
1404 break;
1405 if (i >= broadcast_id)
1406 panic("Max APIC ID exceeded!\n");
1407 pr_err("... fixing up to %d. (tell your hw vendor)\n", i);
1408 set_bit(i, phys_id_present_map);
1409 ioapics[ioapic_idx].mp_config.apicid = i;
1410 } else {
1411 apic_pr_verbose("Setting %d in the phys_id_present_map\n",
1412 mpc_ioapic_id(ioapic_idx));
1413 set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map);
1414 }
1415
1416 /*
1417 * We need to adjust the IRQ routing table if the ID
1418 * changed.
1419 */
1420 if (old_id != mpc_ioapic_id(ioapic_idx)) {
1421 for (i = 0; i < mp_irq_entries; i++) {
1422 if (mp_irqs[i].dstapic == old_id)
1423 mp_irqs[i].dstapic = mpc_ioapic_id(ioapic_idx);
1424 }
1425 }
1426
1427 /*
1428 * Update the ID register according to the right value from
1429 * the MPC table if they are different.
1430 */
1431 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1432 continue;
1433
1434 apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...",
1435 mpc_ioapic_id(ioapic_idx));
1436
1437 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1438 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
1439 io_apic_write(ioapic_idx, 0, reg_00.raw);
1440 reg_00.raw = io_apic_read(ioapic_idx, 0);
1441 }
1442 /* Sanity check */
1443 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1444 pr_cont("could not set ID!\n");
1445 else
1446 apic_pr_verbose(" ok.\n");
1447 }
1448}
1449
1450void __init setup_ioapic_ids_from_mpc(void)
1451{
1452
1453 if (acpi_ioapic)
1454 return;
1455 /*
1456 * Don't check I/O APIC IDs for xAPIC systems. They have
1457 * no meaning without the serial APIC bus.
1458 */
1459 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1460 || APIC_XAPIC(boot_cpu_apic_version))
1461 return;
1462 setup_ioapic_ids_from_mpc_nocheck();
1463}
1464#endif
1465
1466int no_timer_check __initdata;
1467
1468static int __init notimercheck(char *s)
1469{
1470 no_timer_check = 1;
1471 return 1;
1472}
1473__setup("no_timer_check", notimercheck);
1474
1475static void __init delay_with_tsc(void)
1476{
1477 unsigned long long start, now;
1478 unsigned long end = jiffies + 4;
1479
1480 start = rdtsc();
1481
1482 /*
1483 * We don't know the TSC frequency yet, but waiting for
1484 * 40000000000/HZ TSC cycles is safe:
1485 * 4 GHz == 10 jiffies
1486 * 1 GHz == 40 jiffies
1487 */
1488 do {
1489 rep_nop();
1490 now = rdtsc();
1491 } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, end));
1492}
1493
1494static void __init delay_without_tsc(void)
1495{
1496 unsigned long end = jiffies + 4;
1497 int band = 1;
1498
1499 /*
1500 * We don't know any frequency yet, but waiting for
1501 * 40940000000/HZ cycles is safe:
1502 * 4 GHz == 10 jiffies
1503 * 1 GHz == 40 jiffies
1504 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1505 */
1506 do {
1507 __delay(((1U << band++) * 10000000UL) / HZ);
1508 } while (band < 12 && time_before_eq(jiffies, end));
1509}
1510
1511/*
1512 * There is a nasty bug in some older SMP boards, their mptable lies
1513 * about the timer IRQ. We do the following to work around the situation:
1514 *
1515 * - timer IRQ defaults to IO-APIC IRQ
1516 * - if this function detects that timer IRQs are defunct, then we fall
1517 * back to ISA timer IRQs
1518 */
1519static int __init timer_irq_works(void)
1520{
1521 unsigned long t1 = jiffies;
1522
1523 if (no_timer_check)
1524 return 1;
1525
1526 local_irq_enable();
1527 if (boot_cpu_has(X86_FEATURE_TSC))
1528 delay_with_tsc();
1529 else
1530 delay_without_tsc();
1531
1532 /*
1533 * Expect a few ticks at least, to be sure some possible
1534 * glue logic does not lock up after one or two first
1535 * ticks in a non-ExtINT mode. Also the local APIC
1536 * might have cached one ExtINT interrupt. Finally, at
1537 * least one tick may be lost due to delays.
1538 */
1539
1540 local_irq_disable();
1541
1542 /* Did jiffies advance? */
1543 return time_after(jiffies, t1 + 4);
1544}
1545
1546/*
1547 * In the SMP+IOAPIC case it might happen that there are an unspecified
1548 * number of pending IRQ events unhandled. These cases are very rare,
1549 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1550 * better to do it this way as thus we do not have to be aware of
1551 * 'pending' interrupts in the IRQ path, except at this point.
1552 *
1553 *
1554 * Edge triggered needs to resend any interrupt that was delayed but this
1555 * is now handled in the device independent code.
1556 *
1557 * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to
1558 * make sure that we get the edge. If it is already asserted for some
1559 * reason, we need return 1 to indicate that is was pending.
1560 *
1561 * This is not complete - we should be able to fake an edge even if it
1562 * isn't on the 8259A...
1563 */
1564static unsigned int startup_ioapic_irq(struct irq_data *data)
1565{
1566 int was_pending = 0, irq = data->irq;
1567
1568 guard(raw_spinlock_irqsave)(&ioapic_lock);
1569 if (irq < nr_legacy_irqs()) {
1570 legacy_pic->mask(irq);
1571 if (legacy_pic->irq_pending(irq))
1572 was_pending = 1;
1573 }
1574 __unmask_ioapic(data->chip_data);
1575 return was_pending;
1576}
1577
1578atomic_t irq_mis_count;
1579
1580#ifdef CONFIG_GENERIC_PENDING_IRQ
1581static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1582{
1583 struct irq_pin_list *entry;
1584
1585 guard(raw_spinlock_irqsave)(&ioapic_lock);
1586 for_each_irq_pin(entry, data->irq_2_pin) {
1587 struct IO_APIC_route_entry e;
1588 int pin;
1589
1590 pin = entry->pin;
1591 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1592 /* Is the remote IRR bit set? */
1593 if (e.irr)
1594 return true;
1595 }
1596 return false;
1597}
1598
1599static inline bool ioapic_prepare_move(struct irq_data *data)
1600{
1601 /* If we are moving the IRQ we need to mask it */
1602 if (unlikely(irqd_is_setaffinity_pending(data))) {
1603 if (!irqd_irq_masked(data))
1604 mask_ioapic_irq(data);
1605 return true;
1606 }
1607 return false;
1608}
1609
1610static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1611{
1612 if (unlikely(moveit)) {
1613 /*
1614 * Only migrate the irq if the ack has been received.
1615 *
1616 * On rare occasions the broadcast level triggered ack gets
1617 * delayed going to ioapics, and if we reprogram the
1618 * vector while Remote IRR is still set the irq will never
1619 * fire again.
1620 *
1621 * To prevent this scenario we read the Remote IRR bit
1622 * of the ioapic. This has two effects.
1623 * - On any sane system the read of the ioapic will
1624 * flush writes (and acks) going to the ioapic from
1625 * this cpu.
1626 * - We get to see if the ACK has actually been delivered.
1627 *
1628 * Based on failed experiments of reprogramming the
1629 * ioapic entry from outside of irq context starting
1630 * with masking the ioapic entry and then polling until
1631 * Remote IRR was clear before reprogramming the
1632 * ioapic I don't trust the Remote IRR bit to be
1633 * completely accurate.
1634 *
1635 * However there appears to be no other way to plug
1636 * this race, so if the Remote IRR bit is not
1637 * accurate and is causing problems then it is a hardware bug
1638 * and you can go talk to the chipset vendor about it.
1639 */
1640 if (!io_apic_level_ack_pending(data->chip_data))
1641 irq_move_masked_irq(data);
1642 /* If the IRQ is masked in the core, leave it: */
1643 if (!irqd_irq_masked(data))
1644 unmask_ioapic_irq(data);
1645 }
1646}
1647#else
1648static inline bool ioapic_prepare_move(struct irq_data *data)
1649{
1650 return false;
1651}
1652static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1653{
1654}
1655#endif
1656
1657static void ioapic_ack_level(struct irq_data *irq_data)
1658{
1659 struct irq_cfg *cfg = irqd_cfg(irq_data);
1660 unsigned long v;
1661 bool moveit;
1662 int i;
1663
1664 irq_complete_move(cfg);
1665 moveit = ioapic_prepare_move(irq_data);
1666
1667 /*
1668 * It appears there is an erratum which affects at least version 0x11
1669 * of I/O APIC (that's the 82093AA and cores integrated into various
1670 * chipsets). Under certain conditions a level-triggered interrupt is
1671 * erroneously delivered as edge-triggered one but the respective IRR
1672 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1673 * message but it will never arrive and further interrupts are blocked
1674 * from the source. The exact reason is so far unknown, but the
1675 * phenomenon was observed when two consecutive interrupt requests
1676 * from a given source get delivered to the same CPU and the source is
1677 * temporarily disabled in between.
1678 *
1679 * A workaround is to simulate an EOI message manually. We achieve it
1680 * by setting the trigger mode to edge and then to level when the edge
1681 * trigger mode gets detected in the TMR of a local APIC for a
1682 * level-triggered interrupt. We mask the source for the time of the
1683 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1684 * The idea is from Manfred Spraul. --macro
1685 *
1686 * Also in the case when cpu goes offline, fixup_irqs() will forward
1687 * any unhandled interrupt on the offlined cpu to the new cpu
1688 * destination that is handling the corresponding interrupt. This
1689 * interrupt forwarding is done via IPI's. Hence, in this case also
1690 * level-triggered io-apic interrupt will be seen as an edge
1691 * interrupt in the IRR. And we can't rely on the cpu's EOI
1692 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1693 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1694 * supporting EOI register, we do an explicit EOI to clear the
1695 * remote IRR and on IO-APIC's which don't have an EOI register,
1696 * we use the above logic (mask+edge followed by unmask+level) from
1697 * Manfred Spraul to clear the remote IRR.
1698 */
1699 i = cfg->vector;
1700 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1701
1702 /*
1703 * We must acknowledge the irq before we move it or the acknowledge will
1704 * not propagate properly.
1705 */
1706 apic_eoi();
1707
1708 /*
1709 * Tail end of clearing remote IRR bit (either by delivering the EOI
1710 * message via io-apic EOI register write or simulating it using
1711 * mask+edge followed by unmask+level logic) manually when the
1712 * level triggered interrupt is seen as the edge triggered interrupt
1713 * at the cpu.
1714 */
1715 if (!(v & (1 << (i & 0x1f)))) {
1716 atomic_inc(&irq_mis_count);
1717 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1718 }
1719
1720 ioapic_finish_move(irq_data, moveit);
1721}
1722
1723static void ioapic_ir_ack_level(struct irq_data *irq_data)
1724{
1725 struct mp_chip_data *data = irq_data->chip_data;
1726
1727 /*
1728 * Intr-remapping uses pin number as the virtual vector
1729 * in the RTE. Actual vector is programmed in
1730 * intr-remapping table entry. Hence for the io-apic
1731 * EOI we use the pin number.
1732 */
1733 apic_ack_irq(irq_data);
1734 eoi_ioapic_pin(data->entry.vector, data);
1735}
1736
1737/*
1738 * The I/OAPIC is just a device for generating MSI messages from legacy
1739 * interrupt pins. Various fields of the RTE translate into bits of the
1740 * resulting MSI which had a historical meaning.
1741 *
1742 * With interrupt remapping, many of those bits have different meanings
1743 * in the underlying MSI, but the way that the I/OAPIC transforms them
1744 * from its RTE to the MSI message is the same. This function allows
1745 * the parent IRQ domain to compose the MSI message, then takes the
1746 * relevant bits to put them in the appropriate places in the RTE in
1747 * order to generate that message when the IRQ happens.
1748 *
1749 * The setup here relies on a preconfigured route entry (is_level,
1750 * active_low, masked) because the parent domain is merely composing the
1751 * generic message routing information which is used for the MSI.
1752 */
1753static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1754 struct IO_APIC_route_entry *entry)
1755{
1756 struct msi_msg msg;
1757
1758 /* Let the parent domain compose the MSI message */
1759 irq_chip_compose_msi_msg(irq_data, &msg);
1760
1761 /*
1762 * - Real vector
1763 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1764 * - AMD/IR: 8bit IRTE index
1765 */
1766 entry->vector = msg.arch_data.vector;
1767 /* Delivery mode (for DMAR/IR all 0) */
1768 entry->delivery_mode = msg.arch_data.delivery_mode;
1769 /* Destination mode or DMAR/IR index bit 15 */
1770 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1771 /* DMAR/IR: 1, 0 for all other modes */
1772 entry->ir_format = msg.arch_addr_lo.dmar_format;
1773 /*
1774 * - DMAR/IR: index bit 0-14.
1775 *
1776 * - Virt: If the host supports x2apic without a virtualized IR
1777 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1778 * 8-14 of the destination id.
1779 *
1780 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1781 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1782 */
1783 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1784}
1785
1786static void ioapic_configure_entry(struct irq_data *irqd)
1787{
1788 struct mp_chip_data *mpd = irqd->chip_data;
1789 struct irq_pin_list *entry;
1790
1791 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1792
1793 for_each_irq_pin(entry, mpd->irq_2_pin)
1794 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1795}
1796
1797static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force)
1798{
1799 struct irq_data *parent = irq_data->parent_data;
1800 int ret;
1801
1802 ret = parent->chip->irq_set_affinity(parent, mask, force);
1803
1804 guard(raw_spinlock_irqsave)(&ioapic_lock);
1805 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1806 ioapic_configure_entry(irq_data);
1807
1808 return ret;
1809}
1810
1811/*
1812 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1813 * be in flight, but not yet serviced by the target CPU. That means
1814 * __synchronize_hardirq() would return and claim that everything is calmed
1815 * down. So free_irq() would proceed and deactivate the interrupt and free
1816 * resources.
1817 *
1818 * Once the target CPU comes around to service it it will find a cleared
1819 * vector and complain. While the spurious interrupt is harmless, the full
1820 * release of resources might prevent the interrupt from being acknowledged
1821 * which keeps the hardware in a weird state.
1822 *
1823 * Verify that the corresponding Remote-IRR bits are clear.
1824 */
1825static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_irq_state which,
1826 bool *state)
1827{
1828 struct mp_chip_data *mcd = irqd->chip_data;
1829 struct IO_APIC_route_entry rentry;
1830 struct irq_pin_list *p;
1831
1832 if (which != IRQCHIP_STATE_ACTIVE)
1833 return -EINVAL;
1834
1835 *state = false;
1836
1837 guard(raw_spinlock)(&ioapic_lock);
1838 for_each_irq_pin(p, mcd->irq_2_pin) {
1839 rentry = __ioapic_read_entry(p->apic, p->pin);
1840 /*
1841 * The remote IRR is only valid in level trigger mode. It's
1842 * meaning is undefined for edge triggered interrupts and
1843 * irrelevant because the IO-APIC treats them as fire and
1844 * forget.
1845 */
1846 if (rentry.irr && rentry.is_level) {
1847 *state = true;
1848 break;
1849 }
1850 }
1851 return 0;
1852}
1853
1854static struct irq_chip ioapic_chip __read_mostly = {
1855 .name = "IO-APIC",
1856 .irq_startup = startup_ioapic_irq,
1857 .irq_mask = mask_ioapic_irq,
1858 .irq_unmask = unmask_ioapic_irq,
1859 .irq_ack = irq_chip_ack_parent,
1860 .irq_eoi = ioapic_ack_level,
1861 .irq_set_affinity = ioapic_set_affinity,
1862 .irq_retrigger = irq_chip_retrigger_hierarchy,
1863 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1864 .flags = IRQCHIP_SKIP_SET_WAKE |
1865 IRQCHIP_AFFINITY_PRE_STARTUP,
1866};
1867
1868static struct irq_chip ioapic_ir_chip __read_mostly = {
1869 .name = "IR-IO-APIC",
1870 .irq_startup = startup_ioapic_irq,
1871 .irq_mask = mask_ioapic_irq,
1872 .irq_unmask = unmask_ioapic_irq,
1873 .irq_ack = irq_chip_ack_parent,
1874 .irq_eoi = ioapic_ir_ack_level,
1875 .irq_set_affinity = ioapic_set_affinity,
1876 .irq_retrigger = irq_chip_retrigger_hierarchy,
1877 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1878 .flags = IRQCHIP_SKIP_SET_WAKE |
1879 IRQCHIP_AFFINITY_PRE_STARTUP,
1880};
1881
1882static inline void init_IO_APIC_traps(void)
1883{
1884 struct irq_cfg *cfg;
1885 unsigned int irq;
1886
1887 for_each_active_irq(irq) {
1888 cfg = irq_cfg(irq);
1889 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1890 /*
1891 * Hmm.. We don't have an entry for this, so
1892 * default to an old-fashioned 8259 interrupt if we
1893 * can. Otherwise set the dummy interrupt chip.
1894 */
1895 if (irq < nr_legacy_irqs())
1896 legacy_pic->make_irq(irq);
1897 else
1898 irq_set_chip(irq, &no_irq_chip);
1899 }
1900 }
1901}
1902
1903/*
1904 * The local APIC irq-chip implementation:
1905 */
1906static void mask_lapic_irq(struct irq_data *data)
1907{
1908 unsigned long v = apic_read(APIC_LVT0);
1909
1910 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1911}
1912
1913static void unmask_lapic_irq(struct irq_data *data)
1914{
1915 unsigned long v = apic_read(APIC_LVT0);
1916
1917 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1918}
1919
1920static void ack_lapic_irq(struct irq_data *data)
1921{
1922 apic_eoi();
1923}
1924
1925static struct irq_chip lapic_chip __read_mostly = {
1926 .name = "local-APIC",
1927 .irq_mask = mask_lapic_irq,
1928 .irq_unmask = unmask_lapic_irq,
1929 .irq_ack = ack_lapic_irq,
1930};
1931
1932static void lapic_register_intr(int irq)
1933{
1934 irq_clear_status_flags(irq, IRQ_LEVEL);
1935 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge");
1936}
1937
1938/*
1939 * This looks a bit hackish but it's about the only one way of sending
1940 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1941 * not support the ExtINT mode, unfortunately. We need to send these
1942 * cycles as some i82489DX-based boards have glue logic that keeps the
1943 * 8259A interrupt line asserted until INTA. --macro
1944 */
1945static inline void __init unlock_ExtINT_logic(void)
1946{
1947 unsigned char save_control, save_freq_select;
1948 struct IO_APIC_route_entry entry0, entry1;
1949 int apic, pin, i;
1950 u32 apic_id;
1951
1952 pin = find_isa_irq_pin(8, mp_INT);
1953 if (pin == -1) {
1954 WARN_ON_ONCE(1);
1955 return;
1956 }
1957 apic = find_isa_irq_apic(8, mp_INT);
1958 if (apic == -1) {
1959 WARN_ON_ONCE(1);
1960 return;
1961 }
1962
1963 entry0 = ioapic_read_entry(apic, pin);
1964 clear_IO_APIC_pin(apic, pin);
1965
1966 apic_id = read_apic_id();
1967 memset(&entry1, 0, sizeof(entry1));
1968
1969 entry1.dest_mode_logical = true;
1970 entry1.masked = false;
1971 entry1.destid_0_7 = apic_id & 0xFF;
1972 entry1.virt_destid_8_14 = apic_id >> 8;
1973 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1974 entry1.active_low = entry0.active_low;
1975 entry1.is_level = false;
1976 entry1.vector = 0;
1977
1978 ioapic_write_entry(apic, pin, entry1);
1979
1980 save_control = CMOS_READ(RTC_CONTROL);
1981 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1982 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1983 RTC_FREQ_SELECT);
1984 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1985
1986 i = 100;
1987 while (i-- > 0) {
1988 mdelay(10);
1989 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1990 i -= 10;
1991 }
1992
1993 CMOS_WRITE(save_control, RTC_CONTROL);
1994 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1995 clear_IO_APIC_pin(apic, pin);
1996
1997 ioapic_write_entry(apic, pin, entry0);
1998}
1999
2000static int disable_timer_pin_1 __initdata;
2001/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2002static int __init disable_timer_pin_setup(char *arg)
2003{
2004 disable_timer_pin_1 = 1;
2005 return 0;
2006}
2007early_param("disable_timer_pin_1", disable_timer_pin_setup);
2008
2009static int __init mp_alloc_timer_irq(int ioapic, int pin)
2010{
2011 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2012 int irq = -1;
2013
2014 if (domain) {
2015 struct irq_alloc_info info;
2016
2017 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2018 info.devid = mpc_ioapic_id(ioapic);
2019 info.ioapic.pin = pin;
2020 guard(mutex)(&ioapic_mutex);
2021 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2022 }
2023
2024 return irq;
2025}
2026
2027static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
2028 int oldapic, int oldpin,
2029 int newapic, int newpin)
2030{
2031 struct irq_pin_list *entry;
2032
2033 for_each_irq_pin(entry, data->irq_2_pin) {
2034 if (entry->apic == oldapic && entry->pin == oldpin) {
2035 entry->apic = newapic;
2036 entry->pin = newpin;
2037 return;
2038 }
2039 }
2040
2041 /* Old apic/pin didn't exist, so just add a new one */
2042 add_pin_to_irq_node(data, node, newapic, newpin);
2043}
2044
2045/*
2046 * This code may look a bit paranoid, but it's supposed to cooperate with
2047 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2048 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2049 * fanatically on his truly buggy board.
2050 */
2051static inline void __init check_timer(void)
2052{
2053 struct irq_data *irq_data = irq_get_irq_data(0);
2054 struct mp_chip_data *data = irq_data->chip_data;
2055 struct irq_cfg *cfg = irqd_cfg(irq_data);
2056 int node = cpu_to_node(0);
2057 int apic1, pin1, apic2, pin2;
2058 int no_pin1 = 0;
2059
2060 if (!global_clock_event)
2061 return;
2062
2063 local_irq_disable();
2064
2065 /*
2066 * get/set the timer IRQ vector:
2067 */
2068 legacy_pic->mask(0);
2069
2070 /*
2071 * As IRQ0 is to be enabled in the 8259A, the virtual
2072 * wire has to be disabled in the local APIC. Also
2073 * timer interrupts need to be acknowledged manually in
2074 * the 8259A for the i82489DX when using the NMI
2075 * watchdog as that APIC treats NMIs as level-triggered.
2076 * The AEOI mode will finish them in the 8259A
2077 * automatically.
2078 */
2079 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2080 legacy_pic->init(1);
2081
2082 pin1 = find_isa_irq_pin(0, mp_INT);
2083 apic1 = find_isa_irq_apic(0, mp_INT);
2084 pin2 = ioapic_i8259.pin;
2085 apic2 = ioapic_i8259.apic;
2086
2087 pr_info("..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2088 cfg->vector, apic1, pin1, apic2, pin2);
2089
2090 /*
2091 * Some BIOS writers are clueless and report the ExtINTA
2092 * I/O APIC input from the cascaded 8259A as the timer
2093 * interrupt input. So just in case, if only one pin
2094 * was found above, try it both directly and through the
2095 * 8259A.
2096 */
2097 if (pin1 == -1) {
2098 panic_if_irq_remap(FW_BUG "Timer not connected to IO-APIC");
2099 pin1 = pin2;
2100 apic1 = apic2;
2101 no_pin1 = 1;
2102 } else if (pin2 == -1) {
2103 pin2 = pin1;
2104 apic2 = apic1;
2105 }
2106
2107 if (pin1 != -1) {
2108 /* Ok, does IRQ0 through the IOAPIC work? */
2109 if (no_pin1) {
2110 mp_alloc_timer_irq(apic1, pin1);
2111 } else {
2112 /*
2113 * for edge trigger, it's already unmasked,
2114 * so only need to unmask if it is level-trigger
2115 * do we really have level trigger timer?
2116 */
2117 int idx = find_irq_entry(apic1, pin1, mp_INT);
2118
2119 if (idx != -1 && irq_is_level(idx))
2120 unmask_ioapic_irq(irq_get_irq_data(0));
2121 }
2122 irq_domain_deactivate_irq(irq_data);
2123 irq_domain_activate_irq(irq_data, false);
2124 if (timer_irq_works()) {
2125 if (disable_timer_pin_1 > 0)
2126 clear_IO_APIC_pin(0, pin1);
2127 goto out;
2128 }
2129 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2130 clear_IO_APIC_pin(apic1, pin1);
2131 if (!no_pin1)
2132 pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2133
2134 pr_info("...trying to set up timer (IRQ0) through the 8259A ...\n");
2135 pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2);
2136 /*
2137 * legacy devices should be connected to IO APIC #0
2138 */
2139 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2140 irq_domain_deactivate_irq(irq_data);
2141 irq_domain_activate_irq(irq_data, false);
2142 legacy_pic->unmask(0);
2143 if (timer_irq_works()) {
2144 pr_info("....... works.\n");
2145 goto out;
2146 }
2147 /*
2148 * Cleanup, just in case ...
2149 */
2150 legacy_pic->mask(0);
2151 clear_IO_APIC_pin(apic2, pin2);
2152 pr_info("....... failed.\n");
2153 }
2154
2155 pr_info("...trying to set up timer as Virtual Wire IRQ...\n");
2156
2157 lapic_register_intr(0);
2158 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2159 legacy_pic->unmask(0);
2160
2161 if (timer_irq_works()) {
2162 pr_info("..... works.\n");
2163 goto out;
2164 }
2165 legacy_pic->mask(0);
2166 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2167 pr_info("..... failed.\n");
2168
2169 pr_info("...trying to set up timer as ExtINT IRQ...\n");
2170
2171 legacy_pic->init(0);
2172 legacy_pic->make_irq(0);
2173 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2174 legacy_pic->unmask(0);
2175
2176 unlock_ExtINT_logic();
2177
2178 if (timer_irq_works()) {
2179 pr_info("..... works.\n");
2180 goto out;
2181 }
2182
2183 pr_info("..... failed :\n");
2184 if (apic_is_x2apic_enabled()) {
2185 pr_info("Perhaps problem with the pre-enabled x2apic mode\n"
2186 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2187 }
2188 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2189 "report. Then try booting with the 'noapic' option.\n");
2190out:
2191 local_irq_enable();
2192}
2193
2194/*
2195 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2196 * to devices. However there may be an I/O APIC pin available for
2197 * this interrupt regardless. The pin may be left unconnected, but
2198 * typically it will be reused as an ExtINT cascade interrupt for
2199 * the master 8259A. In the MPS case such a pin will normally be
2200 * reported as an ExtINT interrupt in the MP table. With ACPI
2201 * there is no provision for ExtINT interrupts, and in the absence
2202 * of an override it would be treated as an ordinary ISA I/O APIC
2203 * interrupt, that is edge-triggered and unmasked by default. We
2204 * used to do this, but it caused problems on some systems because
2205 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2206 * the same ExtINT cascade interrupt to drive the local APIC of the
2207 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2208 * the I/O APIC in all cases now. No actual device should request
2209 * it anyway. --macro
2210 */
2211#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2212
2213static int mp_irqdomain_create(int ioapic)
2214{
2215 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2216 int hwirqs = mp_ioapic_pin_count(ioapic);
2217 struct ioapic *ip = &ioapics[ioapic];
2218 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2219 struct irq_domain *parent;
2220 struct fwnode_handle *fn;
2221 struct irq_fwspec fwspec;
2222
2223 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2224 return 0;
2225
2226 /* Handle device tree enumerated APICs proper */
2227 if (cfg->dev) {
2228 fn = of_node_to_fwnode(cfg->dev);
2229 } else {
2230 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2231 if (!fn)
2232 return -ENOMEM;
2233 }
2234
2235 fwspec.fwnode = fn;
2236 fwspec.param_count = 1;
2237 fwspec.param[0] = mpc_ioapic_id(ioapic);
2238
2239 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_GENERIC_MSI);
2240 if (!parent) {
2241 if (!cfg->dev)
2242 irq_domain_free_fwnode(fn);
2243 return -ENODEV;
2244 }
2245
2246 ip->irqdomain = irq_domain_create_hierarchy(parent, 0, hwirqs, fn, cfg->ops,
2247 (void *)(long)ioapic);
2248 if (!ip->irqdomain) {
2249 /* Release fw handle if it was allocated above */
2250 if (!cfg->dev)
2251 irq_domain_free_fwnode(fn);
2252 return -ENOMEM;
2253 }
2254
2255 if (cfg->type == IOAPIC_DOMAIN_LEGACY || cfg->type == IOAPIC_DOMAIN_STRICT)
2256 ioapic_dynirq_base = max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1);
2257
2258 return 0;
2259}
2260
2261static void ioapic_destroy_irqdomain(int idx)
2262{
2263 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2264 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2265
2266 if (ioapics[idx].irqdomain) {
2267 irq_domain_remove(ioapics[idx].irqdomain);
2268 if (!cfg->dev)
2269 irq_domain_free_fwnode(fn);
2270 ioapics[idx].irqdomain = NULL;
2271 }
2272}
2273
2274void __init setup_IO_APIC(void)
2275{
2276 int ioapic;
2277
2278 if (ioapic_is_disabled || !nr_ioapics)
2279 return;
2280
2281 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2282
2283 apic_pr_verbose("ENABLING IO-APIC IRQs\n");
2284 for_each_ioapic(ioapic)
2285 BUG_ON(mp_irqdomain_create(ioapic));
2286
2287 /* Set up IO-APIC IRQ routing. */
2288 x86_init.mpparse.setup_ioapic_ids();
2289
2290 sync_Arb_IDs();
2291 setup_IO_APIC_irqs();
2292 init_IO_APIC_traps();
2293 if (nr_legacy_irqs())
2294 check_timer();
2295
2296 ioapic_initialized = 1;
2297}
2298
2299static void resume_ioapic_id(int ioapic_idx)
2300{
2301 union IO_APIC_reg_00 reg_00;
2302
2303 guard(raw_spinlock_irqsave)(&ioapic_lock);
2304 reg_00.raw = io_apic_read(ioapic_idx, 0);
2305 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2306 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2307 io_apic_write(ioapic_idx, 0, reg_00.raw);
2308 }
2309}
2310
2311static void ioapic_resume(void)
2312{
2313 int ioapic_idx;
2314
2315 for_each_ioapic_reverse(ioapic_idx)
2316 resume_ioapic_id(ioapic_idx);
2317
2318 restore_ioapic_entries();
2319}
2320
2321static struct syscore_ops ioapic_syscore_ops = {
2322 .suspend = save_ioapic_entries,
2323 .resume = ioapic_resume,
2324};
2325
2326static int __init ioapic_init_ops(void)
2327{
2328 register_syscore_ops(&ioapic_syscore_ops);
2329
2330 return 0;
2331}
2332
2333device_initcall(ioapic_init_ops);
2334
2335static int io_apic_get_redir_entries(int ioapic)
2336{
2337 union IO_APIC_reg_01 reg_01;
2338
2339 guard(raw_spinlock_irqsave)(&ioapic_lock);
2340 reg_01.raw = io_apic_read(ioapic, 1);
2341
2342 /*
2343 * The register returns the maximum index redir index supported,
2344 * which is one less than the total number of redir entries.
2345 */
2346 return reg_01.bits.entries + 1;
2347}
2348
2349unsigned int arch_dynirq_lower_bound(unsigned int from)
2350{
2351 unsigned int ret;
2352
2353 /*
2354 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2355 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2356 */
2357 ret = ioapic_dynirq_base ? : gsi_top;
2358
2359 /*
2360 * For DT enabled machines ioapic_dynirq_base is irrelevant and
2361 * always 0. gsi_top can be 0 if there is no IO/APIC registered.
2362 * 0 is an invalid interrupt number for dynamic allocations. Return
2363 * @from instead.
2364 */
2365 return ret ? : from;
2366}
2367
2368#ifdef CONFIG_X86_32
2369static int io_apic_get_unique_id(int ioapic, int apic_id)
2370{
2371 static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC);
2372 const u32 broadcast_id = 0xF;
2373 union IO_APIC_reg_00 reg_00;
2374 int i = 0;
2375
2376 /* Initialize the ID map */
2377 if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC))
2378 copy_phys_cpu_present_map(apic_id_map);
2379
2380 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
2381 reg_00.raw = io_apic_read(ioapic, 0);
2382
2383 if (apic_id >= broadcast_id) {
2384 pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n",
2385 ioapic, apic_id, reg_00.bits.ID);
2386 apic_id = reg_00.bits.ID;
2387 }
2388
2389 /* Every APIC in a system must have a unique ID */
2390 if (test_bit(apic_id, apic_id_map)) {
2391 for (i = 0; i < broadcast_id; i++) {
2392 if (!test_bit(i, apic_id_map))
2393 break;
2394 }
2395
2396 if (i == broadcast_id)
2397 panic("Max apic_id exceeded!\n");
2398
2399 pr_warn("IOAPIC[%d]: apic_id %d already used, trying %d\n", ioapic, apic_id, i);
2400 apic_id = i;
2401 }
2402
2403 set_bit(apic_id, apic_id_map);
2404
2405 if (reg_00.bits.ID != apic_id) {
2406 reg_00.bits.ID = apic_id;
2407
2408 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
2409 io_apic_write(ioapic, 0, reg_00.raw);
2410 reg_00.raw = io_apic_read(ioapic, 0);
2411 }
2412
2413 /* Sanity check */
2414 if (reg_00.bits.ID != apic_id) {
2415 pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2416 return -1;
2417 }
2418 }
2419
2420 apic_pr_verbose("IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2421
2422 return apic_id;
2423}
2424
2425static u8 io_apic_unique_id(int idx, u8 id)
2426{
2427 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && !APIC_XAPIC(boot_cpu_apic_version))
2428 return io_apic_get_unique_id(idx, id);
2429 return id;
2430}
2431#else
2432static u8 io_apic_unique_id(int idx, u8 id)
2433{
2434 union IO_APIC_reg_00 reg_00;
2435 DECLARE_BITMAP(used, 256);
2436 u8 new_id;
2437 int i;
2438
2439 bitmap_zero(used, 256);
2440 for_each_ioapic(i)
2441 __set_bit(mpc_ioapic_id(i), used);
2442
2443 /* Hand out the requested id if available */
2444 if (!test_bit(id, used))
2445 return id;
2446
2447 /*
2448 * Read the current id from the ioapic and keep it if
2449 * available.
2450 */
2451 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
2452 reg_00.raw = io_apic_read(idx, 0);
2453
2454 new_id = reg_00.bits.ID;
2455 if (!test_bit(new_id, used)) {
2456 apic_pr_verbose("IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2457 idx, new_id, id);
2458 return new_id;
2459 }
2460
2461 /* Get the next free id and write it to the ioapic. */
2462 new_id = find_first_zero_bit(used, 256);
2463 reg_00.bits.ID = new_id;
2464 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
2465 io_apic_write(idx, 0, reg_00.raw);
2466 reg_00.raw = io_apic_read(idx, 0);
2467 }
2468 /* Sanity check */
2469 BUG_ON(reg_00.bits.ID != new_id);
2470
2471 return new_id;
2472}
2473#endif
2474
2475static int io_apic_get_version(int ioapic)
2476{
2477 union IO_APIC_reg_01 reg_01;
2478
2479 guard(raw_spinlock_irqsave)(&ioapic_lock);
2480 reg_01.raw = io_apic_read(ioapic, 1);
2481
2482 return reg_01.bits.version;
2483}
2484
2485/*
2486 * This function updates target affinity of IOAPIC interrupts to include
2487 * the CPUs which came online during SMP bringup.
2488 */
2489#define IOAPIC_RESOURCE_NAME_SIZE 11
2490
2491static struct resource *ioapic_resources;
2492
2493static struct resource * __init ioapic_setup_resources(void)
2494{
2495 struct resource *res;
2496 unsigned long n;
2497 char *mem;
2498 int i;
2499
2500 if (nr_ioapics == 0)
2501 return NULL;
2502
2503 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2504 n *= nr_ioapics;
2505
2506 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2507 if (!mem)
2508 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2509 res = (void *)mem;
2510
2511 mem += sizeof(struct resource) * nr_ioapics;
2512
2513 for_each_ioapic(i) {
2514 res[i].name = mem;
2515 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2516 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2517 mem += IOAPIC_RESOURCE_NAME_SIZE;
2518 ioapics[i].iomem_res = &res[i];
2519 }
2520
2521 ioapic_resources = res;
2522
2523 return res;
2524}
2525
2526static void io_apic_set_fixmap(enum fixed_addresses idx, phys_addr_t phys)
2527{
2528 pgprot_t flags = FIXMAP_PAGE_NOCACHE;
2529
2530 /*
2531 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot
2532 * bits, just like normal ioremap():
2533 */
2534 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
2535 if (x86_platform.hyper.is_private_mmio(phys))
2536 flags = pgprot_encrypted(flags);
2537 else
2538 flags = pgprot_decrypted(flags);
2539 }
2540
2541 __set_fixmap(idx, phys, flags);
2542}
2543
2544void __init io_apic_init_mappings(void)
2545{
2546 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2547 struct resource *ioapic_res;
2548 int i;
2549
2550 ioapic_res = ioapic_setup_resources();
2551 for_each_ioapic(i) {
2552 if (smp_found_config) {
2553 ioapic_phys = mpc_ioapic_addr(i);
2554#ifdef CONFIG_X86_32
2555 if (!ioapic_phys) {
2556 pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, "
2557 "disabling IO/APIC support!\n");
2558 smp_found_config = 0;
2559 ioapic_is_disabled = true;
2560 goto fake_ioapic_page;
2561 }
2562#endif
2563 } else {
2564#ifdef CONFIG_X86_32
2565fake_ioapic_page:
2566#endif
2567 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2568 PAGE_SIZE);
2569 if (!ioapic_phys)
2570 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2571 __func__, PAGE_SIZE, PAGE_SIZE);
2572 ioapic_phys = __pa(ioapic_phys);
2573 }
2574 io_apic_set_fixmap(idx, ioapic_phys);
2575 apic_pr_verbose("mapped IOAPIC to %08lx (%08lx)\n",
2576 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys);
2577 idx++;
2578
2579 ioapic_res->start = ioapic_phys;
2580 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2581 ioapic_res++;
2582 }
2583}
2584
2585void __init ioapic_insert_resources(void)
2586{
2587 struct resource *r = ioapic_resources;
2588 int i;
2589
2590 if (!r) {
2591 if (nr_ioapics > 0)
2592 pr_err("IO APIC resources couldn't be allocated.\n");
2593 return;
2594 }
2595
2596 for_each_ioapic(i) {
2597 insert_resource(&iomem_resource, r);
2598 r++;
2599 }
2600}
2601
2602int mp_find_ioapic(u32 gsi)
2603{
2604 int i;
2605
2606 if (nr_ioapics == 0)
2607 return -1;
2608
2609 /* Find the IOAPIC that manages this GSI. */
2610 for_each_ioapic(i) {
2611 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2612
2613 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2614 return i;
2615 }
2616
2617 pr_err("ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2618 return -1;
2619}
2620
2621int mp_find_ioapic_pin(int ioapic, u32 gsi)
2622{
2623 struct mp_ioapic_gsi *gsi_cfg;
2624
2625 if (WARN_ON(ioapic < 0))
2626 return -1;
2627
2628 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2629 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2630 return -1;
2631
2632 return gsi - gsi_cfg->gsi_base;
2633}
2634
2635static int bad_ioapic_register(int idx)
2636{
2637 union IO_APIC_reg_00 reg_00;
2638 union IO_APIC_reg_01 reg_01;
2639 union IO_APIC_reg_02 reg_02;
2640
2641 reg_00.raw = io_apic_read(idx, 0);
2642 reg_01.raw = io_apic_read(idx, 1);
2643 reg_02.raw = io_apic_read(idx, 2);
2644
2645 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2646 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2647 mpc_ioapic_addr(idx));
2648 return 1;
2649 }
2650
2651 return 0;
2652}
2653
2654static int find_free_ioapic_entry(void)
2655{
2656 for (int idx = 0; idx < MAX_IO_APICS; idx++) {
2657 if (ioapics[idx].nr_registers == 0)
2658 return idx;
2659 }
2660 return MAX_IO_APICS;
2661}
2662
2663/**
2664 * mp_register_ioapic - Register an IOAPIC device
2665 * @id: hardware IOAPIC ID
2666 * @address: physical address of IOAPIC register area
2667 * @gsi_base: base of GSI associated with the IOAPIC
2668 * @cfg: configuration information for the IOAPIC
2669 */
2670int mp_register_ioapic(int id, u32 address, u32 gsi_base, struct ioapic_domain_cfg *cfg)
2671{
2672 bool hotplug = !!ioapic_initialized;
2673 struct mp_ioapic_gsi *gsi_cfg;
2674 int idx, ioapic, entries;
2675 u32 gsi_end;
2676
2677 if (!address) {
2678 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2679 return -EINVAL;
2680 }
2681
2682 for_each_ioapic(ioapic) {
2683 if (ioapics[ioapic].mp_config.apicaddr == address) {
2684 pr_warn("address 0x%x conflicts with IOAPIC%d\n", address, ioapic);
2685 return -EEXIST;
2686 }
2687 }
2688
2689 idx = find_free_ioapic_entry();
2690 if (idx >= MAX_IO_APICS) {
2691 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2692 MAX_IO_APICS, idx);
2693 return -ENOSPC;
2694 }
2695
2696 ioapics[idx].mp_config.type = MP_IOAPIC;
2697 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2698 ioapics[idx].mp_config.apicaddr = address;
2699
2700 io_apic_set_fixmap(FIX_IO_APIC_BASE_0 + idx, address);
2701 if (bad_ioapic_register(idx)) {
2702 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2703 return -ENODEV;
2704 }
2705
2706 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2707 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2708
2709 /*
2710 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2711 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2712 */
2713 entries = io_apic_get_redir_entries(idx);
2714 gsi_end = gsi_base + entries - 1;
2715 for_each_ioapic(ioapic) {
2716 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2717 if ((gsi_base >= gsi_cfg->gsi_base &&
2718 gsi_base <= gsi_cfg->gsi_end) ||
2719 (gsi_end >= gsi_cfg->gsi_base &&
2720 gsi_end <= gsi_cfg->gsi_end)) {
2721 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2722 gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2723 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2724 return -ENOSPC;
2725 }
2726 }
2727 gsi_cfg = mp_ioapic_gsi_routing(idx);
2728 gsi_cfg->gsi_base = gsi_base;
2729 gsi_cfg->gsi_end = gsi_end;
2730
2731 ioapics[idx].irqdomain = NULL;
2732 ioapics[idx].irqdomain_cfg = *cfg;
2733
2734 /*
2735 * If mp_register_ioapic() is called during early boot stage when
2736 * walking ACPI/DT tables, it's too early to create irqdomain,
2737 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2738 */
2739 if (hotplug) {
2740 if (mp_irqdomain_create(idx)) {
2741 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2742 return -ENOMEM;
2743 }
2744 alloc_ioapic_saved_registers(idx);
2745 }
2746
2747 if (gsi_cfg->gsi_end >= gsi_top)
2748 gsi_top = gsi_cfg->gsi_end + 1;
2749 if (nr_ioapics <= idx)
2750 nr_ioapics = idx + 1;
2751
2752 /* Set nr_registers to mark entry present */
2753 ioapics[idx].nr_registers = entries;
2754
2755 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2756 idx, mpc_ioapic_id(idx), mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2757 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2758
2759 return 0;
2760}
2761
2762int mp_unregister_ioapic(u32 gsi_base)
2763{
2764 int ioapic, pin;
2765 int found = 0;
2766
2767 for_each_ioapic(ioapic) {
2768 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2769 found = 1;
2770 break;
2771 }
2772 }
2773
2774 if (!found) {
2775 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2776 return -ENODEV;
2777 }
2778
2779 for_each_pin(ioapic, pin) {
2780 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2781 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2782 struct mp_chip_data *data;
2783
2784 if (irq >= 0) {
2785 data = irq_get_chip_data(irq);
2786 if (data && data->count) {
2787 pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic);
2788 return -EBUSY;
2789 }
2790 }
2791 }
2792
2793 /* Mark entry not present */
2794 ioapics[ioapic].nr_registers = 0;
2795 ioapic_destroy_irqdomain(ioapic);
2796 free_ioapic_saved_registers(ioapic);
2797 if (ioapics[ioapic].iomem_res)
2798 release_resource(ioapics[ioapic].iomem_res);
2799 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2800 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2801
2802 return 0;
2803}
2804
2805int mp_ioapic_registered(u32 gsi_base)
2806{
2807 int ioapic;
2808
2809 for_each_ioapic(ioapic)
2810 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2811 return 1;
2812
2813 return 0;
2814}
2815
2816static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2817 struct irq_alloc_info *info)
2818{
2819 if (info && info->ioapic.valid) {
2820 data->is_level = info->ioapic.is_level;
2821 data->active_low = info->ioapic.active_low;
2822 } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_low) < 0) {
2823 /* PCI interrupts are always active low level triggered. */
2824 data->is_level = true;
2825 data->active_low = true;
2826 }
2827}
2828
2829/*
2830 * Configure the I/O-APIC specific fields in the routing entry.
2831 *
2832 * This is important to setup the I/O-APIC specific bits (is_level,
2833 * active_low, masked) because the underlying parent domain will only
2834 * provide the routing information and is oblivious of the I/O-APIC
2835 * specific bits.
2836 *
2837 * The entry is just preconfigured at this point and not written into the
2838 * RTE. This happens later during activation which will fill in the actual
2839 * routing information.
2840 */
2841static void mp_preconfigure_entry(struct mp_chip_data *data)
2842{
2843 struct IO_APIC_route_entry *entry = &data->entry;
2844
2845 memset(entry, 0, sizeof(*entry));
2846 entry->is_level = data->is_level;
2847 entry->active_low = data->active_low;
2848 /*
2849 * Mask level triggered irqs. Edge triggered irqs are masked
2850 * by the irq core code in case they fire.
2851 */
2852 entry->masked = data->is_level;
2853}
2854
2855int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2856 unsigned int nr_irqs, void *arg)
2857{
2858 struct irq_alloc_info *info = arg;
2859 struct mp_chip_data *data;
2860 struct irq_data *irq_data;
2861 int ret, ioapic, pin;
2862 unsigned long flags;
2863
2864 if (!info || nr_irqs > 1)
2865 return -EINVAL;
2866 irq_data = irq_domain_get_irq_data(domain, virq);
2867 if (!irq_data)
2868 return -EINVAL;
2869
2870 ioapic = mp_irqdomain_ioapic_idx(domain);
2871 pin = info->ioapic.pin;
2872 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2873 return -EEXIST;
2874
2875 data = kzalloc(sizeof(*data), GFP_KERNEL);
2876 if (!data)
2877 return -ENOMEM;
2878
2879 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2880 if (ret < 0)
2881 goto free_data;
2882
2883 INIT_LIST_HEAD(&data->irq_2_pin);
2884 irq_data->hwirq = info->ioapic.pin;
2885 irq_data->chip = (domain->parent == x86_vector_domain) ?
2886 &ioapic_chip : &ioapic_ir_chip;
2887 irq_data->chip_data = data;
2888 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2889
2890 if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)) {
2891 ret = -ENOMEM;
2892 goto free_irqs;
2893 }
2894
2895 mp_preconfigure_entry(data);
2896 mp_register_handler(virq, data->is_level);
2897
2898 local_irq_save(flags);
2899 if (virq < nr_legacy_irqs())
2900 legacy_pic->mask(virq);
2901 local_irq_restore(flags);
2902
2903 apic_pr_verbose("IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
2904 ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_low);
2905 return 0;
2906
2907free_irqs:
2908 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2909free_data:
2910 kfree(data);
2911 return ret;
2912}
2913
2914void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2915 unsigned int nr_irqs)
2916{
2917 struct irq_data *irq_data;
2918 struct mp_chip_data *data;
2919
2920 BUG_ON(nr_irqs != 1);
2921 irq_data = irq_domain_get_irq_data(domain, virq);
2922 if (irq_data && irq_data->chip_data) {
2923 data = irq_data->chip_data;
2924 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
2925 WARN_ON(!list_empty(&data->irq_2_pin));
2926 kfree(irq_data->chip_data);
2927 }
2928 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2929}
2930
2931int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_data, bool reserve)
2932{
2933 guard(raw_spinlock_irqsave)(&ioapic_lock);
2934 ioapic_configure_entry(irq_data);
2935 return 0;
2936}
2937
2938void mp_irqdomain_deactivate(struct irq_domain *domain,
2939 struct irq_data *irq_data)
2940{
2941 /* It won't be called for IRQ with multiple IOAPIC pins associated */
2942 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
2943}
2944
2945int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
2946{
2947 return (int)(long)domain->host_data;
2948}
2949
2950const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
2951 .alloc = mp_irqdomain_alloc,
2952 .free = mp_irqdomain_free,
2953 .activate = mp_irqdomain_activate,
2954 .deactivate = mp_irqdomain_deactivate,
2955};