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1/*
2 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <asm/sizes.h>
15
16#include <plat/omap_hwmod.h>
17#include <plat/serial.h>
18#include <plat/l3_2xxx.h>
19#include <plat/l4_2xxx.h>
20
21#include "omap_hwmod_common_data.h"
22
23static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
24 {
25 .pa_start = OMAP2_UART1_BASE,
26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
27 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
28 },
29 { }
30};
31
32static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
33 {
34 .pa_start = OMAP2_UART2_BASE,
35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
36 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
37 },
38 { }
39};
40
41static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
42 {
43 .pa_start = OMAP2_UART3_BASE,
44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
45 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
46 },
47 { }
48};
49
50static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
51 {
52 .pa_start = 0x4802a000,
53 .pa_end = 0x4802a000 + SZ_1K - 1,
54 .flags = ADDR_TYPE_RT
55 },
56 { }
57};
58
59static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
60 {
61 .pa_start = 0x48078000,
62 .pa_end = 0x48078000 + SZ_1K - 1,
63 .flags = ADDR_TYPE_RT
64 },
65 { }
66};
67
68static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
69 {
70 .pa_start = 0x4807a000,
71 .pa_end = 0x4807a000 + SZ_1K - 1,
72 .flags = ADDR_TYPE_RT
73 },
74 { }
75};
76
77static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
78 {
79 .pa_start = 0x4807c000,
80 .pa_end = 0x4807c000 + SZ_1K - 1,
81 .flags = ADDR_TYPE_RT
82 },
83 { }
84};
85
86static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
87 {
88 .pa_start = 0x4807e000,
89 .pa_end = 0x4807e000 + SZ_1K - 1,
90 .flags = ADDR_TYPE_RT
91 },
92 { }
93};
94
95static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
96 {
97 .pa_start = 0x48080000,
98 .pa_end = 0x48080000 + SZ_1K - 1,
99 .flags = ADDR_TYPE_RT
100 },
101 { }
102};
103
104static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
105 {
106 .pa_start = 0x48082000,
107 .pa_end = 0x48082000 + SZ_1K - 1,
108 .flags = ADDR_TYPE_RT
109 },
110 { }
111};
112
113static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
114 {
115 .pa_start = 0x48084000,
116 .pa_end = 0x48084000 + SZ_1K - 1,
117 .flags = ADDR_TYPE_RT
118 },
119 { }
120};
121
122struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
123 {
124 .name = "mpu",
125 .pa_start = 0x48076000,
126 .pa_end = 0x480760ff,
127 .flags = ADDR_TYPE_RT
128 },
129 { }
130};
131
132/*
133 * Common interconnect data
134 */
135
136/* L3 -> L4_CORE interface */
137struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
138 .master = &omap2xxx_l3_main_hwmod,
139 .slave = &omap2xxx_l4_core_hwmod,
140 .user = OCP_USER_MPU | OCP_USER_SDMA,
141};
142
143/* MPU -> L3 interface */
144struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
145 .master = &omap2xxx_mpu_hwmod,
146 .slave = &omap2xxx_l3_main_hwmod,
147 .user = OCP_USER_MPU,
148};
149
150/* DSS -> l3 */
151struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
152 .master = &omap2xxx_dss_core_hwmod,
153 .slave = &omap2xxx_l3_main_hwmod,
154 .fw = {
155 .omap2 = {
156 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
157 .flags = OMAP_FIREWALL_L3,
158 }
159 },
160 .user = OCP_USER_MPU | OCP_USER_SDMA,
161};
162
163/* L4_CORE -> L4_WKUP interface */
164struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
165 .master = &omap2xxx_l4_core_hwmod,
166 .slave = &omap2xxx_l4_wkup_hwmod,
167 .user = OCP_USER_MPU | OCP_USER_SDMA,
168};
169
170/* L4 CORE -> UART1 interface */
171struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
172 .master = &omap2xxx_l4_core_hwmod,
173 .slave = &omap2xxx_uart1_hwmod,
174 .clk = "uart1_ick",
175 .addr = omap2xxx_uart1_addr_space,
176 .user = OCP_USER_MPU | OCP_USER_SDMA,
177};
178
179/* L4 CORE -> UART2 interface */
180struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
181 .master = &omap2xxx_l4_core_hwmod,
182 .slave = &omap2xxx_uart2_hwmod,
183 .clk = "uart2_ick",
184 .addr = omap2xxx_uart2_addr_space,
185 .user = OCP_USER_MPU | OCP_USER_SDMA,
186};
187
188/* L4 PER -> UART3 interface */
189struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
190 .master = &omap2xxx_l4_core_hwmod,
191 .slave = &omap2xxx_uart3_hwmod,
192 .clk = "uart3_ick",
193 .addr = omap2xxx_uart3_addr_space,
194 .user = OCP_USER_MPU | OCP_USER_SDMA,
195};
196
197/* l4 core -> mcspi1 interface */
198struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
199 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_mcspi1_hwmod,
201 .clk = "mcspi1_ick",
202 .addr = omap2_mcspi1_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
204};
205
206/* l4 core -> mcspi2 interface */
207struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
208 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_mcspi2_hwmod,
210 .clk = "mcspi2_ick",
211 .addr = omap2_mcspi2_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA,
213};
214
215/* l4_core -> timer2 */
216struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
217 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_timer2_hwmod,
219 .clk = "gpt2_ick",
220 .addr = omap2xxx_timer2_addrs,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
222};
223
224/* l4_core -> timer3 */
225struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
226 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_timer3_hwmod,
228 .clk = "gpt3_ick",
229 .addr = omap2xxx_timer3_addrs,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
233/* l4_core -> timer4 */
234struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
235 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_timer4_hwmod,
237 .clk = "gpt4_ick",
238 .addr = omap2xxx_timer4_addrs,
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240};
241
242/* l4_core -> timer5 */
243struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer5_hwmod,
246 .clk = "gpt5_ick",
247 .addr = omap2xxx_timer5_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
249};
250
251/* l4_core -> timer6 */
252struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer6_hwmod,
255 .clk = "gpt6_ick",
256 .addr = omap2xxx_timer6_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA,
258};
259
260/* l4_core -> timer7 */
261struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
262 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer7_hwmod,
264 .clk = "gpt7_ick",
265 .addr = omap2xxx_timer7_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
267};
268
269/* l4_core -> timer8 */
270struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
271 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer8_hwmod,
273 .clk = "gpt8_ick",
274 .addr = omap2xxx_timer8_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA,
276};
277
278/* l4_core -> timer9 */
279struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
280 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer9_hwmod,
282 .clk = "gpt9_ick",
283 .addr = omap2xxx_timer9_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285};
286
287/* l4_core -> timer10 */
288struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
289 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer10_hwmod,
291 .clk = "gpt10_ick",
292 .addr = omap2_timer10_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA,
294};
295
296/* l4_core -> timer11 */
297struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
298 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer11_hwmod,
300 .clk = "gpt11_ick",
301 .addr = omap2_timer11_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
303};
304
305/* l4_core -> timer12 */
306struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
307 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer12_hwmod,
309 .clk = "gpt12_ick",
310 .addr = omap2xxx_timer12_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
312};
313
314/* l4_core -> dss */
315struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
316 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_dss_core_hwmod,
318 .clk = "dss_ick",
319 .addr = omap2_dss_addrs,
320 .fw = {
321 .omap2 = {
322 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
323 .flags = OMAP_FIREWALL_L4,
324 }
325 },
326 .user = OCP_USER_MPU | OCP_USER_SDMA,
327};
328
329/* l4_core -> dss_dispc */
330struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
331 .master = &omap2xxx_l4_core_hwmod,
332 .slave = &omap2xxx_dss_dispc_hwmod,
333 .clk = "dss_ick",
334 .addr = omap2_dss_dispc_addrs,
335 .fw = {
336 .omap2 = {
337 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
338 .flags = OMAP_FIREWALL_L4,
339 }
340 },
341 .user = OCP_USER_MPU | OCP_USER_SDMA,
342};
343
344/* l4_core -> dss_rfbi */
345struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
346 .master = &omap2xxx_l4_core_hwmod,
347 .slave = &omap2xxx_dss_rfbi_hwmod,
348 .clk = "dss_ick",
349 .addr = omap2_dss_rfbi_addrs,
350 .fw = {
351 .omap2 = {
352 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
353 .flags = OMAP_FIREWALL_L4,
354 }
355 },
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357};
358
359/* l4_core -> dss_venc */
360struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
361 .master = &omap2xxx_l4_core_hwmod,
362 .slave = &omap2xxx_dss_venc_hwmod,
363 .clk = "dss_ick",
364 .addr = omap2_dss_venc_addrs,
365 .fw = {
366 .omap2 = {
367 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
368 .flags = OMAP_FIREWALL_L4,
369 }
370 },
371 .flags = OCPIF_SWSUP_IDLE,
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
374
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Paul Walmsley
7 *
8 * XXX handle crossbar/shared link difference for L3?
9 * XXX these should be marked initdata for multi-OMAP kernels
10 */
11#include <linux/sizes.h>
12
13#include "omap_hwmod.h"
14#include "l3_2xxx.h"
15#include "l4_2xxx.h"
16
17#include "omap_hwmod_common_data.h"
18
19/*
20 * Common interconnect data
21 */
22
23/* L3 -> L4_CORE interface */
24struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
25 .master = &omap2xxx_l3_main_hwmod,
26 .slave = &omap2xxx_l4_core_hwmod,
27 .user = OCP_USER_MPU | OCP_USER_SDMA,
28};
29
30/* MPU -> L3 interface */
31struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
32 .master = &omap2xxx_mpu_hwmod,
33 .slave = &omap2xxx_l3_main_hwmod,
34 .user = OCP_USER_MPU,
35};
36
37/* DSS -> l3 */
38struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
39 .master = &omap2xxx_dss_core_hwmod,
40 .slave = &omap2xxx_l3_main_hwmod,
41 .fw = {
42 .omap2 = {
43 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
44 .flags = OMAP_FIREWALL_L3,
45 },
46 },
47 .user = OCP_USER_MPU | OCP_USER_SDMA,
48};
49
50/* L4_CORE -> L4_WKUP interface */
51struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
52 .master = &omap2xxx_l4_core_hwmod,
53 .slave = &omap2xxx_l4_wkup_hwmod,
54 .user = OCP_USER_MPU | OCP_USER_SDMA,
55};
56
57/* L4 CORE -> UART1 interface */
58struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
59 .master = &omap2xxx_l4_core_hwmod,
60 .slave = &omap2xxx_uart1_hwmod,
61 .clk = "uart1_ick",
62 .user = OCP_USER_MPU | OCP_USER_SDMA,
63};
64
65/* L4 CORE -> UART2 interface */
66struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
67 .master = &omap2xxx_l4_core_hwmod,
68 .slave = &omap2xxx_uart2_hwmod,
69 .clk = "uart2_ick",
70 .user = OCP_USER_MPU | OCP_USER_SDMA,
71};
72
73/* L4 PER -> UART3 interface */
74struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
75 .master = &omap2xxx_l4_core_hwmod,
76 .slave = &omap2xxx_uart3_hwmod,
77 .clk = "uart3_ick",
78 .user = OCP_USER_MPU | OCP_USER_SDMA,
79};
80
81/* l4 core -> mcspi1 interface */
82struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
83 .master = &omap2xxx_l4_core_hwmod,
84 .slave = &omap2xxx_mcspi1_hwmod,
85 .clk = "mcspi1_ick",
86 .user = OCP_USER_MPU | OCP_USER_SDMA,
87};
88
89/* l4 core -> mcspi2 interface */
90struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
91 .master = &omap2xxx_l4_core_hwmod,
92 .slave = &omap2xxx_mcspi2_hwmod,
93 .clk = "mcspi2_ick",
94 .user = OCP_USER_MPU | OCP_USER_SDMA,
95};
96
97/* l4_core -> timer3 */
98struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
99 .master = &omap2xxx_l4_core_hwmod,
100 .slave = &omap2xxx_timer3_hwmod,
101 .clk = "gpt3_ick",
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
103};
104
105/* l4_core -> timer4 */
106struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
107 .master = &omap2xxx_l4_core_hwmod,
108 .slave = &omap2xxx_timer4_hwmod,
109 .clk = "gpt4_ick",
110 .user = OCP_USER_MPU | OCP_USER_SDMA,
111};
112
113/* l4_core -> timer5 */
114struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
115 .master = &omap2xxx_l4_core_hwmod,
116 .slave = &omap2xxx_timer5_hwmod,
117 .clk = "gpt5_ick",
118 .user = OCP_USER_MPU | OCP_USER_SDMA,
119};
120
121/* l4_core -> timer6 */
122struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
123 .master = &omap2xxx_l4_core_hwmod,
124 .slave = &omap2xxx_timer6_hwmod,
125 .clk = "gpt6_ick",
126 .user = OCP_USER_MPU | OCP_USER_SDMA,
127};
128
129/* l4_core -> timer7 */
130struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
131 .master = &omap2xxx_l4_core_hwmod,
132 .slave = &omap2xxx_timer7_hwmod,
133 .clk = "gpt7_ick",
134 .user = OCP_USER_MPU | OCP_USER_SDMA,
135};
136
137/* l4_core -> timer8 */
138struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
139 .master = &omap2xxx_l4_core_hwmod,
140 .slave = &omap2xxx_timer8_hwmod,
141 .clk = "gpt8_ick",
142 .user = OCP_USER_MPU | OCP_USER_SDMA,
143};
144
145/* l4_core -> timer9 */
146struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
147 .master = &omap2xxx_l4_core_hwmod,
148 .slave = &omap2xxx_timer9_hwmod,
149 .clk = "gpt9_ick",
150 .user = OCP_USER_MPU | OCP_USER_SDMA,
151};
152
153/* l4_core -> timer10 */
154struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
155 .master = &omap2xxx_l4_core_hwmod,
156 .slave = &omap2xxx_timer10_hwmod,
157 .clk = "gpt10_ick",
158 .user = OCP_USER_MPU | OCP_USER_SDMA,
159};
160
161/* l4_core -> timer11 */
162struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
163 .master = &omap2xxx_l4_core_hwmod,
164 .slave = &omap2xxx_timer11_hwmod,
165 .clk = "gpt11_ick",
166 .user = OCP_USER_MPU | OCP_USER_SDMA,
167};
168
169/* l4_core -> timer12 */
170struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
171 .master = &omap2xxx_l4_core_hwmod,
172 .slave = &omap2xxx_timer12_hwmod,
173 .clk = "gpt12_ick",
174 .user = OCP_USER_MPU | OCP_USER_SDMA,
175};
176
177/* l4_core -> dss */
178struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
179 .master = &omap2xxx_l4_core_hwmod,
180 .slave = &omap2xxx_dss_core_hwmod,
181 .clk = "dss_ick",
182 .fw = {
183 .omap2 = {
184 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
185 .flags = OMAP_FIREWALL_L4,
186 },
187 },
188 .user = OCP_USER_MPU | OCP_USER_SDMA,
189};
190
191/* l4_core -> dss_dispc */
192struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
193 .master = &omap2xxx_l4_core_hwmod,
194 .slave = &omap2xxx_dss_dispc_hwmod,
195 .clk = "dss_ick",
196 .fw = {
197 .omap2 = {
198 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
199 .flags = OMAP_FIREWALL_L4,
200 },
201 },
202 .user = OCP_USER_MPU | OCP_USER_SDMA,
203};
204
205/* l4_core -> dss_rfbi */
206struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
207 .master = &omap2xxx_l4_core_hwmod,
208 .slave = &omap2xxx_dss_rfbi_hwmod,
209 .clk = "dss_ick",
210 .fw = {
211 .omap2 = {
212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
213 .flags = OMAP_FIREWALL_L4,
214 },
215 },
216 .user = OCP_USER_MPU | OCP_USER_SDMA,
217};
218
219/* l4_core -> dss_venc */
220struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
221 .master = &omap2xxx_l4_core_hwmod,
222 .slave = &omap2xxx_dss_venc_hwmod,
223 .clk = "dss_ick",
224 .fw = {
225 .omap2 = {
226 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
227 .flags = OMAP_FIREWALL_L4,
228 },
229 },
230 .flags = OCPIF_SWSUP_IDLE,
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232};
233
234/* l4_core -> rng */
235struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
236 .master = &omap2xxx_l4_core_hwmod,
237 .slave = &omap2xxx_rng_hwmod,
238 .clk = "rng_ick",
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240};
241
242/* l4 core -> sham interface */
243struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_sham_hwmod,
246 .clk = "sha_ick",
247 .user = OCP_USER_MPU | OCP_USER_SDMA,
248};
249
250/* l4 core -> aes interface */
251struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
252 .master = &omap2xxx_l4_core_hwmod,
253 .slave = &omap2xxx_aes_hwmod,
254 .clk = "aes_ick",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256};