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1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include <plat/hardware.h>
21#include <plat/clkdev_omap.h>
22
23#include "iomap.h"
24#include "clock.h"
25#include "clock2xxx.h"
26#include "opp2xxx.h"
27#include "cm2xxx_3xxx.h"
28#include "prm2xxx_3xxx.h"
29#include "prm-regbits-24xx.h"
30#include "cm-regbits-24xx.h"
31#include "sdrc.h"
32#include "control.h"
33
34#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
35
36/*
37 * 2430 clock tree.
38 *
39 * NOTE:In many cases here we are assigning a 'default' parent. In
40 * many cases the parent is selectable. The set parent calls will
41 * also switch sources.
42 *
43 * Several sources are given initial rates which may be wrong, this will
44 * be fixed up in the init func.
45 *
46 * Things are broadly separated below by clock domains. It is
47 * noteworthy that most peripherals have dependencies on multiple clock
48 * domains. Many get their interface clocks from the L4 domain, but get
49 * functional clocks from fixed sources or other core domain derived
50 * clocks.
51 */
52
53/* Base external input clocks */
54static struct clk func_32k_ck = {
55 .name = "func_32k_ck",
56 .ops = &clkops_null,
57 .rate = 32768,
58 .clkdm_name = "wkup_clkdm",
59};
60
61static struct clk secure_32k_ck = {
62 .name = "secure_32k_ck",
63 .ops = &clkops_null,
64 .rate = 32768,
65 .clkdm_name = "wkup_clkdm",
66};
67
68/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
69static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
70 .name = "osc_ck",
71 .ops = &clkops_oscck,
72 .clkdm_name = "wkup_clkdm",
73 .recalc = &omap2_osc_clk_recalc,
74};
75
76/* Without modem likely 12MHz, with modem likely 13MHz */
77static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
78 .name = "sys_ck", /* ~ ref_clk also */
79 .ops = &clkops_null,
80 .parent = &osc_ck,
81 .clkdm_name = "wkup_clkdm",
82 .recalc = &omap2xxx_sys_clk_recalc,
83};
84
85static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
86 .name = "alt_ck",
87 .ops = &clkops_null,
88 .rate = 54000000,
89 .clkdm_name = "wkup_clkdm",
90};
91
92/* Optional external clock input for McBSP CLKS */
93static struct clk mcbsp_clks = {
94 .name = "mcbsp_clks",
95 .ops = &clkops_null,
96};
97
98/*
99 * Analog domain root source clocks
100 */
101
102/* dpll_ck, is broken out in to special cases through clksel */
103/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
104 * deal with this
105 */
106
107static struct dpll_data dpll_dd = {
108 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
109 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
110 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
111 .clk_bypass = &sys_ck,
112 .clk_ref = &sys_ck,
113 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
114 .enable_mask = OMAP24XX_EN_DPLL_MASK,
115 .max_multiplier = 1023,
116 .min_divider = 1,
117 .max_divider = 16,
118};
119
120/*
121 * XXX Cannot add round_rate here yet, as this is still a composite clock,
122 * not just a DPLL
123 */
124static struct clk dpll_ck = {
125 .name = "dpll_ck",
126 .ops = &clkops_omap2xxx_dpll_ops,
127 .parent = &sys_ck, /* Can be func_32k also */
128 .dpll_data = &dpll_dd,
129 .clkdm_name = "wkup_clkdm",
130 .recalc = &omap2_dpllcore_recalc,
131 .set_rate = &omap2_reprogram_dpllcore,
132};
133
134static struct clk apll96_ck = {
135 .name = "apll96_ck",
136 .ops = &clkops_apll96,
137 .parent = &sys_ck,
138 .rate = 96000000,
139 .flags = ENABLE_ON_INIT,
140 .clkdm_name = "wkup_clkdm",
141 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
142 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
143};
144
145static struct clk apll54_ck = {
146 .name = "apll54_ck",
147 .ops = &clkops_apll54,
148 .parent = &sys_ck,
149 .rate = 54000000,
150 .flags = ENABLE_ON_INIT,
151 .clkdm_name = "wkup_clkdm",
152 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
153 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
154};
155
156/*
157 * PRCM digital base sources
158 */
159
160/* func_54m_ck */
161
162static const struct clksel_rate func_54m_apll54_rates[] = {
163 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
164 { .div = 0 },
165};
166
167static const struct clksel_rate func_54m_alt_rates[] = {
168 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
169 { .div = 0 },
170};
171
172static const struct clksel func_54m_clksel[] = {
173 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
174 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
175 { .parent = NULL },
176};
177
178static struct clk func_54m_ck = {
179 .name = "func_54m_ck",
180 .ops = &clkops_null,
181 .parent = &apll54_ck, /* can also be alt_clk */
182 .clkdm_name = "wkup_clkdm",
183 .init = &omap2_init_clksel_parent,
184 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
185 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
186 .clksel = func_54m_clksel,
187 .recalc = &omap2_clksel_recalc,
188};
189
190static struct clk core_ck = {
191 .name = "core_ck",
192 .ops = &clkops_null,
193 .parent = &dpll_ck, /* can also be 32k */
194 .clkdm_name = "wkup_clkdm",
195 .recalc = &followparent_recalc,
196};
197
198/* func_96m_ck */
199static const struct clksel_rate func_96m_apll96_rates[] = {
200 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
201 { .div = 0 },
202};
203
204static const struct clksel_rate func_96m_alt_rates[] = {
205 { .div = 1, .val = 1, .flags = RATE_IN_243X },
206 { .div = 0 },
207};
208
209static const struct clksel func_96m_clksel[] = {
210 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
211 { .parent = &alt_ck, .rates = func_96m_alt_rates },
212 { .parent = NULL }
213};
214
215static struct clk func_96m_ck = {
216 .name = "func_96m_ck",
217 .ops = &clkops_null,
218 .parent = &apll96_ck,
219 .clkdm_name = "wkup_clkdm",
220 .init = &omap2_init_clksel_parent,
221 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
222 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
223 .clksel = func_96m_clksel,
224 .recalc = &omap2_clksel_recalc,
225};
226
227/* func_48m_ck */
228
229static const struct clksel_rate func_48m_apll96_rates[] = {
230 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
231 { .div = 0 },
232};
233
234static const struct clksel_rate func_48m_alt_rates[] = {
235 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
236 { .div = 0 },
237};
238
239static const struct clksel func_48m_clksel[] = {
240 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
241 { .parent = &alt_ck, .rates = func_48m_alt_rates },
242 { .parent = NULL }
243};
244
245static struct clk func_48m_ck = {
246 .name = "func_48m_ck",
247 .ops = &clkops_null,
248 .parent = &apll96_ck, /* 96M or Alt */
249 .clkdm_name = "wkup_clkdm",
250 .init = &omap2_init_clksel_parent,
251 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
252 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
253 .clksel = func_48m_clksel,
254 .recalc = &omap2_clksel_recalc,
255 .round_rate = &omap2_clksel_round_rate,
256 .set_rate = &omap2_clksel_set_rate
257};
258
259static struct clk func_12m_ck = {
260 .name = "func_12m_ck",
261 .ops = &clkops_null,
262 .parent = &func_48m_ck,
263 .fixed_div = 4,
264 .clkdm_name = "wkup_clkdm",
265 .recalc = &omap_fixed_divisor_recalc,
266};
267
268/* Secure timer, only available in secure mode */
269static struct clk wdt1_osc_ck = {
270 .name = "ck_wdt1_osc",
271 .ops = &clkops_null, /* RMK: missing? */
272 .parent = &osc_ck,
273 .recalc = &followparent_recalc,
274};
275
276/*
277 * The common_clkout* clksel_rate structs are common to
278 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
279 * sys_clkout2_* are 2420-only, so the
280 * clksel_rate flags fields are inaccurate for those clocks. This is
281 * harmless since access to those clocks are gated by the struct clk
282 * flags fields, which mark them as 2420-only.
283 */
284static const struct clksel_rate common_clkout_src_core_rates[] = {
285 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
286 { .div = 0 }
287};
288
289static const struct clksel_rate common_clkout_src_sys_rates[] = {
290 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
291 { .div = 0 }
292};
293
294static const struct clksel_rate common_clkout_src_96m_rates[] = {
295 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
296 { .div = 0 }
297};
298
299static const struct clksel_rate common_clkout_src_54m_rates[] = {
300 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
301 { .div = 0 }
302};
303
304static const struct clksel common_clkout_src_clksel[] = {
305 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
306 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
307 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
308 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
309 { .parent = NULL }
310};
311
312static struct clk sys_clkout_src = {
313 .name = "sys_clkout_src",
314 .ops = &clkops_omap2_dflt,
315 .parent = &func_54m_ck,
316 .clkdm_name = "wkup_clkdm",
317 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
318 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
319 .init = &omap2_init_clksel_parent,
320 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
321 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
322 .clksel = common_clkout_src_clksel,
323 .recalc = &omap2_clksel_recalc,
324 .round_rate = &omap2_clksel_round_rate,
325 .set_rate = &omap2_clksel_set_rate
326};
327
328static const struct clksel_rate common_clkout_rates[] = {
329 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
330 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
331 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
332 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
333 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
334 { .div = 0 },
335};
336
337static const struct clksel sys_clkout_clksel[] = {
338 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
339 { .parent = NULL }
340};
341
342static struct clk sys_clkout = {
343 .name = "sys_clkout",
344 .ops = &clkops_null,
345 .parent = &sys_clkout_src,
346 .clkdm_name = "wkup_clkdm",
347 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
348 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
349 .clksel = sys_clkout_clksel,
350 .recalc = &omap2_clksel_recalc,
351 .round_rate = &omap2_clksel_round_rate,
352 .set_rate = &omap2_clksel_set_rate
353};
354
355static struct clk emul_ck = {
356 .name = "emul_ck",
357 .ops = &clkops_omap2_dflt,
358 .parent = &func_54m_ck,
359 .clkdm_name = "wkup_clkdm",
360 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
361 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
362 .recalc = &followparent_recalc,
363
364};
365
366/*
367 * MPU clock domain
368 * Clocks:
369 * MPU_FCLK, MPU_ICLK
370 * INT_M_FCLK, INT_M_I_CLK
371 *
372 * - Individual clocks are hardware managed.
373 * - Base divider comes from: CM_CLKSEL_MPU
374 *
375 */
376static const struct clksel_rate mpu_core_rates[] = {
377 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
378 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
379 { .div = 0 },
380};
381
382static const struct clksel mpu_clksel[] = {
383 { .parent = &core_ck, .rates = mpu_core_rates },
384 { .parent = NULL }
385};
386
387static struct clk mpu_ck = { /* Control cpu */
388 .name = "mpu_ck",
389 .ops = &clkops_null,
390 .parent = &core_ck,
391 .clkdm_name = "mpu_clkdm",
392 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
394 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
395 .clksel = mpu_clksel,
396 .recalc = &omap2_clksel_recalc,
397};
398
399/*
400 * DSP (2430-IVA2.1) clock domain
401 * Clocks:
402 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
403 *
404 * Won't be too specific here. The core clock comes into this block
405 * it is divided then tee'ed. One branch goes directly to xyz enable
406 * controls. The other branch gets further divided by 2 then possibly
407 * routed into a synchronizer and out of clocks abc.
408 */
409static const struct clksel_rate dsp_fck_core_rates[] = {
410 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
411 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
412 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
413 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
414 { .div = 0 },
415};
416
417static const struct clksel dsp_fck_clksel[] = {
418 { .parent = &core_ck, .rates = dsp_fck_core_rates },
419 { .parent = NULL }
420};
421
422static struct clk dsp_fck = {
423 .name = "dsp_fck",
424 .ops = &clkops_omap2_dflt_wait,
425 .parent = &core_ck,
426 .clkdm_name = "dsp_clkdm",
427 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
428 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
429 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
430 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
431 .clksel = dsp_fck_clksel,
432 .recalc = &omap2_clksel_recalc,
433};
434
435static const struct clksel dsp_ick_clksel[] = {
436 { .parent = &dsp_fck, .rates = dsp_ick_rates },
437 { .parent = NULL }
438};
439
440/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
441static struct clk iva2_1_ick = {
442 .name = "iva2_1_ick",
443 .ops = &clkops_omap2_dflt_wait,
444 .parent = &dsp_fck,
445 .clkdm_name = "dsp_clkdm",
446 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
447 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
448 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
449 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
450 .clksel = dsp_ick_clksel,
451 .recalc = &omap2_clksel_recalc,
452};
453
454/*
455 * L3 clock domain
456 * L3 clocks are used for both interface and functional clocks to
457 * multiple entities. Some of these clocks are completely managed
458 * by hardware, and some others allow software control. Hardware
459 * managed ones general are based on directly CLK_REQ signals and
460 * various auto idle settings. The functional spec sets many of these
461 * as 'tie-high' for their enables.
462 *
463 * I-CLOCKS:
464 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
465 * CAM, HS-USB.
466 * F-CLOCK
467 * SSI.
468 *
469 * GPMC memories and SDRC have timing and clock sensitive registers which
470 * may very well need notification when the clock changes. Currently for low
471 * operating points, these are taken care of in sleep.S.
472 */
473static const struct clksel_rate core_l3_core_rates[] = {
474 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
475 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
476 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
477 { .div = 0 }
478};
479
480static const struct clksel core_l3_clksel[] = {
481 { .parent = &core_ck, .rates = core_l3_core_rates },
482 { .parent = NULL }
483};
484
485static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
486 .name = "core_l3_ck",
487 .ops = &clkops_null,
488 .parent = &core_ck,
489 .clkdm_name = "core_l3_clkdm",
490 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
491 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
492 .clksel = core_l3_clksel,
493 .recalc = &omap2_clksel_recalc,
494};
495
496/* usb_l4_ick */
497static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
498 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
499 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
500 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
501 { .div = 0 }
502};
503
504static const struct clksel usb_l4_ick_clksel[] = {
505 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
506 { .parent = NULL },
507};
508
509/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
510static struct clk usb_l4_ick = { /* FS-USB interface clock */
511 .name = "usb_l4_ick",
512 .ops = &clkops_omap2_iclk_dflt_wait,
513 .parent = &core_l3_ck,
514 .clkdm_name = "core_l4_clkdm",
515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
516 .enable_bit = OMAP24XX_EN_USB_SHIFT,
517 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
518 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
519 .clksel = usb_l4_ick_clksel,
520 .recalc = &omap2_clksel_recalc,
521};
522
523/*
524 * L4 clock management domain
525 *
526 * This domain contains lots of interface clocks from the L4 interface, some
527 * functional clocks. Fixed APLL functional source clocks are managed in
528 * this domain.
529 */
530static const struct clksel_rate l4_core_l3_rates[] = {
531 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
532 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
533 { .div = 0 }
534};
535
536static const struct clksel l4_clksel[] = {
537 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
538 { .parent = NULL }
539};
540
541static struct clk l4_ck = { /* used both as an ick and fck */
542 .name = "l4_ck",
543 .ops = &clkops_null,
544 .parent = &core_l3_ck,
545 .clkdm_name = "core_l4_clkdm",
546 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
547 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
548 .clksel = l4_clksel,
549 .recalc = &omap2_clksel_recalc,
550};
551
552/*
553 * SSI is in L3 management domain, its direct parent is core not l3,
554 * many core power domain entities are grouped into the L3 clock
555 * domain.
556 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
557 *
558 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
559 */
560static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
561 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
562 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
563 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
564 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
565 { .div = 5, .val = 5, .flags = RATE_IN_243X },
566 { .div = 0 }
567};
568
569static const struct clksel ssi_ssr_sst_fck_clksel[] = {
570 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
571 { .parent = NULL }
572};
573
574static struct clk ssi_ssr_sst_fck = {
575 .name = "ssi_fck",
576 .ops = &clkops_omap2_dflt_wait,
577 .parent = &core_ck,
578 .clkdm_name = "core_l3_clkdm",
579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
580 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
581 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
582 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
583 .clksel = ssi_ssr_sst_fck_clksel,
584 .recalc = &omap2_clksel_recalc,
585};
586
587/*
588 * Presumably this is the same as SSI_ICLK.
589 * TRM contradicts itself on what clockdomain SSI_ICLK is in
590 */
591static struct clk ssi_l4_ick = {
592 .name = "ssi_l4_ick",
593 .ops = &clkops_omap2_iclk_dflt_wait,
594 .parent = &l4_ck,
595 .clkdm_name = "core_l4_clkdm",
596 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
597 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
598 .recalc = &followparent_recalc,
599};
600
601
602/*
603 * GFX clock domain
604 * Clocks:
605 * GFX_FCLK, GFX_ICLK
606 * GFX_CG1(2d), GFX_CG2(3d)
607 *
608 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
609 * The 2d and 3d clocks run at a hardware determined
610 * divided value of fclk.
611 *
612 */
613
614/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
615static const struct clksel gfx_fck_clksel[] = {
616 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
617 { .parent = NULL },
618};
619
620static struct clk gfx_3d_fck = {
621 .name = "gfx_3d_fck",
622 .ops = &clkops_omap2_dflt_wait,
623 .parent = &core_l3_ck,
624 .clkdm_name = "gfx_clkdm",
625 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
626 .enable_bit = OMAP24XX_EN_3D_SHIFT,
627 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
628 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
629 .clksel = gfx_fck_clksel,
630 .recalc = &omap2_clksel_recalc,
631 .round_rate = &omap2_clksel_round_rate,
632 .set_rate = &omap2_clksel_set_rate
633};
634
635static struct clk gfx_2d_fck = {
636 .name = "gfx_2d_fck",
637 .ops = &clkops_omap2_dflt_wait,
638 .parent = &core_l3_ck,
639 .clkdm_name = "gfx_clkdm",
640 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
641 .enable_bit = OMAP24XX_EN_2D_SHIFT,
642 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
643 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
644 .clksel = gfx_fck_clksel,
645 .recalc = &omap2_clksel_recalc,
646};
647
648/* This interface clock does not have a CM_AUTOIDLE bit */
649static struct clk gfx_ick = {
650 .name = "gfx_ick", /* From l3 */
651 .ops = &clkops_omap2_dflt_wait,
652 .parent = &core_l3_ck,
653 .clkdm_name = "gfx_clkdm",
654 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
655 .enable_bit = OMAP_EN_GFX_SHIFT,
656 .recalc = &followparent_recalc,
657};
658
659/*
660 * Modem clock domain (2430)
661 * CLOCKS:
662 * MDM_OSC_CLK
663 * MDM_ICLK
664 * These clocks are usable in chassis mode only.
665 */
666static const struct clksel_rate mdm_ick_core_rates[] = {
667 { .div = 1, .val = 1, .flags = RATE_IN_243X },
668 { .div = 4, .val = 4, .flags = RATE_IN_243X },
669 { .div = 6, .val = 6, .flags = RATE_IN_243X },
670 { .div = 9, .val = 9, .flags = RATE_IN_243X },
671 { .div = 0 }
672};
673
674static const struct clksel mdm_ick_clksel[] = {
675 { .parent = &core_ck, .rates = mdm_ick_core_rates },
676 { .parent = NULL }
677};
678
679static struct clk mdm_ick = { /* used both as a ick and fck */
680 .name = "mdm_ick",
681 .ops = &clkops_omap2_iclk_dflt_wait,
682 .parent = &core_ck,
683 .clkdm_name = "mdm_clkdm",
684 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
685 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
686 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
687 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
688 .clksel = mdm_ick_clksel,
689 .recalc = &omap2_clksel_recalc,
690};
691
692static struct clk mdm_osc_ck = {
693 .name = "mdm_osc_ck",
694 .ops = &clkops_omap2_mdmclk_dflt_wait,
695 .parent = &osc_ck,
696 .clkdm_name = "mdm_clkdm",
697 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
698 .enable_bit = OMAP2430_EN_OSC_SHIFT,
699 .recalc = &followparent_recalc,
700};
701
702/*
703 * DSS clock domain
704 * CLOCKs:
705 * DSS_L4_ICLK, DSS_L3_ICLK,
706 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
707 *
708 * DSS is both initiator and target.
709 */
710/* XXX Add RATE_NOT_VALIDATED */
711
712static const struct clksel_rate dss1_fck_sys_rates[] = {
713 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
714 { .div = 0 }
715};
716
717static const struct clksel_rate dss1_fck_core_rates[] = {
718 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
719 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
720 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
721 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
722 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
723 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
724 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
725 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
726 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
727 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
728 { .div = 0 }
729};
730
731static const struct clksel dss1_fck_clksel[] = {
732 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
733 { .parent = &core_ck, .rates = dss1_fck_core_rates },
734 { .parent = NULL },
735};
736
737static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
738 .name = "dss_ick",
739 .ops = &clkops_omap2_iclk_dflt,
740 .parent = &l4_ck, /* really both l3 and l4 */
741 .clkdm_name = "dss_clkdm",
742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
743 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
744 .recalc = &followparent_recalc,
745};
746
747static struct clk dss1_fck = {
748 .name = "dss1_fck",
749 .ops = &clkops_omap2_dflt,
750 .parent = &core_ck, /* Core or sys */
751 .clkdm_name = "dss_clkdm",
752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
753 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
754 .init = &omap2_init_clksel_parent,
755 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
756 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
757 .clksel = dss1_fck_clksel,
758 .recalc = &omap2_clksel_recalc,
759};
760
761static const struct clksel_rate dss2_fck_sys_rates[] = {
762 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
763 { .div = 0 }
764};
765
766static const struct clksel_rate dss2_fck_48m_rates[] = {
767 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
768 { .div = 0 }
769};
770
771static const struct clksel dss2_fck_clksel[] = {
772 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
773 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
774 { .parent = NULL }
775};
776
777static struct clk dss2_fck = { /* Alt clk used in power management */
778 .name = "dss2_fck",
779 .ops = &clkops_omap2_dflt,
780 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
781 .clkdm_name = "dss_clkdm",
782 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
783 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
784 .init = &omap2_init_clksel_parent,
785 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
786 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
787 .clksel = dss2_fck_clksel,
788 .recalc = &omap2_clksel_recalc,
789};
790
791static struct clk dss_54m_fck = { /* Alt clk used in power management */
792 .name = "dss_54m_fck", /* 54m tv clk */
793 .ops = &clkops_omap2_dflt_wait,
794 .parent = &func_54m_ck,
795 .clkdm_name = "dss_clkdm",
796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
797 .enable_bit = OMAP24XX_EN_TV_SHIFT,
798 .recalc = &followparent_recalc,
799};
800
801static struct clk wu_l4_ick = {
802 .name = "wu_l4_ick",
803 .ops = &clkops_null,
804 .parent = &sys_ck,
805 .clkdm_name = "wkup_clkdm",
806 .recalc = &followparent_recalc,
807};
808
809/*
810 * CORE power domain ICLK & FCLK defines.
811 * Many of the these can have more than one possible parent. Entries
812 * here will likely have an L4 interface parent, and may have multiple
813 * functional clock parents.
814 */
815static const struct clksel_rate gpt_alt_rates[] = {
816 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
817 { .div = 0 }
818};
819
820static const struct clksel omap24xx_gpt_clksel[] = {
821 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
822 { .parent = &sys_ck, .rates = gpt_sys_rates },
823 { .parent = &alt_ck, .rates = gpt_alt_rates },
824 { .parent = NULL },
825};
826
827static struct clk gpt1_ick = {
828 .name = "gpt1_ick",
829 .ops = &clkops_omap2_iclk_dflt_wait,
830 .parent = &wu_l4_ick,
831 .clkdm_name = "wkup_clkdm",
832 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
833 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
834 .recalc = &followparent_recalc,
835};
836
837static struct clk gpt1_fck = {
838 .name = "gpt1_fck",
839 .ops = &clkops_omap2_dflt_wait,
840 .parent = &func_32k_ck,
841 .clkdm_name = "core_l4_clkdm",
842 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
843 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
844 .init = &omap2_init_clksel_parent,
845 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
846 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
847 .clksel = omap24xx_gpt_clksel,
848 .recalc = &omap2_clksel_recalc,
849 .round_rate = &omap2_clksel_round_rate,
850 .set_rate = &omap2_clksel_set_rate
851};
852
853static struct clk gpt2_ick = {
854 .name = "gpt2_ick",
855 .ops = &clkops_omap2_iclk_dflt_wait,
856 .parent = &l4_ck,
857 .clkdm_name = "core_l4_clkdm",
858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
859 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
860 .recalc = &followparent_recalc,
861};
862
863static struct clk gpt2_fck = {
864 .name = "gpt2_fck",
865 .ops = &clkops_omap2_dflt_wait,
866 .parent = &func_32k_ck,
867 .clkdm_name = "core_l4_clkdm",
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
870 .init = &omap2_init_clksel_parent,
871 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
872 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
873 .clksel = omap24xx_gpt_clksel,
874 .recalc = &omap2_clksel_recalc,
875};
876
877static struct clk gpt3_ick = {
878 .name = "gpt3_ick",
879 .ops = &clkops_omap2_iclk_dflt_wait,
880 .parent = &l4_ck,
881 .clkdm_name = "core_l4_clkdm",
882 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
883 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
884 .recalc = &followparent_recalc,
885};
886
887static struct clk gpt3_fck = {
888 .name = "gpt3_fck",
889 .ops = &clkops_omap2_dflt_wait,
890 .parent = &func_32k_ck,
891 .clkdm_name = "core_l4_clkdm",
892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
893 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
894 .init = &omap2_init_clksel_parent,
895 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
896 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
897 .clksel = omap24xx_gpt_clksel,
898 .recalc = &omap2_clksel_recalc,
899};
900
901static struct clk gpt4_ick = {
902 .name = "gpt4_ick",
903 .ops = &clkops_omap2_iclk_dflt_wait,
904 .parent = &l4_ck,
905 .clkdm_name = "core_l4_clkdm",
906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
907 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
908 .recalc = &followparent_recalc,
909};
910
911static struct clk gpt4_fck = {
912 .name = "gpt4_fck",
913 .ops = &clkops_omap2_dflt_wait,
914 .parent = &func_32k_ck,
915 .clkdm_name = "core_l4_clkdm",
916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
917 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
918 .init = &omap2_init_clksel_parent,
919 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
920 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
921 .clksel = omap24xx_gpt_clksel,
922 .recalc = &omap2_clksel_recalc,
923};
924
925static struct clk gpt5_ick = {
926 .name = "gpt5_ick",
927 .ops = &clkops_omap2_iclk_dflt_wait,
928 .parent = &l4_ck,
929 .clkdm_name = "core_l4_clkdm",
930 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
931 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
932 .recalc = &followparent_recalc,
933};
934
935static struct clk gpt5_fck = {
936 .name = "gpt5_fck",
937 .ops = &clkops_omap2_dflt_wait,
938 .parent = &func_32k_ck,
939 .clkdm_name = "core_l4_clkdm",
940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
941 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
942 .init = &omap2_init_clksel_parent,
943 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
944 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
945 .clksel = omap24xx_gpt_clksel,
946 .recalc = &omap2_clksel_recalc,
947};
948
949static struct clk gpt6_ick = {
950 .name = "gpt6_ick",
951 .ops = &clkops_omap2_iclk_dflt_wait,
952 .parent = &l4_ck,
953 .clkdm_name = "core_l4_clkdm",
954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
955 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
956 .recalc = &followparent_recalc,
957};
958
959static struct clk gpt6_fck = {
960 .name = "gpt6_fck",
961 .ops = &clkops_omap2_dflt_wait,
962 .parent = &func_32k_ck,
963 .clkdm_name = "core_l4_clkdm",
964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
965 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
966 .init = &omap2_init_clksel_parent,
967 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
968 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
969 .clksel = omap24xx_gpt_clksel,
970 .recalc = &omap2_clksel_recalc,
971};
972
973static struct clk gpt7_ick = {
974 .name = "gpt7_ick",
975 .ops = &clkops_omap2_iclk_dflt_wait,
976 .parent = &l4_ck,
977 .clkdm_name = "core_l4_clkdm",
978 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
979 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
980 .recalc = &followparent_recalc,
981};
982
983static struct clk gpt7_fck = {
984 .name = "gpt7_fck",
985 .ops = &clkops_omap2_dflt_wait,
986 .parent = &func_32k_ck,
987 .clkdm_name = "core_l4_clkdm",
988 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
989 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
990 .init = &omap2_init_clksel_parent,
991 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
992 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
993 .clksel = omap24xx_gpt_clksel,
994 .recalc = &omap2_clksel_recalc,
995};
996
997static struct clk gpt8_ick = {
998 .name = "gpt8_ick",
999 .ops = &clkops_omap2_iclk_dflt_wait,
1000 .parent = &l4_ck,
1001 .clkdm_name = "core_l4_clkdm",
1002 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1003 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1004 .recalc = &followparent_recalc,
1005};
1006
1007static struct clk gpt8_fck = {
1008 .name = "gpt8_fck",
1009 .ops = &clkops_omap2_dflt_wait,
1010 .parent = &func_32k_ck,
1011 .clkdm_name = "core_l4_clkdm",
1012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1013 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1014 .init = &omap2_init_clksel_parent,
1015 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1016 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1017 .clksel = omap24xx_gpt_clksel,
1018 .recalc = &omap2_clksel_recalc,
1019};
1020
1021static struct clk gpt9_ick = {
1022 .name = "gpt9_ick",
1023 .ops = &clkops_omap2_iclk_dflt_wait,
1024 .parent = &l4_ck,
1025 .clkdm_name = "core_l4_clkdm",
1026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1027 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1028 .recalc = &followparent_recalc,
1029};
1030
1031static struct clk gpt9_fck = {
1032 .name = "gpt9_fck",
1033 .ops = &clkops_omap2_dflt_wait,
1034 .parent = &func_32k_ck,
1035 .clkdm_name = "core_l4_clkdm",
1036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1037 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1038 .init = &omap2_init_clksel_parent,
1039 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1040 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1041 .clksel = omap24xx_gpt_clksel,
1042 .recalc = &omap2_clksel_recalc,
1043};
1044
1045static struct clk gpt10_ick = {
1046 .name = "gpt10_ick",
1047 .ops = &clkops_omap2_iclk_dflt_wait,
1048 .parent = &l4_ck,
1049 .clkdm_name = "core_l4_clkdm",
1050 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1051 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1052 .recalc = &followparent_recalc,
1053};
1054
1055static struct clk gpt10_fck = {
1056 .name = "gpt10_fck",
1057 .ops = &clkops_omap2_dflt_wait,
1058 .parent = &func_32k_ck,
1059 .clkdm_name = "core_l4_clkdm",
1060 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1061 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1062 .init = &omap2_init_clksel_parent,
1063 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1064 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1065 .clksel = omap24xx_gpt_clksel,
1066 .recalc = &omap2_clksel_recalc,
1067};
1068
1069static struct clk gpt11_ick = {
1070 .name = "gpt11_ick",
1071 .ops = &clkops_omap2_iclk_dflt_wait,
1072 .parent = &l4_ck,
1073 .clkdm_name = "core_l4_clkdm",
1074 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1075 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1076 .recalc = &followparent_recalc,
1077};
1078
1079static struct clk gpt11_fck = {
1080 .name = "gpt11_fck",
1081 .ops = &clkops_omap2_dflt_wait,
1082 .parent = &func_32k_ck,
1083 .clkdm_name = "core_l4_clkdm",
1084 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1085 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1086 .init = &omap2_init_clksel_parent,
1087 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1088 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1089 .clksel = omap24xx_gpt_clksel,
1090 .recalc = &omap2_clksel_recalc,
1091};
1092
1093static struct clk gpt12_ick = {
1094 .name = "gpt12_ick",
1095 .ops = &clkops_omap2_iclk_dflt_wait,
1096 .parent = &l4_ck,
1097 .clkdm_name = "core_l4_clkdm",
1098 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1099 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1100 .recalc = &followparent_recalc,
1101};
1102
1103static struct clk gpt12_fck = {
1104 .name = "gpt12_fck",
1105 .ops = &clkops_omap2_dflt_wait,
1106 .parent = &secure_32k_ck,
1107 .clkdm_name = "core_l4_clkdm",
1108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1109 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1110 .init = &omap2_init_clksel_parent,
1111 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1112 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1113 .clksel = omap24xx_gpt_clksel,
1114 .recalc = &omap2_clksel_recalc,
1115};
1116
1117static struct clk mcbsp1_ick = {
1118 .name = "mcbsp1_ick",
1119 .ops = &clkops_omap2_iclk_dflt_wait,
1120 .parent = &l4_ck,
1121 .clkdm_name = "core_l4_clkdm",
1122 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1123 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1124 .recalc = &followparent_recalc,
1125};
1126
1127static const struct clksel_rate common_mcbsp_96m_rates[] = {
1128 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1129 { .div = 0 }
1130};
1131
1132static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1133 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1134 { .div = 0 }
1135};
1136
1137static const struct clksel mcbsp_fck_clksel[] = {
1138 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1139 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1140 { .parent = NULL }
1141};
1142
1143static struct clk mcbsp1_fck = {
1144 .name = "mcbsp1_fck",
1145 .ops = &clkops_omap2_dflt_wait,
1146 .parent = &func_96m_ck,
1147 .init = &omap2_init_clksel_parent,
1148 .clkdm_name = "core_l4_clkdm",
1149 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1150 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1151 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1152 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1153 .clksel = mcbsp_fck_clksel,
1154 .recalc = &omap2_clksel_recalc,
1155};
1156
1157static struct clk mcbsp2_ick = {
1158 .name = "mcbsp2_ick",
1159 .ops = &clkops_omap2_iclk_dflt_wait,
1160 .parent = &l4_ck,
1161 .clkdm_name = "core_l4_clkdm",
1162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1163 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1164 .recalc = &followparent_recalc,
1165};
1166
1167static struct clk mcbsp2_fck = {
1168 .name = "mcbsp2_fck",
1169 .ops = &clkops_omap2_dflt_wait,
1170 .parent = &func_96m_ck,
1171 .init = &omap2_init_clksel_parent,
1172 .clkdm_name = "core_l4_clkdm",
1173 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1174 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1175 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1176 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1177 .clksel = mcbsp_fck_clksel,
1178 .recalc = &omap2_clksel_recalc,
1179};
1180
1181static struct clk mcbsp3_ick = {
1182 .name = "mcbsp3_ick",
1183 .ops = &clkops_omap2_iclk_dflt_wait,
1184 .parent = &l4_ck,
1185 .clkdm_name = "core_l4_clkdm",
1186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1187 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1188 .recalc = &followparent_recalc,
1189};
1190
1191static struct clk mcbsp3_fck = {
1192 .name = "mcbsp3_fck",
1193 .ops = &clkops_omap2_dflt_wait,
1194 .parent = &func_96m_ck,
1195 .init = &omap2_init_clksel_parent,
1196 .clkdm_name = "core_l4_clkdm",
1197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1198 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1199 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1200 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
1201 .clksel = mcbsp_fck_clksel,
1202 .recalc = &omap2_clksel_recalc,
1203};
1204
1205static struct clk mcbsp4_ick = {
1206 .name = "mcbsp4_ick",
1207 .ops = &clkops_omap2_iclk_dflt_wait,
1208 .parent = &l4_ck,
1209 .clkdm_name = "core_l4_clkdm",
1210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1211 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1212 .recalc = &followparent_recalc,
1213};
1214
1215static struct clk mcbsp4_fck = {
1216 .name = "mcbsp4_fck",
1217 .ops = &clkops_omap2_dflt_wait,
1218 .parent = &func_96m_ck,
1219 .init = &omap2_init_clksel_parent,
1220 .clkdm_name = "core_l4_clkdm",
1221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1222 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1223 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1224 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
1225 .clksel = mcbsp_fck_clksel,
1226 .recalc = &omap2_clksel_recalc,
1227};
1228
1229static struct clk mcbsp5_ick = {
1230 .name = "mcbsp5_ick",
1231 .ops = &clkops_omap2_iclk_dflt_wait,
1232 .parent = &l4_ck,
1233 .clkdm_name = "core_l4_clkdm",
1234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1235 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1236 .recalc = &followparent_recalc,
1237};
1238
1239static struct clk mcbsp5_fck = {
1240 .name = "mcbsp5_fck",
1241 .ops = &clkops_omap2_dflt_wait,
1242 .parent = &func_96m_ck,
1243 .init = &omap2_init_clksel_parent,
1244 .clkdm_name = "core_l4_clkdm",
1245 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1246 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1247 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1248 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1249 .clksel = mcbsp_fck_clksel,
1250 .recalc = &omap2_clksel_recalc,
1251};
1252
1253static struct clk mcspi1_ick = {
1254 .name = "mcspi1_ick",
1255 .ops = &clkops_omap2_iclk_dflt_wait,
1256 .parent = &l4_ck,
1257 .clkdm_name = "core_l4_clkdm",
1258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1259 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1260 .recalc = &followparent_recalc,
1261};
1262
1263static struct clk mcspi1_fck = {
1264 .name = "mcspi1_fck",
1265 .ops = &clkops_omap2_dflt_wait,
1266 .parent = &func_48m_ck,
1267 .clkdm_name = "core_l4_clkdm",
1268 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1269 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1270 .recalc = &followparent_recalc,
1271};
1272
1273static struct clk mcspi2_ick = {
1274 .name = "mcspi2_ick",
1275 .ops = &clkops_omap2_iclk_dflt_wait,
1276 .parent = &l4_ck,
1277 .clkdm_name = "core_l4_clkdm",
1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1279 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1280 .recalc = &followparent_recalc,
1281};
1282
1283static struct clk mcspi2_fck = {
1284 .name = "mcspi2_fck",
1285 .ops = &clkops_omap2_dflt_wait,
1286 .parent = &func_48m_ck,
1287 .clkdm_name = "core_l4_clkdm",
1288 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1289 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1290 .recalc = &followparent_recalc,
1291};
1292
1293static struct clk mcspi3_ick = {
1294 .name = "mcspi3_ick",
1295 .ops = &clkops_omap2_iclk_dflt_wait,
1296 .parent = &l4_ck,
1297 .clkdm_name = "core_l4_clkdm",
1298 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1299 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1300 .recalc = &followparent_recalc,
1301};
1302
1303static struct clk mcspi3_fck = {
1304 .name = "mcspi3_fck",
1305 .ops = &clkops_omap2_dflt_wait,
1306 .parent = &func_48m_ck,
1307 .clkdm_name = "core_l4_clkdm",
1308 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1309 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1310 .recalc = &followparent_recalc,
1311};
1312
1313static struct clk uart1_ick = {
1314 .name = "uart1_ick",
1315 .ops = &clkops_omap2_iclk_dflt_wait,
1316 .parent = &l4_ck,
1317 .clkdm_name = "core_l4_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1319 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1320 .recalc = &followparent_recalc,
1321};
1322
1323static struct clk uart1_fck = {
1324 .name = "uart1_fck",
1325 .ops = &clkops_omap2_dflt_wait,
1326 .parent = &func_48m_ck,
1327 .clkdm_name = "core_l4_clkdm",
1328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1329 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1330 .recalc = &followparent_recalc,
1331};
1332
1333static struct clk uart2_ick = {
1334 .name = "uart2_ick",
1335 .ops = &clkops_omap2_iclk_dflt_wait,
1336 .parent = &l4_ck,
1337 .clkdm_name = "core_l4_clkdm",
1338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1339 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1340 .recalc = &followparent_recalc,
1341};
1342
1343static struct clk uart2_fck = {
1344 .name = "uart2_fck",
1345 .ops = &clkops_omap2_dflt_wait,
1346 .parent = &func_48m_ck,
1347 .clkdm_name = "core_l4_clkdm",
1348 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1349 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1350 .recalc = &followparent_recalc,
1351};
1352
1353static struct clk uart3_ick = {
1354 .name = "uart3_ick",
1355 .ops = &clkops_omap2_iclk_dflt_wait,
1356 .parent = &l4_ck,
1357 .clkdm_name = "core_l4_clkdm",
1358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1359 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1360 .recalc = &followparent_recalc,
1361};
1362
1363static struct clk uart3_fck = {
1364 .name = "uart3_fck",
1365 .ops = &clkops_omap2_dflt_wait,
1366 .parent = &func_48m_ck,
1367 .clkdm_name = "core_l4_clkdm",
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1369 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1370 .recalc = &followparent_recalc,
1371};
1372
1373static struct clk gpios_ick = {
1374 .name = "gpios_ick",
1375 .ops = &clkops_omap2_iclk_dflt_wait,
1376 .parent = &wu_l4_ick,
1377 .clkdm_name = "wkup_clkdm",
1378 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1379 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1380 .recalc = &followparent_recalc,
1381};
1382
1383static struct clk gpios_fck = {
1384 .name = "gpios_fck",
1385 .ops = &clkops_omap2_dflt_wait,
1386 .parent = &func_32k_ck,
1387 .clkdm_name = "wkup_clkdm",
1388 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1389 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1390 .recalc = &followparent_recalc,
1391};
1392
1393static struct clk mpu_wdt_ick = {
1394 .name = "mpu_wdt_ick",
1395 .ops = &clkops_omap2_iclk_dflt_wait,
1396 .parent = &wu_l4_ick,
1397 .clkdm_name = "wkup_clkdm",
1398 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1399 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1400 .recalc = &followparent_recalc,
1401};
1402
1403static struct clk mpu_wdt_fck = {
1404 .name = "mpu_wdt_fck",
1405 .ops = &clkops_omap2_dflt_wait,
1406 .parent = &func_32k_ck,
1407 .clkdm_name = "wkup_clkdm",
1408 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1409 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1410 .recalc = &followparent_recalc,
1411};
1412
1413static struct clk sync_32k_ick = {
1414 .name = "sync_32k_ick",
1415 .ops = &clkops_omap2_iclk_dflt_wait,
1416 .flags = ENABLE_ON_INIT,
1417 .parent = &wu_l4_ick,
1418 .clkdm_name = "wkup_clkdm",
1419 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1420 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1421 .recalc = &followparent_recalc,
1422};
1423
1424static struct clk wdt1_ick = {
1425 .name = "wdt1_ick",
1426 .ops = &clkops_omap2_iclk_dflt_wait,
1427 .parent = &wu_l4_ick,
1428 .clkdm_name = "wkup_clkdm",
1429 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1430 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1431 .recalc = &followparent_recalc,
1432};
1433
1434static struct clk omapctrl_ick = {
1435 .name = "omapctrl_ick",
1436 .ops = &clkops_omap2_iclk_dflt_wait,
1437 .flags = ENABLE_ON_INIT,
1438 .parent = &wu_l4_ick,
1439 .clkdm_name = "wkup_clkdm",
1440 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1441 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1442 .recalc = &followparent_recalc,
1443};
1444
1445static struct clk icr_ick = {
1446 .name = "icr_ick",
1447 .ops = &clkops_omap2_iclk_dflt_wait,
1448 .parent = &wu_l4_ick,
1449 .clkdm_name = "wkup_clkdm",
1450 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1451 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1452 .recalc = &followparent_recalc,
1453};
1454
1455static struct clk cam_ick = {
1456 .name = "cam_ick",
1457 .ops = &clkops_omap2_iclk_dflt,
1458 .parent = &l4_ck,
1459 .clkdm_name = "core_l4_clkdm",
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1461 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1462 .recalc = &followparent_recalc,
1463};
1464
1465/*
1466 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1467 * split into two separate clocks, since the parent clocks are different
1468 * and the clockdomains are also different.
1469 */
1470static struct clk cam_fck = {
1471 .name = "cam_fck",
1472 .ops = &clkops_omap2_dflt,
1473 .parent = &func_96m_ck,
1474 .clkdm_name = "core_l3_clkdm",
1475 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1477 .recalc = &followparent_recalc,
1478};
1479
1480static struct clk mailboxes_ick = {
1481 .name = "mailboxes_ick",
1482 .ops = &clkops_omap2_iclk_dflt_wait,
1483 .parent = &l4_ck,
1484 .clkdm_name = "core_l4_clkdm",
1485 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1486 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1487 .recalc = &followparent_recalc,
1488};
1489
1490static struct clk wdt4_ick = {
1491 .name = "wdt4_ick",
1492 .ops = &clkops_omap2_iclk_dflt_wait,
1493 .parent = &l4_ck,
1494 .clkdm_name = "core_l4_clkdm",
1495 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1496 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1497 .recalc = &followparent_recalc,
1498};
1499
1500static struct clk wdt4_fck = {
1501 .name = "wdt4_fck",
1502 .ops = &clkops_omap2_dflt_wait,
1503 .parent = &func_32k_ck,
1504 .clkdm_name = "core_l4_clkdm",
1505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1507 .recalc = &followparent_recalc,
1508};
1509
1510static struct clk mspro_ick = {
1511 .name = "mspro_ick",
1512 .ops = &clkops_omap2_iclk_dflt_wait,
1513 .parent = &l4_ck,
1514 .clkdm_name = "core_l4_clkdm",
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1516 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1517 .recalc = &followparent_recalc,
1518};
1519
1520static struct clk mspro_fck = {
1521 .name = "mspro_fck",
1522 .ops = &clkops_omap2_dflt_wait,
1523 .parent = &func_96m_ck,
1524 .clkdm_name = "core_l4_clkdm",
1525 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1527 .recalc = &followparent_recalc,
1528};
1529
1530static struct clk fac_ick = {
1531 .name = "fac_ick",
1532 .ops = &clkops_omap2_iclk_dflt_wait,
1533 .parent = &l4_ck,
1534 .clkdm_name = "core_l4_clkdm",
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1536 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1537 .recalc = &followparent_recalc,
1538};
1539
1540static struct clk fac_fck = {
1541 .name = "fac_fck",
1542 .ops = &clkops_omap2_dflt_wait,
1543 .parent = &func_12m_ck,
1544 .clkdm_name = "core_l4_clkdm",
1545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1547 .recalc = &followparent_recalc,
1548};
1549
1550static struct clk hdq_ick = {
1551 .name = "hdq_ick",
1552 .ops = &clkops_omap2_iclk_dflt_wait,
1553 .parent = &l4_ck,
1554 .clkdm_name = "core_l4_clkdm",
1555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1556 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1557 .recalc = &followparent_recalc,
1558};
1559
1560static struct clk hdq_fck = {
1561 .name = "hdq_fck",
1562 .ops = &clkops_omap2_dflt_wait,
1563 .parent = &func_12m_ck,
1564 .clkdm_name = "core_l4_clkdm",
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1567 .recalc = &followparent_recalc,
1568};
1569
1570/*
1571 * XXX This is marked as a 2420-only define, but it claims to be present
1572 * on 2430 also. Double-check.
1573 */
1574static struct clk i2c2_ick = {
1575 .name = "i2c2_ick",
1576 .ops = &clkops_omap2_iclk_dflt_wait,
1577 .parent = &l4_ck,
1578 .clkdm_name = "core_l4_clkdm",
1579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1580 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1581 .recalc = &followparent_recalc,
1582};
1583
1584static struct clk i2chs2_fck = {
1585 .name = "i2chs2_fck",
1586 .ops = &clkops_omap2430_i2chs_wait,
1587 .parent = &func_96m_ck,
1588 .clkdm_name = "core_l4_clkdm",
1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1590 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1591 .recalc = &followparent_recalc,
1592};
1593
1594/*
1595 * XXX This is marked as a 2420-only define, but it claims to be present
1596 * on 2430 also. Double-check.
1597 */
1598static struct clk i2c1_ick = {
1599 .name = "i2c1_ick",
1600 .ops = &clkops_omap2_iclk_dflt_wait,
1601 .parent = &l4_ck,
1602 .clkdm_name = "core_l4_clkdm",
1603 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1604 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1605 .recalc = &followparent_recalc,
1606};
1607
1608static struct clk i2chs1_fck = {
1609 .name = "i2chs1_fck",
1610 .ops = &clkops_omap2430_i2chs_wait,
1611 .parent = &func_96m_ck,
1612 .clkdm_name = "core_l4_clkdm",
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1614 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1615 .recalc = &followparent_recalc,
1616};
1617
1618/*
1619 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1620 * accesses derived from this data.
1621 */
1622static struct clk gpmc_fck = {
1623 .name = "gpmc_fck",
1624 .ops = &clkops_omap2_iclk_idle_only,
1625 .parent = &core_l3_ck,
1626 .flags = ENABLE_ON_INIT,
1627 .clkdm_name = "core_l3_clkdm",
1628 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1629 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1630 .recalc = &followparent_recalc,
1631};
1632
1633static struct clk sdma_fck = {
1634 .name = "sdma_fck",
1635 .ops = &clkops_null, /* RMK: missing? */
1636 .parent = &core_l3_ck,
1637 .clkdm_name = "core_l3_clkdm",
1638 .recalc = &followparent_recalc,
1639};
1640
1641/*
1642 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1643 * accesses derived from this data.
1644 */
1645static struct clk sdma_ick = {
1646 .name = "sdma_ick",
1647 .ops = &clkops_omap2_iclk_idle_only,
1648 .parent = &core_l3_ck,
1649 .clkdm_name = "core_l3_clkdm",
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1651 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1652 .recalc = &followparent_recalc,
1653};
1654
1655static struct clk sdrc_ick = {
1656 .name = "sdrc_ick",
1657 .ops = &clkops_omap2_iclk_idle_only,
1658 .parent = &core_l3_ck,
1659 .flags = ENABLE_ON_INIT,
1660 .clkdm_name = "core_l3_clkdm",
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1662 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1663 .recalc = &followparent_recalc,
1664};
1665
1666static struct clk des_ick = {
1667 .name = "des_ick",
1668 .ops = &clkops_omap2_iclk_dflt_wait,
1669 .parent = &l4_ck,
1670 .clkdm_name = "core_l4_clkdm",
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1672 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1673 .recalc = &followparent_recalc,
1674};
1675
1676static struct clk sha_ick = {
1677 .name = "sha_ick",
1678 .ops = &clkops_omap2_iclk_dflt_wait,
1679 .parent = &l4_ck,
1680 .clkdm_name = "core_l4_clkdm",
1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1682 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1683 .recalc = &followparent_recalc,
1684};
1685
1686static struct clk rng_ick = {
1687 .name = "rng_ick",
1688 .ops = &clkops_omap2_iclk_dflt_wait,
1689 .parent = &l4_ck,
1690 .clkdm_name = "core_l4_clkdm",
1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1692 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1693 .recalc = &followparent_recalc,
1694};
1695
1696static struct clk aes_ick = {
1697 .name = "aes_ick",
1698 .ops = &clkops_omap2_iclk_dflt_wait,
1699 .parent = &l4_ck,
1700 .clkdm_name = "core_l4_clkdm",
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1702 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1703 .recalc = &followparent_recalc,
1704};
1705
1706static struct clk pka_ick = {
1707 .name = "pka_ick",
1708 .ops = &clkops_omap2_iclk_dflt_wait,
1709 .parent = &l4_ck,
1710 .clkdm_name = "core_l4_clkdm",
1711 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1712 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1713 .recalc = &followparent_recalc,
1714};
1715
1716static struct clk usb_fck = {
1717 .name = "usb_fck",
1718 .ops = &clkops_omap2_dflt_wait,
1719 .parent = &func_48m_ck,
1720 .clkdm_name = "core_l3_clkdm",
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1722 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1723 .recalc = &followparent_recalc,
1724};
1725
1726static struct clk usbhs_ick = {
1727 .name = "usbhs_ick",
1728 .ops = &clkops_omap2_iclk_dflt_wait,
1729 .parent = &core_l3_ck,
1730 .clkdm_name = "core_l3_clkdm",
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1732 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1733 .recalc = &followparent_recalc,
1734};
1735
1736static struct clk mmchs1_ick = {
1737 .name = "mmchs1_ick",
1738 .ops = &clkops_omap2_iclk_dflt_wait,
1739 .parent = &l4_ck,
1740 .clkdm_name = "core_l4_clkdm",
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1742 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1743 .recalc = &followparent_recalc,
1744};
1745
1746static struct clk mmchs1_fck = {
1747 .name = "mmchs1_fck",
1748 .ops = &clkops_omap2_dflt_wait,
1749 .parent = &func_96m_ck,
1750 .clkdm_name = "core_l4_clkdm",
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1752 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1753 .recalc = &followparent_recalc,
1754};
1755
1756static struct clk mmchs2_ick = {
1757 .name = "mmchs2_ick",
1758 .ops = &clkops_omap2_iclk_dflt_wait,
1759 .parent = &l4_ck,
1760 .clkdm_name = "core_l4_clkdm",
1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1762 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1763 .recalc = &followparent_recalc,
1764};
1765
1766static struct clk mmchs2_fck = {
1767 .name = "mmchs2_fck",
1768 .ops = &clkops_omap2_dflt_wait,
1769 .parent = &func_96m_ck,
1770 .clkdm_name = "core_l4_clkdm",
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1772 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1773 .recalc = &followparent_recalc,
1774};
1775
1776static struct clk gpio5_ick = {
1777 .name = "gpio5_ick",
1778 .ops = &clkops_omap2_iclk_dflt_wait,
1779 .parent = &l4_ck,
1780 .clkdm_name = "core_l4_clkdm",
1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1782 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1783 .recalc = &followparent_recalc,
1784};
1785
1786static struct clk gpio5_fck = {
1787 .name = "gpio5_fck",
1788 .ops = &clkops_omap2_dflt_wait,
1789 .parent = &func_32k_ck,
1790 .clkdm_name = "core_l4_clkdm",
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1792 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1793 .recalc = &followparent_recalc,
1794};
1795
1796static struct clk mdm_intc_ick = {
1797 .name = "mdm_intc_ick",
1798 .ops = &clkops_omap2_iclk_dflt_wait,
1799 .parent = &l4_ck,
1800 .clkdm_name = "core_l4_clkdm",
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1802 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1803 .recalc = &followparent_recalc,
1804};
1805
1806static struct clk mmchsdb1_fck = {
1807 .name = "mmchsdb1_fck",
1808 .ops = &clkops_omap2_dflt_wait,
1809 .parent = &func_32k_ck,
1810 .clkdm_name = "core_l4_clkdm",
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1812 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1813 .recalc = &followparent_recalc,
1814};
1815
1816static struct clk mmchsdb2_fck = {
1817 .name = "mmchsdb2_fck",
1818 .ops = &clkops_omap2_dflt_wait,
1819 .parent = &func_32k_ck,
1820 .clkdm_name = "core_l4_clkdm",
1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1822 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1823 .recalc = &followparent_recalc,
1824};
1825
1826/*
1827 * This clock is a composite clock which does entire set changes then
1828 * forces a rebalance. It keys on the MPU speed, but it really could
1829 * be any key speed part of a set in the rate table.
1830 *
1831 * to really change a set, you need memory table sets which get changed
1832 * in sram, pre-notifiers & post notifiers, changing the top set, without
1833 * having low level display recalc's won't work... this is why dpm notifiers
1834 * work, isr's off, walk a list of clocks already _off_ and not messing with
1835 * the bus.
1836 *
1837 * This clock should have no parent. It embodies the entire upper level
1838 * active set. A parent will mess up some of the init also.
1839 */
1840static struct clk virt_prcm_set = {
1841 .name = "virt_prcm_set",
1842 .ops = &clkops_null,
1843 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1844 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1845 .set_rate = &omap2_select_table_rate,
1846 .round_rate = &omap2_round_to_table_rate,
1847};
1848
1849
1850/*
1851 * clkdev integration
1852 */
1853
1854static struct omap_clk omap2430_clks[] = {
1855 /* external root sources */
1856 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1857 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1858 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1861 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
1862 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
1863 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
1864 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
1865 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
1866 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1867 /* internal analog sources */
1868 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1869 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1870 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1871 /* internal prcm root sources */
1872 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1873 CLK(NULL, "core_ck", &core_ck, CK_243X),
1874 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
1875 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
1876 CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
1877 CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
1878 CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
1879 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1880 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1881 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1882 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1883 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1884 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1885 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1886 /* mpu domain clocks */
1887 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1888 /* dsp domain clocks */
1889 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1890 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1891 /* GFX domain clocks */
1892 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1893 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1894 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1895 /* Modem domain clocks */
1896 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1897 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1898 /* DSS domain clocks */
1899 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1900 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1901 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1902 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1903 /* L3 domain clocks */
1904 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1905 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1906 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1907 /* L4 domain clocks */
1908 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1909 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1910 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1911 /* virtual meta-group clock */
1912 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1913 /* general l4 interface ck, multi-parent functional clk */
1914 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1915 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1916 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1917 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1918 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1919 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1920 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1921 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1922 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1923 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1924 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1925 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1926 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1927 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1928 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1929 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1930 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1931 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1932 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1933 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1934 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1935 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1936 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1937 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1938 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1939 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1940 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1941 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1942 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1943 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1944 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1945 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1946 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1947 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1948 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1949 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1950 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1951 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1952 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1953 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1954 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1955 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1956 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1957 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1958 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1959 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1960 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1961 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1962 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1963 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1964 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1965 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1966 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1967 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1968 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1969 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1970 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1971 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1972 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1973 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1974 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1975 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1976 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1977 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1978 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1979 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1980 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1981 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1982 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1983 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1984 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1985 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1986 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1987 CLK(NULL, "des_ick", &des_ick, CK_243X),
1988 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1989 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1990 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1991 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1992 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1993 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1994 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1995 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
1996 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1997 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
1998 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1999 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
2000 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2001 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2002 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2003 CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
2004 CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
2005 CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
2006 CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
2007 CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
2008 CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
2009 CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
2010 CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
2011 CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
2012 CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
2013 CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
2014 CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
2015 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
2016 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
2017 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
2018 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
2019 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
2020 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
2021 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
2022 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
2023 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
2024 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
2025 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
2026 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
2027 CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
2028 CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
2029 CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
2030 CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
2031 CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
2032 CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
2033 CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
2034 CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
2035 CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
2036 CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
2037 CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
2038 CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
2039};
2040
2041/*
2042 * init code
2043 */
2044
2045int __init omap2430_clk_init(void)
2046{
2047 const struct prcm_config *prcm;
2048 struct omap_clk *c;
2049 u32 clkrate;
2050
2051 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2052 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
2053 cpu_mask = RATE_IN_243X;
2054 rate_table = omap2430_rate_table;
2055
2056 clk_init(&omap2_clk_functions);
2057
2058 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2059 c++)
2060 clk_preinit(c->lk.clk);
2061
2062 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2063 propagate_rate(&osc_ck);
2064 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2065 propagate_rate(&sys_ck);
2066
2067 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2068 c++) {
2069 clkdev_add(&c->lk);
2070 clk_register(c->lk.clk);
2071 omap2_init_clk_clkdm(c->lk.clk);
2072 }
2073
2074 /* Disable autoidle on all clocks; let the PM code enable it later */
2075 omap_clk_disable_autoidle_all();
2076
2077 /* Check the MPU rate set by bootloader */
2078 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2079 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
2080 if (!(prcm->flags & cpu_mask))
2081 continue;
2082 if (prcm->xtal_speed != sys_ck.rate)
2083 continue;
2084 if (prcm->dpll_speed <= clkrate)
2085 break;
2086 }
2087 curr_prcm_set = prcm;
2088
2089 recalculate_root_clocks();
2090
2091 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2092 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2093 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2094
2095 /*
2096 * Only enable those clocks we will need, let the drivers
2097 * enable other clocks as necessary
2098 */
2099 clk_enable_init_clocks();
2100
2101 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2102 vclk = clk_get(NULL, "virt_prcm_set");
2103 sclk = clk_get(NULL, "sys_ck");
2104 dclk = clk_get(NULL, "dpll_ck");
2105
2106 return 0;
2107}
2108