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1/*
2 * MPC512x PSC in SPI mode driver.
3 *
4 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
5 * Original port from 52xx driver:
6 * Hongjun Chen <hong-jun.chen@freescale.com>
7 *
8 * Fork of mpc52xx_psc_spi.c:
9 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/of_address.h>
23#include <linux/of_platform.h>
24#include <linux/workqueue.h>
25#include <linux/completion.h>
26#include <linux/io.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/spi/spi.h>
30#include <linux/fsl_devices.h>
31#include <asm/mpc52xx_psc.h>
32
33struct mpc512x_psc_spi {
34 void (*cs_control)(struct spi_device *spi, bool on);
35 u32 sysclk;
36
37 /* driver internal data */
38 struct mpc52xx_psc __iomem *psc;
39 struct mpc512x_psc_fifo __iomem *fifo;
40 unsigned int irq;
41 u8 bits_per_word;
42 u8 busy;
43 u32 mclk;
44 u8 eofbyte;
45
46 struct workqueue_struct *workqueue;
47 struct work_struct work;
48
49 struct list_head queue;
50 spinlock_t lock; /* Message queue lock */
51
52 struct completion done;
53};
54
55/* controller state */
56struct mpc512x_psc_spi_cs {
57 int bits_per_word;
58 int speed_hz;
59};
60
61/* set clock freq, clock ramp, bits per work
62 * if t is NULL then reset the values to the default values
63 */
64static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
65 struct spi_transfer *t)
66{
67 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
68
69 cs->speed_hz = (t && t->speed_hz)
70 ? t->speed_hz : spi->max_speed_hz;
71 cs->bits_per_word = (t && t->bits_per_word)
72 ? t->bits_per_word : spi->bits_per_word;
73 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
74 return 0;
75}
76
77static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
78{
79 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
80 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
81 struct mpc52xx_psc __iomem *psc = mps->psc;
82 u32 sicr;
83 u32 ccr;
84 u16 bclkdiv;
85
86 sicr = in_be32(&psc->sicr);
87
88 /* Set clock phase and polarity */
89 if (spi->mode & SPI_CPHA)
90 sicr |= 0x00001000;
91 else
92 sicr &= ~0x00001000;
93
94 if (spi->mode & SPI_CPOL)
95 sicr |= 0x00002000;
96 else
97 sicr &= ~0x00002000;
98
99 if (spi->mode & SPI_LSB_FIRST)
100 sicr |= 0x10000000;
101 else
102 sicr &= ~0x10000000;
103 out_be32(&psc->sicr, sicr);
104
105 ccr = in_be32(&psc->ccr);
106 ccr &= 0xFF000000;
107 if (cs->speed_hz)
108 bclkdiv = (mps->mclk / cs->speed_hz) - 1;
109 else
110 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
111
112 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
113 out_be32(&psc->ccr, ccr);
114 mps->bits_per_word = cs->bits_per_word;
115
116 if (mps->cs_control)
117 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
118}
119
120static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
121{
122 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
123
124 if (mps->cs_control)
125 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
126
127}
128
129/* extract and scale size field in txsz or rxsz */
130#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
131
132#define EOFBYTE 1
133
134static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
135 struct spi_transfer *t)
136{
137 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
138 struct mpc52xx_psc __iomem *psc = mps->psc;
139 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
140 size_t len = t->len;
141 u8 *tx_buf = (u8 *)t->tx_buf;
142 u8 *rx_buf = (u8 *)t->rx_buf;
143
144 if (!tx_buf && !rx_buf && t->len)
145 return -EINVAL;
146
147 /* Zero MR2 */
148 in_8(&psc->mode);
149 out_8(&psc->mode, 0x0);
150
151 while (len) {
152 int count;
153 int i;
154 u8 data;
155 size_t fifosz;
156 int rxcount;
157
158 /*
159 * The number of bytes that can be sent at a time
160 * depends on the fifo size.
161 */
162 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
163 count = min(fifosz, len);
164
165 for (i = count; i > 0; i--) {
166 data = tx_buf ? *tx_buf++ : 0;
167 if (len == EOFBYTE)
168 setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF);
169 out_8(&fifo->txdata_8, data);
170 len--;
171 }
172
173 INIT_COMPLETION(mps->done);
174
175 /* interrupt on tx fifo empty */
176 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
177 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
178
179 /* enable transmiter/receiver */
180 out_8(&psc->command,
181 MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
182
183 wait_for_completion(&mps->done);
184
185 mdelay(1);
186
187 /* rx fifo should have count bytes in it */
188 rxcount = in_be32(&fifo->rxcnt);
189 if (rxcount != count)
190 mdelay(1);
191
192 rxcount = in_be32(&fifo->rxcnt);
193 if (rxcount != count) {
194 dev_warn(&spi->dev, "expected %d bytes in rx fifo "
195 "but got %d\n", count, rxcount);
196 }
197
198 rxcount = min(rxcount, count);
199 for (i = rxcount; i > 0; i--) {
200 data = in_8(&fifo->rxdata_8);
201 if (rx_buf)
202 *rx_buf++ = data;
203 }
204 while (in_be32(&fifo->rxcnt)) {
205 in_8(&fifo->rxdata_8);
206 }
207
208 out_8(&psc->command,
209 MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
210 }
211 /* disable transmiter/receiver and fifo interrupt */
212 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
213 out_be32(&fifo->tximr, 0);
214 return 0;
215}
216
217static void mpc512x_psc_spi_work(struct work_struct *work)
218{
219 struct mpc512x_psc_spi *mps = container_of(work,
220 struct mpc512x_psc_spi,
221 work);
222
223 spin_lock_irq(&mps->lock);
224 mps->busy = 1;
225 while (!list_empty(&mps->queue)) {
226 struct spi_message *m;
227 struct spi_device *spi;
228 struct spi_transfer *t = NULL;
229 unsigned cs_change;
230 int status;
231
232 m = container_of(mps->queue.next, struct spi_message, queue);
233 list_del_init(&m->queue);
234 spin_unlock_irq(&mps->lock);
235
236 spi = m->spi;
237 cs_change = 1;
238 status = 0;
239 list_for_each_entry(t, &m->transfers, transfer_list) {
240 if (t->bits_per_word || t->speed_hz) {
241 status = mpc512x_psc_spi_transfer_setup(spi, t);
242 if (status < 0)
243 break;
244 }
245
246 if (cs_change)
247 mpc512x_psc_spi_activate_cs(spi);
248 cs_change = t->cs_change;
249
250 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
251 if (status)
252 break;
253 m->actual_length += t->len;
254
255 if (t->delay_usecs)
256 udelay(t->delay_usecs);
257
258 if (cs_change)
259 mpc512x_psc_spi_deactivate_cs(spi);
260 }
261
262 m->status = status;
263 m->complete(m->context);
264
265 if (status || !cs_change)
266 mpc512x_psc_spi_deactivate_cs(spi);
267
268 mpc512x_psc_spi_transfer_setup(spi, NULL);
269
270 spin_lock_irq(&mps->lock);
271 }
272 mps->busy = 0;
273 spin_unlock_irq(&mps->lock);
274}
275
276static int mpc512x_psc_spi_setup(struct spi_device *spi)
277{
278 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
279 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
280 unsigned long flags;
281
282 if (spi->bits_per_word % 8)
283 return -EINVAL;
284
285 if (!cs) {
286 cs = kzalloc(sizeof *cs, GFP_KERNEL);
287 if (!cs)
288 return -ENOMEM;
289 spi->controller_state = cs;
290 }
291
292 cs->bits_per_word = spi->bits_per_word;
293 cs->speed_hz = spi->max_speed_hz;
294
295 spin_lock_irqsave(&mps->lock, flags);
296 if (!mps->busy)
297 mpc512x_psc_spi_deactivate_cs(spi);
298 spin_unlock_irqrestore(&mps->lock, flags);
299
300 return 0;
301}
302
303static int mpc512x_psc_spi_transfer(struct spi_device *spi,
304 struct spi_message *m)
305{
306 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
307 unsigned long flags;
308
309 m->actual_length = 0;
310 m->status = -EINPROGRESS;
311
312 spin_lock_irqsave(&mps->lock, flags);
313 list_add_tail(&m->queue, &mps->queue);
314 queue_work(mps->workqueue, &mps->work);
315 spin_unlock_irqrestore(&mps->lock, flags);
316
317 return 0;
318}
319
320static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
321{
322 kfree(spi->controller_state);
323}
324
325static int mpc512x_psc_spi_port_config(struct spi_master *master,
326 struct mpc512x_psc_spi *mps)
327{
328 struct mpc52xx_psc __iomem *psc = mps->psc;
329 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
330 struct clk *spiclk;
331 int ret = 0;
332 char name[32];
333 u32 sicr;
334 u32 ccr;
335 u16 bclkdiv;
336
337 sprintf(name, "psc%d_mclk", master->bus_num);
338 spiclk = clk_get(&master->dev, name);
339 clk_enable(spiclk);
340 mps->mclk = clk_get_rate(spiclk);
341 clk_put(spiclk);
342
343 /* Reset the PSC into a known state */
344 out_8(&psc->command, MPC52xx_PSC_RST_RX);
345 out_8(&psc->command, MPC52xx_PSC_RST_TX);
346 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
347
348 /* Disable psc interrupts all useful interrupts are in fifo */
349 out_be16(&psc->isr_imr.imr, 0);
350
351 /* Disable fifo interrupts, will be enabled later */
352 out_be32(&fifo->tximr, 0);
353 out_be32(&fifo->rximr, 0);
354
355 /* Setup fifo slice address and size */
356 /*out_be32(&fifo->txsz, 0x0fe00004);*/
357 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
358
359 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
360 0x00800000 | /* GenClk = 1 -- internal clk */
361 0x00008000 | /* SPI = 1 */
362 0x00004000 | /* MSTR = 1 -- SPI master */
363 0x00000800; /* UseEOF = 1 -- SS low until EOF */
364
365 out_be32(&psc->sicr, sicr);
366
367 ccr = in_be32(&psc->ccr);
368 ccr &= 0xFF000000;
369 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
370 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
371 out_be32(&psc->ccr, ccr);
372
373 /* Set 2ms DTL delay */
374 out_8(&psc->ctur, 0x00);
375 out_8(&psc->ctlr, 0x82);
376
377 /* we don't use the alarms */
378 out_be32(&fifo->rxalarm, 0xfff);
379 out_be32(&fifo->txalarm, 0);
380
381 /* Enable FIFO slices for Rx/Tx */
382 out_be32(&fifo->rxcmd,
383 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
384 out_be32(&fifo->txcmd,
385 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
386
387 mps->bits_per_word = 8;
388
389 return ret;
390}
391
392static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
393{
394 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
395 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
396
397 /* clear interrupt and wake up the work queue */
398 if (in_be32(&fifo->txisr) &
399 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
400 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
401 out_be32(&fifo->tximr, 0);
402 complete(&mps->done);
403 return IRQ_HANDLED;
404 }
405 return IRQ_NONE;
406}
407
408/* bus_num is used only for the case dev->platform_data == NULL */
409static int __devinit mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
410 u32 size, unsigned int irq,
411 s16 bus_num)
412{
413 struct fsl_spi_platform_data *pdata = dev->platform_data;
414 struct mpc512x_psc_spi *mps;
415 struct spi_master *master;
416 int ret;
417 void *tempp;
418
419 master = spi_alloc_master(dev, sizeof *mps);
420 if (master == NULL)
421 return -ENOMEM;
422
423 dev_set_drvdata(dev, master);
424 mps = spi_master_get_devdata(master);
425 mps->irq = irq;
426
427 if (pdata == NULL) {
428 dev_err(dev, "probe called without platform data, no "
429 "cs_control function will be called\n");
430 mps->cs_control = NULL;
431 mps->sysclk = 0;
432 master->bus_num = bus_num;
433 master->num_chipselect = 255;
434 } else {
435 mps->cs_control = pdata->cs_control;
436 mps->sysclk = pdata->sysclk;
437 master->bus_num = pdata->bus_num;
438 master->num_chipselect = pdata->max_chipselect;
439 }
440
441 master->setup = mpc512x_psc_spi_setup;
442 master->transfer = mpc512x_psc_spi_transfer;
443 master->cleanup = mpc512x_psc_spi_cleanup;
444 master->dev.of_node = dev->of_node;
445
446 tempp = ioremap(regaddr, size);
447 if (!tempp) {
448 dev_err(dev, "could not ioremap I/O port range\n");
449 ret = -EFAULT;
450 goto free_master;
451 }
452 mps->psc = tempp;
453 mps->fifo =
454 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
455
456 ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
457 "mpc512x-psc-spi", mps);
458 if (ret)
459 goto free_master;
460
461 ret = mpc512x_psc_spi_port_config(master, mps);
462 if (ret < 0)
463 goto free_irq;
464
465 spin_lock_init(&mps->lock);
466 init_completion(&mps->done);
467 INIT_WORK(&mps->work, mpc512x_psc_spi_work);
468 INIT_LIST_HEAD(&mps->queue);
469
470 mps->workqueue =
471 create_singlethread_workqueue(dev_name(master->dev.parent));
472 if (mps->workqueue == NULL) {
473 ret = -EBUSY;
474 goto free_irq;
475 }
476
477 ret = spi_register_master(master);
478 if (ret < 0)
479 goto unreg_master;
480
481 return ret;
482
483unreg_master:
484 destroy_workqueue(mps->workqueue);
485free_irq:
486 free_irq(mps->irq, mps);
487free_master:
488 if (mps->psc)
489 iounmap(mps->psc);
490 spi_master_put(master);
491
492 return ret;
493}
494
495static int __devexit mpc512x_psc_spi_do_remove(struct device *dev)
496{
497 struct spi_master *master = dev_get_drvdata(dev);
498 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
499
500 flush_workqueue(mps->workqueue);
501 destroy_workqueue(mps->workqueue);
502 spi_unregister_master(master);
503 free_irq(mps->irq, mps);
504 if (mps->psc)
505 iounmap(mps->psc);
506
507 return 0;
508}
509
510static int __devinit mpc512x_psc_spi_of_probe(struct platform_device *op)
511{
512 const u32 *regaddr_p;
513 u64 regaddr64, size64;
514 s16 id = -1;
515
516 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
517 if (!regaddr_p) {
518 dev_err(&op->dev, "Invalid PSC address\n");
519 return -EINVAL;
520 }
521 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
522
523 /* get PSC id (0..11, used by port_config) */
524 if (op->dev.platform_data == NULL) {
525 const u32 *psc_nump;
526
527 psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
528 if (!psc_nump || *psc_nump > 11) {
529 dev_err(&op->dev, "mpc512x_psc_spi: Device node %s "
530 "has invalid cell-index property\n",
531 op->dev.of_node->full_name);
532 return -EINVAL;
533 }
534 id = *psc_nump;
535 }
536
537 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
538 irq_of_parse_and_map(op->dev.of_node, 0), id);
539}
540
541static int __devexit mpc512x_psc_spi_of_remove(struct platform_device *op)
542{
543 return mpc512x_psc_spi_do_remove(&op->dev);
544}
545
546static struct of_device_id mpc512x_psc_spi_of_match[] = {
547 { .compatible = "fsl,mpc5121-psc-spi", },
548 {},
549};
550
551MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
552
553static struct platform_driver mpc512x_psc_spi_of_driver = {
554 .probe = mpc512x_psc_spi_of_probe,
555 .remove = __devexit_p(mpc512x_psc_spi_of_remove),
556 .driver = {
557 .name = "mpc512x-psc-spi",
558 .owner = THIS_MODULE,
559 .of_match_table = mpc512x_psc_spi_of_match,
560 },
561};
562module_platform_driver(mpc512x_psc_spi_of_driver);
563
564MODULE_AUTHOR("John Rigby");
565MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
566MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC512x PSC in SPI mode driver.
4 *
5 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
6 * Original port from 52xx driver:
7 * Hongjun Chen <hong-jun.chen@freescale.com>
8 *
9 * Fork of mpc52xx_psc_spi.c:
10 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/of_platform.h>
20#include <linux/completion.h>
21#include <linux/io.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/spi/spi.h>
25#include <linux/fsl_devices.h>
26#include <linux/gpio.h>
27#include <asm/mpc52xx_psc.h>
28
29enum {
30 TYPE_MPC5121,
31 TYPE_MPC5125,
32};
33
34/*
35 * This macro abstracts the differences in the PSC register layout between
36 * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
37 */
38#define psc_addr(mps, regname) ({ \
39 void *__ret = NULL; \
40 switch (mps->type) { \
41 case TYPE_MPC5121: { \
42 struct mpc52xx_psc __iomem *psc = mps->psc; \
43 __ret = &psc->regname; \
44 }; \
45 break; \
46 case TYPE_MPC5125: { \
47 struct mpc5125_psc __iomem *psc = mps->psc; \
48 __ret = &psc->regname; \
49 }; \
50 break; \
51 } \
52 __ret; })
53
54struct mpc512x_psc_spi {
55 void (*cs_control)(struct spi_device *spi, bool on);
56
57 /* driver internal data */
58 int type;
59 void __iomem *psc;
60 struct mpc512x_psc_fifo __iomem *fifo;
61 unsigned int irq;
62 u8 bits_per_word;
63 struct clk *clk_mclk;
64 struct clk *clk_ipg;
65 u32 mclk_rate;
66
67 struct completion txisrdone;
68};
69
70/* controller state */
71struct mpc512x_psc_spi_cs {
72 int bits_per_word;
73 int speed_hz;
74};
75
76/* set clock freq, clock ramp, bits per work
77 * if t is NULL then reset the values to the default values
78 */
79static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
80 struct spi_transfer *t)
81{
82 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
83
84 cs->speed_hz = (t && t->speed_hz)
85 ? t->speed_hz : spi->max_speed_hz;
86 cs->bits_per_word = (t && t->bits_per_word)
87 ? t->bits_per_word : spi->bits_per_word;
88 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
89 return 0;
90}
91
92static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
93{
94 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
95 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
96 u32 sicr;
97 u32 ccr;
98 int speed;
99 u16 bclkdiv;
100
101 sicr = in_be32(psc_addr(mps, sicr));
102
103 /* Set clock phase and polarity */
104 if (spi->mode & SPI_CPHA)
105 sicr |= 0x00001000;
106 else
107 sicr &= ~0x00001000;
108
109 if (spi->mode & SPI_CPOL)
110 sicr |= 0x00002000;
111 else
112 sicr &= ~0x00002000;
113
114 if (spi->mode & SPI_LSB_FIRST)
115 sicr |= 0x10000000;
116 else
117 sicr &= ~0x10000000;
118 out_be32(psc_addr(mps, sicr), sicr);
119
120 ccr = in_be32(psc_addr(mps, ccr));
121 ccr &= 0xFF000000;
122 speed = cs->speed_hz;
123 if (!speed)
124 speed = 1000000; /* default 1MHz */
125 bclkdiv = (mps->mclk_rate / speed) - 1;
126
127 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
128 out_be32(psc_addr(mps, ccr), ccr);
129 mps->bits_per_word = cs->bits_per_word;
130
131 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
132 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
133}
134
135static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
136{
137 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
138
139 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
140 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
141
142}
143
144/* extract and scale size field in txsz or rxsz */
145#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
146
147#define EOFBYTE 1
148
149static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
150 struct spi_transfer *t)
151{
152 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
153 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
154 size_t tx_len = t->len;
155 size_t rx_len = t->len;
156 u8 *tx_buf = (u8 *)t->tx_buf;
157 u8 *rx_buf = (u8 *)t->rx_buf;
158
159 if (!tx_buf && !rx_buf && t->len)
160 return -EINVAL;
161
162 while (rx_len || tx_len) {
163 size_t txcount;
164 u8 data;
165 size_t fifosz;
166 size_t rxcount;
167 int rxtries;
168
169 /*
170 * send the TX bytes in as large a chunk as possible
171 * but neither exceed the TX nor the RX FIFOs
172 */
173 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
174 txcount = min(fifosz, tx_len);
175 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
176 fifosz -= in_be32(&fifo->rxcnt) + 1;
177 txcount = min(fifosz, txcount);
178 if (txcount) {
179
180 /* fill the TX FIFO */
181 while (txcount-- > 0) {
182 data = tx_buf ? *tx_buf++ : 0;
183 if (tx_len == EOFBYTE && t->cs_change)
184 setbits32(&fifo->txcmd,
185 MPC512x_PSC_FIFO_EOF);
186 out_8(&fifo->txdata_8, data);
187 tx_len--;
188 }
189
190 /* have the ISR trigger when the TX FIFO is empty */
191 reinit_completion(&mps->txisrdone);
192 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
193 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
194 wait_for_completion(&mps->txisrdone);
195 }
196
197 /*
198 * consume as much RX data as the FIFO holds, while we
199 * iterate over the transfer's TX data length
200 *
201 * only insist in draining all the remaining RX bytes
202 * when the TX bytes were exhausted (that's at the very
203 * end of this transfer, not when still iterating over
204 * the transfer's chunks)
205 */
206 rxtries = 50;
207 do {
208
209 /*
210 * grab whatever was in the FIFO when we started
211 * looking, don't bother fetching what was added to
212 * the FIFO while we read from it -- we'll return
213 * here eventually and prefer sending out remaining
214 * TX data
215 */
216 fifosz = in_be32(&fifo->rxcnt);
217 rxcount = min(fifosz, rx_len);
218 while (rxcount-- > 0) {
219 data = in_8(&fifo->rxdata_8);
220 if (rx_buf)
221 *rx_buf++ = data;
222 rx_len--;
223 }
224
225 /*
226 * come back later if there still is TX data to send,
227 * bail out of the RX drain loop if all of the TX data
228 * was sent and all of the RX data was received (i.e.
229 * when the transmission has completed)
230 */
231 if (tx_len)
232 break;
233 if (!rx_len)
234 break;
235
236 /*
237 * TX data transmission has completed while RX data
238 * is still pending -- that's a transient situation
239 * which depends on wire speed and specific
240 * hardware implementation details (buffering) yet
241 * should resolve very quickly
242 *
243 * just yield for a moment to not hog the CPU for
244 * too long when running SPI at low speed
245 *
246 * the timeout range is rather arbitrary and tries
247 * to balance throughput against system load; the
248 * chosen values result in a minimal timeout of 50
249 * times 10us and thus work at speeds as low as
250 * some 20kbps, while the maximum timeout at the
251 * transfer's end could be 5ms _if_ nothing else
252 * ticks in the system _and_ RX data still wasn't
253 * received, which only occurs in situations that
254 * are exceptional; removing the unpredictability
255 * of the timeout either decreases throughput
256 * (longer timeouts), or puts more load on the
257 * system (fixed short timeouts) or requires the
258 * use of a timeout API instead of a counter and an
259 * unknown inner delay
260 */
261 usleep_range(10, 100);
262
263 } while (--rxtries > 0);
264 if (!tx_len && rx_len && !rxtries) {
265 /*
266 * not enough RX bytes even after several retries
267 * and the resulting rather long timeout?
268 */
269 rxcount = in_be32(&fifo->rxcnt);
270 dev_warn(&spi->dev,
271 "short xfer, missing %zd RX bytes, FIFO level %zd\n",
272 rx_len, rxcount);
273 }
274
275 /*
276 * drain and drop RX data which "should not be there" in
277 * the first place, for undisturbed transmission this turns
278 * into a NOP (except for the FIFO level fetch)
279 */
280 if (!tx_len && !rx_len) {
281 while (in_be32(&fifo->rxcnt))
282 in_8(&fifo->rxdata_8);
283 }
284
285 }
286 return 0;
287}
288
289static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
290 struct spi_message *m)
291{
292 struct spi_device *spi;
293 unsigned cs_change;
294 int status;
295 struct spi_transfer *t;
296
297 spi = m->spi;
298 cs_change = 1;
299 status = 0;
300 list_for_each_entry(t, &m->transfers, transfer_list) {
301 status = mpc512x_psc_spi_transfer_setup(spi, t);
302 if (status < 0)
303 break;
304
305 if (cs_change)
306 mpc512x_psc_spi_activate_cs(spi);
307 cs_change = t->cs_change;
308
309 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
310 if (status)
311 break;
312 m->actual_length += t->len;
313
314 spi_transfer_delay_exec(t);
315
316 if (cs_change)
317 mpc512x_psc_spi_deactivate_cs(spi);
318 }
319
320 m->status = status;
321 if (m->complete)
322 m->complete(m->context);
323
324 if (status || !cs_change)
325 mpc512x_psc_spi_deactivate_cs(spi);
326
327 mpc512x_psc_spi_transfer_setup(spi, NULL);
328
329 spi_finalize_current_message(master);
330 return status;
331}
332
333static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
334{
335 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
336
337 dev_dbg(&master->dev, "%s()\n", __func__);
338
339 /* Zero MR2 */
340 in_8(psc_addr(mps, mr2));
341 out_8(psc_addr(mps, mr2), 0x0);
342
343 /* enable transmitter/receiver */
344 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
345
346 return 0;
347}
348
349static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
350{
351 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
352 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
353
354 dev_dbg(&master->dev, "%s()\n", __func__);
355
356 /* disable transmitter/receiver and fifo interrupt */
357 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
358 out_be32(&fifo->tximr, 0);
359
360 return 0;
361}
362
363static int mpc512x_psc_spi_setup(struct spi_device *spi)
364{
365 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
366 int ret;
367
368 if (spi->bits_per_word % 8)
369 return -EINVAL;
370
371 if (!cs) {
372 cs = kzalloc(sizeof *cs, GFP_KERNEL);
373 if (!cs)
374 return -ENOMEM;
375
376 if (gpio_is_valid(spi->cs_gpio)) {
377 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
378 if (ret) {
379 dev_err(&spi->dev, "can't get CS gpio: %d\n",
380 ret);
381 kfree(cs);
382 return ret;
383 }
384 gpio_direction_output(spi->cs_gpio,
385 spi->mode & SPI_CS_HIGH ? 0 : 1);
386 }
387
388 spi->controller_state = cs;
389 }
390
391 cs->bits_per_word = spi->bits_per_word;
392 cs->speed_hz = spi->max_speed_hz;
393
394 return 0;
395}
396
397static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
398{
399 if (gpio_is_valid(spi->cs_gpio))
400 gpio_free(spi->cs_gpio);
401 kfree(spi->controller_state);
402}
403
404static int mpc512x_psc_spi_port_config(struct spi_master *master,
405 struct mpc512x_psc_spi *mps)
406{
407 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
408 u32 sicr;
409 u32 ccr;
410 int speed;
411 u16 bclkdiv;
412
413 /* Reset the PSC into a known state */
414 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
415 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
416 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
417
418 /* Disable psc interrupts all useful interrupts are in fifo */
419 out_be16(psc_addr(mps, isr_imr.imr), 0);
420
421 /* Disable fifo interrupts, will be enabled later */
422 out_be32(&fifo->tximr, 0);
423 out_be32(&fifo->rximr, 0);
424
425 /* Setup fifo slice address and size */
426 /*out_be32(&fifo->txsz, 0x0fe00004);*/
427 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
428
429 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
430 0x00800000 | /* GenClk = 1 -- internal clk */
431 0x00008000 | /* SPI = 1 */
432 0x00004000 | /* MSTR = 1 -- SPI master */
433 0x00000800; /* UseEOF = 1 -- SS low until EOF */
434
435 out_be32(psc_addr(mps, sicr), sicr);
436
437 ccr = in_be32(psc_addr(mps, ccr));
438 ccr &= 0xFF000000;
439 speed = 1000000; /* default 1MHz */
440 bclkdiv = (mps->mclk_rate / speed) - 1;
441 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
442 out_be32(psc_addr(mps, ccr), ccr);
443
444 /* Set 2ms DTL delay */
445 out_8(psc_addr(mps, ctur), 0x00);
446 out_8(psc_addr(mps, ctlr), 0x82);
447
448 /* we don't use the alarms */
449 out_be32(&fifo->rxalarm, 0xfff);
450 out_be32(&fifo->txalarm, 0);
451
452 /* Enable FIFO slices for Rx/Tx */
453 out_be32(&fifo->rxcmd,
454 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
455 out_be32(&fifo->txcmd,
456 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
457
458 mps->bits_per_word = 8;
459
460 return 0;
461}
462
463static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
464{
465 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
466 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
467
468 /* clear interrupt and wake up the rx/tx routine */
469 if (in_be32(&fifo->txisr) &
470 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
471 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
472 out_be32(&fifo->tximr, 0);
473 complete(&mps->txisrdone);
474 return IRQ_HANDLED;
475 }
476 return IRQ_NONE;
477}
478
479static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
480{
481 gpio_set_value(spi->cs_gpio, onoff);
482}
483
484static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
485 u32 size, unsigned int irq)
486{
487 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
488 struct mpc512x_psc_spi *mps;
489 struct spi_master *master;
490 int ret;
491 void *tempp;
492 struct clk *clk;
493
494 master = spi_alloc_master(dev, sizeof *mps);
495 if (master == NULL)
496 return -ENOMEM;
497
498 dev_set_drvdata(dev, master);
499 mps = spi_master_get_devdata(master);
500 mps->type = (int)of_device_get_match_data(dev);
501 mps->irq = irq;
502
503 if (pdata == NULL) {
504 mps->cs_control = mpc512x_spi_cs_control;
505 } else {
506 mps->cs_control = pdata->cs_control;
507 master->bus_num = pdata->bus_num;
508 master->num_chipselect = pdata->max_chipselect;
509 }
510
511 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
512 master->setup = mpc512x_psc_spi_setup;
513 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
514 master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
515 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
516 master->cleanup = mpc512x_psc_spi_cleanup;
517 master->dev.of_node = dev->of_node;
518
519 tempp = devm_ioremap(dev, regaddr, size);
520 if (!tempp) {
521 dev_err(dev, "could not ioremap I/O port range\n");
522 ret = -EFAULT;
523 goto free_master;
524 }
525 mps->psc = tempp;
526 mps->fifo =
527 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
528 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
529 "mpc512x-psc-spi", mps);
530 if (ret)
531 goto free_master;
532 init_completion(&mps->txisrdone);
533
534 clk = devm_clk_get(dev, "mclk");
535 if (IS_ERR(clk)) {
536 ret = PTR_ERR(clk);
537 goto free_master;
538 }
539 ret = clk_prepare_enable(clk);
540 if (ret)
541 goto free_master;
542 mps->clk_mclk = clk;
543 mps->mclk_rate = clk_get_rate(clk);
544
545 clk = devm_clk_get(dev, "ipg");
546 if (IS_ERR(clk)) {
547 ret = PTR_ERR(clk);
548 goto free_mclk_clock;
549 }
550 ret = clk_prepare_enable(clk);
551 if (ret)
552 goto free_mclk_clock;
553 mps->clk_ipg = clk;
554
555 ret = mpc512x_psc_spi_port_config(master, mps);
556 if (ret < 0)
557 goto free_ipg_clock;
558
559 ret = devm_spi_register_master(dev, master);
560 if (ret < 0)
561 goto free_ipg_clock;
562
563 return ret;
564
565free_ipg_clock:
566 clk_disable_unprepare(mps->clk_ipg);
567free_mclk_clock:
568 clk_disable_unprepare(mps->clk_mclk);
569free_master:
570 spi_master_put(master);
571
572 return ret;
573}
574
575static int mpc512x_psc_spi_do_remove(struct device *dev)
576{
577 struct spi_master *master = dev_get_drvdata(dev);
578 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
579
580 clk_disable_unprepare(mps->clk_mclk);
581 clk_disable_unprepare(mps->clk_ipg);
582
583 return 0;
584}
585
586static int mpc512x_psc_spi_of_probe(struct platform_device *op)
587{
588 const u32 *regaddr_p;
589 u64 regaddr64, size64;
590
591 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
592 if (!regaddr_p) {
593 dev_err(&op->dev, "Invalid PSC address\n");
594 return -EINVAL;
595 }
596 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
597
598 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
599 irq_of_parse_and_map(op->dev.of_node, 0));
600}
601
602static int mpc512x_psc_spi_of_remove(struct platform_device *op)
603{
604 return mpc512x_psc_spi_do_remove(&op->dev);
605}
606
607static const struct of_device_id mpc512x_psc_spi_of_match[] = {
608 { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
609 { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
610 {},
611};
612
613MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
614
615static struct platform_driver mpc512x_psc_spi_of_driver = {
616 .probe = mpc512x_psc_spi_of_probe,
617 .remove = mpc512x_psc_spi_of_remove,
618 .driver = {
619 .name = "mpc512x-psc-spi",
620 .of_match_table = mpc512x_psc_spi_of_match,
621 },
622};
623module_platform_driver(mpc512x_psc_spi_of_driver);
624
625MODULE_AUTHOR("John Rigby");
626MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
627MODULE_LICENSE("GPL");