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1/*
2 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
3 *
4 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/bitops.h>
14#include <linux/cdev.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmapool.h>
17#include <linux/fs.h>
18#include <linux/hdlc.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/platform_device.h>
22#include <linux/poll.h>
23#include <linux/slab.h>
24#include <mach/npe.h>
25#include <mach/qmgr.h>
26
27#define DEBUG_DESC 0
28#define DEBUG_RX 0
29#define DEBUG_TX 0
30#define DEBUG_PKT_BYTES 0
31#define DEBUG_CLOSE 0
32
33#define DRV_NAME "ixp4xx_hss"
34
35#define PKT_EXTRA_FLAGS 0 /* orig 1 */
36#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
37#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
38
39#define RX_DESCS 16 /* also length of all RX queues */
40#define TX_DESCS 16 /* also length of all TX queues */
41
42#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
43#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
44#define MAX_CLOSE_WAIT 1000 /* microseconds */
45#define HSS_COUNT 2
46#define FRAME_SIZE 256 /* doesn't matter at this point */
47#define FRAME_OFFSET 0
48#define MAX_CHANNELS (FRAME_SIZE / 8)
49
50#define NAPI_WEIGHT 16
51
52/* Queue IDs */
53#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
54#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
55#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
56#define HSS0_PKT_TX1_QUEUE 15
57#define HSS0_PKT_TX2_QUEUE 16
58#define HSS0_PKT_TX3_QUEUE 17
59#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
60#define HSS0_PKT_RXFREE1_QUEUE 19
61#define HSS0_PKT_RXFREE2_QUEUE 20
62#define HSS0_PKT_RXFREE3_QUEUE 21
63#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
64
65#define HSS1_CHL_RXTRIG_QUEUE 10
66#define HSS1_PKT_RX_QUEUE 0
67#define HSS1_PKT_TX0_QUEUE 5
68#define HSS1_PKT_TX1_QUEUE 6
69#define HSS1_PKT_TX2_QUEUE 7
70#define HSS1_PKT_TX3_QUEUE 8
71#define HSS1_PKT_RXFREE0_QUEUE 1
72#define HSS1_PKT_RXFREE1_QUEUE 2
73#define HSS1_PKT_RXFREE2_QUEUE 3
74#define HSS1_PKT_RXFREE3_QUEUE 4
75#define HSS1_PKT_TXDONE_QUEUE 9
76
77#define NPE_PKT_MODE_HDLC 0
78#define NPE_PKT_MODE_RAW 1
79#define NPE_PKT_MODE_56KMODE 2
80#define NPE_PKT_MODE_56KENDIAN_MSB 4
81
82/* PKT_PIPE_HDLC_CFG_WRITE flags */
83#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
84#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
85#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
86
87
88/* hss_config, PCRs */
89/* Frame sync sampling, default = active low */
90#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
91#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
92#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
93
94/* Frame sync pin: input (default) or output generated off a given clk edge */
95#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
96#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
97
98/* Frame and data clock sampling on edge, default = falling */
99#define PCR_FCLK_EDGE_RISING 0x08000000
100#define PCR_DCLK_EDGE_RISING 0x04000000
101
102/* Clock direction, default = input */
103#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
104
105/* Generate/Receive frame pulses, default = enabled */
106#define PCR_FRM_PULSE_DISABLED 0x01000000
107
108 /* Data rate is full (default) or half the configured clk speed */
109#define PCR_HALF_CLK_RATE 0x00200000
110
111/* Invert data between NPE and HSS FIFOs? (default = no) */
112#define PCR_DATA_POLARITY_INVERT 0x00100000
113
114/* TX/RX endianness, default = LSB */
115#define PCR_MSB_ENDIAN 0x00080000
116
117/* Normal (default) / open drain mode (TX only) */
118#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
119
120/* No framing bit transmitted and expected on RX? (default = framing bit) */
121#define PCR_SOF_NO_FBIT 0x00020000
122
123/* Drive data pins? */
124#define PCR_TX_DATA_ENABLE 0x00010000
125
126/* Voice 56k type: drive the data pins low (default), high, high Z */
127#define PCR_TX_V56K_HIGH 0x00002000
128#define PCR_TX_V56K_HIGH_IMP 0x00004000
129
130/* Unassigned type: drive the data pins low (default), high, high Z */
131#define PCR_TX_UNASS_HIGH 0x00000800
132#define PCR_TX_UNASS_HIGH_IMP 0x00001000
133
134/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
135#define PCR_TX_FB_HIGH_IMP 0x00000400
136
137/* 56k data endiannes - which bit unused: high (default) or low */
138#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
139
140/* 56k data transmission type: 32/8 bit data (default) or 56K data */
141#define PCR_TX_56KS_56K_DATA 0x00000100
142
143/* hss_config, cCR */
144/* Number of packetized clients, default = 1 */
145#define CCR_NPE_HFIFO_2_HDLC 0x04000000
146#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
147
148/* default = no loopback */
149#define CCR_LOOPBACK 0x02000000
150
151/* HSS number, default = 0 (first) */
152#define CCR_SECOND_HSS 0x01000000
153
154
155/* hss_config, clkCR: main:10, num:10, denom:12 */
156#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
157
158#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
159#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
160#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
161#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
162#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
163#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
164
165#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
166#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
167#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
168#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
169#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
170#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
171
172/*
173 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
174 * A (10 bits), B (10 bits) and C (12 bits).
175 * IXP42x HSS clock generator operation (verified with an oscilloscope):
176 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
177 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
178 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
179 * (A + 1) bits wide.
180 *
181 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
182 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
183 * minimum freq = 66.666 MHz / (A + 1)
184 * maximum freq = 66.666 MHz / A
185 *
186 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
187 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
188 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
189 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
190 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
191 * The sequence consists of 4 complete clock periods, thus the average
192 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
193 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
194 */
195
196/* hss_config, LUT entries */
197#define TDMMAP_UNASSIGNED 0
198#define TDMMAP_HDLC 1 /* HDLC - packetized */
199#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
200#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
201
202/* offsets into HSS config */
203#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
204#define HSS_CONFIG_RX_PCR 0x04
205#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
206#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
207#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
208#define HSS_CONFIG_RX_FCR 0x14
209#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
210#define HSS_CONFIG_RX_LUT 0x38
211
212
213/* NPE command codes */
214/* writes the ConfigWord value to the location specified by offset */
215#define PORT_CONFIG_WRITE 0x40
216
217/* triggers the NPE to load the contents of the configuration table */
218#define PORT_CONFIG_LOAD 0x41
219
220/* triggers the NPE to return an HssErrorReadResponse message */
221#define PORT_ERROR_READ 0x42
222
223/* triggers the NPE to reset internal status and enable the HssPacketized
224 operation for the flow specified by pPipe */
225#define PKT_PIPE_FLOW_ENABLE 0x50
226#define PKT_PIPE_FLOW_DISABLE 0x51
227#define PKT_NUM_PIPES_WRITE 0x52
228#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
229#define PKT_PIPE_HDLC_CFG_WRITE 0x54
230#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
231#define PKT_PIPE_RX_SIZE_WRITE 0x56
232#define PKT_PIPE_MODE_WRITE 0x57
233
234/* HDLC packet status values - desc->status */
235#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
236#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
237#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
238#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
239 this packet (if buf_len < pkt_len) */
240#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
241#define ERR_HDLC_ABORT 6 /* abort sequence received */
242#define ERR_DISCONNECTING 7 /* disconnect is in progress */
243
244
245#ifdef __ARMEB__
246typedef struct sk_buff buffer_t;
247#define free_buffer dev_kfree_skb
248#define free_buffer_irq dev_kfree_skb_irq
249#else
250typedef void buffer_t;
251#define free_buffer kfree
252#define free_buffer_irq kfree
253#endif
254
255struct port {
256 struct device *dev;
257 struct npe *npe;
258 struct net_device *netdev;
259 struct napi_struct napi;
260 struct hss_plat_info *plat;
261 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
262 struct desc *desc_tab; /* coherent */
263 u32 desc_tab_phys;
264 unsigned int id;
265 unsigned int clock_type, clock_rate, loopback;
266 unsigned int initialized, carrier;
267 u8 hdlc_cfg;
268 u32 clock_reg;
269};
270
271/* NPE message structure */
272struct msg {
273#ifdef __ARMEB__
274 u8 cmd, unused, hss_port, index;
275 union {
276 struct { u8 data8a, data8b, data8c, data8d; };
277 struct { u16 data16a, data16b; };
278 struct { u32 data32; };
279 };
280#else
281 u8 index, hss_port, unused, cmd;
282 union {
283 struct { u8 data8d, data8c, data8b, data8a; };
284 struct { u16 data16b, data16a; };
285 struct { u32 data32; };
286 };
287#endif
288};
289
290/* HDLC packet descriptor */
291struct desc {
292 u32 next; /* pointer to next buffer, unused */
293
294#ifdef __ARMEB__
295 u16 buf_len; /* buffer length */
296 u16 pkt_len; /* packet length */
297 u32 data; /* pointer to data buffer in RAM */
298 u8 status;
299 u8 error_count;
300 u16 __reserved;
301#else
302 u16 pkt_len; /* packet length */
303 u16 buf_len; /* buffer length */
304 u32 data; /* pointer to data buffer in RAM */
305 u16 __reserved;
306 u8 error_count;
307 u8 status;
308#endif
309 u32 __reserved1[4];
310};
311
312
313#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
314 (n) * sizeof(struct desc))
315#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
316
317#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
318 ((n) + RX_DESCS) * sizeof(struct desc))
319#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
320
321/*****************************************************************************
322 * global variables
323 ****************************************************************************/
324
325static int ports_open;
326static struct dma_pool *dma_pool;
327static spinlock_t npe_lock;
328
329static const struct {
330 int tx, txdone, rx, rxfree;
331}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
332 HSS0_PKT_RXFREE0_QUEUE},
333 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
334 HSS1_PKT_RXFREE0_QUEUE},
335};
336
337/*****************************************************************************
338 * utility functions
339 ****************************************************************************/
340
341static inline struct port* dev_to_port(struct net_device *dev)
342{
343 return dev_to_hdlc(dev)->priv;
344}
345
346#ifndef __ARMEB__
347static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
348{
349 int i;
350 for (i = 0; i < cnt; i++)
351 dest[i] = swab32(src[i]);
352}
353#endif
354
355/*****************************************************************************
356 * HSS access
357 ****************************************************************************/
358
359static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
360{
361 u32 *val = (u32*)msg;
362 if (npe_send_message(port->npe, msg, what)) {
363 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
364 port->id, val[0], val[1], npe_name(port->npe));
365 BUG();
366 }
367}
368
369static void hss_config_set_lut(struct port *port)
370{
371 struct msg msg;
372 int ch;
373
374 memset(&msg, 0, sizeof(msg));
375 msg.cmd = PORT_CONFIG_WRITE;
376 msg.hss_port = port->id;
377
378 for (ch = 0; ch < MAX_CHANNELS; ch++) {
379 msg.data32 >>= 2;
380 msg.data32 |= TDMMAP_HDLC << 30;
381
382 if (ch % 16 == 15) {
383 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
384 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
385
386 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
387 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
388 }
389 }
390}
391
392static void hss_config(struct port *port)
393{
394 struct msg msg;
395
396 memset(&msg, 0, sizeof(msg));
397 msg.cmd = PORT_CONFIG_WRITE;
398 msg.hss_port = port->id;
399 msg.index = HSS_CONFIG_TX_PCR;
400 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
401 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
402 if (port->clock_type == CLOCK_INT)
403 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
404 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
405
406 msg.index = HSS_CONFIG_RX_PCR;
407 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
408 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
409
410 memset(&msg, 0, sizeof(msg));
411 msg.cmd = PORT_CONFIG_WRITE;
412 msg.hss_port = port->id;
413 msg.index = HSS_CONFIG_CORE_CR;
414 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
415 (port->id ? CCR_SECOND_HSS : 0);
416 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
417
418 memset(&msg, 0, sizeof(msg));
419 msg.cmd = PORT_CONFIG_WRITE;
420 msg.hss_port = port->id;
421 msg.index = HSS_CONFIG_CLOCK_CR;
422 msg.data32 = port->clock_reg;
423 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
424
425 memset(&msg, 0, sizeof(msg));
426 msg.cmd = PORT_CONFIG_WRITE;
427 msg.hss_port = port->id;
428 msg.index = HSS_CONFIG_TX_FCR;
429 msg.data16a = FRAME_OFFSET;
430 msg.data16b = FRAME_SIZE - 1;
431 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
432
433 memset(&msg, 0, sizeof(msg));
434 msg.cmd = PORT_CONFIG_WRITE;
435 msg.hss_port = port->id;
436 msg.index = HSS_CONFIG_RX_FCR;
437 msg.data16a = FRAME_OFFSET;
438 msg.data16b = FRAME_SIZE - 1;
439 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
440
441 hss_config_set_lut(port);
442
443 memset(&msg, 0, sizeof(msg));
444 msg.cmd = PORT_CONFIG_LOAD;
445 msg.hss_port = port->id;
446 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
447
448 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
449 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
450 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
451 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
452 BUG();
453 }
454
455 /* HDLC may stop working without this - check FIXME */
456 npe_recv_message(port->npe, &msg, "FLUSH_IT");
457}
458
459static void hss_set_hdlc_cfg(struct port *port)
460{
461 struct msg msg;
462
463 memset(&msg, 0, sizeof(msg));
464 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
465 msg.hss_port = port->id;
466 msg.data8a = port->hdlc_cfg; /* rx_cfg */
467 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
468 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
469}
470
471static u32 hss_get_status(struct port *port)
472{
473 struct msg msg;
474
475 memset(&msg, 0, sizeof(msg));
476 msg.cmd = PORT_ERROR_READ;
477 msg.hss_port = port->id;
478 hss_npe_send(port, &msg, "PORT_ERROR_READ");
479 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
480 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
481 BUG();
482 }
483
484 return msg.data32;
485}
486
487static void hss_start_hdlc(struct port *port)
488{
489 struct msg msg;
490
491 memset(&msg, 0, sizeof(msg));
492 msg.cmd = PKT_PIPE_FLOW_ENABLE;
493 msg.hss_port = port->id;
494 msg.data32 = 0;
495 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
496}
497
498static void hss_stop_hdlc(struct port *port)
499{
500 struct msg msg;
501
502 memset(&msg, 0, sizeof(msg));
503 msg.cmd = PKT_PIPE_FLOW_DISABLE;
504 msg.hss_port = port->id;
505 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
506 hss_get_status(port); /* make sure it's halted */
507}
508
509static int hss_load_firmware(struct port *port)
510{
511 struct msg msg;
512 int err;
513
514 if (port->initialized)
515 return 0;
516
517 if (!npe_running(port->npe) &&
518 (err = npe_load_firmware(port->npe, npe_name(port->npe),
519 port->dev)))
520 return err;
521
522 /* HDLC mode configuration */
523 memset(&msg, 0, sizeof(msg));
524 msg.cmd = PKT_NUM_PIPES_WRITE;
525 msg.hss_port = port->id;
526 msg.data8a = PKT_NUM_PIPES;
527 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
528
529 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
530 msg.data8a = PKT_PIPE_FIFO_SIZEW;
531 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
532
533 msg.cmd = PKT_PIPE_MODE_WRITE;
534 msg.data8a = NPE_PKT_MODE_HDLC;
535 /* msg.data8b = inv_mask */
536 /* msg.data8c = or_mask */
537 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
538
539 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
540 msg.data16a = HDLC_MAX_MRU; /* including CRC */
541 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
542
543 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
544 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
545 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
546
547 port->initialized = 1;
548 return 0;
549}
550
551/*****************************************************************************
552 * packetized (HDLC) operation
553 ****************************************************************************/
554
555static inline void debug_pkt(struct net_device *dev, const char *func,
556 u8 *data, int len)
557{
558#if DEBUG_PKT_BYTES
559 int i;
560
561 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
562 for (i = 0; i < len; i++) {
563 if (i >= DEBUG_PKT_BYTES)
564 break;
565 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
566 }
567 printk("\n");
568#endif
569}
570
571
572static inline void debug_desc(u32 phys, struct desc *desc)
573{
574#if DEBUG_DESC
575 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
576 phys, desc->next, desc->buf_len, desc->pkt_len,
577 desc->data, desc->status, desc->error_count);
578#endif
579}
580
581static inline int queue_get_desc(unsigned int queue, struct port *port,
582 int is_tx)
583{
584 u32 phys, tab_phys, n_desc;
585 struct desc *tab;
586
587 if (!(phys = qmgr_get_entry(queue)))
588 return -1;
589
590 BUG_ON(phys & 0x1F);
591 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
592 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
593 n_desc = (phys - tab_phys) / sizeof(struct desc);
594 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
595 debug_desc(phys, &tab[n_desc]);
596 BUG_ON(tab[n_desc].next);
597 return n_desc;
598}
599
600static inline void queue_put_desc(unsigned int queue, u32 phys,
601 struct desc *desc)
602{
603 debug_desc(phys, desc);
604 BUG_ON(phys & 0x1F);
605 qmgr_put_entry(queue, phys);
606 /* Don't check for queue overflow here, we've allocated sufficient
607 length and queues >= 32 don't support this check anyway. */
608}
609
610
611static inline void dma_unmap_tx(struct port *port, struct desc *desc)
612{
613#ifdef __ARMEB__
614 dma_unmap_single(&port->netdev->dev, desc->data,
615 desc->buf_len, DMA_TO_DEVICE);
616#else
617 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
618 ALIGN((desc->data & 3) + desc->buf_len, 4),
619 DMA_TO_DEVICE);
620#endif
621}
622
623
624static void hss_hdlc_set_carrier(void *pdev, int carrier)
625{
626 struct net_device *netdev = pdev;
627 struct port *port = dev_to_port(netdev);
628 unsigned long flags;
629
630 spin_lock_irqsave(&npe_lock, flags);
631 port->carrier = carrier;
632 if (!port->loopback) {
633 if (carrier)
634 netif_carrier_on(netdev);
635 else
636 netif_carrier_off(netdev);
637 }
638 spin_unlock_irqrestore(&npe_lock, flags);
639}
640
641static void hss_hdlc_rx_irq(void *pdev)
642{
643 struct net_device *dev = pdev;
644 struct port *port = dev_to_port(dev);
645
646#if DEBUG_RX
647 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
648#endif
649 qmgr_disable_irq(queue_ids[port->id].rx);
650 napi_schedule(&port->napi);
651}
652
653static int hss_hdlc_poll(struct napi_struct *napi, int budget)
654{
655 struct port *port = container_of(napi, struct port, napi);
656 struct net_device *dev = port->netdev;
657 unsigned int rxq = queue_ids[port->id].rx;
658 unsigned int rxfreeq = queue_ids[port->id].rxfree;
659 int received = 0;
660
661#if DEBUG_RX
662 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
663#endif
664
665 while (received < budget) {
666 struct sk_buff *skb;
667 struct desc *desc;
668 int n;
669#ifdef __ARMEB__
670 struct sk_buff *temp;
671 u32 phys;
672#endif
673
674 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
675#if DEBUG_RX
676 printk(KERN_DEBUG "%s: hss_hdlc_poll"
677 " napi_complete\n", dev->name);
678#endif
679 napi_complete(napi);
680 qmgr_enable_irq(rxq);
681 if (!qmgr_stat_empty(rxq) &&
682 napi_reschedule(napi)) {
683#if DEBUG_RX
684 printk(KERN_DEBUG "%s: hss_hdlc_poll"
685 " napi_reschedule succeeded\n",
686 dev->name);
687#endif
688 qmgr_disable_irq(rxq);
689 continue;
690 }
691#if DEBUG_RX
692 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
693 dev->name);
694#endif
695 return received; /* all work done */
696 }
697
698 desc = rx_desc_ptr(port, n);
699#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
700 if (desc->error_count)
701 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
702 " errors %u\n", dev->name, desc->status,
703 desc->error_count);
704#endif
705 skb = NULL;
706 switch (desc->status) {
707 case 0:
708#ifdef __ARMEB__
709 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
710 phys = dma_map_single(&dev->dev, skb->data,
711 RX_SIZE,
712 DMA_FROM_DEVICE);
713 if (dma_mapping_error(&dev->dev, phys)) {
714 dev_kfree_skb(skb);
715 skb = NULL;
716 }
717 }
718#else
719 skb = netdev_alloc_skb(dev, desc->pkt_len);
720#endif
721 if (!skb)
722 dev->stats.rx_dropped++;
723 break;
724 case ERR_HDLC_ALIGN:
725 case ERR_HDLC_ABORT:
726 dev->stats.rx_frame_errors++;
727 dev->stats.rx_errors++;
728 break;
729 case ERR_HDLC_FCS:
730 dev->stats.rx_crc_errors++;
731 dev->stats.rx_errors++;
732 break;
733 case ERR_HDLC_TOO_LONG:
734 dev->stats.rx_length_errors++;
735 dev->stats.rx_errors++;
736 break;
737 default: /* FIXME - remove printk */
738 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
739 desc->status, desc->error_count);
740 dev->stats.rx_errors++;
741 }
742
743 if (!skb) {
744 /* put the desc back on RX-ready queue */
745 desc->buf_len = RX_SIZE;
746 desc->pkt_len = desc->status = 0;
747 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
748 continue;
749 }
750
751 /* process received frame */
752#ifdef __ARMEB__
753 temp = skb;
754 skb = port->rx_buff_tab[n];
755 dma_unmap_single(&dev->dev, desc->data,
756 RX_SIZE, DMA_FROM_DEVICE);
757#else
758 dma_sync_single_for_cpu(&dev->dev, desc->data,
759 RX_SIZE, DMA_FROM_DEVICE);
760 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
761 ALIGN(desc->pkt_len, 4) / 4);
762#endif
763 skb_put(skb, desc->pkt_len);
764
765 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
766
767 skb->protocol = hdlc_type_trans(skb, dev);
768 dev->stats.rx_packets++;
769 dev->stats.rx_bytes += skb->len;
770 netif_receive_skb(skb);
771
772 /* put the new buffer on RX-free queue */
773#ifdef __ARMEB__
774 port->rx_buff_tab[n] = temp;
775 desc->data = phys;
776#endif
777 desc->buf_len = RX_SIZE;
778 desc->pkt_len = 0;
779 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
780 received++;
781 }
782#if DEBUG_RX
783 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
784#endif
785 return received; /* not all work done */
786}
787
788
789static void hss_hdlc_txdone_irq(void *pdev)
790{
791 struct net_device *dev = pdev;
792 struct port *port = dev_to_port(dev);
793 int n_desc;
794
795#if DEBUG_TX
796 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
797#endif
798 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
799 port, 1)) >= 0) {
800 struct desc *desc;
801 int start;
802
803 desc = tx_desc_ptr(port, n_desc);
804
805 dev->stats.tx_packets++;
806 dev->stats.tx_bytes += desc->pkt_len;
807
808 dma_unmap_tx(port, desc);
809#if DEBUG_TX
810 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
811 dev->name, port->tx_buff_tab[n_desc]);
812#endif
813 free_buffer_irq(port->tx_buff_tab[n_desc]);
814 port->tx_buff_tab[n_desc] = NULL;
815
816 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
817 queue_put_desc(port->plat->txreadyq,
818 tx_desc_phys(port, n_desc), desc);
819 if (start) { /* TX-ready queue was empty */
820#if DEBUG_TX
821 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
822 " ready\n", dev->name);
823#endif
824 netif_wake_queue(dev);
825 }
826 }
827}
828
829static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
830{
831 struct port *port = dev_to_port(dev);
832 unsigned int txreadyq = port->plat->txreadyq;
833 int len, offset, bytes, n;
834 void *mem;
835 u32 phys;
836 struct desc *desc;
837
838#if DEBUG_TX
839 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
840#endif
841
842 if (unlikely(skb->len > HDLC_MAX_MRU)) {
843 dev_kfree_skb(skb);
844 dev->stats.tx_errors++;
845 return NETDEV_TX_OK;
846 }
847
848 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
849
850 len = skb->len;
851#ifdef __ARMEB__
852 offset = 0; /* no need to keep alignment */
853 bytes = len;
854 mem = skb->data;
855#else
856 offset = (int)skb->data & 3; /* keep 32-bit alignment */
857 bytes = ALIGN(offset + len, 4);
858 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
859 dev_kfree_skb(skb);
860 dev->stats.tx_dropped++;
861 return NETDEV_TX_OK;
862 }
863 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
864 dev_kfree_skb(skb);
865#endif
866
867 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
868 if (dma_mapping_error(&dev->dev, phys)) {
869#ifdef __ARMEB__
870 dev_kfree_skb(skb);
871#else
872 kfree(mem);
873#endif
874 dev->stats.tx_dropped++;
875 return NETDEV_TX_OK;
876 }
877
878 n = queue_get_desc(txreadyq, port, 1);
879 BUG_ON(n < 0);
880 desc = tx_desc_ptr(port, n);
881
882#ifdef __ARMEB__
883 port->tx_buff_tab[n] = skb;
884#else
885 port->tx_buff_tab[n] = mem;
886#endif
887 desc->data = phys + offset;
888 desc->buf_len = desc->pkt_len = len;
889
890 wmb();
891 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
892
893 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
894#if DEBUG_TX
895 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
896#endif
897 netif_stop_queue(dev);
898 /* we could miss TX ready interrupt */
899 if (!qmgr_stat_below_low_watermark(txreadyq)) {
900#if DEBUG_TX
901 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
902 dev->name);
903#endif
904 netif_wake_queue(dev);
905 }
906 }
907
908#if DEBUG_TX
909 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
910#endif
911 return NETDEV_TX_OK;
912}
913
914
915static int request_hdlc_queues(struct port *port)
916{
917 int err;
918
919 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
920 "%s:RX-free", port->netdev->name);
921 if (err)
922 return err;
923
924 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
925 "%s:RX", port->netdev->name);
926 if (err)
927 goto rel_rxfree;
928
929 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
930 "%s:TX", port->netdev->name);
931 if (err)
932 goto rel_rx;
933
934 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
935 "%s:TX-ready", port->netdev->name);
936 if (err)
937 goto rel_tx;
938
939 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
940 "%s:TX-done", port->netdev->name);
941 if (err)
942 goto rel_txready;
943 return 0;
944
945rel_txready:
946 qmgr_release_queue(port->plat->txreadyq);
947rel_tx:
948 qmgr_release_queue(queue_ids[port->id].tx);
949rel_rx:
950 qmgr_release_queue(queue_ids[port->id].rx);
951rel_rxfree:
952 qmgr_release_queue(queue_ids[port->id].rxfree);
953 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
954 port->netdev->name);
955 return err;
956}
957
958static void release_hdlc_queues(struct port *port)
959{
960 qmgr_release_queue(queue_ids[port->id].rxfree);
961 qmgr_release_queue(queue_ids[port->id].rx);
962 qmgr_release_queue(queue_ids[port->id].txdone);
963 qmgr_release_queue(queue_ids[port->id].tx);
964 qmgr_release_queue(port->plat->txreadyq);
965}
966
967static int init_hdlc_queues(struct port *port)
968{
969 int i;
970
971 if (!ports_open)
972 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
973 POOL_ALLOC_SIZE, 32, 0)))
974 return -ENOMEM;
975
976 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
977 &port->desc_tab_phys)))
978 return -ENOMEM;
979 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
980 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
981 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
982
983 /* Setup RX buffers */
984 for (i = 0; i < RX_DESCS; i++) {
985 struct desc *desc = rx_desc_ptr(port, i);
986 buffer_t *buff;
987 void *data;
988#ifdef __ARMEB__
989 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
990 return -ENOMEM;
991 data = buff->data;
992#else
993 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
994 return -ENOMEM;
995 data = buff;
996#endif
997 desc->buf_len = RX_SIZE;
998 desc->data = dma_map_single(&port->netdev->dev, data,
999 RX_SIZE, DMA_FROM_DEVICE);
1000 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1001 free_buffer(buff);
1002 return -EIO;
1003 }
1004 port->rx_buff_tab[i] = buff;
1005 }
1006
1007 return 0;
1008}
1009
1010static void destroy_hdlc_queues(struct port *port)
1011{
1012 int i;
1013
1014 if (port->desc_tab) {
1015 for (i = 0; i < RX_DESCS; i++) {
1016 struct desc *desc = rx_desc_ptr(port, i);
1017 buffer_t *buff = port->rx_buff_tab[i];
1018 if (buff) {
1019 dma_unmap_single(&port->netdev->dev,
1020 desc->data, RX_SIZE,
1021 DMA_FROM_DEVICE);
1022 free_buffer(buff);
1023 }
1024 }
1025 for (i = 0; i < TX_DESCS; i++) {
1026 struct desc *desc = tx_desc_ptr(port, i);
1027 buffer_t *buff = port->tx_buff_tab[i];
1028 if (buff) {
1029 dma_unmap_tx(port, desc);
1030 free_buffer(buff);
1031 }
1032 }
1033 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1034 port->desc_tab = NULL;
1035 }
1036
1037 if (!ports_open && dma_pool) {
1038 dma_pool_destroy(dma_pool);
1039 dma_pool = NULL;
1040 }
1041}
1042
1043static int hss_hdlc_open(struct net_device *dev)
1044{
1045 struct port *port = dev_to_port(dev);
1046 unsigned long flags;
1047 int i, err = 0;
1048
1049 if ((err = hdlc_open(dev)))
1050 return err;
1051
1052 if ((err = hss_load_firmware(port)))
1053 goto err_hdlc_close;
1054
1055 if ((err = request_hdlc_queues(port)))
1056 goto err_hdlc_close;
1057
1058 if ((err = init_hdlc_queues(port)))
1059 goto err_destroy_queues;
1060
1061 spin_lock_irqsave(&npe_lock, flags);
1062 if (port->plat->open)
1063 if ((err = port->plat->open(port->id, dev,
1064 hss_hdlc_set_carrier)))
1065 goto err_unlock;
1066 spin_unlock_irqrestore(&npe_lock, flags);
1067
1068 /* Populate queues with buffers, no failure after this point */
1069 for (i = 0; i < TX_DESCS; i++)
1070 queue_put_desc(port->plat->txreadyq,
1071 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1072
1073 for (i = 0; i < RX_DESCS; i++)
1074 queue_put_desc(queue_ids[port->id].rxfree,
1075 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1076
1077 napi_enable(&port->napi);
1078 netif_start_queue(dev);
1079
1080 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1081 hss_hdlc_rx_irq, dev);
1082
1083 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1084 hss_hdlc_txdone_irq, dev);
1085 qmgr_enable_irq(queue_ids[port->id].txdone);
1086
1087 ports_open++;
1088
1089 hss_set_hdlc_cfg(port);
1090 hss_config(port);
1091
1092 hss_start_hdlc(port);
1093
1094 /* we may already have RX data, enables IRQ */
1095 napi_schedule(&port->napi);
1096 return 0;
1097
1098err_unlock:
1099 spin_unlock_irqrestore(&npe_lock, flags);
1100err_destroy_queues:
1101 destroy_hdlc_queues(port);
1102 release_hdlc_queues(port);
1103err_hdlc_close:
1104 hdlc_close(dev);
1105 return err;
1106}
1107
1108static int hss_hdlc_close(struct net_device *dev)
1109{
1110 struct port *port = dev_to_port(dev);
1111 unsigned long flags;
1112 int i, buffs = RX_DESCS; /* allocated RX buffers */
1113
1114 spin_lock_irqsave(&npe_lock, flags);
1115 ports_open--;
1116 qmgr_disable_irq(queue_ids[port->id].rx);
1117 netif_stop_queue(dev);
1118 napi_disable(&port->napi);
1119
1120 hss_stop_hdlc(port);
1121
1122 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1123 buffs--;
1124 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1125 buffs--;
1126
1127 if (buffs)
1128 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1129 buffs);
1130
1131 buffs = TX_DESCS;
1132 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1133 buffs--; /* cancel TX */
1134
1135 i = 0;
1136 do {
1137 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1138 buffs--;
1139 if (!buffs)
1140 break;
1141 } while (++i < MAX_CLOSE_WAIT);
1142
1143 if (buffs)
1144 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1145 buffs);
1146#if DEBUG_CLOSE
1147 if (!buffs)
1148 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1149#endif
1150 qmgr_disable_irq(queue_ids[port->id].txdone);
1151
1152 if (port->plat->close)
1153 port->plat->close(port->id, dev);
1154 spin_unlock_irqrestore(&npe_lock, flags);
1155
1156 destroy_hdlc_queues(port);
1157 release_hdlc_queues(port);
1158 hdlc_close(dev);
1159 return 0;
1160}
1161
1162
1163static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1164 unsigned short parity)
1165{
1166 struct port *port = dev_to_port(dev);
1167
1168 if (encoding != ENCODING_NRZ)
1169 return -EINVAL;
1170
1171 switch(parity) {
1172 case PARITY_CRC16_PR1_CCITT:
1173 port->hdlc_cfg = 0;
1174 return 0;
1175
1176 case PARITY_CRC32_PR1_CCITT:
1177 port->hdlc_cfg = PKT_HDLC_CRC_32;
1178 return 0;
1179
1180 default:
1181 return -EINVAL;
1182 }
1183}
1184
1185static u32 check_clock(u32 rate, u32 a, u32 b, u32 c,
1186 u32 *best, u32 *best_diff, u32 *reg)
1187{
1188 /* a is 10-bit, b is 10-bit, c is 12-bit */
1189 u64 new_rate;
1190 u32 new_diff;
1191
1192 new_rate = ixp4xx_timer_freq * (u64)(c + 1);
1193 do_div(new_rate, a * (c + 1) + b + 1);
1194 new_diff = abs((u32)new_rate - rate);
1195
1196 if (new_diff < *best_diff) {
1197 *best = new_rate;
1198 *best_diff = new_diff;
1199 *reg = (a << 22) | (b << 12) | c;
1200 }
1201 return new_diff;
1202}
1203
1204static void find_best_clock(u32 rate, u32 *best, u32 *reg)
1205{
1206 u32 a, b, diff = 0xFFFFFFFF;
1207
1208 a = ixp4xx_timer_freq / rate;
1209
1210 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1211 check_clock(rate, 0x3FF, 1, 1, best, &diff, reg);
1212 return;
1213 }
1214 if (a == 0) { /* > 66.666 MHz */
1215 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1216 rate = ixp4xx_timer_freq;
1217 }
1218
1219 if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */
1220 check_clock(rate, a - 1, 1, 1, best, &diff, reg);
1221 return;
1222 }
1223
1224 for (b = 0; b < 0x400; b++) {
1225 u64 c = (b + 1) * (u64)rate;
1226 do_div(c, ixp4xx_timer_freq - rate * a);
1227 c--;
1228 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1229 if (b == 0 && /* also try a bit higher rate */
1230 !check_clock(rate, a - 1, 1, 1, best, &diff, reg))
1231 return;
1232 check_clock(rate, a, b, 0xFFF, best, &diff, reg);
1233 return;
1234 }
1235 if (!check_clock(rate, a, b, c, best, &diff, reg))
1236 return;
1237 if (!check_clock(rate, a, b, c + 1, best, &diff, reg))
1238 return;
1239 }
1240}
1241
1242static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1243{
1244 const size_t size = sizeof(sync_serial_settings);
1245 sync_serial_settings new_line;
1246 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1247 struct port *port = dev_to_port(dev);
1248 unsigned long flags;
1249 int clk;
1250
1251 if (cmd != SIOCWANDEV)
1252 return hdlc_ioctl(dev, ifr, cmd);
1253
1254 switch(ifr->ifr_settings.type) {
1255 case IF_GET_IFACE:
1256 ifr->ifr_settings.type = IF_IFACE_V35;
1257 if (ifr->ifr_settings.size < size) {
1258 ifr->ifr_settings.size = size; /* data size wanted */
1259 return -ENOBUFS;
1260 }
1261 memset(&new_line, 0, sizeof(new_line));
1262 new_line.clock_type = port->clock_type;
1263 new_line.clock_rate = port->clock_rate;
1264 new_line.loopback = port->loopback;
1265 if (copy_to_user(line, &new_line, size))
1266 return -EFAULT;
1267 return 0;
1268
1269 case IF_IFACE_SYNC_SERIAL:
1270 case IF_IFACE_V35:
1271 if(!capable(CAP_NET_ADMIN))
1272 return -EPERM;
1273 if (copy_from_user(&new_line, line, size))
1274 return -EFAULT;
1275
1276 clk = new_line.clock_type;
1277 if (port->plat->set_clock)
1278 clk = port->plat->set_clock(port->id, clk);
1279
1280 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1281 return -EINVAL; /* No such clock setting */
1282
1283 if (new_line.loopback != 0 && new_line.loopback != 1)
1284 return -EINVAL;
1285
1286 port->clock_type = clk; /* Update settings */
1287 if (clk == CLOCK_INT)
1288 find_best_clock(new_line.clock_rate, &port->clock_rate,
1289 &port->clock_reg);
1290 else {
1291 port->clock_rate = 0;
1292 port->clock_reg = CLK42X_SPEED_2048KHZ;
1293 }
1294 port->loopback = new_line.loopback;
1295
1296 spin_lock_irqsave(&npe_lock, flags);
1297
1298 if (dev->flags & IFF_UP)
1299 hss_config(port);
1300
1301 if (port->loopback || port->carrier)
1302 netif_carrier_on(port->netdev);
1303 else
1304 netif_carrier_off(port->netdev);
1305 spin_unlock_irqrestore(&npe_lock, flags);
1306
1307 return 0;
1308
1309 default:
1310 return hdlc_ioctl(dev, ifr, cmd);
1311 }
1312}
1313
1314/*****************************************************************************
1315 * initialization
1316 ****************************************************************************/
1317
1318static const struct net_device_ops hss_hdlc_ops = {
1319 .ndo_open = hss_hdlc_open,
1320 .ndo_stop = hss_hdlc_close,
1321 .ndo_change_mtu = hdlc_change_mtu,
1322 .ndo_start_xmit = hdlc_start_xmit,
1323 .ndo_do_ioctl = hss_hdlc_ioctl,
1324};
1325
1326static int __devinit hss_init_one(struct platform_device *pdev)
1327{
1328 struct port *port;
1329 struct net_device *dev;
1330 hdlc_device *hdlc;
1331 int err;
1332
1333 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1334 return -ENOMEM;
1335
1336 if ((port->npe = npe_request(0)) == NULL) {
1337 err = -ENODEV;
1338 goto err_free;
1339 }
1340
1341 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1342 err = -ENOMEM;
1343 goto err_plat;
1344 }
1345
1346 SET_NETDEV_DEV(dev, &pdev->dev);
1347 hdlc = dev_to_hdlc(dev);
1348 hdlc->attach = hss_hdlc_attach;
1349 hdlc->xmit = hss_hdlc_xmit;
1350 dev->netdev_ops = &hss_hdlc_ops;
1351 dev->tx_queue_len = 100;
1352 port->clock_type = CLOCK_EXT;
1353 port->clock_rate = 0;
1354 port->clock_reg = CLK42X_SPEED_2048KHZ;
1355 port->id = pdev->id;
1356 port->dev = &pdev->dev;
1357 port->plat = pdev->dev.platform_data;
1358 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1359
1360 if ((err = register_hdlc_device(dev)))
1361 goto err_free_netdev;
1362
1363 platform_set_drvdata(pdev, port);
1364
1365 netdev_info(dev, "HSS-%i\n", port->id);
1366 return 0;
1367
1368err_free_netdev:
1369 free_netdev(dev);
1370err_plat:
1371 npe_release(port->npe);
1372err_free:
1373 kfree(port);
1374 return err;
1375}
1376
1377static int __devexit hss_remove_one(struct platform_device *pdev)
1378{
1379 struct port *port = platform_get_drvdata(pdev);
1380
1381 unregister_hdlc_device(port->netdev);
1382 free_netdev(port->netdev);
1383 npe_release(port->npe);
1384 platform_set_drvdata(pdev, NULL);
1385 kfree(port);
1386 return 0;
1387}
1388
1389static struct platform_driver ixp4xx_hss_driver = {
1390 .driver.name = DRV_NAME,
1391 .probe = hss_init_one,
1392 .remove = hss_remove_one,
1393};
1394
1395static int __init hss_init_module(void)
1396{
1397 if ((ixp4xx_read_feature_bits() &
1398 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1399 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1400 return -ENODEV;
1401
1402 spin_lock_init(&npe_lock);
1403
1404 return platform_driver_register(&ixp4xx_hss_driver);
1405}
1406
1407static void __exit hss_cleanup_module(void)
1408{
1409 platform_driver_unregister(&ixp4xx_hss_driver);
1410}
1411
1412MODULE_AUTHOR("Krzysztof Halasa");
1413MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1414MODULE_LICENSE("GPL v2");
1415MODULE_ALIAS("platform:ixp4xx_hss");
1416module_init(hss_init_module);
1417module_exit(hss_cleanup_module);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/wan_ixp4xx_hss.h>
21#include <linux/poll.h>
22#include <linux/slab.h>
23#include <linux/soc/ixp4xx/npe.h>
24#include <linux/soc/ixp4xx/qmgr.h>
25
26#define DEBUG_DESC 0
27#define DEBUG_RX 0
28#define DEBUG_TX 0
29#define DEBUG_PKT_BYTES 0
30#define DEBUG_CLOSE 0
31
32#define DRV_NAME "ixp4xx_hss"
33
34#define PKT_EXTRA_FLAGS 0 /* orig 1 */
35#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
36#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
37
38#define RX_DESCS 16 /* also length of all RX queues */
39#define TX_DESCS 16 /* also length of all TX queues */
40
41#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
42#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
43#define MAX_CLOSE_WAIT 1000 /* microseconds */
44#define HSS_COUNT 2
45#define FRAME_SIZE 256 /* doesn't matter at this point */
46#define FRAME_OFFSET 0
47#define MAX_CHANNELS (FRAME_SIZE / 8)
48
49#define NAPI_WEIGHT 16
50
51/* Queue IDs */
52#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
53#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
54#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
55#define HSS0_PKT_TX1_QUEUE 15
56#define HSS0_PKT_TX2_QUEUE 16
57#define HSS0_PKT_TX3_QUEUE 17
58#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
59#define HSS0_PKT_RXFREE1_QUEUE 19
60#define HSS0_PKT_RXFREE2_QUEUE 20
61#define HSS0_PKT_RXFREE3_QUEUE 21
62#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
63
64#define HSS1_CHL_RXTRIG_QUEUE 10
65#define HSS1_PKT_RX_QUEUE 0
66#define HSS1_PKT_TX0_QUEUE 5
67#define HSS1_PKT_TX1_QUEUE 6
68#define HSS1_PKT_TX2_QUEUE 7
69#define HSS1_PKT_TX3_QUEUE 8
70#define HSS1_PKT_RXFREE0_QUEUE 1
71#define HSS1_PKT_RXFREE1_QUEUE 2
72#define HSS1_PKT_RXFREE2_QUEUE 3
73#define HSS1_PKT_RXFREE3_QUEUE 4
74#define HSS1_PKT_TXDONE_QUEUE 9
75
76#define NPE_PKT_MODE_HDLC 0
77#define NPE_PKT_MODE_RAW 1
78#define NPE_PKT_MODE_56KMODE 2
79#define NPE_PKT_MODE_56KENDIAN_MSB 4
80
81/* PKT_PIPE_HDLC_CFG_WRITE flags */
82#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
83#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
84#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
85
86
87/* hss_config, PCRs */
88/* Frame sync sampling, default = active low */
89#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
90#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
91#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
92
93/* Frame sync pin: input (default) or output generated off a given clk edge */
94#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
95#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
96
97/* Frame and data clock sampling on edge, default = falling */
98#define PCR_FCLK_EDGE_RISING 0x08000000
99#define PCR_DCLK_EDGE_RISING 0x04000000
100
101/* Clock direction, default = input */
102#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
103
104/* Generate/Receive frame pulses, default = enabled */
105#define PCR_FRM_PULSE_DISABLED 0x01000000
106
107 /* Data rate is full (default) or half the configured clk speed */
108#define PCR_HALF_CLK_RATE 0x00200000
109
110/* Invert data between NPE and HSS FIFOs? (default = no) */
111#define PCR_DATA_POLARITY_INVERT 0x00100000
112
113/* TX/RX endianness, default = LSB */
114#define PCR_MSB_ENDIAN 0x00080000
115
116/* Normal (default) / open drain mode (TX only) */
117#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
118
119/* No framing bit transmitted and expected on RX? (default = framing bit) */
120#define PCR_SOF_NO_FBIT 0x00020000
121
122/* Drive data pins? */
123#define PCR_TX_DATA_ENABLE 0x00010000
124
125/* Voice 56k type: drive the data pins low (default), high, high Z */
126#define PCR_TX_V56K_HIGH 0x00002000
127#define PCR_TX_V56K_HIGH_IMP 0x00004000
128
129/* Unassigned type: drive the data pins low (default), high, high Z */
130#define PCR_TX_UNASS_HIGH 0x00000800
131#define PCR_TX_UNASS_HIGH_IMP 0x00001000
132
133/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
134#define PCR_TX_FB_HIGH_IMP 0x00000400
135
136/* 56k data endiannes - which bit unused: high (default) or low */
137#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
138
139/* 56k data transmission type: 32/8 bit data (default) or 56K data */
140#define PCR_TX_56KS_56K_DATA 0x00000100
141
142/* hss_config, cCR */
143/* Number of packetized clients, default = 1 */
144#define CCR_NPE_HFIFO_2_HDLC 0x04000000
145#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
146
147/* default = no loopback */
148#define CCR_LOOPBACK 0x02000000
149
150/* HSS number, default = 0 (first) */
151#define CCR_SECOND_HSS 0x01000000
152
153
154/* hss_config, clkCR: main:10, num:10, denom:12 */
155#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
156
157#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
158#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
159#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
160#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
161#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
162#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
163
164#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
165#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
166#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
167#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
168#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
169#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
170
171/*
172 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
173 * A (10 bits), B (10 bits) and C (12 bits).
174 * IXP42x HSS clock generator operation (verified with an oscilloscope):
175 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
176 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
177 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
178 * (A + 1) bits wide.
179 *
180 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
181 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
182 * minimum freq = 66.666 MHz / (A + 1)
183 * maximum freq = 66.666 MHz / A
184 *
185 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
186 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
187 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
188 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
189 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
190 * The sequence consists of 4 complete clock periods, thus the average
191 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
192 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
193 */
194
195/* hss_config, LUT entries */
196#define TDMMAP_UNASSIGNED 0
197#define TDMMAP_HDLC 1 /* HDLC - packetized */
198#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
199#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
200
201/* offsets into HSS config */
202#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
203#define HSS_CONFIG_RX_PCR 0x04
204#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
205#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
206#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
207#define HSS_CONFIG_RX_FCR 0x14
208#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
209#define HSS_CONFIG_RX_LUT 0x38
210
211
212/* NPE command codes */
213/* writes the ConfigWord value to the location specified by offset */
214#define PORT_CONFIG_WRITE 0x40
215
216/* triggers the NPE to load the contents of the configuration table */
217#define PORT_CONFIG_LOAD 0x41
218
219/* triggers the NPE to return an HssErrorReadResponse message */
220#define PORT_ERROR_READ 0x42
221
222/* triggers the NPE to reset internal status and enable the HssPacketized
223 operation for the flow specified by pPipe */
224#define PKT_PIPE_FLOW_ENABLE 0x50
225#define PKT_PIPE_FLOW_DISABLE 0x51
226#define PKT_NUM_PIPES_WRITE 0x52
227#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
228#define PKT_PIPE_HDLC_CFG_WRITE 0x54
229#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
230#define PKT_PIPE_RX_SIZE_WRITE 0x56
231#define PKT_PIPE_MODE_WRITE 0x57
232
233/* HDLC packet status values - desc->status */
234#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
235#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
236#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
237#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
238 this packet (if buf_len < pkt_len) */
239#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
240#define ERR_HDLC_ABORT 6 /* abort sequence received */
241#define ERR_DISCONNECTING 7 /* disconnect is in progress */
242
243
244#ifdef __ARMEB__
245typedef struct sk_buff buffer_t;
246#define free_buffer dev_kfree_skb
247#define free_buffer_irq dev_consume_skb_irq
248#else
249typedef void buffer_t;
250#define free_buffer kfree
251#define free_buffer_irq kfree
252#endif
253
254struct port {
255 struct device *dev;
256 struct npe *npe;
257 struct net_device *netdev;
258 struct napi_struct napi;
259 struct hss_plat_info *plat;
260 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
261 struct desc *desc_tab; /* coherent */
262 dma_addr_t desc_tab_phys;
263 unsigned int id;
264 unsigned int clock_type, clock_rate, loopback;
265 unsigned int initialized, carrier;
266 u8 hdlc_cfg;
267 u32 clock_reg;
268};
269
270/* NPE message structure */
271struct msg {
272#ifdef __ARMEB__
273 u8 cmd, unused, hss_port, index;
274 union {
275 struct { u8 data8a, data8b, data8c, data8d; };
276 struct { u16 data16a, data16b; };
277 struct { u32 data32; };
278 };
279#else
280 u8 index, hss_port, unused, cmd;
281 union {
282 struct { u8 data8d, data8c, data8b, data8a; };
283 struct { u16 data16b, data16a; };
284 struct { u32 data32; };
285 };
286#endif
287};
288
289/* HDLC packet descriptor */
290struct desc {
291 u32 next; /* pointer to next buffer, unused */
292
293#ifdef __ARMEB__
294 u16 buf_len; /* buffer length */
295 u16 pkt_len; /* packet length */
296 u32 data; /* pointer to data buffer in RAM */
297 u8 status;
298 u8 error_count;
299 u16 __reserved;
300#else
301 u16 pkt_len; /* packet length */
302 u16 buf_len; /* buffer length */
303 u32 data; /* pointer to data buffer in RAM */
304 u16 __reserved;
305 u8 error_count;
306 u8 status;
307#endif
308 u32 __reserved1[4];
309};
310
311
312#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
313 (n) * sizeof(struct desc))
314#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
315
316#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
317 ((n) + RX_DESCS) * sizeof(struct desc))
318#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
319
320/*****************************************************************************
321 * global variables
322 ****************************************************************************/
323
324static int ports_open;
325static struct dma_pool *dma_pool;
326static spinlock_t npe_lock;
327
328static const struct {
329 int tx, txdone, rx, rxfree;
330}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
331 HSS0_PKT_RXFREE0_QUEUE},
332 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
333 HSS1_PKT_RXFREE0_QUEUE},
334};
335
336/*****************************************************************************
337 * utility functions
338 ****************************************************************************/
339
340static inline struct port* dev_to_port(struct net_device *dev)
341{
342 return dev_to_hdlc(dev)->priv;
343}
344
345#ifndef __ARMEB__
346static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
347{
348 int i;
349 for (i = 0; i < cnt; i++)
350 dest[i] = swab32(src[i]);
351}
352#endif
353
354/*****************************************************************************
355 * HSS access
356 ****************************************************************************/
357
358static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
359{
360 u32 *val = (u32*)msg;
361 if (npe_send_message(port->npe, msg, what)) {
362 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
363 port->id, val[0], val[1], npe_name(port->npe));
364 BUG();
365 }
366}
367
368static void hss_config_set_lut(struct port *port)
369{
370 struct msg msg;
371 int ch;
372
373 memset(&msg, 0, sizeof(msg));
374 msg.cmd = PORT_CONFIG_WRITE;
375 msg.hss_port = port->id;
376
377 for (ch = 0; ch < MAX_CHANNELS; ch++) {
378 msg.data32 >>= 2;
379 msg.data32 |= TDMMAP_HDLC << 30;
380
381 if (ch % 16 == 15) {
382 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
383 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
384
385 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
386 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
387 }
388 }
389}
390
391static void hss_config(struct port *port)
392{
393 struct msg msg;
394
395 memset(&msg, 0, sizeof(msg));
396 msg.cmd = PORT_CONFIG_WRITE;
397 msg.hss_port = port->id;
398 msg.index = HSS_CONFIG_TX_PCR;
399 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
400 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
401 if (port->clock_type == CLOCK_INT)
402 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
403 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
404
405 msg.index = HSS_CONFIG_RX_PCR;
406 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
407 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
408
409 memset(&msg, 0, sizeof(msg));
410 msg.cmd = PORT_CONFIG_WRITE;
411 msg.hss_port = port->id;
412 msg.index = HSS_CONFIG_CORE_CR;
413 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
414 (port->id ? CCR_SECOND_HSS : 0);
415 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
416
417 memset(&msg, 0, sizeof(msg));
418 msg.cmd = PORT_CONFIG_WRITE;
419 msg.hss_port = port->id;
420 msg.index = HSS_CONFIG_CLOCK_CR;
421 msg.data32 = port->clock_reg;
422 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
423
424 memset(&msg, 0, sizeof(msg));
425 msg.cmd = PORT_CONFIG_WRITE;
426 msg.hss_port = port->id;
427 msg.index = HSS_CONFIG_TX_FCR;
428 msg.data16a = FRAME_OFFSET;
429 msg.data16b = FRAME_SIZE - 1;
430 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
431
432 memset(&msg, 0, sizeof(msg));
433 msg.cmd = PORT_CONFIG_WRITE;
434 msg.hss_port = port->id;
435 msg.index = HSS_CONFIG_RX_FCR;
436 msg.data16a = FRAME_OFFSET;
437 msg.data16b = FRAME_SIZE - 1;
438 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
439
440 hss_config_set_lut(port);
441
442 memset(&msg, 0, sizeof(msg));
443 msg.cmd = PORT_CONFIG_LOAD;
444 msg.hss_port = port->id;
445 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
446
447 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
448 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
449 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
450 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
451 BUG();
452 }
453
454 /* HDLC may stop working without this - check FIXME */
455 npe_recv_message(port->npe, &msg, "FLUSH_IT");
456}
457
458static void hss_set_hdlc_cfg(struct port *port)
459{
460 struct msg msg;
461
462 memset(&msg, 0, sizeof(msg));
463 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
464 msg.hss_port = port->id;
465 msg.data8a = port->hdlc_cfg; /* rx_cfg */
466 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
467 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
468}
469
470static u32 hss_get_status(struct port *port)
471{
472 struct msg msg;
473
474 memset(&msg, 0, sizeof(msg));
475 msg.cmd = PORT_ERROR_READ;
476 msg.hss_port = port->id;
477 hss_npe_send(port, &msg, "PORT_ERROR_READ");
478 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
479 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
480 BUG();
481 }
482
483 return msg.data32;
484}
485
486static void hss_start_hdlc(struct port *port)
487{
488 struct msg msg;
489
490 memset(&msg, 0, sizeof(msg));
491 msg.cmd = PKT_PIPE_FLOW_ENABLE;
492 msg.hss_port = port->id;
493 msg.data32 = 0;
494 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
495}
496
497static void hss_stop_hdlc(struct port *port)
498{
499 struct msg msg;
500
501 memset(&msg, 0, sizeof(msg));
502 msg.cmd = PKT_PIPE_FLOW_DISABLE;
503 msg.hss_port = port->id;
504 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
505 hss_get_status(port); /* make sure it's halted */
506}
507
508static int hss_load_firmware(struct port *port)
509{
510 struct msg msg;
511 int err;
512
513 if (port->initialized)
514 return 0;
515
516 if (!npe_running(port->npe) &&
517 (err = npe_load_firmware(port->npe, npe_name(port->npe),
518 port->dev)))
519 return err;
520
521 /* HDLC mode configuration */
522 memset(&msg, 0, sizeof(msg));
523 msg.cmd = PKT_NUM_PIPES_WRITE;
524 msg.hss_port = port->id;
525 msg.data8a = PKT_NUM_PIPES;
526 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
527
528 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
529 msg.data8a = PKT_PIPE_FIFO_SIZEW;
530 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
531
532 msg.cmd = PKT_PIPE_MODE_WRITE;
533 msg.data8a = NPE_PKT_MODE_HDLC;
534 /* msg.data8b = inv_mask */
535 /* msg.data8c = or_mask */
536 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
537
538 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
539 msg.data16a = HDLC_MAX_MRU; /* including CRC */
540 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
541
542 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
543 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
544 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
545
546 port->initialized = 1;
547 return 0;
548}
549
550/*****************************************************************************
551 * packetized (HDLC) operation
552 ****************************************************************************/
553
554static inline void debug_pkt(struct net_device *dev, const char *func,
555 u8 *data, int len)
556{
557#if DEBUG_PKT_BYTES
558 int i;
559
560 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
561 for (i = 0; i < len; i++) {
562 if (i >= DEBUG_PKT_BYTES)
563 break;
564 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
565 }
566 printk("\n");
567#endif
568}
569
570
571static inline void debug_desc(u32 phys, struct desc *desc)
572{
573#if DEBUG_DESC
574 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
575 phys, desc->next, desc->buf_len, desc->pkt_len,
576 desc->data, desc->status, desc->error_count);
577#endif
578}
579
580static inline int queue_get_desc(unsigned int queue, struct port *port,
581 int is_tx)
582{
583 u32 phys, tab_phys, n_desc;
584 struct desc *tab;
585
586 if (!(phys = qmgr_get_entry(queue)))
587 return -1;
588
589 BUG_ON(phys & 0x1F);
590 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
591 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
592 n_desc = (phys - tab_phys) / sizeof(struct desc);
593 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
594 debug_desc(phys, &tab[n_desc]);
595 BUG_ON(tab[n_desc].next);
596 return n_desc;
597}
598
599static inline void queue_put_desc(unsigned int queue, u32 phys,
600 struct desc *desc)
601{
602 debug_desc(phys, desc);
603 BUG_ON(phys & 0x1F);
604 qmgr_put_entry(queue, phys);
605 /* Don't check for queue overflow here, we've allocated sufficient
606 length and queues >= 32 don't support this check anyway. */
607}
608
609
610static inline void dma_unmap_tx(struct port *port, struct desc *desc)
611{
612#ifdef __ARMEB__
613 dma_unmap_single(&port->netdev->dev, desc->data,
614 desc->buf_len, DMA_TO_DEVICE);
615#else
616 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
617 ALIGN((desc->data & 3) + desc->buf_len, 4),
618 DMA_TO_DEVICE);
619#endif
620}
621
622
623static void hss_hdlc_set_carrier(void *pdev, int carrier)
624{
625 struct net_device *netdev = pdev;
626 struct port *port = dev_to_port(netdev);
627 unsigned long flags;
628
629 spin_lock_irqsave(&npe_lock, flags);
630 port->carrier = carrier;
631 if (!port->loopback) {
632 if (carrier)
633 netif_carrier_on(netdev);
634 else
635 netif_carrier_off(netdev);
636 }
637 spin_unlock_irqrestore(&npe_lock, flags);
638}
639
640static void hss_hdlc_rx_irq(void *pdev)
641{
642 struct net_device *dev = pdev;
643 struct port *port = dev_to_port(dev);
644
645#if DEBUG_RX
646 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
647#endif
648 qmgr_disable_irq(queue_ids[port->id].rx);
649 napi_schedule(&port->napi);
650}
651
652static int hss_hdlc_poll(struct napi_struct *napi, int budget)
653{
654 struct port *port = container_of(napi, struct port, napi);
655 struct net_device *dev = port->netdev;
656 unsigned int rxq = queue_ids[port->id].rx;
657 unsigned int rxfreeq = queue_ids[port->id].rxfree;
658 int received = 0;
659
660#if DEBUG_RX
661 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
662#endif
663
664 while (received < budget) {
665 struct sk_buff *skb;
666 struct desc *desc;
667 int n;
668#ifdef __ARMEB__
669 struct sk_buff *temp;
670 u32 phys;
671#endif
672
673 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
674#if DEBUG_RX
675 printk(KERN_DEBUG "%s: hss_hdlc_poll"
676 " napi_complete\n", dev->name);
677#endif
678 napi_complete(napi);
679 qmgr_enable_irq(rxq);
680 if (!qmgr_stat_empty(rxq) &&
681 napi_reschedule(napi)) {
682#if DEBUG_RX
683 printk(KERN_DEBUG "%s: hss_hdlc_poll"
684 " napi_reschedule succeeded\n",
685 dev->name);
686#endif
687 qmgr_disable_irq(rxq);
688 continue;
689 }
690#if DEBUG_RX
691 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
692 dev->name);
693#endif
694 return received; /* all work done */
695 }
696
697 desc = rx_desc_ptr(port, n);
698#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
699 if (desc->error_count)
700 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
701 " errors %u\n", dev->name, desc->status,
702 desc->error_count);
703#endif
704 skb = NULL;
705 switch (desc->status) {
706 case 0:
707#ifdef __ARMEB__
708 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
709 phys = dma_map_single(&dev->dev, skb->data,
710 RX_SIZE,
711 DMA_FROM_DEVICE);
712 if (dma_mapping_error(&dev->dev, phys)) {
713 dev_kfree_skb(skb);
714 skb = NULL;
715 }
716 }
717#else
718 skb = netdev_alloc_skb(dev, desc->pkt_len);
719#endif
720 if (!skb)
721 dev->stats.rx_dropped++;
722 break;
723 case ERR_HDLC_ALIGN:
724 case ERR_HDLC_ABORT:
725 dev->stats.rx_frame_errors++;
726 dev->stats.rx_errors++;
727 break;
728 case ERR_HDLC_FCS:
729 dev->stats.rx_crc_errors++;
730 dev->stats.rx_errors++;
731 break;
732 case ERR_HDLC_TOO_LONG:
733 dev->stats.rx_length_errors++;
734 dev->stats.rx_errors++;
735 break;
736 default: /* FIXME - remove printk */
737 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
738 desc->status, desc->error_count);
739 dev->stats.rx_errors++;
740 }
741
742 if (!skb) {
743 /* put the desc back on RX-ready queue */
744 desc->buf_len = RX_SIZE;
745 desc->pkt_len = desc->status = 0;
746 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
747 continue;
748 }
749
750 /* process received frame */
751#ifdef __ARMEB__
752 temp = skb;
753 skb = port->rx_buff_tab[n];
754 dma_unmap_single(&dev->dev, desc->data,
755 RX_SIZE, DMA_FROM_DEVICE);
756#else
757 dma_sync_single_for_cpu(&dev->dev, desc->data,
758 RX_SIZE, DMA_FROM_DEVICE);
759 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
760 ALIGN(desc->pkt_len, 4) / 4);
761#endif
762 skb_put(skb, desc->pkt_len);
763
764 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
765
766 skb->protocol = hdlc_type_trans(skb, dev);
767 dev->stats.rx_packets++;
768 dev->stats.rx_bytes += skb->len;
769 netif_receive_skb(skb);
770
771 /* put the new buffer on RX-free queue */
772#ifdef __ARMEB__
773 port->rx_buff_tab[n] = temp;
774 desc->data = phys;
775#endif
776 desc->buf_len = RX_SIZE;
777 desc->pkt_len = 0;
778 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
779 received++;
780 }
781#if DEBUG_RX
782 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
783#endif
784 return received; /* not all work done */
785}
786
787
788static void hss_hdlc_txdone_irq(void *pdev)
789{
790 struct net_device *dev = pdev;
791 struct port *port = dev_to_port(dev);
792 int n_desc;
793
794#if DEBUG_TX
795 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
796#endif
797 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
798 port, 1)) >= 0) {
799 struct desc *desc;
800 int start;
801
802 desc = tx_desc_ptr(port, n_desc);
803
804 dev->stats.tx_packets++;
805 dev->stats.tx_bytes += desc->pkt_len;
806
807 dma_unmap_tx(port, desc);
808#if DEBUG_TX
809 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
810 dev->name, port->tx_buff_tab[n_desc]);
811#endif
812 free_buffer_irq(port->tx_buff_tab[n_desc]);
813 port->tx_buff_tab[n_desc] = NULL;
814
815 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
816 queue_put_desc(port->plat->txreadyq,
817 tx_desc_phys(port, n_desc), desc);
818 if (start) { /* TX-ready queue was empty */
819#if DEBUG_TX
820 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
821 " ready\n", dev->name);
822#endif
823 netif_wake_queue(dev);
824 }
825 }
826}
827
828static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
829{
830 struct port *port = dev_to_port(dev);
831 unsigned int txreadyq = port->plat->txreadyq;
832 int len, offset, bytes, n;
833 void *mem;
834 u32 phys;
835 struct desc *desc;
836
837#if DEBUG_TX
838 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
839#endif
840
841 if (unlikely(skb->len > HDLC_MAX_MRU)) {
842 dev_kfree_skb(skb);
843 dev->stats.tx_errors++;
844 return NETDEV_TX_OK;
845 }
846
847 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
848
849 len = skb->len;
850#ifdef __ARMEB__
851 offset = 0; /* no need to keep alignment */
852 bytes = len;
853 mem = skb->data;
854#else
855 offset = (int)skb->data & 3; /* keep 32-bit alignment */
856 bytes = ALIGN(offset + len, 4);
857 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
858 dev_kfree_skb(skb);
859 dev->stats.tx_dropped++;
860 return NETDEV_TX_OK;
861 }
862 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
863 dev_kfree_skb(skb);
864#endif
865
866 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
867 if (dma_mapping_error(&dev->dev, phys)) {
868#ifdef __ARMEB__
869 dev_kfree_skb(skb);
870#else
871 kfree(mem);
872#endif
873 dev->stats.tx_dropped++;
874 return NETDEV_TX_OK;
875 }
876
877 n = queue_get_desc(txreadyq, port, 1);
878 BUG_ON(n < 0);
879 desc = tx_desc_ptr(port, n);
880
881#ifdef __ARMEB__
882 port->tx_buff_tab[n] = skb;
883#else
884 port->tx_buff_tab[n] = mem;
885#endif
886 desc->data = phys + offset;
887 desc->buf_len = desc->pkt_len = len;
888
889 wmb();
890 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
891
892 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
893#if DEBUG_TX
894 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
895#endif
896 netif_stop_queue(dev);
897 /* we could miss TX ready interrupt */
898 if (!qmgr_stat_below_low_watermark(txreadyq)) {
899#if DEBUG_TX
900 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
901 dev->name);
902#endif
903 netif_wake_queue(dev);
904 }
905 }
906
907#if DEBUG_TX
908 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
909#endif
910 return NETDEV_TX_OK;
911}
912
913
914static int request_hdlc_queues(struct port *port)
915{
916 int err;
917
918 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
919 "%s:RX-free", port->netdev->name);
920 if (err)
921 return err;
922
923 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
924 "%s:RX", port->netdev->name);
925 if (err)
926 goto rel_rxfree;
927
928 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
929 "%s:TX", port->netdev->name);
930 if (err)
931 goto rel_rx;
932
933 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
934 "%s:TX-ready", port->netdev->name);
935 if (err)
936 goto rel_tx;
937
938 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
939 "%s:TX-done", port->netdev->name);
940 if (err)
941 goto rel_txready;
942 return 0;
943
944rel_txready:
945 qmgr_release_queue(port->plat->txreadyq);
946rel_tx:
947 qmgr_release_queue(queue_ids[port->id].tx);
948rel_rx:
949 qmgr_release_queue(queue_ids[port->id].rx);
950rel_rxfree:
951 qmgr_release_queue(queue_ids[port->id].rxfree);
952 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
953 port->netdev->name);
954 return err;
955}
956
957static void release_hdlc_queues(struct port *port)
958{
959 qmgr_release_queue(queue_ids[port->id].rxfree);
960 qmgr_release_queue(queue_ids[port->id].rx);
961 qmgr_release_queue(queue_ids[port->id].txdone);
962 qmgr_release_queue(queue_ids[port->id].tx);
963 qmgr_release_queue(port->plat->txreadyq);
964}
965
966static int init_hdlc_queues(struct port *port)
967{
968 int i;
969
970 if (!ports_open) {
971 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
972 POOL_ALLOC_SIZE, 32, 0);
973 if (!dma_pool)
974 return -ENOMEM;
975 }
976
977 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
978 &port->desc_tab_phys)))
979 return -ENOMEM;
980 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
981 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
982 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
983
984 /* Setup RX buffers */
985 for (i = 0; i < RX_DESCS; i++) {
986 struct desc *desc = rx_desc_ptr(port, i);
987 buffer_t *buff;
988 void *data;
989#ifdef __ARMEB__
990 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
991 return -ENOMEM;
992 data = buff->data;
993#else
994 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
995 return -ENOMEM;
996 data = buff;
997#endif
998 desc->buf_len = RX_SIZE;
999 desc->data = dma_map_single(&port->netdev->dev, data,
1000 RX_SIZE, DMA_FROM_DEVICE);
1001 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1002 free_buffer(buff);
1003 return -EIO;
1004 }
1005 port->rx_buff_tab[i] = buff;
1006 }
1007
1008 return 0;
1009}
1010
1011static void destroy_hdlc_queues(struct port *port)
1012{
1013 int i;
1014
1015 if (port->desc_tab) {
1016 for (i = 0; i < RX_DESCS; i++) {
1017 struct desc *desc = rx_desc_ptr(port, i);
1018 buffer_t *buff = port->rx_buff_tab[i];
1019 if (buff) {
1020 dma_unmap_single(&port->netdev->dev,
1021 desc->data, RX_SIZE,
1022 DMA_FROM_DEVICE);
1023 free_buffer(buff);
1024 }
1025 }
1026 for (i = 0; i < TX_DESCS; i++) {
1027 struct desc *desc = tx_desc_ptr(port, i);
1028 buffer_t *buff = port->tx_buff_tab[i];
1029 if (buff) {
1030 dma_unmap_tx(port, desc);
1031 free_buffer(buff);
1032 }
1033 }
1034 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1035 port->desc_tab = NULL;
1036 }
1037
1038 if (!ports_open && dma_pool) {
1039 dma_pool_destroy(dma_pool);
1040 dma_pool = NULL;
1041 }
1042}
1043
1044static int hss_hdlc_open(struct net_device *dev)
1045{
1046 struct port *port = dev_to_port(dev);
1047 unsigned long flags;
1048 int i, err = 0;
1049
1050 if ((err = hdlc_open(dev)))
1051 return err;
1052
1053 if ((err = hss_load_firmware(port)))
1054 goto err_hdlc_close;
1055
1056 if ((err = request_hdlc_queues(port)))
1057 goto err_hdlc_close;
1058
1059 if ((err = init_hdlc_queues(port)))
1060 goto err_destroy_queues;
1061
1062 spin_lock_irqsave(&npe_lock, flags);
1063 if (port->plat->open)
1064 if ((err = port->plat->open(port->id, dev,
1065 hss_hdlc_set_carrier)))
1066 goto err_unlock;
1067 spin_unlock_irqrestore(&npe_lock, flags);
1068
1069 /* Populate queues with buffers, no failure after this point */
1070 for (i = 0; i < TX_DESCS; i++)
1071 queue_put_desc(port->plat->txreadyq,
1072 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1073
1074 for (i = 0; i < RX_DESCS; i++)
1075 queue_put_desc(queue_ids[port->id].rxfree,
1076 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1077
1078 napi_enable(&port->napi);
1079 netif_start_queue(dev);
1080
1081 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1082 hss_hdlc_rx_irq, dev);
1083
1084 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1085 hss_hdlc_txdone_irq, dev);
1086 qmgr_enable_irq(queue_ids[port->id].txdone);
1087
1088 ports_open++;
1089
1090 hss_set_hdlc_cfg(port);
1091 hss_config(port);
1092
1093 hss_start_hdlc(port);
1094
1095 /* we may already have RX data, enables IRQ */
1096 napi_schedule(&port->napi);
1097 return 0;
1098
1099err_unlock:
1100 spin_unlock_irqrestore(&npe_lock, flags);
1101err_destroy_queues:
1102 destroy_hdlc_queues(port);
1103 release_hdlc_queues(port);
1104err_hdlc_close:
1105 hdlc_close(dev);
1106 return err;
1107}
1108
1109static int hss_hdlc_close(struct net_device *dev)
1110{
1111 struct port *port = dev_to_port(dev);
1112 unsigned long flags;
1113 int i, buffs = RX_DESCS; /* allocated RX buffers */
1114
1115 spin_lock_irqsave(&npe_lock, flags);
1116 ports_open--;
1117 qmgr_disable_irq(queue_ids[port->id].rx);
1118 netif_stop_queue(dev);
1119 napi_disable(&port->napi);
1120
1121 hss_stop_hdlc(port);
1122
1123 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1124 buffs--;
1125 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1126 buffs--;
1127
1128 if (buffs)
1129 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1130 buffs);
1131
1132 buffs = TX_DESCS;
1133 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1134 buffs--; /* cancel TX */
1135
1136 i = 0;
1137 do {
1138 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1139 buffs--;
1140 if (!buffs)
1141 break;
1142 } while (++i < MAX_CLOSE_WAIT);
1143
1144 if (buffs)
1145 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1146 buffs);
1147#if DEBUG_CLOSE
1148 if (!buffs)
1149 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1150#endif
1151 qmgr_disable_irq(queue_ids[port->id].txdone);
1152
1153 if (port->plat->close)
1154 port->plat->close(port->id, dev);
1155 spin_unlock_irqrestore(&npe_lock, flags);
1156
1157 destroy_hdlc_queues(port);
1158 release_hdlc_queues(port);
1159 hdlc_close(dev);
1160 return 0;
1161}
1162
1163
1164static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1165 unsigned short parity)
1166{
1167 struct port *port = dev_to_port(dev);
1168
1169 if (encoding != ENCODING_NRZ)
1170 return -EINVAL;
1171
1172 switch(parity) {
1173 case PARITY_CRC16_PR1_CCITT:
1174 port->hdlc_cfg = 0;
1175 return 0;
1176
1177 case PARITY_CRC32_PR1_CCITT:
1178 port->hdlc_cfg = PKT_HDLC_CRC_32;
1179 return 0;
1180
1181 default:
1182 return -EINVAL;
1183 }
1184}
1185
1186static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1187 u32 *best, u32 *best_diff, u32 *reg)
1188{
1189 /* a is 10-bit, b is 10-bit, c is 12-bit */
1190 u64 new_rate;
1191 u32 new_diff;
1192
1193 new_rate = timer_freq * (u64)(c + 1);
1194 do_div(new_rate, a * (c + 1) + b + 1);
1195 new_diff = abs((u32)new_rate - rate);
1196
1197 if (new_diff < *best_diff) {
1198 *best = new_rate;
1199 *best_diff = new_diff;
1200 *reg = (a << 22) | (b << 12) | c;
1201 }
1202 return new_diff;
1203}
1204
1205static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1206{
1207 u32 a, b, diff = 0xFFFFFFFF;
1208
1209 a = timer_freq / rate;
1210
1211 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1212 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1213 return;
1214 }
1215 if (a == 0) { /* > 66.666 MHz */
1216 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1217 rate = timer_freq;
1218 }
1219
1220 if (rate * a == timer_freq) { /* don't divide by 0 later */
1221 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1222 return;
1223 }
1224
1225 for (b = 0; b < 0x400; b++) {
1226 u64 c = (b + 1) * (u64)rate;
1227 do_div(c, timer_freq - rate * a);
1228 c--;
1229 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1230 if (b == 0 && /* also try a bit higher rate */
1231 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1232 &diff, reg))
1233 return;
1234 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1235 &diff, reg);
1236 return;
1237 }
1238 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1239 return;
1240 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1241 reg))
1242 return;
1243 }
1244}
1245
1246static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1247{
1248 const size_t size = sizeof(sync_serial_settings);
1249 sync_serial_settings new_line;
1250 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1251 struct port *port = dev_to_port(dev);
1252 unsigned long flags;
1253 int clk;
1254
1255 if (cmd != SIOCWANDEV)
1256 return hdlc_ioctl(dev, ifr, cmd);
1257
1258 switch(ifr->ifr_settings.type) {
1259 case IF_GET_IFACE:
1260 ifr->ifr_settings.type = IF_IFACE_V35;
1261 if (ifr->ifr_settings.size < size) {
1262 ifr->ifr_settings.size = size; /* data size wanted */
1263 return -ENOBUFS;
1264 }
1265 memset(&new_line, 0, sizeof(new_line));
1266 new_line.clock_type = port->clock_type;
1267 new_line.clock_rate = port->clock_rate;
1268 new_line.loopback = port->loopback;
1269 if (copy_to_user(line, &new_line, size))
1270 return -EFAULT;
1271 return 0;
1272
1273 case IF_IFACE_SYNC_SERIAL:
1274 case IF_IFACE_V35:
1275 if(!capable(CAP_NET_ADMIN))
1276 return -EPERM;
1277 if (copy_from_user(&new_line, line, size))
1278 return -EFAULT;
1279
1280 clk = new_line.clock_type;
1281 if (port->plat->set_clock)
1282 clk = port->plat->set_clock(port->id, clk);
1283
1284 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1285 return -EINVAL; /* No such clock setting */
1286
1287 if (new_line.loopback != 0 && new_line.loopback != 1)
1288 return -EINVAL;
1289
1290 port->clock_type = clk; /* Update settings */
1291 if (clk == CLOCK_INT)
1292 find_best_clock(port->plat->timer_freq,
1293 new_line.clock_rate,
1294 &port->clock_rate, &port->clock_reg);
1295 else {
1296 port->clock_rate = 0;
1297 port->clock_reg = CLK42X_SPEED_2048KHZ;
1298 }
1299 port->loopback = new_line.loopback;
1300
1301 spin_lock_irqsave(&npe_lock, flags);
1302
1303 if (dev->flags & IFF_UP)
1304 hss_config(port);
1305
1306 if (port->loopback || port->carrier)
1307 netif_carrier_on(port->netdev);
1308 else
1309 netif_carrier_off(port->netdev);
1310 spin_unlock_irqrestore(&npe_lock, flags);
1311
1312 return 0;
1313
1314 default:
1315 return hdlc_ioctl(dev, ifr, cmd);
1316 }
1317}
1318
1319/*****************************************************************************
1320 * initialization
1321 ****************************************************************************/
1322
1323static const struct net_device_ops hss_hdlc_ops = {
1324 .ndo_open = hss_hdlc_open,
1325 .ndo_stop = hss_hdlc_close,
1326 .ndo_start_xmit = hdlc_start_xmit,
1327 .ndo_do_ioctl = hss_hdlc_ioctl,
1328};
1329
1330static int hss_init_one(struct platform_device *pdev)
1331{
1332 struct port *port;
1333 struct net_device *dev;
1334 hdlc_device *hdlc;
1335 int err;
1336
1337 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1338 return -ENOMEM;
1339
1340 if ((port->npe = npe_request(0)) == NULL) {
1341 err = -ENODEV;
1342 goto err_free;
1343 }
1344
1345 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1346 err = -ENOMEM;
1347 goto err_plat;
1348 }
1349
1350 SET_NETDEV_DEV(dev, &pdev->dev);
1351 hdlc = dev_to_hdlc(dev);
1352 hdlc->attach = hss_hdlc_attach;
1353 hdlc->xmit = hss_hdlc_xmit;
1354 dev->netdev_ops = &hss_hdlc_ops;
1355 dev->tx_queue_len = 100;
1356 port->clock_type = CLOCK_EXT;
1357 port->clock_rate = 0;
1358 port->clock_reg = CLK42X_SPEED_2048KHZ;
1359 port->id = pdev->id;
1360 port->dev = &pdev->dev;
1361 port->plat = pdev->dev.platform_data;
1362 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1363
1364 if ((err = register_hdlc_device(dev)))
1365 goto err_free_netdev;
1366
1367 platform_set_drvdata(pdev, port);
1368
1369 netdev_info(dev, "initialized\n");
1370 return 0;
1371
1372err_free_netdev:
1373 free_netdev(dev);
1374err_plat:
1375 npe_release(port->npe);
1376err_free:
1377 kfree(port);
1378 return err;
1379}
1380
1381static int hss_remove_one(struct platform_device *pdev)
1382{
1383 struct port *port = platform_get_drvdata(pdev);
1384
1385 unregister_hdlc_device(port->netdev);
1386 free_netdev(port->netdev);
1387 npe_release(port->npe);
1388 kfree(port);
1389 return 0;
1390}
1391
1392static struct platform_driver ixp4xx_hss_driver = {
1393 .driver.name = DRV_NAME,
1394 .probe = hss_init_one,
1395 .remove = hss_remove_one,
1396};
1397
1398static int __init hss_init_module(void)
1399{
1400 if ((ixp4xx_read_feature_bits() &
1401 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1402 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1403 return -ENODEV;
1404
1405 spin_lock_init(&npe_lock);
1406
1407 return platform_driver_register(&ixp4xx_hss_driver);
1408}
1409
1410static void __exit hss_cleanup_module(void)
1411{
1412 platform_driver_unregister(&ixp4xx_hss_driver);
1413}
1414
1415MODULE_AUTHOR("Krzysztof Halasa");
1416MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1417MODULE_LICENSE("GPL v2");
1418MODULE_ALIAS("platform:ixp4xx_hss");
1419module_init(hss_init_module);
1420module_exit(hss_cleanup_module);