1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/bitops.h>
   8#include <linux/err.h>
   9#include <linux/platform_device.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/of_device.h>
  13#include <linux/clk-provider.h>
  14#include <linux/regmap.h>
  15#include <linux/reset-controller.h>
  16
  17#include <dt-bindings/clock/qcom,gcc-msm8996.h>
  18
  19#include "common.h"
  20#include "clk-regmap.h"
  21#include "clk-alpha-pll.h"
  22#include "clk-rcg.h"
  23#include "clk-branch.h"
  24#include "reset.h"
  25#include "gdsc.h"
  26
  27enum {
  28	P_XO,
  29	P_GPLL0,
  30	P_GPLL2,
  31	P_GPLL3,
  32	P_GPLL1,
  33	P_GPLL2_EARLY,
  34	P_GPLL0_EARLY_DIV,
  35	P_SLEEP_CLK,
  36	P_GPLL4,
  37	P_AUD_REF_CLK,
  38	P_GPLL1_EARLY_DIV
  39};
  40
  41static const struct parent_map gcc_sleep_clk_map[] = {
  42	{ P_SLEEP_CLK, 5 }
  43};
  44
  45static const char * const gcc_sleep_clk[] = {
  46	"sleep_clk"
  47};
  48
  49static const struct parent_map gcc_xo_gpll0_map[] = {
  50	{ P_XO, 0 },
  51	{ P_GPLL0, 1 }
  52};
  53
  54static const char * const gcc_xo_gpll0[] = {
  55	"xo",
  56	"gpll0"
  57};
  58
  59static const struct parent_map gcc_xo_sleep_clk_map[] = {
  60	{ P_XO, 0 },
  61	{ P_SLEEP_CLK, 5 }
  62};
  63
  64static const char * const gcc_xo_sleep_clk[] = {
  65	"xo",
  66	"sleep_clk"
  67};
  68
  69static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  70	{ P_XO, 0 },
  71	{ P_GPLL0, 1 },
  72	{ P_GPLL0_EARLY_DIV, 6 }
  73};
  74
  75static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  76	"xo",
  77	"gpll0",
  78	"gpll0_early_div"
  79};
  80
  81static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  82	{ P_XO, 0 },
  83	{ P_GPLL0, 1 },
  84	{ P_GPLL4, 5 }
  85};
  86
  87static const char * const gcc_xo_gpll0_gpll4[] = {
  88	"xo",
  89	"gpll0",
  90	"gpll4"
  91};
  92
  93static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
  94	{ P_XO, 0 },
  95	{ P_GPLL0, 1 },
  96	{ P_AUD_REF_CLK, 2 }
  97};
  98
  99static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 100	"xo",
 101	"gpll0",
 102	"aud_ref_clk"
 103};
 104
 105static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 106	{ P_XO, 0 },
 107	{ P_GPLL0, 1 },
 108	{ P_SLEEP_CLK, 5 },
 109	{ P_GPLL0_EARLY_DIV, 6 }
 110};
 111
 112static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 113	"xo",
 114	"gpll0",
 115	"sleep_clk",
 116	"gpll0_early_div"
 117};
 118
 119static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 120	{ P_XO, 0 },
 121	{ P_GPLL0, 1 },
 122	{ P_GPLL4, 5 },
 123	{ P_GPLL0_EARLY_DIV, 6 }
 124};
 125
 126static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 127	"xo",
 128	"gpll0",
 129	"gpll4",
 130	"gpll0_early_div"
 131};
 132
 133static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 134	{ P_XO, 0 },
 135	{ P_GPLL0, 1 },
 136	{ P_GPLL1_EARLY_DIV, 3 },
 137	{ P_GPLL1, 4 },
 138	{ P_GPLL4, 5 },
 139	{ P_GPLL0_EARLY_DIV, 6 }
 140};
 141
 142static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 143	"xo",
 144	"gpll0",
 145	"gpll1_early_div",
 146	"gpll1",
 147	"gpll4",
 148	"gpll0_early_div"
 149};
 150
 151static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 152	{ P_XO, 0 },
 153	{ P_GPLL0, 1 },
 154	{ P_GPLL2, 2 },
 155	{ P_GPLL3, 3 },
 156	{ P_GPLL1, 4 },
 157	{ P_GPLL2_EARLY, 5 },
 158	{ P_GPLL0_EARLY_DIV, 6 }
 159};
 160
 161static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 162	"xo",
 163	"gpll0",
 164	"gpll2",
 165	"gpll3",
 166	"gpll1",
 167	"gpll2_early",
 168	"gpll0_early_div"
 169};
 170
 171static struct clk_fixed_factor xo = {
 172	.mult = 1,
 173	.div = 1,
 174	.hw.init = &(struct clk_init_data){
 175		.name = "xo",
 176		.parent_names = (const char *[]){ "xo_board" },
 177		.num_parents = 1,
 178		.ops = &clk_fixed_factor_ops,
 179	},
 180};
 181
 182static struct clk_alpha_pll gpll0_early = {
 183	.offset = 0x00000,
 184	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 185	.clkr = {
 186		.enable_reg = 0x52000,
 187		.enable_mask = BIT(0),
 188		.hw.init = &(struct clk_init_data){
 189			.name = "gpll0_early",
 190			.parent_names = (const char *[]){ "xo" },
 191			.num_parents = 1,
 192			.ops = &clk_alpha_pll_ops,
 193		},
 194	},
 195};
 196
 197static struct clk_fixed_factor gpll0_early_div = {
 198	.mult = 1,
 199	.div = 2,
 200	.hw.init = &(struct clk_init_data){
 201		.name = "gpll0_early_div",
 202		.parent_names = (const char *[]){ "gpll0_early" },
 203		.num_parents = 1,
 204		.ops = &clk_fixed_factor_ops,
 205	},
 206};
 207
 208static struct clk_alpha_pll_postdiv gpll0 = {
 209	.offset = 0x00000,
 210	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 211	.clkr.hw.init = &(struct clk_init_data){
 212		.name = "gpll0",
 213		.parent_names = (const char *[]){ "gpll0_early" },
 214		.num_parents = 1,
 215		.ops = &clk_alpha_pll_postdiv_ops,
 216	},
 217};
 218
 219static struct clk_branch gcc_mmss_gpll0_div_clk = {
 220	.halt_check = BRANCH_HALT_DELAY,
 221	.clkr = {
 222		.enable_reg = 0x5200c,
 223		.enable_mask = BIT(0),
 224		.hw.init = &(struct clk_init_data){
 225			.name = "gcc_mmss_gpll0_div_clk",
 226			.parent_names = (const char *[]){ "gpll0" },
 227			.num_parents = 1,
 228			.flags = CLK_SET_RATE_PARENT,
 229			.ops = &clk_branch2_ops,
 230		},
 231	},
 232};
 233
 234static struct clk_branch gcc_mss_gpll0_div_clk = {
 235	.halt_check = BRANCH_HALT_DELAY,
 236	.clkr = {
 237		.enable_reg = 0x5200c,
 238		.enable_mask = BIT(2),
 239		.hw.init = &(struct clk_init_data){
 240			.name = "gcc_mss_gpll0_div_clk",
 241			.parent_names = (const char *[]){ "gpll0" },
 242			.num_parents = 1,
 243			.flags = CLK_SET_RATE_PARENT,
 244			.ops = &clk_branch2_ops
 245		},
 246	},
 247};
 248
 249static struct clk_alpha_pll gpll4_early = {
 250	.offset = 0x77000,
 251	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 252	.clkr = {
 253		.enable_reg = 0x52000,
 254		.enable_mask = BIT(4),
 255		.hw.init = &(struct clk_init_data){
 256			.name = "gpll4_early",
 257			.parent_names = (const char *[]){ "xo" },
 258			.num_parents = 1,
 259			.ops = &clk_alpha_pll_ops,
 260		},
 261	},
 262};
 263
 264static struct clk_alpha_pll_postdiv gpll4 = {
 265	.offset = 0x77000,
 266	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 267	.clkr.hw.init = &(struct clk_init_data){
 268		.name = "gpll4",
 269		.parent_names = (const char *[]){ "gpll4_early" },
 270		.num_parents = 1,
 271		.ops = &clk_alpha_pll_postdiv_ops,
 272	},
 273};
 274
 275static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 276	F(19200000, P_XO, 1, 0, 0),
 277	F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 278	F(100000000, P_GPLL0, 6, 0, 0),
 279	F(150000000, P_GPLL0, 4, 0, 0),
 280	F(200000000, P_GPLL0, 3, 0, 0),
 281	F(240000000, P_GPLL0, 2.5, 0, 0),
 282	{ }
 283};
 284
 285static struct clk_rcg2 system_noc_clk_src = {
 286	.cmd_rcgr = 0x0401c,
 287	.hid_width = 5,
 288	.parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 289	.freq_tbl = ftbl_system_noc_clk_src,
 290	.clkr.hw.init = &(struct clk_init_data){
 291		.name = "system_noc_clk_src",
 292		.parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 293		.num_parents = 7,
 294		.ops = &clk_rcg2_ops,
 295	},
 296};
 297
 298static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 299	F(19200000, P_XO, 1, 0, 0),
 300	F(37500000, P_GPLL0, 16, 0, 0),
 301	F(75000000, P_GPLL0, 8, 0, 0),
 302	{ }
 303};
 304
 305static struct clk_rcg2 config_noc_clk_src = {
 306	.cmd_rcgr = 0x0500c,
 307	.hid_width = 5,
 308	.parent_map = gcc_xo_gpll0_map,
 309	.freq_tbl = ftbl_config_noc_clk_src,
 310	.clkr.hw.init = &(struct clk_init_data){
 311		.name = "config_noc_clk_src",
 312		.parent_names = gcc_xo_gpll0,
 313		.num_parents = 2,
 314		.ops = &clk_rcg2_ops,
 315	},
 316};
 317
 318static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 319	F(19200000, P_XO, 1, 0, 0),
 320	F(37500000, P_GPLL0, 16, 0, 0),
 321	F(50000000, P_GPLL0, 12, 0, 0),
 322	F(75000000, P_GPLL0, 8, 0, 0),
 323	F(100000000, P_GPLL0, 6, 0, 0),
 324	{ }
 325};
 326
 327static struct clk_rcg2 periph_noc_clk_src = {
 328	.cmd_rcgr = 0x06014,
 329	.hid_width = 5,
 330	.parent_map = gcc_xo_gpll0_map,
 331	.freq_tbl = ftbl_periph_noc_clk_src,
 332	.clkr.hw.init = &(struct clk_init_data){
 333		.name = "periph_noc_clk_src",
 334		.parent_names = gcc_xo_gpll0,
 335		.num_parents = 2,
 336		.ops = &clk_rcg2_ops,
 337	},
 338};
 339
 340static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 341	F(19200000, P_XO, 1, 0, 0),
 342	F(120000000, P_GPLL0, 5, 0, 0),
 343	F(150000000, P_GPLL0, 4, 0, 0),
 344	{ }
 345};
 346
 347static struct clk_rcg2 usb30_master_clk_src = {
 348	.cmd_rcgr = 0x0f014,
 349	.mnd_width = 8,
 350	.hid_width = 5,
 351	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 352	.freq_tbl = ftbl_usb30_master_clk_src,
 353	.clkr.hw.init = &(struct clk_init_data){
 354		.name = "usb30_master_clk_src",
 355		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 356		.num_parents = 3,
 357		.ops = &clk_rcg2_ops,
 358	},
 359};
 360
 361static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 362	F(19200000, P_XO, 1, 0, 0),
 363	{ }
 364};
 365
 366static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 367	.cmd_rcgr = 0x0f028,
 368	.hid_width = 5,
 369	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 370	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 371	.clkr.hw.init = &(struct clk_init_data){
 372		.name = "usb30_mock_utmi_clk_src",
 373		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 374		.num_parents = 3,
 375		.ops = &clk_rcg2_ops,
 376	},
 377};
 378
 379static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 380	F(1200000, P_XO, 16, 0, 0),
 381	{ }
 382};
 383
 384static struct clk_rcg2 usb3_phy_aux_clk_src = {
 385	.cmd_rcgr = 0x5000c,
 386	.hid_width = 5,
 387	.parent_map = gcc_xo_sleep_clk_map,
 388	.freq_tbl = ftbl_usb3_phy_aux_clk_src,
 389	.clkr.hw.init = &(struct clk_init_data){
 390		.name = "usb3_phy_aux_clk_src",
 391		.parent_names = gcc_xo_sleep_clk,
 392		.num_parents = 2,
 393		.ops = &clk_rcg2_ops,
 394	},
 395};
 396
 397static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 398	F(120000000, P_GPLL0, 5, 0, 0),
 399	{ }
 400};
 401
 402static struct clk_rcg2 usb20_master_clk_src = {
 403	.cmd_rcgr = 0x12010,
 404	.mnd_width = 8,
 405	.hid_width = 5,
 406	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 407	.freq_tbl = ftbl_usb20_master_clk_src,
 408	.clkr.hw.init = &(struct clk_init_data){
 409		.name = "usb20_master_clk_src",
 410		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 411		.num_parents = 3,
 412		.ops = &clk_rcg2_ops,
 413	},
 414};
 415
 416static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 417	.cmd_rcgr = 0x12024,
 418	.hid_width = 5,
 419	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 420	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 421	.clkr.hw.init = &(struct clk_init_data){
 422		.name = "usb20_mock_utmi_clk_src",
 423		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 424		.num_parents = 3,
 425		.ops = &clk_rcg2_ops,
 426	},
 427};
 428
 429static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 430	F(144000, P_XO, 16, 3, 25),
 431	F(400000, P_XO, 12, 1, 4),
 432	F(20000000, P_GPLL0, 15, 1, 2),
 433	F(25000000, P_GPLL0, 12, 1, 2),
 434	F(50000000, P_GPLL0, 12, 0, 0),
 435	F(96000000, P_GPLL4, 4, 0, 0),
 436	F(192000000, P_GPLL4, 2, 0, 0),
 437	F(384000000, P_GPLL4, 1, 0, 0),
 438	{ }
 439};
 440
 441static struct clk_rcg2 sdcc1_apps_clk_src = {
 442	.cmd_rcgr = 0x13010,
 443	.mnd_width = 8,
 444	.hid_width = 5,
 445	.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 446	.freq_tbl = ftbl_sdcc1_apps_clk_src,
 447	.clkr.hw.init = &(struct clk_init_data){
 448		.name = "sdcc1_apps_clk_src",
 449		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 450		.num_parents = 4,
 451		.ops = &clk_rcg2_floor_ops,
 452	},
 453};
 454
 455static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 456	F(19200000, P_XO, 1, 0, 0),
 457	F(150000000, P_GPLL0, 4, 0, 0),
 458	F(300000000, P_GPLL0, 2, 0, 0),
 459	{ }
 460};
 461
 462static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 463	.cmd_rcgr = 0x13024,
 464	.hid_width = 5,
 465	.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 466	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 467	.clkr.hw.init = &(struct clk_init_data){
 468		.name = "sdcc1_ice_core_clk_src",
 469		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 470		.num_parents = 4,
 471		.ops = &clk_rcg2_ops,
 472	},
 473};
 474
 475static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 476	F(144000, P_XO, 16, 3, 25),
 477	F(400000, P_XO, 12, 1, 4),
 478	F(20000000, P_GPLL0, 15, 1, 2),
 479	F(25000000, P_GPLL0, 12, 1, 2),
 480	F(50000000, P_GPLL0, 12, 0, 0),
 481	F(100000000, P_GPLL0, 6, 0, 0),
 482	F(200000000, P_GPLL0, 3, 0, 0),
 483	{ }
 484};
 485
 486static struct clk_rcg2 sdcc2_apps_clk_src = {
 487	.cmd_rcgr = 0x14010,
 488	.mnd_width = 8,
 489	.hid_width = 5,
 490	.parent_map = gcc_xo_gpll0_gpll4_map,
 491	.freq_tbl = ftbl_sdcc2_apps_clk_src,
 492	.clkr.hw.init = &(struct clk_init_data){
 493		.name = "sdcc2_apps_clk_src",
 494		.parent_names = gcc_xo_gpll0_gpll4,
 495		.num_parents = 3,
 496		.ops = &clk_rcg2_floor_ops,
 497	},
 498};
 499
 500static struct clk_rcg2 sdcc3_apps_clk_src = {
 501	.cmd_rcgr = 0x15010,
 502	.mnd_width = 8,
 503	.hid_width = 5,
 504	.parent_map = gcc_xo_gpll0_gpll4_map,
 505	.freq_tbl = ftbl_sdcc2_apps_clk_src,
 506	.clkr.hw.init = &(struct clk_init_data){
 507		.name = "sdcc3_apps_clk_src",
 508		.parent_names = gcc_xo_gpll0_gpll4,
 509		.num_parents = 3,
 510		.ops = &clk_rcg2_floor_ops,
 511	},
 512};
 513
 514static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 515	F(144000, P_XO, 16, 3, 25),
 516	F(400000, P_XO, 12, 1, 4),
 517	F(20000000, P_GPLL0, 15, 1, 2),
 518	F(25000000, P_GPLL0, 12, 1, 2),
 519	F(50000000, P_GPLL0, 12, 0, 0),
 520	F(100000000, P_GPLL0, 6, 0, 0),
 521	{ }
 522};
 523
 524static struct clk_rcg2 sdcc4_apps_clk_src = {
 525	.cmd_rcgr = 0x16010,
 526	.mnd_width = 8,
 527	.hid_width = 5,
 528	.parent_map = gcc_xo_gpll0_map,
 529	.freq_tbl = ftbl_sdcc4_apps_clk_src,
 530	.clkr.hw.init = &(struct clk_init_data){
 531		.name = "sdcc4_apps_clk_src",
 532		.parent_names = gcc_xo_gpll0,
 533		.num_parents = 2,
 534		.ops = &clk_rcg2_floor_ops,
 535	},
 536};
 537
 538static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 539	F(960000, P_XO, 10, 1, 2),
 540	F(4800000, P_XO, 4, 0, 0),
 541	F(9600000, P_XO, 2, 0, 0),
 542	F(15000000, P_GPLL0, 10, 1, 4),
 543	F(19200000, P_XO, 1, 0, 0),
 544	F(25000000, P_GPLL0, 12, 1, 2),
 545	F(50000000, P_GPLL0, 12, 0, 0),
 546	{ }
 547};
 548
 549static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 550	.cmd_rcgr = 0x1900c,
 551	.mnd_width = 8,
 552	.hid_width = 5,
 553	.parent_map = gcc_xo_gpll0_map,
 554	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 555	.clkr.hw.init = &(struct clk_init_data){
 556		.name = "blsp1_qup1_spi_apps_clk_src",
 557		.parent_names = gcc_xo_gpll0,
 558		.num_parents = 2,
 559		.ops = &clk_rcg2_ops,
 560	},
 561};
 562
 563static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 564	F(19200000, P_XO, 1, 0, 0),
 565	F(50000000, P_GPLL0, 12, 0, 0),
 566	{ }
 567};
 568
 569static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 570	.cmd_rcgr = 0x19020,
 571	.hid_width = 5,
 572	.parent_map = gcc_xo_gpll0_map,
 573	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 574	.clkr.hw.init = &(struct clk_init_data){
 575		.name = "blsp1_qup1_i2c_apps_clk_src",
 576		.parent_names = gcc_xo_gpll0,
 577		.num_parents = 2,
 578		.ops = &clk_rcg2_ops,
 579	},
 580};
 581
 582static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 583	F(3686400, P_GPLL0, 1, 96, 15625),
 584	F(7372800, P_GPLL0, 1, 192, 15625),
 585	F(14745600, P_GPLL0, 1, 384, 15625),
 586	F(16000000, P_GPLL0, 5, 2, 15),
 587	F(19200000, P_XO, 1, 0, 0),
 588	F(24000000, P_GPLL0, 5, 1, 5),
 589	F(32000000, P_GPLL0, 1, 4, 75),
 590	F(40000000, P_GPLL0, 15, 0, 0),
 591	F(46400000, P_GPLL0, 1, 29, 375),
 592	F(48000000, P_GPLL0, 12.5, 0, 0),
 593	F(51200000, P_GPLL0, 1, 32, 375),
 594	F(56000000, P_GPLL0, 1, 7, 75),
 595	F(58982400, P_GPLL0, 1, 1536, 15625),
 596	F(60000000, P_GPLL0, 10, 0, 0),
 597	F(63157895, P_GPLL0, 9.5, 0, 0),
 598	{ }
 599};
 600
 601static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 602	.cmd_rcgr = 0x1a00c,
 603	.mnd_width = 16,
 604	.hid_width = 5,
 605	.parent_map = gcc_xo_gpll0_map,
 606	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 607	.clkr.hw.init = &(struct clk_init_data){
 608		.name = "blsp1_uart1_apps_clk_src",
 609		.parent_names = gcc_xo_gpll0,
 610		.num_parents = 2,
 611		.ops = &clk_rcg2_ops,
 612	},
 613};
 614
 615static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 616	.cmd_rcgr = 0x1b00c,
 617	.mnd_width = 8,
 618	.hid_width = 5,
 619	.parent_map = gcc_xo_gpll0_map,
 620	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 621	.clkr.hw.init = &(struct clk_init_data){
 622		.name = "blsp1_qup2_spi_apps_clk_src",
 623		.parent_names = gcc_xo_gpll0,
 624		.num_parents = 2,
 625		.ops = &clk_rcg2_ops,
 626	},
 627};
 628
 629static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 630	.cmd_rcgr = 0x1b020,
 631	.hid_width = 5,
 632	.parent_map = gcc_xo_gpll0_map,
 633	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 634	.clkr.hw.init = &(struct clk_init_data){
 635		.name = "blsp1_qup2_i2c_apps_clk_src",
 636		.parent_names = gcc_xo_gpll0,
 637		.num_parents = 2,
 638		.ops = &clk_rcg2_ops,
 639	},
 640};
 641
 642static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 643	.cmd_rcgr = 0x1c00c,
 644	.mnd_width = 16,
 645	.hid_width = 5,
 646	.parent_map = gcc_xo_gpll0_map,
 647	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 648	.clkr.hw.init = &(struct clk_init_data){
 649		.name = "blsp1_uart2_apps_clk_src",
 650		.parent_names = gcc_xo_gpll0,
 651		.num_parents = 2,
 652		.ops = &clk_rcg2_ops,
 653	},
 654};
 655
 656static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 657	.cmd_rcgr = 0x1d00c,
 658	.mnd_width = 8,
 659	.hid_width = 5,
 660	.parent_map = gcc_xo_gpll0_map,
 661	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 662	.clkr.hw.init = &(struct clk_init_data){
 663		.name = "blsp1_qup3_spi_apps_clk_src",
 664		.parent_names = gcc_xo_gpll0,
 665		.num_parents = 2,
 666		.ops = &clk_rcg2_ops,
 667	},
 668};
 669
 670static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 671	.cmd_rcgr = 0x1d020,
 672	.hid_width = 5,
 673	.parent_map = gcc_xo_gpll0_map,
 674	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 675	.clkr.hw.init = &(struct clk_init_data){
 676		.name = "blsp1_qup3_i2c_apps_clk_src",
 677		.parent_names = gcc_xo_gpll0,
 678		.num_parents = 2,
 679		.ops = &clk_rcg2_ops,
 680	},
 681};
 682
 683static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 684	.cmd_rcgr = 0x1e00c,
 685	.mnd_width = 16,
 686	.hid_width = 5,
 687	.parent_map = gcc_xo_gpll0_map,
 688	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 689	.clkr.hw.init = &(struct clk_init_data){
 690		.name = "blsp1_uart3_apps_clk_src",
 691		.parent_names = gcc_xo_gpll0,
 692		.num_parents = 2,
 693		.ops = &clk_rcg2_ops,
 694	},
 695};
 696
 697static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 698	.cmd_rcgr = 0x1f00c,
 699	.mnd_width = 8,
 700	.hid_width = 5,
 701	.parent_map = gcc_xo_gpll0_map,
 702	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 703	.clkr.hw.init = &(struct clk_init_data){
 704		.name = "blsp1_qup4_spi_apps_clk_src",
 705		.parent_names = gcc_xo_gpll0,
 706		.num_parents = 2,
 707		.ops = &clk_rcg2_ops,
 708	},
 709};
 710
 711static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 712	.cmd_rcgr = 0x1f020,
 713	.hid_width = 5,
 714	.parent_map = gcc_xo_gpll0_map,
 715	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 716	.clkr.hw.init = &(struct clk_init_data){
 717		.name = "blsp1_qup4_i2c_apps_clk_src",
 718		.parent_names = gcc_xo_gpll0,
 719		.num_parents = 2,
 720		.ops = &clk_rcg2_ops,
 721	},
 722};
 723
 724static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 725	.cmd_rcgr = 0x2000c,
 726	.mnd_width = 16,
 727	.hid_width = 5,
 728	.parent_map = gcc_xo_gpll0_map,
 729	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 730	.clkr.hw.init = &(struct clk_init_data){
 731		.name = "blsp1_uart4_apps_clk_src",
 732		.parent_names = gcc_xo_gpll0,
 733		.num_parents = 2,
 734		.ops = &clk_rcg2_ops,
 735	},
 736};
 737
 738static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 739	.cmd_rcgr = 0x2100c,
 740	.mnd_width = 8,
 741	.hid_width = 5,
 742	.parent_map = gcc_xo_gpll0_map,
 743	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 744	.clkr.hw.init = &(struct clk_init_data){
 745		.name = "blsp1_qup5_spi_apps_clk_src",
 746		.parent_names = gcc_xo_gpll0,
 747		.num_parents = 2,
 748		.ops = &clk_rcg2_ops,
 749	},
 750};
 751
 752static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 753	.cmd_rcgr = 0x21020,
 754	.hid_width = 5,
 755	.parent_map = gcc_xo_gpll0_map,
 756	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 757	.clkr.hw.init = &(struct clk_init_data){
 758		.name = "blsp1_qup5_i2c_apps_clk_src",
 759		.parent_names = gcc_xo_gpll0,
 760		.num_parents = 2,
 761		.ops = &clk_rcg2_ops,
 762	},
 763};
 764
 765static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 766	.cmd_rcgr = 0x2200c,
 767	.mnd_width = 16,
 768	.hid_width = 5,
 769	.parent_map = gcc_xo_gpll0_map,
 770	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 771	.clkr.hw.init = &(struct clk_init_data){
 772		.name = "blsp1_uart5_apps_clk_src",
 773		.parent_names = gcc_xo_gpll0,
 774		.num_parents = 2,
 775		.ops = &clk_rcg2_ops,
 776	},
 777};
 778
 779static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 780	.cmd_rcgr = 0x2300c,
 781	.mnd_width = 8,
 782	.hid_width = 5,
 783	.parent_map = gcc_xo_gpll0_map,
 784	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 785	.clkr.hw.init = &(struct clk_init_data){
 786		.name = "blsp1_qup6_spi_apps_clk_src",
 787		.parent_names = gcc_xo_gpll0,
 788		.num_parents = 2,
 789		.ops = &clk_rcg2_ops,
 790	},
 791};
 792
 793static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 794	.cmd_rcgr = 0x23020,
 795	.hid_width = 5,
 796	.parent_map = gcc_xo_gpll0_map,
 797	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 798	.clkr.hw.init = &(struct clk_init_data){
 799		.name = "blsp1_qup6_i2c_apps_clk_src",
 800		.parent_names = gcc_xo_gpll0,
 801		.num_parents = 2,
 802		.ops = &clk_rcg2_ops,
 803	},
 804};
 805
 806static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 807	.cmd_rcgr = 0x2400c,
 808	.mnd_width = 16,
 809	.hid_width = 5,
 810	.parent_map = gcc_xo_gpll0_map,
 811	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 812	.clkr.hw.init = &(struct clk_init_data){
 813		.name = "blsp1_uart6_apps_clk_src",
 814		.parent_names = gcc_xo_gpll0,
 815		.num_parents = 2,
 816		.ops = &clk_rcg2_ops,
 817	},
 818};
 819
 820static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 821	.cmd_rcgr = 0x2600c,
 822	.mnd_width = 8,
 823	.hid_width = 5,
 824	.parent_map = gcc_xo_gpll0_map,
 825	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 826	.clkr.hw.init = &(struct clk_init_data){
 827		.name = "blsp2_qup1_spi_apps_clk_src",
 828		.parent_names = gcc_xo_gpll0,
 829		.num_parents = 2,
 830		.ops = &clk_rcg2_ops,
 831	},
 832};
 833
 834static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 835	.cmd_rcgr = 0x26020,
 836	.hid_width = 5,
 837	.parent_map = gcc_xo_gpll0_map,
 838	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 839	.clkr.hw.init = &(struct clk_init_data){
 840		.name = "blsp2_qup1_i2c_apps_clk_src",
 841		.parent_names = gcc_xo_gpll0,
 842		.num_parents = 2,
 843		.ops = &clk_rcg2_ops,
 844	},
 845};
 846
 847static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 848	.cmd_rcgr = 0x2700c,
 849	.mnd_width = 16,
 850	.hid_width = 5,
 851	.parent_map = gcc_xo_gpll0_map,
 852	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 853	.clkr.hw.init = &(struct clk_init_data){
 854		.name = "blsp2_uart1_apps_clk_src",
 855		.parent_names = gcc_xo_gpll0,
 856		.num_parents = 2,
 857		.ops = &clk_rcg2_ops,
 858	},
 859};
 860
 861static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 862	.cmd_rcgr = 0x2800c,
 863	.mnd_width = 8,
 864	.hid_width = 5,
 865	.parent_map = gcc_xo_gpll0_map,
 866	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 867	.clkr.hw.init = &(struct clk_init_data){
 868		.name = "blsp2_qup2_spi_apps_clk_src",
 869		.parent_names = gcc_xo_gpll0,
 870		.num_parents = 2,
 871		.ops = &clk_rcg2_ops,
 872	},
 873};
 874
 875static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 876	.cmd_rcgr = 0x28020,
 877	.hid_width = 5,
 878	.parent_map = gcc_xo_gpll0_map,
 879	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 880	.clkr.hw.init = &(struct clk_init_data){
 881		.name = "blsp2_qup2_i2c_apps_clk_src",
 882		.parent_names = gcc_xo_gpll0,
 883		.num_parents = 2,
 884		.ops = &clk_rcg2_ops,
 885	},
 886};
 887
 888static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 889	.cmd_rcgr = 0x2900c,
 890	.mnd_width = 16,
 891	.hid_width = 5,
 892	.parent_map = gcc_xo_gpll0_map,
 893	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 894	.clkr.hw.init = &(struct clk_init_data){
 895		.name = "blsp2_uart2_apps_clk_src",
 896		.parent_names = gcc_xo_gpll0,
 897		.num_parents = 2,
 898		.ops = &clk_rcg2_ops,
 899	},
 900};
 901
 902static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 903	.cmd_rcgr = 0x2a00c,
 904	.mnd_width = 8,
 905	.hid_width = 5,
 906	.parent_map = gcc_xo_gpll0_map,
 907	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 908	.clkr.hw.init = &(struct clk_init_data){
 909		.name = "blsp2_qup3_spi_apps_clk_src",
 910		.parent_names = gcc_xo_gpll0,
 911		.num_parents = 2,
 912		.ops = &clk_rcg2_ops,
 913	},
 914};
 915
 916static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 917	.cmd_rcgr = 0x2a020,
 918	.hid_width = 5,
 919	.parent_map = gcc_xo_gpll0_map,
 920	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 921	.clkr.hw.init = &(struct clk_init_data){
 922		.name = "blsp2_qup3_i2c_apps_clk_src",
 923		.parent_names = gcc_xo_gpll0,
 924		.num_parents = 2,
 925		.ops = &clk_rcg2_ops,
 926	},
 927};
 928
 929static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 930	.cmd_rcgr = 0x2b00c,
 931	.mnd_width = 16,
 932	.hid_width = 5,
 933	.parent_map = gcc_xo_gpll0_map,
 934	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 935	.clkr.hw.init = &(struct clk_init_data){
 936		.name = "blsp2_uart3_apps_clk_src",
 937		.parent_names = gcc_xo_gpll0,
 938		.num_parents = 2,
 939		.ops = &clk_rcg2_ops,
 940	},
 941};
 942
 943static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 944	.cmd_rcgr = 0x2c00c,
 945	.mnd_width = 8,
 946	.hid_width = 5,
 947	.parent_map = gcc_xo_gpll0_map,
 948	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 949	.clkr.hw.init = &(struct clk_init_data){
 950		.name = "blsp2_qup4_spi_apps_clk_src",
 951		.parent_names = gcc_xo_gpll0,
 952		.num_parents = 2,
 953		.ops = &clk_rcg2_ops,
 954	},
 955};
 956
 957static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 958	.cmd_rcgr = 0x2c020,
 959	.hid_width = 5,
 960	.parent_map = gcc_xo_gpll0_map,
 961	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 962	.clkr.hw.init = &(struct clk_init_data){
 963		.name = "blsp2_qup4_i2c_apps_clk_src",
 964		.parent_names = gcc_xo_gpll0,
 965		.num_parents = 2,
 966		.ops = &clk_rcg2_ops,
 967	},
 968};
 969
 970static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 971	.cmd_rcgr = 0x2d00c,
 972	.mnd_width = 16,
 973	.hid_width = 5,
 974	.parent_map = gcc_xo_gpll0_map,
 975	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 976	.clkr.hw.init = &(struct clk_init_data){
 977		.name = "blsp2_uart4_apps_clk_src",
 978		.parent_names = gcc_xo_gpll0,
 979		.num_parents = 2,
 980		.ops = &clk_rcg2_ops,
 981	},
 982};
 983
 984static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 985	.cmd_rcgr = 0x2e00c,
 986	.mnd_width = 8,
 987	.hid_width = 5,
 988	.parent_map = gcc_xo_gpll0_map,
 989	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 990	.clkr.hw.init = &(struct clk_init_data){
 991		.name = "blsp2_qup5_spi_apps_clk_src",
 992		.parent_names = gcc_xo_gpll0,
 993		.num_parents = 2,
 994		.ops = &clk_rcg2_ops,
 995	},
 996};
 997
 998static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 999	.cmd_rcgr = 0x2e020,
1000	.hid_width = 5,
1001	.parent_map = gcc_xo_gpll0_map,
1002	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1003	.clkr.hw.init = &(struct clk_init_data){
1004		.name = "blsp2_qup5_i2c_apps_clk_src",
1005		.parent_names = gcc_xo_gpll0,
1006		.num_parents = 2,
1007		.ops = &clk_rcg2_ops,
1008	},
1009};
1010
1011static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1012	.cmd_rcgr = 0x2f00c,
1013	.mnd_width = 16,
1014	.hid_width = 5,
1015	.parent_map = gcc_xo_gpll0_map,
1016	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1017	.clkr.hw.init = &(struct clk_init_data){
1018		.name = "blsp2_uart5_apps_clk_src",
1019		.parent_names = gcc_xo_gpll0,
1020		.num_parents = 2,
1021		.ops = &clk_rcg2_ops,
1022	},
1023};
1024
1025static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1026	.cmd_rcgr = 0x3000c,
1027	.mnd_width = 8,
1028	.hid_width = 5,
1029	.parent_map = gcc_xo_gpll0_map,
1030	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1031	.clkr.hw.init = &(struct clk_init_data){
1032		.name = "blsp2_qup6_spi_apps_clk_src",
1033		.parent_names = gcc_xo_gpll0,
1034		.num_parents = 2,
1035		.ops = &clk_rcg2_ops,
1036	},
1037};
1038
1039static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1040	.cmd_rcgr = 0x30020,
1041	.hid_width = 5,
1042	.parent_map = gcc_xo_gpll0_map,
1043	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1044	.clkr.hw.init = &(struct clk_init_data){
1045		.name = "blsp2_qup6_i2c_apps_clk_src",
1046		.parent_names = gcc_xo_gpll0,
1047		.num_parents = 2,
1048		.ops = &clk_rcg2_ops,
1049	},
1050};
1051
1052static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1053	.cmd_rcgr = 0x3100c,
1054	.mnd_width = 16,
1055	.hid_width = 5,
1056	.parent_map = gcc_xo_gpll0_map,
1057	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1058	.clkr.hw.init = &(struct clk_init_data){
1059		.name = "blsp2_uart6_apps_clk_src",
1060		.parent_names = gcc_xo_gpll0,
1061		.num_parents = 2,
1062		.ops = &clk_rcg2_ops,
1063	},
1064};
1065
1066static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1067	F(60000000, P_GPLL0, 10, 0, 0),
1068	{ }
1069};
1070
1071static struct clk_rcg2 pdm2_clk_src = {
1072	.cmd_rcgr = 0x33010,
1073	.hid_width = 5,
1074	.parent_map = gcc_xo_gpll0_map,
1075	.freq_tbl = ftbl_pdm2_clk_src,
1076	.clkr.hw.init = &(struct clk_init_data){
1077		.name = "pdm2_clk_src",
1078		.parent_names = gcc_xo_gpll0,
1079		.num_parents = 2,
1080		.ops = &clk_rcg2_ops,
1081	},
1082};
1083
1084static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1085	F(105495, P_XO, 1, 1, 182),
1086	{ }
1087};
1088
1089static struct clk_rcg2 tsif_ref_clk_src = {
1090	.cmd_rcgr = 0x36010,
1091	.mnd_width = 8,
1092	.hid_width = 5,
1093	.parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1094	.freq_tbl = ftbl_tsif_ref_clk_src,
1095	.clkr.hw.init = &(struct clk_init_data){
1096		.name = "tsif_ref_clk_src",
1097		.parent_names = gcc_xo_gpll0_aud_ref_clk,
1098		.num_parents = 3,
1099		.ops = &clk_rcg2_ops,
1100	},
1101};
1102
1103static struct clk_rcg2 gcc_sleep_clk_src = {
1104	.cmd_rcgr = 0x43014,
1105	.hid_width = 5,
1106	.parent_map = gcc_sleep_clk_map,
1107	.clkr.hw.init = &(struct clk_init_data){
1108		.name = "gcc_sleep_clk_src",
1109		.parent_names = gcc_sleep_clk,
1110		.num_parents = 1,
1111		.ops = &clk_rcg2_ops,
1112	},
1113};
1114
1115static struct clk_rcg2 hmss_rbcpr_clk_src = {
1116	.cmd_rcgr = 0x48040,
1117	.hid_width = 5,
1118	.parent_map = gcc_xo_gpll0_map,
1119	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1120	.clkr.hw.init = &(struct clk_init_data){
1121		.name = "hmss_rbcpr_clk_src",
1122		.parent_names = gcc_xo_gpll0,
1123		.num_parents = 2,
1124		.ops = &clk_rcg2_ops,
1125	},
1126};
1127
1128static struct clk_rcg2 hmss_gpll0_clk_src = {
1129	.cmd_rcgr = 0x48058,
1130	.hid_width = 5,
1131	.parent_map = gcc_xo_gpll0_map,
1132	.clkr.hw.init = &(struct clk_init_data){
1133		.name = "hmss_gpll0_clk_src",
1134		.parent_names = gcc_xo_gpll0,
1135		.num_parents = 2,
1136		.ops = &clk_rcg2_ops,
1137	},
1138};
1139
1140static const struct freq_tbl ftbl_gp1_clk_src[] = {
1141	F(19200000, P_XO, 1, 0, 0),
1142	F(100000000, P_GPLL0, 6, 0, 0),
1143	F(200000000, P_GPLL0, 3, 0, 0),
1144	{ }
1145};
1146
1147static struct clk_rcg2 gp1_clk_src = {
1148	.cmd_rcgr = 0x64004,
1149	.mnd_width = 8,
1150	.hid_width = 5,
1151	.parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1152	.freq_tbl = ftbl_gp1_clk_src,
1153	.clkr.hw.init = &(struct clk_init_data){
1154		.name = "gp1_clk_src",
1155		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1156		.num_parents = 4,
1157		.ops = &clk_rcg2_ops,
1158	},
1159};
1160
1161static struct clk_rcg2 gp2_clk_src = {
1162	.cmd_rcgr = 0x65004,
1163	.mnd_width = 8,
1164	.hid_width = 5,
1165	.parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1166	.freq_tbl = ftbl_gp1_clk_src,
1167	.clkr.hw.init = &(struct clk_init_data){
1168		.name = "gp2_clk_src",
1169		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1170		.num_parents = 4,
1171		.ops = &clk_rcg2_ops,
1172	},
1173};
1174
1175static struct clk_rcg2 gp3_clk_src = {
1176	.cmd_rcgr = 0x66004,
1177	.mnd_width = 8,
1178	.hid_width = 5,
1179	.parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1180	.freq_tbl = ftbl_gp1_clk_src,
1181	.clkr.hw.init = &(struct clk_init_data){
1182		.name = "gp3_clk_src",
1183		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1184		.num_parents = 4,
1185		.ops = &clk_rcg2_ops,
1186	},
1187};
1188
1189static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1190	F(1010526, P_XO, 1, 1, 19),
1191	{ }
1192};
1193
1194static struct clk_rcg2 pcie_aux_clk_src = {
1195	.cmd_rcgr = 0x6c000,
1196	.mnd_width = 16,
1197	.hid_width = 5,
1198	.parent_map = gcc_xo_sleep_clk_map,
1199	.freq_tbl = ftbl_pcie_aux_clk_src,
1200	.clkr.hw.init = &(struct clk_init_data){
1201		.name = "pcie_aux_clk_src",
1202		.parent_names = gcc_xo_sleep_clk,
1203		.num_parents = 2,
1204		.ops = &clk_rcg2_ops,
1205	},
1206};
1207
1208static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1209	F(100000000, P_GPLL0, 6, 0, 0),
1210	F(200000000, P_GPLL0, 3, 0, 0),
1211	F(240000000, P_GPLL0, 2.5, 0, 0),
1212	{ }
1213};
1214
1215static struct clk_rcg2 ufs_axi_clk_src = {
1216	.cmd_rcgr = 0x75024,
1217	.mnd_width = 8,
1218	.hid_width = 5,
1219	.parent_map = gcc_xo_gpll0_map,
1220	.freq_tbl = ftbl_ufs_axi_clk_src,
1221	.clkr.hw.init = &(struct clk_init_data){
1222		.name = "ufs_axi_clk_src",
1223		.parent_names = gcc_xo_gpll0,
1224		.num_parents = 2,
1225		.ops = &clk_rcg2_ops,
1226	},
1227};
1228
1229static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1230	F(19200000, P_XO, 1, 0, 0),
1231	F(150000000, P_GPLL0, 4, 0, 0),
1232	F(300000000, P_GPLL0, 2, 0, 0),
1233	{ }
1234};
1235
1236static struct clk_rcg2 ufs_ice_core_clk_src = {
1237	.cmd_rcgr = 0x76014,
1238	.hid_width = 5,
1239	.parent_map = gcc_xo_gpll0_map,
1240	.freq_tbl = ftbl_ufs_ice_core_clk_src,
1241	.clkr.hw.init = &(struct clk_init_data){
1242		.name = "ufs_ice_core_clk_src",
1243		.parent_names = gcc_xo_gpll0,
1244		.num_parents = 2,
1245		.ops = &clk_rcg2_ops,
1246	},
1247};
1248
1249static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1250	F(75000000, P_GPLL0, 8, 0, 0),
1251	F(150000000, P_GPLL0, 4, 0, 0),
1252	F(256000000, P_GPLL4, 1.5, 0, 0),
1253	F(300000000, P_GPLL0, 2, 0, 0),
1254	{ }
1255};
1256
1257static struct clk_rcg2 qspi_ser_clk_src = {
1258	.cmd_rcgr = 0x8b00c,
1259	.hid_width = 5,
1260	.parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1261	.freq_tbl = ftbl_qspi_ser_clk_src,
1262	.clkr.hw.init = &(struct clk_init_data){
1263		.name = "qspi_ser_clk_src",
1264		.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1265		.num_parents = 6,
1266		.ops = &clk_rcg2_ops,
1267	},
1268};
1269
1270static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1271	.halt_reg = 0x0f03c,
1272	.clkr = {
1273		.enable_reg = 0x0f03c,
1274		.enable_mask = BIT(0),
1275		.hw.init = &(struct clk_init_data){
1276			.name = "gcc_sys_noc_usb3_axi_clk",
1277			.parent_names = (const char *[]){ "usb30_master_clk_src" },
1278			.num_parents = 1,
1279			.flags = CLK_SET_RATE_PARENT,
1280			.ops = &clk_branch2_ops,
1281		},
1282	},
1283};
1284
1285static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1286	.halt_reg = 0x75038,
1287	.clkr = {
1288		.enable_reg = 0x75038,
1289		.enable_mask = BIT(0),
1290		.hw.init = &(struct clk_init_data){
1291			.name = "gcc_sys_noc_ufs_axi_clk",
1292			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
1293			.num_parents = 1,
1294			.flags = CLK_SET_RATE_PARENT,
1295			.ops = &clk_branch2_ops,
1296		},
1297	},
1298};
1299
1300static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1301	.halt_reg = 0x6010,
1302	.clkr = {
1303		.enable_reg = 0x6010,
1304		.enable_mask = BIT(0),
1305		.hw.init = &(struct clk_init_data){
1306			.name = "gcc_periph_noc_usb20_ahb_clk",
1307			.parent_names = (const char *[]){ "usb20_master_clk_src" },
1308			.num_parents = 1,
1309			.flags = CLK_SET_RATE_PARENT,
1310			.ops = &clk_branch2_ops,
1311		},
1312	},
1313};
1314
1315static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1316	.halt_reg = 0x9008,
1317	.clkr = {
1318		.enable_reg = 0x9008,
1319		.enable_mask = BIT(0),
1320		.hw.init = &(struct clk_init_data){
1321			.name = "gcc_mmss_noc_cfg_ahb_clk",
1322			.parent_names = (const char *[]){ "config_noc_clk_src" },
1323			.num_parents = 1,
1324			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1325			.ops = &clk_branch2_ops,
1326		},
1327	},
1328};
1329
1330static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1331	.halt_reg = 0x9010,
1332	.clkr = {
1333		.enable_reg = 0x9010,
1334		.enable_mask = BIT(0),
1335		.hw.init = &(struct clk_init_data){
1336			.name = "gcc_mmss_bimc_gfx_clk",
1337			.flags = CLK_SET_RATE_PARENT,
1338			.ops = &clk_branch2_ops,
1339		},
1340	},
1341};
1342
1343static struct clk_branch gcc_usb30_master_clk = {
1344	.halt_reg = 0x0f008,
1345	.clkr = {
1346		.enable_reg = 0x0f008,
1347		.enable_mask = BIT(0),
1348		.hw.init = &(struct clk_init_data){
1349			.name = "gcc_usb30_master_clk",
1350			.parent_names = (const char *[]){ "usb30_master_clk_src" },
1351			.num_parents = 1,
1352			.flags = CLK_SET_RATE_PARENT,
1353			.ops = &clk_branch2_ops,
1354		},
1355	},
1356};
1357
1358static struct clk_branch gcc_usb30_sleep_clk = {
1359	.halt_reg = 0x0f00c,
1360	.clkr = {
1361		.enable_reg = 0x0f00c,
1362		.enable_mask = BIT(0),
1363		.hw.init = &(struct clk_init_data){
1364			.name = "gcc_usb30_sleep_clk",
1365			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1366			.num_parents = 1,
1367			.flags = CLK_SET_RATE_PARENT,
1368			.ops = &clk_branch2_ops,
1369		},
1370	},
1371};
1372
1373static struct clk_branch gcc_usb30_mock_utmi_clk = {
1374	.halt_reg = 0x0f010,
1375	.clkr = {
1376		.enable_reg = 0x0f010,
1377		.enable_mask = BIT(0),
1378		.hw.init = &(struct clk_init_data){
1379			.name = "gcc_usb30_mock_utmi_clk",
1380			.parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1381			.num_parents = 1,
1382			.flags = CLK_SET_RATE_PARENT,
1383			.ops = &clk_branch2_ops,
1384		},
1385	},
1386};
1387
1388static struct clk_branch gcc_usb3_phy_aux_clk = {
1389	.halt_reg = 0x50000,
1390	.clkr = {
1391		.enable_reg = 0x50000,
1392		.enable_mask = BIT(0),
1393		.hw.init = &(struct clk_init_data){
1394			.name = "gcc_usb3_phy_aux_clk",
1395			.parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1396			.num_parents = 1,
1397			.flags = CLK_SET_RATE_PARENT,
1398			.ops = &clk_branch2_ops,
1399		},
1400	},
1401};
1402
1403static struct clk_branch gcc_usb3_phy_pipe_clk = {
1404	.halt_reg = 0x50004,
1405	.halt_check = BRANCH_HALT_SKIP,
1406	.clkr = {
1407		.enable_reg = 0x50004,
1408		.enable_mask = BIT(0),
1409		.hw.init = &(struct clk_init_data){
1410			.name = "gcc_usb3_phy_pipe_clk",
1411			.parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1412			.num_parents = 1,
1413			.flags = CLK_SET_RATE_PARENT,
1414			.ops = &clk_branch2_ops,
1415		},
1416	},
1417};
1418
1419static struct clk_branch gcc_usb20_master_clk = {
1420	.halt_reg = 0x12004,
1421	.clkr = {
1422		.enable_reg = 0x12004,
1423		.enable_mask = BIT(0),
1424		.hw.init = &(struct clk_init_data){
1425			.name = "gcc_usb20_master_clk",
1426			.parent_names = (const char *[]){ "usb20_master_clk_src" },
1427			.num_parents = 1,
1428			.flags = CLK_SET_RATE_PARENT,
1429			.ops = &clk_branch2_ops,
1430		},
1431	},
1432};
1433
1434static struct clk_branch gcc_usb20_sleep_clk = {
1435	.halt_reg = 0x12008,
1436	.clkr = {
1437		.enable_reg = 0x12008,
1438		.enable_mask = BIT(0),
1439		.hw.init = &(struct clk_init_data){
1440			.name = "gcc_usb20_sleep_clk",
1441			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1442			.num_parents = 1,
1443			.flags = CLK_SET_RATE_PARENT,
1444			.ops = &clk_branch2_ops,
1445		},
1446	},
1447};
1448
1449static struct clk_branch gcc_usb20_mock_utmi_clk = {
1450	.halt_reg = 0x1200c,
1451	.clkr = {
1452		.enable_reg = 0x1200c,
1453		.enable_mask = BIT(0),
1454		.hw.init = &(struct clk_init_data){
1455			.name = "gcc_usb20_mock_utmi_clk",
1456			.parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1457			.num_parents = 1,
1458			.flags = CLK_SET_RATE_PARENT,
1459			.ops = &clk_branch2_ops,
1460		},
1461	},
1462};
1463
1464static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1465	.halt_reg = 0x6a004,
1466	.clkr = {
1467		.enable_reg = 0x6a004,
1468		.enable_mask = BIT(0),
1469		.hw.init = &(struct clk_init_data){
1470			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
1471			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1472			.num_parents = 1,
1473			.flags = CLK_SET_RATE_PARENT,
1474			.ops = &clk_branch2_ops,
1475		},
1476	},
1477};
1478
1479static struct clk_branch gcc_sdcc1_apps_clk = {
1480	.halt_reg = 0x13004,
1481	.clkr = {
1482		.enable_reg = 0x13004,
1483		.enable_mask = BIT(0),
1484		.hw.init = &(struct clk_init_data){
1485			.name = "gcc_sdcc1_apps_clk",
1486			.parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1487			.num_parents = 1,
1488			.flags = CLK_SET_RATE_PARENT,
1489			.ops = &clk_branch2_ops,
1490		},
1491	},
1492};
1493
1494static struct clk_branch gcc_sdcc1_ahb_clk = {
1495	.halt_reg = 0x13008,
1496	.clkr = {
1497		.enable_reg = 0x13008,
1498		.enable_mask = BIT(0),
1499		.hw.init = &(struct clk_init_data){
1500			.name = "gcc_sdcc1_ahb_clk",
1501			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1502			.num_parents = 1,
1503			.flags = CLK_SET_RATE_PARENT,
1504			.ops = &clk_branch2_ops,
1505		},
1506	},
1507};
1508
1509static struct clk_branch gcc_sdcc1_ice_core_clk = {
1510	.halt_reg = 0x13038,
1511	.clkr = {
1512		.enable_reg = 0x13038,
1513		.enable_mask = BIT(0),
1514		.hw.init = &(struct clk_init_data){
1515			.name = "gcc_sdcc1_ice_core_clk",
1516			.parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1517			.num_parents = 1,
1518			.flags = CLK_SET_RATE_PARENT,
1519			.ops = &clk_branch2_ops,
1520		},
1521	},
1522};
1523
1524static struct clk_branch gcc_sdcc2_apps_clk = {
1525	.halt_reg = 0x14004,
1526	.clkr = {
1527		.enable_reg = 0x14004,
1528		.enable_mask = BIT(0),
1529		.hw.init = &(struct clk_init_data){
1530			.name = "gcc_sdcc2_apps_clk",
1531			.parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1532			.num_parents = 1,
1533			.flags = CLK_SET_RATE_PARENT,
1534			.ops = &clk_branch2_ops,
1535		},
1536	},
1537};
1538
1539static struct clk_branch gcc_sdcc2_ahb_clk = {
1540	.halt_reg = 0x14008,
1541	.clkr = {
1542		.enable_reg = 0x14008,
1543		.enable_mask = BIT(0),
1544		.hw.init = &(struct clk_init_data){
1545			.name = "gcc_sdcc2_ahb_clk",
1546			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1547			.num_parents = 1,
1548			.flags = CLK_SET_RATE_PARENT,
1549			.ops = &clk_branch2_ops,
1550		},
1551	},
1552};
1553
1554static struct clk_branch gcc_sdcc3_apps_clk = {
1555	.halt_reg = 0x15004,
1556	.clkr = {
1557		.enable_reg = 0x15004,
1558		.enable_mask = BIT(0),
1559		.hw.init = &(struct clk_init_data){
1560			.name = "gcc_sdcc3_apps_clk",
1561			.parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1562			.num_parents = 1,
1563			.flags = CLK_SET_RATE_PARENT,
1564			.ops = &clk_branch2_ops,
1565		},
1566	},
1567};
1568
1569static struct clk_branch gcc_sdcc3_ahb_clk = {
1570	.halt_reg = 0x15008,
1571	.clkr = {
1572		.enable_reg = 0x15008,
1573		.enable_mask = BIT(0),
1574		.hw.init = &(struct clk_init_data){
1575			.name = "gcc_sdcc3_ahb_clk",
1576			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1577			.num_parents = 1,
1578			.flags = CLK_SET_RATE_PARENT,
1579			.ops = &clk_branch2_ops,
1580		},
1581	},
1582};
1583
1584static struct clk_branch gcc_sdcc4_apps_clk = {
1585	.halt_reg = 0x16004,
1586	.clkr = {
1587		.enable_reg = 0x16004,
1588		.enable_mask = BIT(0),
1589		.hw.init = &(struct clk_init_data){
1590			.name = "gcc_sdcc4_apps_clk",
1591			.parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1592			.num_parents = 1,
1593			.flags = CLK_SET_RATE_PARENT,
1594			.ops = &clk_branch2_ops,
1595		},
1596	},
1597};
1598
1599static struct clk_branch gcc_sdcc4_ahb_clk = {
1600	.halt_reg = 0x16008,
1601	.clkr = {
1602		.enable_reg = 0x16008,
1603		.enable_mask = BIT(0),
1604		.hw.init = &(struct clk_init_data){
1605			.name = "gcc_sdcc4_ahb_clk",
1606			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1607			.num_parents = 1,
1608			.flags = CLK_SET_RATE_PARENT,
1609			.ops = &clk_branch2_ops,
1610		},
1611	},
1612};
1613
1614static struct clk_branch gcc_blsp1_ahb_clk = {
1615	.halt_reg = 0x17004,
1616	.halt_check = BRANCH_HALT_VOTED,
1617	.clkr = {
1618		.enable_reg = 0x52004,
1619		.enable_mask = BIT(17),
1620		.hw.init = &(struct clk_init_data){
1621			.name = "gcc_blsp1_ahb_clk",
1622			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1623			.num_parents = 1,
1624			.flags = CLK_SET_RATE_PARENT,
1625			.ops = &clk_branch2_ops,
1626		},
1627	},
1628};
1629
1630static struct clk_branch gcc_blsp1_sleep_clk = {
1631	.halt_reg = 0x17008,
1632	.halt_check = BRANCH_HALT_VOTED,
1633	.clkr = {
1634		.enable_reg = 0x52004,
1635		.enable_mask = BIT(16),
1636		.hw.init = &(struct clk_init_data){
1637			.name = "gcc_blsp1_sleep_clk",
1638			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1639			.num_parents = 1,
1640			.flags = CLK_SET_RATE_PARENT,
1641			.ops = &clk_branch2_ops,
1642		},
1643	},
1644};
1645
1646static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1647	.halt_reg = 0x19004,
1648	.clkr = {
1649		.enable_reg = 0x19004,
1650		.enable_mask = BIT(0),
1651		.hw.init = &(struct clk_init_data){
1652			.name = "gcc_blsp1_qup1_spi_apps_clk",
1653			.parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1654			.num_parents = 1,
1655			.flags = CLK_SET_RATE_PARENT,
1656			.ops = &clk_branch2_ops,
1657		},
1658	},
1659};
1660
1661static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1662	.halt_reg = 0x19008,
1663	.clkr = {
1664		.enable_reg = 0x19008,
1665		.enable_mask = BIT(0),
1666		.hw.init = &(struct clk_init_data){
1667			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1668			.parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1669			.num_parents = 1,
1670			.flags = CLK_SET_RATE_PARENT,
1671			.ops = &clk_branch2_ops,
1672		},
1673	},
1674};
1675
1676static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1677	.halt_reg = 0x1a004,
1678	.clkr = {
1679		.enable_reg = 0x1a004,
1680		.enable_mask = BIT(0),
1681		.hw.init = &(struct clk_init_data){
1682			.name = "gcc_blsp1_uart1_apps_clk",
1683			.parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1684			.num_parents = 1,
1685			.flags = CLK_SET_RATE_PARENT,
1686			.ops = &clk_branch2_ops,
1687		},
1688	},
1689};
1690
1691static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1692	.halt_reg = 0x1b004,
1693	.clkr = {
1694		.enable_reg = 0x1b004,
1695		.enable_mask = BIT(0),
1696		.hw.init = &(struct clk_init_data){
1697			.name = "gcc_blsp1_qup2_spi_apps_clk",
1698			.parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1699			.num_parents = 1,
1700			.flags = CLK_SET_RATE_PARENT,
1701			.ops = &clk_branch2_ops,
1702		},
1703	},
1704};
1705
1706static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1707	.halt_reg = 0x1b008,
1708	.clkr = {
1709		.enable_reg = 0x1b008,
1710		.enable_mask = BIT(0),
1711		.hw.init = &(struct clk_init_data){
1712			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1713			.parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1714			.num_parents = 1,
1715			.flags = CLK_SET_RATE_PARENT,
1716			.ops = &clk_branch2_ops,
1717		},
1718	},
1719};
1720
1721static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1722	.halt_reg = 0x1c004,
1723	.clkr = {
1724		.enable_reg = 0x1c004,
1725		.enable_mask = BIT(0),
1726		.hw.init = &(struct clk_init_data){
1727			.name = "gcc_blsp1_uart2_apps_clk",
1728			.parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1729			.num_parents = 1,
1730			.flags = CLK_SET_RATE_PARENT,
1731			.ops = &clk_branch2_ops,
1732		},
1733	},
1734};
1735
1736static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1737	.halt_reg = 0x1d004,
1738	.clkr = {
1739		.enable_reg = 0x1d004,
1740		.enable_mask = BIT(0),
1741		.hw.init = &(struct clk_init_data){
1742			.name = "gcc_blsp1_qup3_spi_apps_clk",
1743			.parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1744			.num_parents = 1,
1745			.flags = CLK_SET_RATE_PARENT,
1746			.ops = &clk_branch2_ops,
1747		},
1748	},
1749};
1750
1751static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1752	.halt_reg = 0x1d008,
1753	.clkr = {
1754		.enable_reg = 0x1d008,
1755		.enable_mask = BIT(0),
1756		.hw.init = &(struct clk_init_data){
1757			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1758			.parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1759			.num_parents = 1,
1760			.flags = CLK_SET_RATE_PARENT,
1761			.ops = &clk_branch2_ops,
1762		},
1763	},
1764};
1765
1766static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1767	.halt_reg = 0x1e004,
1768	.clkr = {
1769		.enable_reg = 0x1e004,
1770		.enable_mask = BIT(0),
1771		.hw.init = &(struct clk_init_data){
1772			.name = "gcc_blsp1_uart3_apps_clk",
1773			.parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1774			.num_parents = 1,
1775			.flags = CLK_SET_RATE_PARENT,
1776			.ops = &clk_branch2_ops,
1777		},
1778	},
1779};
1780
1781static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1782	.halt_reg = 0x1f004,
1783	.clkr = {
1784		.enable_reg = 0x1f004,
1785		.enable_mask = BIT(0),
1786		.hw.init = &(struct clk_init_data){
1787			.name = "gcc_blsp1_qup4_spi_apps_clk",
1788			.parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1789			.num_parents = 1,
1790			.flags = CLK_SET_RATE_PARENT,
1791			.ops = &clk_branch2_ops,
1792		},
1793	},
1794};
1795
1796static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1797	.halt_reg = 0x1f008,
1798	.clkr = {
1799		.enable_reg = 0x1f008,
1800		.enable_mask = BIT(0),
1801		.hw.init = &(struct clk_init_data){
1802			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1803			.parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1804			.num_parents = 1,
1805			.flags = CLK_SET_RATE_PARENT,
1806			.ops = &clk_branch2_ops,
1807		},
1808	},
1809};
1810
1811static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1812	.halt_reg = 0x20004,
1813	.clkr = {
1814		.enable_reg = 0x20004,
1815		.enable_mask = BIT(0),
1816		.hw.init = &(struct clk_init_data){
1817			.name = "gcc_blsp1_uart4_apps_clk",
1818			.parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1819			.num_parents = 1,
1820			.flags = CLK_SET_RATE_PARENT,
1821			.ops = &clk_branch2_ops,
1822		},
1823	},
1824};
1825
1826static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1827	.halt_reg = 0x21004,
1828	.clkr = {
1829		.enable_reg = 0x21004,
1830		.enable_mask = BIT(0),
1831		.hw.init = &(struct clk_init_data){
1832			.name = "gcc_blsp1_qup5_spi_apps_clk",
1833			.parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1834			.num_parents = 1,
1835			.flags = CLK_SET_RATE_PARENT,
1836			.ops = &clk_branch2_ops,
1837		},
1838	},
1839};
1840
1841static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1842	.halt_reg = 0x21008,
1843	.clkr = {
1844		.enable_reg = 0x21008,
1845		.enable_mask = BIT(0),
1846		.hw.init = &(struct clk_init_data){
1847			.name = "gcc_blsp1_qup5_i2c_apps_clk",
1848			.parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1849			.num_parents = 1,
1850			.flags = CLK_SET_RATE_PARENT,
1851			.ops = &clk_branch2_ops,
1852		},
1853	},
1854};
1855
1856static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1857	.halt_reg = 0x22004,
1858	.clkr = {
1859		.enable_reg = 0x22004,
1860		.enable_mask = BIT(0),
1861		.hw.init = &(struct clk_init_data){
1862			.name = "gcc_blsp1_uart5_apps_clk",
1863			.parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1864			.num_parents = 1,
1865			.flags = CLK_SET_RATE_PARENT,
1866			.ops = &clk_branch2_ops,
1867		},
1868	},
1869};
1870
1871static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1872	.halt_reg = 0x23004,
1873	.clkr = {
1874		.enable_reg = 0x23004,
1875		.enable_mask = BIT(0),
1876		.hw.init = &(struct clk_init_data){
1877			.name = "gcc_blsp1_qup6_spi_apps_clk",
1878			.parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1879			.num_parents = 1,
1880			.flags = CLK_SET_RATE_PARENT,
1881			.ops = &clk_branch2_ops,
1882		},
1883	},
1884};
1885
1886static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1887	.halt_reg = 0x23008,
1888	.clkr = {
1889		.enable_reg = 0x23008,
1890		.enable_mask = BIT(0),
1891		.hw.init = &(struct clk_init_data){
1892			.name = "gcc_blsp1_qup6_i2c_apps_clk",
1893			.parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1894			.num_parents = 1,
1895			.flags = CLK_SET_RATE_PARENT,
1896			.ops = &clk_branch2_ops,
1897		},
1898	},
1899};
1900
1901static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1902	.halt_reg = 0x24004,
1903	.clkr = {
1904		.enable_reg = 0x24004,
1905		.enable_mask = BIT(0),
1906		.hw.init = &(struct clk_init_data){
1907			.name = "gcc_blsp1_uart6_apps_clk",
1908			.parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1909			.num_parents = 1,
1910			.flags = CLK_SET_RATE_PARENT,
1911			.ops = &clk_branch2_ops,
1912		},
1913	},
1914};
1915
1916static struct clk_branch gcc_blsp2_ahb_clk = {
1917	.halt_reg = 0x25004,
1918	.halt_check = BRANCH_HALT_VOTED,
1919	.clkr = {
1920		.enable_reg = 0x52004,
1921		.enable_mask = BIT(15),
1922		.hw.init = &(struct clk_init_data){
1923			.name = "gcc_blsp2_ahb_clk",
1924			.parent_names = (const char *[]){ "periph_noc_clk_src" },
1925			.num_parents = 1,
1926			.flags = CLK_SET_RATE_PARENT,
1927			.ops = &clk_branch2_ops,
1928		},
1929	},
1930};
1931
1932static struct clk_branch gcc_blsp2_sleep_clk = {
1933	.halt_reg = 0x25008,
1934	.halt_check = BRANCH_HALT_VOTED,
1935	.clkr = {
1936		.enable_reg = 0x52004,
1937		.enable_mask = BIT(14),
1938		.hw.init = &(struct clk_init_data){
1939			.name = "gcc_blsp2_sleep_clk",
1940			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1941			.num_parents = 1,
1942			.flags = CLK_SET_RATE_PARENT,
1943			.ops = &clk_branch2_ops,
1944		},
1945	},
1946};
1947
1948static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1949	.halt_reg = 0x26004,
1950	.clkr = {
1951		.enable_reg = 0x26004,
1952		.enable_mask = BIT(0),
1953		.hw.init = &(struct clk_init_data){
1954			.name = "gcc_blsp2_qup1_spi_apps_clk",
1955			.parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1956			.num_parents = 1,
1957			.flags = CLK_SET_RATE_PARENT,
1958			.ops = &clk_branch2_ops,
1959		},
1960	},
1961};
1962
1963static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1964	.halt_reg = 0x26008,
1965	.clkr = {
1966		.enable_reg = 0x26008,
1967		.enable_mask = BIT(0),
1968		.hw.init = &(struct clk_init_data){
1969			.name = "gcc_blsp2_qup1_i2c_apps_clk",
1970			.parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1971			.num_parents = 1,
1972			.flags = CLK_SET_RATE_PARENT,
1973			.ops = &clk_branch2_ops,
1974		},
1975	},
1976};
1977
1978static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1979	.halt_reg = 0x27004,
1980	.clkr = {
1981		.enable_reg = 0x27004,
1982		.enable_mask = BIT(0),
1983		.hw.init = &(struct clk_init_data){
1984			.name = "gcc_blsp2_uart1_apps_clk",
1985			.parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1986			.num_parents = 1,
1987			.flags = CLK_SET_RATE_PARENT,
1988			.ops = &clk_branch2_ops,
1989		},
1990	},
1991};
1992
1993static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1994	.halt_reg = 0x28004,
1995	.clkr = {
1996		.enable_reg = 0x28004,
1997		.enable_mask = BIT(0),
1998		.hw.init = &(struct clk_init_data){
1999			.name = "gcc_blsp2_qup2_spi_apps_clk",
2000			.parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
2001			.num_parents = 1,
2002			.flags = CLK_SET_RATE_PARENT,
2003			.ops = &clk_branch2_ops,
2004		},
2005	},
2006};
2007
2008static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2009	.halt_reg = 0x28008,
2010	.clkr = {
2011		.enable_reg = 0x28008,
2012		.enable_mask = BIT(0),
2013		.hw.init = &(struct clk_init_data){
2014			.name = "gcc_blsp2_qup2_i2c_apps_clk",
2015			.parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2016			.num_parents = 1,
2017			.flags = CLK_SET_RATE_PARENT,
2018			.ops = &clk_branch2_ops,
2019		},
2020	},
2021};
2022
2023static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2024	.halt_reg = 0x29004,
2025	.clkr = {
2026		.enable_reg = 0x29004,
2027		.enable_mask = BIT(0),
2028		.hw.init = &(struct clk_init_data){
2029			.name = "gcc_blsp2_uart2_apps_clk",
2030			.parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2031			.num_parents = 1,
2032			.flags = CLK_SET_RATE_PARENT,
2033			.ops = &clk_branch2_ops,
2034		},
2035	},
2036};
2037
2038static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2039	.halt_reg = 0x2a004,
2040	.clkr = {
2041		.enable_reg = 0x2a004,
2042		.enable_mask = BIT(0),
2043		.hw.init = &(struct clk_init_data){
2044			.name = "gcc_blsp2_qup3_spi_apps_clk",
2045			.parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2046			.num_parents = 1,
2047			.flags = CLK_SET_RATE_PARENT,
2048			.ops = &clk_branch2_ops,
2049		},
2050	},
2051};
2052
2053static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2054	.halt_reg = 0x2a008,
2055	.clkr = {
2056		.enable_reg = 0x2a008,
2057		.enable_mask = BIT(0),
2058		.hw.init = &(struct clk_init_data){
2059			.name = "gcc_blsp2_qup3_i2c_apps_clk",
2060			.parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2061			.num_parents = 1,
2062			.flags = CLK_SET_RATE_PARENT,
2063			.ops = &clk_branch2_ops,
2064		},
2065	},
2066};
2067
2068static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2069	.halt_reg = 0x2b004,
2070	.clkr = {
2071		.enable_reg = 0x2b004,
2072		.enable_mask = BIT(0),
2073		.hw.init = &(struct clk_init_data){
2074			.name = "gcc_blsp2_uart3_apps_clk",
2075			.parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2076			.num_parents = 1,
2077			.flags = CLK_SET_RATE_PARENT,
2078			.ops = &clk_branch2_ops,
2079		},
2080	},
2081};
2082
2083static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2084	.halt_reg = 0x2c004,
2085	.clkr = {
2086		.enable_reg = 0x2c004,
2087		.enable_mask = BIT(0),
2088		.hw.init = &(struct clk_init_data){
2089			.name = "gcc_blsp2_qup4_spi_apps_clk",
2090			.parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2091			.num_parents = 1,
2092			.flags = CLK_SET_RATE_PARENT,
2093			.ops = &clk_branch2_ops,
2094		},
2095	},
2096};
2097
2098static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2099	.halt_reg = 0x2c008,
2100	.clkr = {
2101		.enable_reg = 0x2c008,
2102		.enable_mask = BIT(0),
2103		.hw.init = &(struct clk_init_data){
2104			.name = "gcc_blsp2_qup4_i2c_apps_clk",
2105			.parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2106			.num_parents = 1,
2107			.flags = CLK_SET_RATE_PARENT,
2108			.ops = &clk_branch2_ops,
2109		},
2110	},
2111};
2112
2113static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2114	.halt_reg = 0x2d004,
2115	.clkr = {
2116		.enable_reg = 0x2d004,
2117		.enable_mask = BIT(0),
2118		.hw.init = &(struct clk_init_data){
2119			.name = "gcc_blsp2_uart4_apps_clk",
2120			.parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2121			.num_parents = 1,
2122			.flags = CLK_SET_RATE_PARENT,
2123			.ops = &clk_branch2_ops,
2124		},
2125	},
2126};
2127
2128static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2129	.halt_reg = 0x2e004,
2130	.clkr = {
2131		.enable_reg = 0x2e004,
2132		.enable_mask = BIT(0),
2133		.hw.init = &(struct clk_init_data){
2134			.name = "gcc_blsp2_qup5_spi_apps_clk",
2135			.parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2136			.num_parents = 1,
2137			.flags = CLK_SET_RATE_PARENT,
2138			.ops = &clk_branch2_ops,
2139		},
2140	},
2141};
2142
2143static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2144	.halt_reg = 0x2e008,
2145	.clkr = {
2146		.enable_reg = 0x2e008,
2147		.enable_mask = BIT(0),
2148		.hw.init = &(struct clk_init_data){
2149			.name = "gcc_blsp2_qup5_i2c_apps_clk",
2150			.parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2151			.num_parents = 1,
2152			.flags = CLK_SET_RATE_PARENT,
2153			.ops = &clk_branch2_ops,
2154		},
2155	},
2156};
2157
2158static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2159	.halt_reg = 0x2f004,
2160	.clkr = {
2161		.enable_reg = 0x2f004,
2162		.enable_mask = BIT(0),
2163		.hw.init = &(struct clk_init_data){
2164			.name = "gcc_blsp2_uart5_apps_clk",
2165			.parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2166			.num_parents = 1,
2167			.flags = CLK_SET_RATE_PARENT,
2168			.ops = &clk_branch2_ops,
2169		},
2170	},
2171};
2172
2173static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2174	.halt_reg = 0x30004,
2175	.clkr = {
2176		.enable_reg = 0x30004,
2177		.enable_mask = BIT(0),
2178		.hw.init = &(struct clk_init_data){
2179			.name = "gcc_blsp2_qup6_spi_apps_clk",
2180			.parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2181			.num_parents = 1,
2182			.flags = CLK_SET_RATE_PARENT,
2183			.ops = &clk_branch2_ops,
2184		},
2185	},
2186};
2187
2188static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2189	.halt_reg = 0x30008,
2190	.clkr = {
2191		.enable_reg = 0x30008,
2192		.enable_mask = BIT(0),
2193		.hw.init = &(struct clk_init_data){
2194			.name = "gcc_blsp2_qup6_i2c_apps_clk",
2195			.parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2196			.num_parents = 1,
2197			.flags = CLK_SET_RATE_PARENT,
2198			.ops = &clk_branch2_ops,
2199		},
2200	},
2201};
2202
2203static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2204	.halt_reg = 0x31004,
2205	.clkr = {
2206		.enable_reg = 0x31004,
2207		.enable_mask = BIT(0),
2208		.hw.init = &(struct clk_init_data){
2209			.name = "gcc_blsp2_uart6_apps_clk",
2210			.parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2211			.num_parents = 1,
2212			.flags = CLK_SET_RATE_PARENT,
2213			.ops = &clk_branch2_ops,
2214		},
2215	},
2216};
2217
2218static struct clk_branch gcc_pdm_ahb_clk = {
2219	.halt_reg = 0x33004,
2220	.clkr = {
2221		.enable_reg = 0x33004,
2222		.enable_mask = BIT(0),
2223		.hw.init = &(struct clk_init_data){
2224			.name = "gcc_pdm_ahb_clk",
2225			.parent_names = (const char *[]){ "periph_noc_clk_src" },
2226			.num_parents = 1,
2227			.flags = CLK_SET_RATE_PARENT,
2228			.ops = &clk_branch2_ops,
2229		},
2230	},
2231};
2232
2233static struct clk_branch gcc_pdm2_clk = {
2234	.halt_reg = 0x3300c,
2235	.clkr = {
2236		.enable_reg = 0x3300c,
2237		.enable_mask = BIT(0),
2238		.hw.init = &(struct clk_init_data){
2239			.name = "gcc_pdm2_clk",
2240			.parent_names = (const char *[]){ "pdm2_clk_src" },
2241			.num_parents = 1,
2242			.flags = CLK_SET_RATE_PARENT,
2243			.ops = &clk_branch2_ops,
2244		},
2245	},
2246};
2247
2248static struct clk_branch gcc_prng_ahb_clk = {
2249	.halt_reg = 0x34004,
2250	.halt_check = BRANCH_HALT_VOTED,
2251	.clkr = {
2252		.enable_reg = 0x52004,
2253		.enable_mask = BIT(13),
2254		.hw.init = &(struct clk_init_data){
2255			.name = "gcc_prng_ahb_clk",
2256			.parent_names = (const char *[]){ "config_noc_clk_src" },
2257			.num_parents = 1,
2258			.flags = CLK_SET_RATE_PARENT,
2259			.ops = &clk_branch2_ops,
2260		},
2261	},
2262};
2263
2264static struct clk_branch gcc_tsif_ahb_clk = {
2265	.halt_reg = 0x36004,
2266	.clkr = {
2267		.enable_reg = 0x36004,
2268		.enable_mask = BIT(0),
2269		.hw.init = &(struct clk_init_data){
2270			.name = "gcc_tsif_ahb_clk",
2271			.parent_names = (const char *[]){ "periph_noc_clk_src" },
2272			.num_parents = 1,
2273			.flags = CLK_SET_RATE_PARENT,
2274			.ops = &clk_branch2_ops,
2275		},
2276	},
2277};
2278
2279static struct clk_branch gcc_tsif_ref_clk = {
2280	.halt_reg = 0x36008,
2281	.clkr = {
2282		.enable_reg = 0x36008,
2283		.enable_mask = BIT(0),
2284		.hw.init = &(struct clk_init_data){
2285			.name = "gcc_tsif_ref_clk",
2286			.parent_names = (const char *[]){ "tsif_ref_clk_src" },
2287			.num_parents = 1,
2288			.flags = CLK_SET_RATE_PARENT,
2289			.ops = &clk_branch2_ops,
2290		},
2291	},
2292};
2293
2294static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2295	.halt_reg = 0x3600c,
2296	.clkr = {
2297		.enable_reg = 0x3600c,
2298		.enable_mask = BIT(0),
2299		.hw.init = &(struct clk_init_data){
2300			.name = "gcc_tsif_inactivity_timers_clk",
2301			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2302			.num_parents = 1,
2303			.flags = CLK_SET_RATE_PARENT,
2304			.ops = &clk_branch2_ops,
2305		},
2306	},
2307};
2308
2309static struct clk_branch gcc_boot_rom_ahb_clk = {
2310	.halt_reg = 0x38004,
2311	.halt_check = BRANCH_HALT_VOTED,
2312	.clkr = {
2313		.enable_reg = 0x52004,
2314		.enable_mask = BIT(10),
2315		.hw.init = &(struct clk_init_data){
2316			.name = "gcc_boot_rom_ahb_clk",
2317			.parent_names = (const char *[]){ "config_noc_clk_src" },
2318			.num_parents = 1,
2319			.flags = CLK_SET_RATE_PARENT,
2320			.ops = &clk_branch2_ops,
2321		},
2322	},
2323};
2324
2325static struct clk_branch gcc_bimc_gfx_clk = {
2326	.halt_reg = 0x46018,
2327	.clkr = {
2328		.enable_reg = 0x46018,
2329		.enable_mask = BIT(0),
2330		.hw.init = &(struct clk_init_data){
2331			.name = "gcc_bimc_gfx_clk",
2332			.flags = CLK_SET_RATE_PARENT,
2333			.ops = &clk_branch2_ops,
2334		},
2335	},
2336};
2337
2338static struct clk_branch gcc_hmss_rbcpr_clk = {
2339	.halt_reg = 0x4800c,
2340	.clkr = {
2341		.enable_reg = 0x4800c,
2342		.enable_mask = BIT(0),
2343		.hw.init = &(struct clk_init_data){
2344			.name = "gcc_hmss_rbcpr_clk",
2345			.parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2346			.num_parents = 1,
2347			.flags = CLK_SET_RATE_PARENT,
2348			.ops = &clk_branch2_ops,
2349		},
2350	},
2351};
2352
2353static struct clk_branch gcc_gp1_clk = {
2354	.halt_reg = 0x64000,
2355	.clkr = {
2356		.enable_reg = 0x64000,
2357		.enable_mask = BIT(0),
2358		.hw.init = &(struct clk_init_data){
2359			.name = "gcc_gp1_clk",
2360			.parent_names = (const char *[]){ "gp1_clk_src" },
2361			.num_parents = 1,
2362			.flags = CLK_SET_RATE_PARENT,
2363			.ops = &clk_branch2_ops,
2364		},
2365	},
2366};
2367
2368static struct clk_branch gcc_gp2_clk = {
2369	.halt_reg = 0x65000,
2370	.clkr = {
2371		.enable_reg = 0x65000,
2372		.enable_mask = BIT(0),
2373		.hw.init = &(struct clk_init_data){
2374			.name = "gcc_gp2_clk",
2375			.parent_names = (const char *[]){ "gp2_clk_src" },
2376			.num_parents = 1,
2377			.flags = CLK_SET_RATE_PARENT,
2378			.ops = &clk_branch2_ops,
2379		},
2380	},
2381};
2382
2383static struct clk_branch gcc_gp3_clk = {
2384	.halt_reg = 0x66000,
2385	.clkr = {
2386		.enable_reg = 0x66000,
2387		.enable_mask = BIT(0),
2388		.hw.init = &(struct clk_init_data){
2389			.name = "gcc_gp3_clk",
2390			.parent_names = (const char *[]){ "gp3_clk_src" },
2391			.num_parents = 1,
2392			.flags = CLK_SET_RATE_PARENT,
2393			.ops = &clk_branch2_ops,
2394		},
2395	},
2396};
2397
2398static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2399	.halt_reg = 0x6b008,
2400	.clkr = {
2401		.enable_reg = 0x6b008,
2402		.enable_mask = BIT(0),
2403		.hw.init = &(struct clk_init_data){
2404			.name = "gcc_pcie_0_slv_axi_clk",
2405			.parent_names = (const char *[]){ "system_noc_clk_src" },
2406			.num_parents = 1,
2407			.flags = CLK_SET_RATE_PARENT,
2408			.ops = &clk_branch2_ops,
2409		},
2410	},
2411};
2412
2413static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2414	.halt_reg = 0x6b00c,
2415	.clkr = {
2416		.enable_reg = 0x6b00c,
2417		.enable_mask = BIT(0),
2418		.hw.init = &(struct clk_init_data){
2419			.name = "gcc_pcie_0_mstr_axi_clk",
2420			.parent_names = (const char *[]){ "system_noc_clk_src" },
2421			.num_parents = 1,
2422			.flags = CLK_SET_RATE_PARENT,
2423			.ops = &clk_branch2_ops,
2424		},
2425	},
2426};
2427
2428static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2429	.halt_reg = 0x6b010,
2430	.clkr = {
2431		.enable_reg = 0x6b010,
2432		.enable_mask = BIT(0),
2433		.hw.init = &(struct clk_init_data){
2434			.name = "gcc_pcie_0_cfg_ahb_clk",
2435			.parent_names = (const char *[]){ "config_noc_clk_src" },
2436			.num_parents = 1,
2437			.flags = CLK_SET_RATE_PARENT,
2438			.ops = &clk_branch2_ops,
2439		},
2440	},
2441};
2442
2443static struct clk_branch gcc_pcie_0_aux_clk = {
2444	.halt_reg = 0x6b014,
2445	.clkr = {
2446		.enable_reg = 0x6b014,
2447		.enable_mask = BIT(0),
2448		.hw.init = &(struct clk_init_data){
2449			.name = "gcc_pcie_0_aux_clk",
2450			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
2451			.num_parents = 1,
2452			.flags = CLK_SET_RATE_PARENT,
2453			.ops = &clk_branch2_ops,
2454		},
2455	},
2456};
2457
2458static struct clk_branch gcc_pcie_0_pipe_clk = {
2459	.halt_reg = 0x6b018,
2460	.halt_check = BRANCH_HALT_SKIP,
2461	.clkr = {
2462		.enable_reg = 0x6b018,
2463		.enable_mask = BIT(0),
2464		.hw.init = &(struct clk_init_data){
2465			.name = "gcc_pcie_0_pipe_clk",
2466			.parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2467			.num_parents = 1,
2468			.flags = CLK_SET_RATE_PARENT,
2469			.ops = &clk_branch2_ops,
2470		},
2471	},
2472};
2473
2474static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2475	.halt_reg = 0x6d008,
2476	.clkr = {
2477		.enable_reg = 0x6d008,
2478		.enable_mask = BIT(0),
2479		.hw.init = &(struct clk_init_data){
2480			.name = "gcc_pcie_1_slv_axi_clk",
2481			.parent_names = (const char *[]){ "system_noc_clk_src" },
2482			.num_parents = 1,
2483			.flags = CLK_SET_RATE_PARENT,
2484			.ops = &clk_branch2_ops,
2485		},
2486	},
2487};
2488
2489static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2490	.halt_reg = 0x6d00c,
2491	.clkr = {
2492		.enable_reg = 0x6d00c,
2493		.enable_mask = BIT(0),
2494		.hw.init = &(struct clk_init_data){
2495			.name = "gcc_pcie_1_mstr_axi_clk",
2496			.parent_names = (const char *[]){ "system_noc_clk_src" },
2497			.num_parents = 1,
2498			.flags = CLK_SET_RATE_PARENT,
2499			.ops = &clk_branch2_ops,
2500		},
2501	},
2502};
2503
2504static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2505	.halt_reg = 0x6d010,
2506	.clkr = {
2507		.enable_reg = 0x6d010,
2508		.enable_mask = BIT(0),
2509		.hw.init = &(struct clk_init_data){
2510			.name = "gcc_pcie_1_cfg_ahb_clk",
2511			.parent_names = (const char *[]){ "config_noc_clk_src" },
2512			.num_parents = 1,
2513			.flags = CLK_SET_RATE_PARENT,
2514			.ops = &clk_branch2_ops,
2515		},
2516	},
2517};
2518
2519static struct clk_branch gcc_pcie_1_aux_clk = {
2520	.halt_reg = 0x6d014,
2521	.clkr = {
2522		.enable_reg = 0x6d014,
2523		.enable_mask = BIT(0),
2524		.hw.init = &(struct clk_init_data){
2525			.name = "gcc_pcie_1_aux_clk",
2526			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
2527			.num_parents = 1,
2528			.flags = CLK_SET_RATE_PARENT,
2529			.ops = &clk_branch2_ops,
2530		},
2531	},
2532};
2533
2534static struct clk_branch gcc_pcie_1_pipe_clk = {
2535	.halt_reg = 0x6d018,
2536	.halt_check = BRANCH_HALT_SKIP,
2537	.clkr = {
2538		.enable_reg = 0x6d018,
2539		.enable_mask = BIT(0),
2540		.hw.init = &(struct clk_init_data){
2541			.name = "gcc_pcie_1_pipe_clk",
2542			.parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2543			.num_parents = 1,
2544			.flags = CLK_SET_RATE_PARENT,
2545			.ops = &clk_branch2_ops,
2546		},
2547	},
2548};
2549
2550static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2551	.halt_reg = 0x6e008,
2552	.clkr = {
2553		.enable_reg = 0x6e008,
2554		.enable_mask = BIT(0),
2555		.hw.init = &(struct clk_init_data){
2556			.name = "gcc_pcie_2_slv_axi_clk",
2557			.parent_names = (const char *[]){ "system_noc_clk_src" },
2558			.num_parents = 1,
2559			.flags = CLK_SET_RATE_PARENT,
2560			.ops = &clk_branch2_ops,
2561		},
2562	},
2563};
2564
2565static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2566	.halt_reg = 0x6e00c,
2567	.clkr = {
2568		.enable_reg = 0x6e00c,
2569		.enable_mask = BIT(0),
2570		.hw.init = &(struct clk_init_data){
2571			.name = "gcc_pcie_2_mstr_axi_clk",
2572			.parent_names = (const char *[]){ "system_noc_clk_src" },
2573			.num_parents = 1,
2574			.flags = CLK_SET_RATE_PARENT,
2575			.ops = &clk_branch2_ops,
2576		},
2577	},
2578};
2579
2580static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2581	.halt_reg = 0x6e010,
2582	.clkr = {
2583		.enable_reg = 0x6e010,
2584		.enable_mask = BIT(0),
2585		.hw.init = &(struct clk_init_data){
2586			.name = "gcc_pcie_2_cfg_ahb_clk",
2587			.parent_names = (const char *[]){ "config_noc_clk_src" },
2588			.num_parents = 1,
2589			.flags = CLK_SET_RATE_PARENT,
2590			.ops = &clk_branch2_ops,
2591		},
2592	},
2593};
2594
2595static struct clk_branch gcc_pcie_2_aux_clk = {
2596	.halt_reg = 0x6e014,
2597	.clkr = {
2598		.enable_reg = 0x6e014,
2599		.enable_mask = BIT(0),
2600		.hw.init = &(struct clk_init_data){
2601			.name = "gcc_pcie_2_aux_clk",
2602			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
2603			.num_parents = 1,
2604			.flags = CLK_SET_RATE_PARENT,
2605			.ops = &clk_branch2_ops,
2606		},
2607	},
2608};
2609
2610static struct clk_branch gcc_pcie_2_pipe_clk = {
2611	.halt_reg = 0x6e018,
2612	.halt_check = BRANCH_HALT_SKIP,
2613	.clkr = {
2614		.enable_reg = 0x6e018,
2615		.enable_mask = BIT(0),
2616		.hw.init = &(struct clk_init_data){
2617			.name = "gcc_pcie_2_pipe_clk",
2618			.parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2619			.num_parents = 1,
2620			.flags = CLK_SET_RATE_PARENT,
2621			.ops = &clk_branch2_ops,
2622		},
2623	},
2624};
2625
2626static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2627	.halt_reg = 0x6f004,
2628	.clkr = {
2629		.enable_reg = 0x6f004,
2630		.enable_mask = BIT(0),
2631		.hw.init = &(struct clk_init_data){
2632			.name = "gcc_pcie_phy_cfg_ahb_clk",
2633			.parent_names = (const char *[]){ "config_noc_clk_src" },
2634			.num_parents = 1,
2635			.flags = CLK_SET_RATE_PARENT,
2636			.ops = &clk_branch2_ops,
2637		},
2638	},
2639};
2640
2641static struct clk_branch gcc_pcie_phy_aux_clk = {
2642	.halt_reg = 0x6f008,
2643	.clkr = {
2644		.enable_reg = 0x6f008,
2645		.enable_mask = BIT(0),
2646		.hw.init = &(struct clk_init_data){
2647			.name = "gcc_pcie_phy_aux_clk",
2648			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
2649			.num_parents = 1,
2650			.flags = CLK_SET_RATE_PARENT,
2651			.ops = &clk_branch2_ops,
2652		},
2653	},
2654};
2655
2656static struct clk_branch gcc_ufs_axi_clk = {
2657	.halt_reg = 0x75008,
2658	.clkr = {
2659		.enable_reg = 0x75008,
2660		.enable_mask = BIT(0),
2661		.hw.init = &(struct clk_init_data){
2662			.name = "gcc_ufs_axi_clk",
2663			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
2664			.num_parents = 1,
2665			.flags = CLK_SET_RATE_PARENT,
2666			.ops = &clk_branch2_ops,
2667		},
2668	},
2669};
2670
2671static struct clk_branch gcc_ufs_ahb_clk = {
2672	.halt_reg = 0x7500c,
2673	.clkr = {
2674		.enable_reg = 0x7500c,
2675		.enable_mask = BIT(0),
2676		.hw.init = &(struct clk_init_data){
2677			.name = "gcc_ufs_ahb_clk",
2678			.parent_names = (const char *[]){ "config_noc_clk_src" },
2679			.num_parents = 1,
2680			.flags = CLK_SET_RATE_PARENT,
2681			.ops = &clk_branch2_ops,
2682		},
2683	},
2684};
2685
2686static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2687	.mult = 1,
2688	.div = 16,
2689	.hw.init = &(struct clk_init_data){
2690		.name = "ufs_tx_cfg_clk_src",
2691		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
2692		.num_parents = 1,
2693		.flags = CLK_SET_RATE_PARENT,
2694		.ops = &clk_fixed_factor_ops,
2695	},
2696};
2697
2698static struct clk_branch gcc_ufs_tx_cfg_clk = {
2699	.halt_reg = 0x75010,
2700	.clkr = {
2701		.enable_reg = 0x75010,
2702		.enable_mask = BIT(0),
2703		.hw.init = &(struct clk_init_data){
2704			.name = "gcc_ufs_tx_cfg_clk",
2705			.parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2706			.num_parents = 1,
2707			.flags = CLK_SET_RATE_PARENT,
2708			.ops = &clk_branch2_ops,
2709		},
2710	},
2711};
2712
2713static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2714	.mult = 1,
2715	.div = 16,
2716	.hw.init = &(struct clk_init_data){
2717		.name = "ufs_rx_cfg_clk_src",
2718		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
2719		.num_parents = 1,
2720		.flags = CLK_SET_RATE_PARENT,
2721		.ops = &clk_fixed_factor_ops,
2722	},
2723};
2724
2725static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2726	.halt_reg = 0x7d010,
2727	.halt_check = BRANCH_HALT_VOTED,
2728	.clkr = {
2729		.enable_reg = 0x7d010,
2730		.enable_mask = BIT(0),
2731		.hw.init = &(struct clk_init_data){
2732			.name = "hlos1_vote_lpass_core_smmu_clk",
2733			.ops = &clk_branch2_ops,
2734		},
2735	},
2736};
2737
2738static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2739	.halt_reg = 0x7d014,
2740	.halt_check = BRANCH_HALT_VOTED,
2741	.clkr = {
2742		.enable_reg = 0x7d014,
2743		.enable_mask = BIT(0),
2744		.hw.init = &(struct clk_init_data){
2745			.name = "hlos1_vote_lpass_adsp_smmu_clk",
2746			.ops = &clk_branch2_ops,
2747		},
2748	},
2749};
2750
2751static struct clk_branch gcc_ufs_rx_cfg_clk = {
2752	.halt_reg = 0x75014,
2753	.clkr = {
2754		.enable_reg = 0x75014,
2755		.enable_mask = BIT(0),
2756		.hw.init = &(struct clk_init_data){
2757			.name = "gcc_ufs_rx_cfg_clk",
2758			.parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2759			.num_parents = 1,
2760			.flags = CLK_SET_RATE_PARENT,
2761			.ops = &clk_branch2_ops,
2762		},
2763	},
2764};
2765
2766static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2767	.halt_reg = 0x75018,
2768	.halt_check = BRANCH_HALT_SKIP,
2769	.clkr = {
2770		.enable_reg = 0x75018,
2771		.enable_mask = BIT(0),
2772		.hw.init = &(struct clk_init_data){
2773			.name = "gcc_ufs_tx_symbol_0_clk",
2774			.parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2775			.num_parents = 1,
2776			.flags = CLK_SET_RATE_PARENT,
2777			.ops = &clk_branch2_ops,
2778		},
2779	},
2780};
2781
2782static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2783	.halt_reg = 0x7501c,
2784	.halt_check = BRANCH_HALT_SKIP,
2785	.clkr = {
2786		.enable_reg = 0x7501c,
2787		.enable_mask = BIT(0),
2788		.hw.init = &(struct clk_init_data){
2789			.name = "gcc_ufs_rx_symbol_0_clk",
2790			.parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2791			.num_parents = 1,
2792			.flags = CLK_SET_RATE_PARENT,
2793			.ops = &clk_branch2_ops,
2794		},
2795	},
2796};
2797
2798static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2799	.halt_reg = 0x75020,
2800	.halt_check = BRANCH_HALT_SKIP,
2801	.clkr = {
2802		.enable_reg = 0x75020,
2803		.enable_mask = BIT(0),
2804		.hw.init = &(struct clk_init_data){
2805			.name = "gcc_ufs_rx_symbol_1_clk",
2806			.parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2807			.num_parents = 1,
2808			.flags = CLK_SET_RATE_PARENT,
2809			.ops = &clk_branch2_ops,
2810		},
2811	},
2812};
2813
2814static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2815	.mult = 1,
2816	.div = 2,
2817	.hw.init = &(struct clk_init_data){
2818		.name = "ufs_ice_core_postdiv_clk_src",
2819		.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2820		.num_parents = 1,
2821		.flags = CLK_SET_RATE_PARENT,
2822		.ops = &clk_fixed_factor_ops,
2823	},
2824};
2825
2826static struct clk_branch gcc_ufs_unipro_core_clk = {
2827	.halt_reg = 0x7600c,
2828	.clkr = {
2829		.enable_reg = 0x7600c,
2830		.enable_mask = BIT(0),
2831		.hw.init = &(struct clk_init_data){
2832			.name = "gcc_ufs_unipro_core_clk",
2833			.parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2834			.num_parents = 1,
2835			.flags = CLK_SET_RATE_PARENT,
2836			.ops = &clk_branch2_ops,
2837		},
2838	},
2839};
2840
2841static struct clk_branch gcc_ufs_ice_core_clk = {
2842	.halt_reg = 0x76010,
2843	.clkr = {
2844		.enable_reg = 0x76010,
2845		.enable_mask = BIT(0),
2846		.hw.init = &(struct clk_init_data){
2847			.name = "gcc_ufs_ice_core_clk",
2848			.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2849			.num_parents = 1,
2850			.flags = CLK_SET_RATE_PARENT,
2851			.ops = &clk_branch2_ops,
2852		},
2853	},
2854};
2855
2856static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2857	.halt_check = BRANCH_HALT_DELAY,
2858	.clkr = {
2859		.enable_reg = 0x76030,
2860		.enable_mask = BIT(0),
2861		.hw.init = &(struct clk_init_data){
2862			.name = "gcc_ufs_sys_clk_core_clk",
2863			.ops = &clk_branch2_ops,
2864		},
2865	},
2866};
2867
2868static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2869	.halt_check = BRANCH_HALT_DELAY,
2870	.clkr = {
2871		.enable_reg = 0x76034,
2872		.enable_mask = BIT(0),
2873		.hw.init = &(struct clk_init_data){
2874			.name = "gcc_ufs_tx_symbol_clk_core_clk",
2875			.ops = &clk_branch2_ops,
2876		},
2877	},
2878};
2879
2880static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2881	.halt_reg = 0x81008,
2882	.clkr = {
2883		.enable_reg = 0x81008,
2884		.enable_mask = BIT(0),
2885		.hw.init = &(struct clk_init_data){
2886			.name = "gcc_aggre0_snoc_axi_clk",
2887			.parent_names = (const char *[]){ "system_noc_clk_src" },
2888			.num_parents = 1,
2889			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2890			.ops = &clk_branch2_ops,
2891		},
2892	},
2893};
2894
2895static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2896	.halt_reg = 0x8100c,
2897	.clkr = {
2898		.enable_reg = 0x8100c,
2899		.enable_mask = BIT(0),
2900		.hw.init = &(struct clk_init_data){
2901			.name = "gcc_aggre0_cnoc_ahb_clk",
2902			.parent_names = (const char *[]){ "config_noc_clk_src" },
2903			.num_parents = 1,
2904			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2905			.ops = &clk_branch2_ops,
2906		},
2907	},
2908};
2909
2910static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2911	.halt_reg = 0x81014,
2912	.clkr = {
2913		.enable_reg = 0x81014,
2914		.enable_mask = BIT(0),
2915		.hw.init = &(struct clk_init_data){
2916			.name = "gcc_smmu_aggre0_axi_clk",
2917			.parent_names = (const char *[]){ "system_noc_clk_src" },
2918			.num_parents = 1,
2919			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2920			.ops = &clk_branch2_ops,
2921		},
2922	},
2923};
2924
2925static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2926	.halt_reg = 0x81018,
2927	.clkr = {
2928		.enable_reg = 0x81018,
2929		.enable_mask = BIT(0),
2930		.hw.init = &(struct clk_init_data){
2931			.name = "gcc_smmu_aggre0_ahb_clk",
2932			.parent_names = (const char *[]){ "config_noc_clk_src" },
2933			.num_parents = 1,
2934			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2935			.ops = &clk_branch2_ops,
2936		},
2937	},
2938};
2939
2940static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2941	.halt_reg = 0x82014,
2942	.clkr = {
2943		.enable_reg = 0x82014,
2944		.enable_mask = BIT(0),
2945		.hw.init = &(struct clk_init_data){
2946			.name = "gcc_aggre1_pnoc_ahb_clk",
2947			.parent_names = (const char *[]){ "periph_noc_clk_src" },
2948			.num_parents = 1,
2949			.ops = &clk_branch2_ops,
2950		},
2951	},
2952};
2953
2954static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2955	.halt_reg = 0x83014,
2956	.clkr = {
2957		.enable_reg = 0x83014,
2958		.enable_mask = BIT(0),
2959		.hw.init = &(struct clk_init_data){
2960			.name = "gcc_aggre2_ufs_axi_clk",
2961			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
2962			.num_parents = 1,
2963			.flags = CLK_SET_RATE_PARENT,
2964			.ops = &clk_branch2_ops,
2965		},
2966	},
2967};
2968
2969static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2970	.halt_reg = 0x83018,
2971	.clkr = {
2972		.enable_reg = 0x83018,
2973		.enable_mask = BIT(0),
2974		.hw.init = &(struct clk_init_data){
2975			.name = "gcc_aggre2_usb3_axi_clk",
2976			.parent_names = (const char *[]){ "usb30_master_clk_src" },
2977			.num_parents = 1,
2978			.flags = CLK_SET_RATE_PARENT,
2979			.ops = &clk_branch2_ops,
2980		},
2981	},
2982};
2983
2984static struct clk_branch gcc_dcc_ahb_clk = {
2985	.halt_reg = 0x84004,
2986	.clkr = {
2987		.enable_reg = 0x84004,
2988		.enable_mask = BIT(0),
2989		.hw.init = &(struct clk_init_data){
2990			.name = "gcc_dcc_ahb_clk",
2991			.parent_names = (const char *[]){ "config_noc_clk_src" },
2992			.num_parents = 1,
2993			.ops = &clk_branch2_ops,
2994		},
2995	},
2996};
2997
2998static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
2999	.halt_reg = 0x85000,
3000	.clkr = {
3001		.enable_reg = 0x85000,
3002		.enable_mask = BIT(0),
3003		.hw.init = &(struct clk_init_data){
3004			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
3005			.parent_names = (const char *[]){ "config_noc_clk_src" },
3006			.num_parents = 1,
3007			.ops = &clk_branch2_ops,
3008		},
3009	},
3010};
3011
3012static struct clk_branch gcc_qspi_ahb_clk = {
3013	.halt_reg = 0x8b004,
3014	.clkr = {
3015		.enable_reg = 0x8b004,
3016		.enable_mask = BIT(0),
3017		.hw.init = &(struct clk_init_data){
3018			.name = "gcc_qspi_ahb_clk",
3019			.parent_names = (const char *[]){ "periph_noc_clk_src" },
3020			.num_parents = 1,
3021			.flags = CLK_SET_RATE_PARENT,
3022			.ops = &clk_branch2_ops,
3023		},
3024	},
3025};
3026
3027static struct clk_branch gcc_qspi_ser_clk = {
3028	.halt_reg = 0x8b008,
3029	.clkr = {
3030		.enable_reg = 0x8b008,
3031		.enable_mask = BIT(0),
3032		.hw.init = &(struct clk_init_data){
3033			.name = "gcc_qspi_ser_clk",
3034			.parent_names = (const char *[]){ "qspi_ser_clk_src" },
3035			.num_parents = 1,
3036			.flags = CLK_SET_RATE_PARENT,
3037			.ops = &clk_branch2_ops,
3038		},
3039	},
3040};
3041
3042static struct clk_branch gcc_usb3_clkref_clk = {
3043	.halt_reg = 0x8800C,
3044	.clkr = {
3045		.enable_reg = 0x8800C,
3046		.enable_mask = BIT(0),
3047		.hw.init = &(struct clk_init_data){
3048			.name = "gcc_usb3_clkref_clk",
3049			.parent_data = &(const struct clk_parent_data){
3050				.fw_name = "cxo2",
3051				.name = "xo",
3052			},
3053			.num_parents = 1,
3054			.ops = &clk_branch2_ops,
3055		},
3056	},
3057};
3058
3059static struct clk_branch gcc_hdmi_clkref_clk = {
3060	.halt_reg = 0x88000,
3061	.clkr = {
3062		.enable_reg = 0x88000,
3063		.enable_mask = BIT(0),
3064		.hw.init = &(struct clk_init_data){
3065			.name = "gcc_hdmi_clkref_clk",
3066			.parent_data = &(const struct clk_parent_data){
3067				.fw_name = "cxo2",
3068				.name = "xo",
3069			},
3070			.num_parents = 1,
3071			.ops = &clk_branch2_ops,
3072		},
3073	},
3074};
3075
3076static struct clk_branch gcc_edp_clkref_clk = {
3077	.halt_reg = 0x88004,
3078	.clkr = {
3079		.enable_reg = 0x88004,
3080		.enable_mask = BIT(0),
3081		.hw.init = &(struct clk_init_data){
3082			.name = "gcc_edp_clkref_clk",
3083			.parent_data = &(const struct clk_parent_data){
3084				.fw_name = "cxo2",
3085				.name = "xo",
3086			},
3087			.num_parents = 1,
3088			.ops = &clk_branch2_ops,
3089		},
3090	},
3091};
3092
3093static struct clk_branch gcc_ufs_clkref_clk = {
3094	.halt_reg = 0x88008,
3095	.clkr = {
3096		.enable_reg = 0x88008,
3097		.enable_mask = BIT(0),
3098		.hw.init = &(struct clk_init_data){
3099			.name = "gcc_ufs_clkref_clk",
3100			.parent_data = &(const struct clk_parent_data){
3101				.fw_name = "cxo2",
3102				.name = "xo",
3103			},
3104			.num_parents = 1,
3105			.ops = &clk_branch2_ops,
3106		},
3107	},
3108};
3109
3110static struct clk_branch gcc_pcie_clkref_clk = {
3111	.halt_reg = 0x88010,
3112	.clkr = {
3113		.enable_reg = 0x88010,
3114		.enable_mask = BIT(0),
3115		.hw.init = &(struct clk_init_data){
3116			.name = "gcc_pcie_clkref_clk",
3117			.parent_data = &(const struct clk_parent_data){
3118				.fw_name = "cxo2",
3119				.name = "xo",
3120			},
3121			.num_parents = 1,
3122			.ops = &clk_branch2_ops,
3123		},
3124	},
3125};
3126
3127static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3128	.halt_reg = 0x88014,
3129	.clkr = {
3130		.enable_reg = 0x88014,
3131		.enable_mask = BIT(0),
3132		.hw.init = &(struct clk_init_data){
3133			.name = "gcc_rx2_usb2_clkref_clk",
3134			.parent_data = &(const struct clk_parent_data){
3135				.fw_name = "cxo2",
3136				.name = "xo",
3137			},
3138			.num_parents = 1,
3139			.ops = &clk_branch2_ops,
3140		},
3141	},
3142};
3143
3144static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3145	.halt_reg = 0x88018,
3146	.clkr = {
3147		.enable_reg = 0x88018,
3148		.enable_mask = BIT(0),
3149		.hw.init = &(struct clk_init_data){
3150			.name = "gcc_rx1_usb2_clkref_clk",
3151			.parent_data = &(const struct clk_parent_data){
3152				.fw_name = "cxo2",
3153				.name = "xo",
3154			},
3155			.num_parents = 1,
3156			.ops = &clk_branch2_ops,
3157		},
3158	},
3159};
3160
3161static struct clk_branch gcc_mss_cfg_ahb_clk = {
3162	.halt_reg = 0x8a000,
3163	.clkr = {
3164		.enable_reg = 0x8a000,
3165		.enable_mask = BIT(0),
3166		.hw.init = &(struct clk_init_data){
3167			.name = "gcc_mss_cfg_ahb_clk",
3168			.parent_names = (const char *[]){ "config_noc_clk_src" },
3169			.num_parents = 1,
3170			.ops = &clk_branch2_ops,
3171		},
3172	},
3173};
3174
3175static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
3176	.halt_reg = 0x8a004,
3177	.clkr = {
3178		.enable_reg = 0x8a004,
3179		.enable_mask = BIT(0),
3180		.hw.init = &(struct clk_init_data){
3181			.name = "gcc_mss_mnoc_bimc_axi_clk",
3182			.parent_names = (const char *[]){ "system_noc_clk_src" },
3183			.num_parents = 1,
3184			.ops = &clk_branch2_ops,
3185		},
3186	},
3187};
3188
3189static struct clk_branch gcc_mss_snoc_axi_clk = {
3190	.halt_reg = 0x8a024,
3191	.clkr = {
3192		.enable_reg = 0x8a024,
3193		.enable_mask = BIT(0),
3194		.hw.init = &(struct clk_init_data){
3195			.name = "gcc_mss_snoc_axi_clk",
3196			.parent_names = (const char *[]){ "system_noc_clk_src" },
3197			.num_parents = 1,
3198			.ops = &clk_branch2_ops,
3199		},
3200	},
3201};
3202
3203static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3204	.halt_reg = 0x8a028,
3205	.clkr = {
3206		.enable_reg = 0x8a028,
3207		.enable_mask = BIT(0),
3208		.hw.init = &(struct clk_init_data){
3209			.name = "gcc_mss_q6_bimc_axi_clk",
3210			.parent_names = (const char *[]){ "system_noc_clk_src" },
3211			.num_parents = 1,
3212			.ops = &clk_branch2_ops,
3213		},
3214	},
3215};
3216
3217static struct clk_hw *gcc_msm8996_hws[] = {
3218	&xo.hw,
3219	&gpll0_early_div.hw,
3220	&ufs_tx_cfg_clk_src.hw,
3221	&ufs_rx_cfg_clk_src.hw,
3222	&ufs_ice_core_postdiv_clk_src.hw,
3223};
3224
3225static struct gdsc aggre0_noc_gdsc = {
3226	.gdscr = 0x81004,
3227	.gds_hw_ctrl = 0x81028,
3228	.pd = {
3229		.name = "aggre0_noc",
3230	},
3231	.pwrsts = PWRSTS_OFF_ON,
3232	.flags = VOTABLE | ALWAYS_ON,
3233};
3234
3235static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3236	.gdscr = 0x7d024,
3237	.pd = {
3238		.name = "hlos1_vote_aggre0_noc",
3239	},
3240	.pwrsts = PWRSTS_OFF_ON,
3241	.flags = VOTABLE,
3242};
3243
3244static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3245	.gdscr = 0x7d034,
3246	.pd = {
3247		.name = "hlos1_vote_lpass_adsp",
3248	},
3249	.pwrsts = PWRSTS_OFF_ON,
3250	.flags = VOTABLE,
3251};
3252
3253static struct gdsc hlos1_vote_lpass_core_gdsc = {
3254	.gdscr = 0x7d038,
3255	.pd = {
3256		.name = "hlos1_vote_lpass_core",
3257	},
3258	.pwrsts = PWRSTS_OFF_ON,
3259	.flags = VOTABLE,
3260};
3261
3262static struct gdsc usb30_gdsc = {
3263	.gdscr = 0xf004,
3264	.pd = {
3265		.name = "usb30",
3266	},
3267	.pwrsts = PWRSTS_OFF_ON,
3268};
3269
3270static struct gdsc pcie0_gdsc = {
3271	.gdscr = 0x6b004,
3272	.pd = {
3273		.name = "pcie0",
3274	},
3275	.pwrsts = PWRSTS_OFF_ON,
3276};
3277
3278static struct gdsc pcie1_gdsc = {
3279	.gdscr = 0x6d004,
3280	.pd = {
3281		.name = "pcie1",
3282	},
3283	.pwrsts = PWRSTS_OFF_ON,
3284};
3285
3286static struct gdsc pcie2_gdsc = {
3287	.gdscr = 0x6e004,
3288	.pd = {
3289		.name = "pcie2",
3290	},
3291	.pwrsts = PWRSTS_OFF_ON,
3292};
3293
3294static struct gdsc ufs_gdsc = {
3295	.gdscr = 0x75004,
3296	.pd = {
3297		.name = "ufs",
3298	},
3299	.pwrsts = PWRSTS_OFF_ON,
3300};
3301
3302static struct clk_regmap *gcc_msm8996_clocks[] = {
3303	[GPLL0_EARLY] = &gpll0_early.clkr,
3304	[GPLL0] = &gpll0.clkr,
3305	[GPLL4_EARLY] = &gpll4_early.clkr,
3306	[GPLL4] = &gpll4.clkr,
3307	[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3308	[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3309	[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3310	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3311	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3312	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3313	[USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3314	[USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3315	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3316	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3317	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3318	[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3319	[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3320	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3321	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3322	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3323	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3324	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3325	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3326	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3327	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3328	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3329	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3330	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3331	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3332	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3333	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3334	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3335	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3336	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3337	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3338	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3339	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3340	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3341	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3342	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3343	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3344	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3345	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3346	[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3347	[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3348	[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3349	[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3350	[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3351	[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3352	[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3353	[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3354	[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3355	[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3356	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3357	[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3358	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3359	[HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3360	[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3361	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3362	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3363	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3364	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3365	[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3366	[UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3367	[QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3368	[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3369	[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3370	[GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3371	[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3372	[GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3373	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3374	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3375	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3376	[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3377	[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3378	[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3379	[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3380	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3381	[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3382	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3383	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3384	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3385	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3386	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3387	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3388	[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3389	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3390	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3391	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3392	[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3393	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3394	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3395	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3396	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3397	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3398	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3399	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3400	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3401	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3402	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3403	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3404	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3405	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3406	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3407	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3408	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3409	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3410	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3411	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3412	[GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3413	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3414	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3415	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3416	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3417	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3418	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3419	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3420	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3421	[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3422	[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3423	[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3424	[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3425	[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3426	[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3427	[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3428	[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3429	[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3430	[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3431	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3432	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3433	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3434	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3435	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3436	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3437	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3438	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3439	[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3440	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3441	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3442	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3443	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3444	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3445	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3446	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3447	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3448	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3449	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3450	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3451	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3452	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3453	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3454	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3455	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3456	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3457	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3458	[GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3459	[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3460	[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3461	[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3462	[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3463	[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3464	[GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3465	[GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3466	[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3467	[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3468	[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3469	[GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3470	[GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3471	[GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3472	[GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3473	[GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3474	[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3475	[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3476	[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3477	[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3478	[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3479	[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3480	[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3481	[GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3482	[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3483	[GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3484	[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3485	[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3486	[GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3487	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3488	[GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
3489	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3490	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3491	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3492	[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
3493	[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
3494	[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
3495	[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
3496	[GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
3497};
3498
3499static struct gdsc *gcc_msm8996_gdscs[] = {
3500	[AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3501	[HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3502	[HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3503	[HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3504	[USB30_GDSC] = &usb30_gdsc,
3505	[PCIE0_GDSC] = &pcie0_gdsc,
3506	[PCIE1_GDSC] = &pcie1_gdsc,
3507	[PCIE2_GDSC] = &pcie2_gdsc,
3508	[UFS_GDSC] = &ufs_gdsc,
3509};
3510
3511static const struct qcom_reset_map gcc_msm8996_resets[] = {
3512	[GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3513	[GCC_CONFIG_NOC_BCR] = { 0x5000 },
3514	[GCC_PERIPH_NOC_BCR] = { 0x6000 },
3515	[GCC_IMEM_BCR] = { 0x8000 },
3516	[GCC_MMSS_BCR] = { 0x9000 },
3517	[GCC_PIMEM_BCR] = { 0x0a000 },
3518	[GCC_QDSS_BCR] = { 0x0c000 },
3519	[GCC_USB_30_BCR] = { 0x0f000 },
3520	[GCC_USB_20_BCR] = { 0x12000 },
3521	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3522	[GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3523	[GCC_USB3_PHY_BCR] = { 0x50020 },
3524	[GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3525	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3526	[GCC_SDCC1_BCR] = { 0x13000 },
3527	[GCC_SDCC2_BCR] = { 0x14000 },
3528	[GCC_SDCC3_BCR] = { 0x15000 },
3529	[GCC_SDCC4_BCR] = { 0x16000 },
3530	[GCC_BLSP1_BCR] = { 0x17000 },
3531	[GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3532	[GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3533	[GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3534	[GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3535	[GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3536	[GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3537	[GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3538	[GCC_BLSP1_UART4_BCR] = { 0x20000 },
3539	[GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3540	[GCC_BLSP1_UART5_BCR] = { 0x22000 },
3541	[GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3542	[GCC_BLSP1_UART6_BCR] = { 0x24000 },
3543	[GCC_BLSP2_BCR] = { 0x25000 },
3544	[GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3545	[GCC_BLSP2_UART1_BCR] = { 0x27000 },
3546	[GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3547	[GCC_BLSP2_UART2_BCR] = { 0x29000 },
3548	[GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3549	[GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3550	[GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3551	[GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3552	[GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3553	[GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3554	[GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3555	[GCC_BLSP2_UART6_BCR] = { 0x31000 },
3556	[GCC_PDM_BCR] = { 0x33000 },
3557	[GCC_PRNG_BCR] = { 0x34000 },
3558	[GCC_TSIF_BCR] = { 0x36000 },
3559	[GCC_TCSR_BCR] = { 0x37000 },
3560	[GCC_BOOT_ROM_BCR] = { 0x38000 },
3561	[GCC_MSG_RAM_BCR] = { 0x39000 },
3562	[GCC_TLMM_BCR] = { 0x3a000 },
3563	[GCC_MPM_BCR] = { 0x3b000 },
3564	[GCC_SEC_CTRL_BCR] = { 0x3d000 },
3565	[GCC_SPMI_BCR] = { 0x3f000 },
3566	[GCC_SPDM_BCR] = { 0x40000 },
3567	[GCC_CE1_BCR] = { 0x41000 },
3568	[GCC_BIMC_BCR] = { 0x44000 },
3569	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3570	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3571	[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3572	[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3573	[GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3574	[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3575	[GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3576	[GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3577	[GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3578	[GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3579	[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3580	[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3581	[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3582	[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3583	[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3584	[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3585	[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3586	[GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3587	[GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3588	[GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3589	[GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3590	[GCC_APB2JTAG_BCR] = { 0x4c000 },
3591	[GCC_RBCPR_CX_BCR] = { 0x4e000 },
3592	[GCC_RBCPR_MX_BCR] = { 0x4f000 },
3593	[GCC_PCIE_0_BCR] = { 0x6b000 },
3594	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3595	[GCC_PCIE_1_BCR] = { 0x6d000 },
3596	[GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3597	[GCC_PCIE_2_BCR] = { 0x6e000 },
3598	[GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3599	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
3600	[GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3601	[GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3602	[GCC_DCD_BCR] = { 0x70000 },
3603	[GCC_OBT_ODT_BCR] = { 0x73000 },
3604	[GCC_UFS_BCR] = { 0x75000 },
3605	[GCC_SSC_BCR] = { 0x63000 },
3606	[GCC_VS_BCR] = { 0x7a000 },
3607	[GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3608	[GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3609	[GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3610	[GCC_DCC_BCR] = { 0x84000 },
3611	[GCC_IPA_BCR] = { 0x89000 },
3612	[GCC_QSPI_BCR] = { 0x8b000 },
3613	[GCC_SKL_BCR] = { 0x8c000 },
3614	[GCC_MSMPU_BCR] = { 0x8d000 },
3615	[GCC_MSS_Q6_BCR] = { 0x8e000 },
3616	[GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3617	[GCC_MSS_RESTART] = { 0x8f008 },
3618};
3619
3620static const struct regmap_config gcc_msm8996_regmap_config = {
3621	.reg_bits	= 32,
3622	.reg_stride	= 4,
3623	.val_bits	= 32,
3624	.max_register	= 0x8f010,
3625	.fast_io	= true,
3626};
3627
3628static const struct qcom_cc_desc gcc_msm8996_desc = {
3629	.config = &gcc_msm8996_regmap_config,
3630	.clks = gcc_msm8996_clocks,
3631	.num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3632	.resets = gcc_msm8996_resets,
3633	.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3634	.gdscs = gcc_msm8996_gdscs,
3635	.num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3636	.clk_hws = gcc_msm8996_hws,
3637	.num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
3638};
3639
3640static const struct of_device_id gcc_msm8996_match_table[] = {
3641	{ .compatible = "qcom,gcc-msm8996" },
3642	{ }
3643};
3644MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3645
3646static int gcc_msm8996_probe(struct platform_device *pdev)
3647{
3648	struct regmap *regmap;
3649
3650	regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3651	if (IS_ERR(regmap))
3652		return PTR_ERR(regmap);
3653
3654	/*
3655	 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3656	 * turned off by hardware during certain apps low power modes.
3657	 */
3658	regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3659
3660	return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3661}
3662
3663static struct platform_driver gcc_msm8996_driver = {
3664	.probe		= gcc_msm8996_probe,
3665	.driver		= {
3666		.name	= "gcc-msm8996",
3667		.of_match_table = gcc_msm8996_match_table,
3668	},
3669};
3670
3671static int __init gcc_msm8996_init(void)
3672{
3673	return platform_driver_register(&gcc_msm8996_driver);
3674}
3675core_initcall(gcc_msm8996_init);
3676
3677static void __exit gcc_msm8996_exit(void)
3678{
3679	platform_driver_unregister(&gcc_msm8996_driver);
3680}
3681module_exit(gcc_msm8996_exit);
3682
3683MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3684MODULE_LICENSE("GPL v2");
3685MODULE_ALIAS("platform:gcc-msm8996");