Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 */
4
5#include <linux/kernel.h>
6#include <linux/init.h>
7#include <linux/err.h>
8#include <linux/ctype.h>
9#include <linux/io.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/module.h>
13#include <linux/regmap.h>
14
15#include <dt-bindings/clock/qcom,gcc-msm8994.h>
16
17#include "common.h"
18#include "clk-regmap.h"
19#include "clk-alpha-pll.h"
20#include "clk-rcg.h"
21#include "clk-branch.h"
22#include "reset.h"
23
24enum {
25 P_XO,
26 P_GPLL0,
27 P_GPLL4,
28};
29
30static const struct parent_map gcc_xo_gpll0_map[] = {
31 { P_XO, 0 },
32 { P_GPLL0, 1 },
33};
34
35static const char * const gcc_xo_gpll0[] = {
36 "xo",
37 "gpll0",
38};
39
40static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
41 { P_XO, 0 },
42 { P_GPLL0, 1 },
43 { P_GPLL4, 5 },
44};
45
46static const char * const gcc_xo_gpll0_gpll4[] = {
47 "xo",
48 "gpll0",
49 "gpll4",
50};
51
52static struct clk_fixed_factor xo = {
53 .mult = 1,
54 .div = 1,
55 .hw.init = &(struct clk_init_data)
56 {
57 .name = "xo",
58 .parent_names = (const char *[]) { "xo_board" },
59 .num_parents = 1,
60 .ops = &clk_fixed_factor_ops,
61 },
62};
63
64static struct clk_alpha_pll gpll0_early = {
65 .offset = 0x00000,
66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
67 .clkr = {
68 .enable_reg = 0x1480,
69 .enable_mask = BIT(0),
70 .hw.init = &(struct clk_init_data)
71 {
72 .name = "gpll0_early",
73 .parent_names = (const char *[]) { "xo" },
74 .num_parents = 1,
75 .ops = &clk_alpha_pll_ops,
76 },
77 },
78};
79
80static struct clk_alpha_pll_postdiv gpll0 = {
81 .offset = 0x00000,
82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
83 .clkr.hw.init = &(struct clk_init_data)
84 {
85 .name = "gpll0",
86 .parent_names = (const char *[]) { "gpll0_early" },
87 .num_parents = 1,
88 .ops = &clk_alpha_pll_postdiv_ops,
89 },
90};
91
92static struct clk_alpha_pll gpll4_early = {
93 .offset = 0x1dc0,
94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
95 .clkr = {
96 .enable_reg = 0x1480,
97 .enable_mask = BIT(4),
98 .hw.init = &(struct clk_init_data)
99 {
100 .name = "gpll4_early",
101 .parent_names = (const char *[]) { "xo" },
102 .num_parents = 1,
103 .ops = &clk_alpha_pll_ops,
104 },
105 },
106};
107
108static struct clk_alpha_pll_postdiv gpll4 = {
109 .offset = 0x1dc0,
110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
111 .clkr.hw.init = &(struct clk_init_data)
112 {
113 .name = "gpll4",
114 .parent_names = (const char *[]) { "gpll4_early" },
115 .num_parents = 1,
116 .ops = &clk_alpha_pll_postdiv_ops,
117 },
118};
119
120static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
121 F(50000000, P_GPLL0, 12, 0, 0),
122 F(100000000, P_GPLL0, 6, 0, 0),
123 F(150000000, P_GPLL0, 4, 0, 0),
124 F(171430000, P_GPLL0, 3.5, 0, 0),
125 F(200000000, P_GPLL0, 3, 0, 0),
126 F(240000000, P_GPLL0, 2.5, 0, 0),
127 { }
128};
129
130static struct clk_rcg2 ufs_axi_clk_src = {
131 .cmd_rcgr = 0x1d68,
132 .mnd_width = 8,
133 .hid_width = 5,
134 .parent_map = gcc_xo_gpll0_map,
135 .freq_tbl = ftbl_ufs_axi_clk_src,
136 .clkr.hw.init = &(struct clk_init_data)
137 {
138 .name = "ufs_axi_clk_src",
139 .parent_names = gcc_xo_gpll0,
140 .num_parents = 2,
141 .ops = &clk_rcg2_ops,
142 },
143};
144
145static struct freq_tbl ftbl_usb30_master_clk_src[] = {
146 F(19200000, P_XO, 1, 0, 0),
147 F(125000000, P_GPLL0, 1, 5, 24),
148 { }
149};
150
151static struct clk_rcg2 usb30_master_clk_src = {
152 .cmd_rcgr = 0x03d4,
153 .mnd_width = 8,
154 .hid_width = 5,
155 .parent_map = gcc_xo_gpll0_map,
156 .freq_tbl = ftbl_usb30_master_clk_src,
157 .clkr.hw.init = &(struct clk_init_data)
158 {
159 .name = "usb30_master_clk_src",
160 .parent_names = gcc_xo_gpll0,
161 .num_parents = 2,
162 .ops = &clk_rcg2_ops,
163 },
164};
165
166static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
167 F(19200000, P_XO, 1, 0, 0),
168 F(50000000, P_GPLL0, 12, 0, 0),
169 { }
170};
171
172static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
173 .cmd_rcgr = 0x0660,
174 .hid_width = 5,
175 .parent_map = gcc_xo_gpll0_map,
176 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
177 .clkr.hw.init = &(struct clk_init_data)
178 {
179 .name = "blsp1_qup1_i2c_apps_clk_src",
180 .parent_names = gcc_xo_gpll0,
181 .num_parents = 2,
182 .ops = &clk_rcg2_ops,
183 },
184};
185
186static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
187 F(960000, P_XO, 10, 1, 2),
188 F(4800000, P_XO, 4, 0, 0),
189 F(9600000, P_XO, 2, 0, 0),
190 F(15000000, P_GPLL0, 10, 1, 4),
191 F(19200000, P_XO, 1, 0, 0),
192 F(24000000, P_GPLL0, 12.5, 1, 2),
193 F(25000000, P_GPLL0, 12, 1, 2),
194 F(48000000, P_GPLL0, 12.5, 0, 0),
195 F(50000000, P_GPLL0, 12, 0, 0),
196 { }
197};
198
199static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
200 .cmd_rcgr = 0x064c,
201 .mnd_width = 8,
202 .hid_width = 5,
203 .parent_map = gcc_xo_gpll0_map,
204 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
205 .clkr.hw.init = &(struct clk_init_data)
206 {
207 .name = "blsp1_qup1_spi_apps_clk_src",
208 .parent_names = gcc_xo_gpll0,
209 .num_parents = 2,
210 .ops = &clk_rcg2_ops,
211 },
212};
213
214static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
215 .cmd_rcgr = 0x06e0,
216 .hid_width = 5,
217 .parent_map = gcc_xo_gpll0_map,
218 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
219 .clkr.hw.init = &(struct clk_init_data)
220 {
221 .name = "blsp1_qup2_i2c_apps_clk_src",
222 .parent_names = gcc_xo_gpll0,
223 .num_parents = 2,
224 .ops = &clk_rcg2_ops,
225 },
226};
227
228static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
229 .cmd_rcgr = 0x06cc,
230 .mnd_width = 8,
231 .hid_width = 5,
232 .parent_map = gcc_xo_gpll0_map,
233 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
234 .clkr.hw.init = &(struct clk_init_data)
235 {
236 .name = "blsp1_qup2_spi_apps_clk_src",
237 .parent_names = gcc_xo_gpll0,
238 .num_parents = 2,
239 .ops = &clk_rcg2_ops,
240 },
241};
242
243static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
244 .cmd_rcgr = 0x0760,
245 .hid_width = 5,
246 .parent_map = gcc_xo_gpll0_map,
247 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
248 .clkr.hw.init = &(struct clk_init_data)
249 {
250 .name = "blsp1_qup3_i2c_apps_clk_src",
251 .parent_names = gcc_xo_gpll0,
252 .num_parents = 2,
253 .ops = &clk_rcg2_ops,
254 },
255};
256
257static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
258 .cmd_rcgr = 0x074c,
259 .mnd_width = 8,
260 .hid_width = 5,
261 .parent_map = gcc_xo_gpll0_map,
262 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
263 .clkr.hw.init = &(struct clk_init_data)
264 {
265 .name = "blsp1_qup3_spi_apps_clk_src",
266 .parent_names = gcc_xo_gpll0,
267 .num_parents = 2,
268 .ops = &clk_rcg2_ops,
269 },
270};
271
272static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
273 .cmd_rcgr = 0x07e0,
274 .hid_width = 5,
275 .parent_map = gcc_xo_gpll0_map,
276 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
277 .clkr.hw.init = &(struct clk_init_data)
278 {
279 .name = "blsp1_qup4_i2c_apps_clk_src",
280 .parent_names = gcc_xo_gpll0,
281 .num_parents = 2,
282 .ops = &clk_rcg2_ops,
283 },
284};
285
286static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
287 .cmd_rcgr = 0x07cc,
288 .mnd_width = 8,
289 .hid_width = 5,
290 .parent_map = gcc_xo_gpll0_map,
291 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
292 .clkr.hw.init = &(struct clk_init_data)
293 {
294 .name = "blsp1_qup4_spi_apps_clk_src",
295 .parent_names = gcc_xo_gpll0,
296 .num_parents = 2,
297 .ops = &clk_rcg2_ops,
298 },
299};
300
301static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
302 .cmd_rcgr = 0x0860,
303 .hid_width = 5,
304 .parent_map = gcc_xo_gpll0_map,
305 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
306 .clkr.hw.init = &(struct clk_init_data)
307 {
308 .name = "blsp1_qup5_i2c_apps_clk_src",
309 .parent_names = gcc_xo_gpll0,
310 .num_parents = 2,
311 .ops = &clk_rcg2_ops,
312 },
313};
314
315static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
316 .cmd_rcgr = 0x084c,
317 .mnd_width = 8,
318 .hid_width = 5,
319 .parent_map = gcc_xo_gpll0_map,
320 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
321 .clkr.hw.init = &(struct clk_init_data)
322 {
323 .name = "blsp1_qup5_spi_apps_clk_src",
324 .parent_names = gcc_xo_gpll0,
325 .num_parents = 2,
326 .ops = &clk_rcg2_ops,
327 },
328};
329
330static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
331 .cmd_rcgr = 0x08e0,
332 .hid_width = 5,
333 .parent_map = gcc_xo_gpll0_map,
334 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
335 .clkr.hw.init = &(struct clk_init_data)
336 {
337 .name = "blsp1_qup6_i2c_apps_clk_src",
338 .parent_names = gcc_xo_gpll0,
339 .num_parents = 2,
340 .ops = &clk_rcg2_ops,
341 },
342};
343
344static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
345 .cmd_rcgr = 0x08cc,
346 .mnd_width = 8,
347 .hid_width = 5,
348 .parent_map = gcc_xo_gpll0_map,
349 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
350 .clkr.hw.init = &(struct clk_init_data)
351 {
352 .name = "blsp1_qup6_spi_apps_clk_src",
353 .parent_names = gcc_xo_gpll0,
354 .num_parents = 2,
355 .ops = &clk_rcg2_ops,
356 },
357};
358
359static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
360 F(3686400, P_GPLL0, 1, 96, 15625),
361 F(7372800, P_GPLL0, 1, 192, 15625),
362 F(14745600, P_GPLL0, 1, 384, 15625),
363 F(16000000, P_GPLL0, 5, 2, 15),
364 F(19200000, P_XO, 1, 0, 0),
365 F(24000000, P_GPLL0, 5, 1, 5),
366 F(32000000, P_GPLL0, 1, 4, 75),
367 F(40000000, P_GPLL0, 15, 0, 0),
368 F(46400000, P_GPLL0, 1, 29, 375),
369 F(48000000, P_GPLL0, 12.5, 0, 0),
370 F(51200000, P_GPLL0, 1, 32, 375),
371 F(56000000, P_GPLL0, 1, 7, 75),
372 F(58982400, P_GPLL0, 1, 1536, 15625),
373 F(60000000, P_GPLL0, 10, 0, 0),
374 F(63160000, P_GPLL0, 9.5, 0, 0),
375 { }
376};
377
378static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
379 .cmd_rcgr = 0x068c,
380 .mnd_width = 16,
381 .hid_width = 5,
382 .parent_map = gcc_xo_gpll0_map,
383 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
384 .clkr.hw.init = &(struct clk_init_data)
385 {
386 .name = "blsp1_uart1_apps_clk_src",
387 .parent_names = gcc_xo_gpll0,
388 .num_parents = 2,
389 .ops = &clk_rcg2_ops,
390 },
391};
392
393static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
394 .cmd_rcgr = 0x070c,
395 .mnd_width = 16,
396 .hid_width = 5,
397 .parent_map = gcc_xo_gpll0_map,
398 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
399 .clkr.hw.init = &(struct clk_init_data)
400 {
401 .name = "blsp1_uart2_apps_clk_src",
402 .parent_names = gcc_xo_gpll0,
403 .num_parents = 2,
404 .ops = &clk_rcg2_ops,
405 },
406};
407
408static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
409 .cmd_rcgr = 0x078c,
410 .mnd_width = 16,
411 .hid_width = 5,
412 .parent_map = gcc_xo_gpll0_map,
413 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
414 .clkr.hw.init = &(struct clk_init_data)
415 {
416 .name = "blsp1_uart3_apps_clk_src",
417 .parent_names = gcc_xo_gpll0,
418 .num_parents = 2,
419 .ops = &clk_rcg2_ops,
420 },
421};
422
423static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
424 .cmd_rcgr = 0x080c,
425 .mnd_width = 16,
426 .hid_width = 5,
427 .parent_map = gcc_xo_gpll0_map,
428 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
429 .clkr.hw.init = &(struct clk_init_data)
430 {
431 .name = "blsp1_uart4_apps_clk_src",
432 .parent_names = gcc_xo_gpll0,
433 .num_parents = 2,
434 .ops = &clk_rcg2_ops,
435 },
436};
437
438static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
439 .cmd_rcgr = 0x088c,
440 .mnd_width = 16,
441 .hid_width = 5,
442 .parent_map = gcc_xo_gpll0_map,
443 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
444 .clkr.hw.init = &(struct clk_init_data)
445 {
446 .name = "blsp1_uart5_apps_clk_src",
447 .parent_names = gcc_xo_gpll0,
448 .num_parents = 2,
449 .ops = &clk_rcg2_ops,
450 },
451};
452
453static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
454 .cmd_rcgr = 0x090c,
455 .mnd_width = 16,
456 .hid_width = 5,
457 .parent_map = gcc_xo_gpll0_map,
458 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
459 .clkr.hw.init = &(struct clk_init_data)
460 {
461 .name = "blsp1_uart6_apps_clk_src",
462 .parent_names = gcc_xo_gpll0,
463 .num_parents = 2,
464 .ops = &clk_rcg2_ops,
465 },
466};
467
468static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
469 .cmd_rcgr = 0x09a0,
470 .hid_width = 5,
471 .parent_map = gcc_xo_gpll0_map,
472 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
473 .clkr.hw.init = &(struct clk_init_data)
474 {
475 .name = "blsp2_qup1_i2c_apps_clk_src",
476 .parent_names = gcc_xo_gpll0,
477 .num_parents = 2,
478 .ops = &clk_rcg2_ops,
479 },
480};
481
482static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
483 .cmd_rcgr = 0x098c,
484 .mnd_width = 8,
485 .hid_width = 5,
486 .parent_map = gcc_xo_gpll0_map,
487 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
488 .clkr.hw.init = &(struct clk_init_data)
489 {
490 .name = "blsp2_qup1_spi_apps_clk_src",
491 .parent_names = gcc_xo_gpll0,
492 .num_parents = 2,
493 .ops = &clk_rcg2_ops,
494 },
495};
496
497static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
498 .cmd_rcgr = 0x0a20,
499 .hid_width = 5,
500 .parent_map = gcc_xo_gpll0_map,
501 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
502 .clkr.hw.init = &(struct clk_init_data)
503 {
504 .name = "blsp2_qup2_i2c_apps_clk_src",
505 .parent_names = gcc_xo_gpll0,
506 .num_parents = 2,
507 .ops = &clk_rcg2_ops,
508 },
509};
510
511static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
512 .cmd_rcgr = 0x0a0c,
513 .mnd_width = 8,
514 .hid_width = 5,
515 .parent_map = gcc_xo_gpll0_map,
516 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
517 .clkr.hw.init = &(struct clk_init_data)
518 {
519 .name = "blsp2_qup2_spi_apps_clk_src",
520 .parent_names = gcc_xo_gpll0,
521 .num_parents = 2,
522 .ops = &clk_rcg2_ops,
523 },
524};
525
526static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
527 .cmd_rcgr = 0x0aa0,
528 .hid_width = 5,
529 .parent_map = gcc_xo_gpll0_map,
530 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
531 .clkr.hw.init = &(struct clk_init_data)
532 {
533 .name = "blsp2_qup3_i2c_apps_clk_src",
534 .parent_names = gcc_xo_gpll0,
535 .num_parents = 2,
536 .ops = &clk_rcg2_ops,
537 },
538};
539
540static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
541 .cmd_rcgr = 0x0a8c,
542 .mnd_width = 8,
543 .hid_width = 5,
544 .parent_map = gcc_xo_gpll0_map,
545 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
546 .clkr.hw.init = &(struct clk_init_data)
547 {
548 .name = "blsp2_qup3_spi_apps_clk_src",
549 .parent_names = gcc_xo_gpll0,
550 .num_parents = 2,
551 .ops = &clk_rcg2_ops,
552 },
553};
554
555static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
556 .cmd_rcgr = 0x0b20,
557 .hid_width = 5,
558 .parent_map = gcc_xo_gpll0_map,
559 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
560 .clkr.hw.init = &(struct clk_init_data)
561 {
562 .name = "blsp2_qup4_i2c_apps_clk_src",
563 .parent_names = gcc_xo_gpll0,
564 .num_parents = 2,
565 .ops = &clk_rcg2_ops,
566 },
567};
568
569static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
570 .cmd_rcgr = 0x0b0c,
571 .mnd_width = 8,
572 .hid_width = 5,
573 .parent_map = gcc_xo_gpll0_map,
574 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
575 .clkr.hw.init = &(struct clk_init_data)
576 {
577 .name = "blsp2_qup4_spi_apps_clk_src",
578 .parent_names = gcc_xo_gpll0,
579 .num_parents = 2,
580 .ops = &clk_rcg2_ops,
581 },
582};
583
584static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
585 .cmd_rcgr = 0x0ba0,
586 .hid_width = 5,
587 .parent_map = gcc_xo_gpll0_map,
588 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
589 .clkr.hw.init = &(struct clk_init_data)
590 {
591 .name = "blsp2_qup5_i2c_apps_clk_src",
592 .parent_names = gcc_xo_gpll0,
593 .num_parents = 2,
594 .ops = &clk_rcg2_ops,
595 },
596};
597
598static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
599 .cmd_rcgr = 0x0b8c,
600 .mnd_width = 8,
601 .hid_width = 5,
602 .parent_map = gcc_xo_gpll0_map,
603 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
604 .clkr.hw.init = &(struct clk_init_data)
605 {
606 .name = "blsp2_qup5_spi_apps_clk_src",
607 .parent_names = gcc_xo_gpll0,
608 .num_parents = 2,
609 .ops = &clk_rcg2_ops,
610 },
611};
612
613static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
614 .cmd_rcgr = 0x0c20,
615 .hid_width = 5,
616 .parent_map = gcc_xo_gpll0_map,
617 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
618 .clkr.hw.init = &(struct clk_init_data)
619 {
620 .name = "blsp2_qup6_i2c_apps_clk_src",
621 .parent_names = gcc_xo_gpll0,
622 .num_parents = 2,
623 .ops = &clk_rcg2_ops,
624 },
625};
626
627static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
628 .cmd_rcgr = 0x0c0c,
629 .mnd_width = 8,
630 .hid_width = 5,
631 .parent_map = gcc_xo_gpll0_map,
632 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
633 .clkr.hw.init = &(struct clk_init_data)
634 {
635 .name = "blsp2_qup6_spi_apps_clk_src",
636 .parent_names = gcc_xo_gpll0,
637 .num_parents = 2,
638 .ops = &clk_rcg2_ops,
639 },
640};
641
642static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
643 .cmd_rcgr = 0x09cc,
644 .mnd_width = 16,
645 .hid_width = 5,
646 .parent_map = gcc_xo_gpll0_map,
647 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
648 .clkr.hw.init = &(struct clk_init_data)
649 {
650 .name = "blsp2_uart1_apps_clk_src",
651 .parent_names = gcc_xo_gpll0,
652 .num_parents = 2,
653 .ops = &clk_rcg2_ops,
654 },
655};
656
657static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
658 .cmd_rcgr = 0x0a4c,
659 .mnd_width = 16,
660 .hid_width = 5,
661 .parent_map = gcc_xo_gpll0_map,
662 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
663 .clkr.hw.init = &(struct clk_init_data)
664 {
665 .name = "blsp2_uart2_apps_clk_src",
666 .parent_names = gcc_xo_gpll0,
667 .num_parents = 2,
668 .ops = &clk_rcg2_ops,
669 },
670};
671
672static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
673 .cmd_rcgr = 0x0acc,
674 .mnd_width = 16,
675 .hid_width = 5,
676 .parent_map = gcc_xo_gpll0_map,
677 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
678 .clkr.hw.init = &(struct clk_init_data)
679 {
680 .name = "blsp2_uart3_apps_clk_src",
681 .parent_names = gcc_xo_gpll0,
682 .num_parents = 2,
683 .ops = &clk_rcg2_ops,
684 },
685};
686
687static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
688 .cmd_rcgr = 0x0b4c,
689 .mnd_width = 16,
690 .hid_width = 5,
691 .parent_map = gcc_xo_gpll0_map,
692 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
693 .clkr.hw.init = &(struct clk_init_data)
694 {
695 .name = "blsp2_uart4_apps_clk_src",
696 .parent_names = gcc_xo_gpll0,
697 .num_parents = 2,
698 .ops = &clk_rcg2_ops,
699 },
700};
701
702static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
703 .cmd_rcgr = 0x0bcc,
704 .mnd_width = 16,
705 .hid_width = 5,
706 .parent_map = gcc_xo_gpll0_map,
707 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
708 .clkr.hw.init = &(struct clk_init_data)
709 {
710 .name = "blsp2_uart5_apps_clk_src",
711 .parent_names = gcc_xo_gpll0,
712 .num_parents = 2,
713 .ops = &clk_rcg2_ops,
714 },
715};
716
717static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
718 .cmd_rcgr = 0x0c4c,
719 .mnd_width = 16,
720 .hid_width = 5,
721 .parent_map = gcc_xo_gpll0_map,
722 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
723 .clkr.hw.init = &(struct clk_init_data)
724 {
725 .name = "blsp2_uart6_apps_clk_src",
726 .parent_names = gcc_xo_gpll0,
727 .num_parents = 2,
728 .ops = &clk_rcg2_ops,
729 },
730};
731
732static struct freq_tbl ftbl_gp1_clk_src[] = {
733 F(19200000, P_XO, 1, 0, 0),
734 F(100000000, P_GPLL0, 6, 0, 0),
735 F(200000000, P_GPLL0, 3, 0, 0),
736 { }
737};
738
739static struct clk_rcg2 gp1_clk_src = {
740 .cmd_rcgr = 0x1904,
741 .mnd_width = 8,
742 .hid_width = 5,
743 .parent_map = gcc_xo_gpll0_map,
744 .freq_tbl = ftbl_gp1_clk_src,
745 .clkr.hw.init = &(struct clk_init_data)
746 {
747 .name = "gp1_clk_src",
748 .parent_names = gcc_xo_gpll0,
749 .num_parents = 2,
750 .ops = &clk_rcg2_ops,
751 },
752};
753
754static struct freq_tbl ftbl_gp2_clk_src[] = {
755 F(19200000, P_XO, 1, 0, 0),
756 F(100000000, P_GPLL0, 6, 0, 0),
757 F(200000000, P_GPLL0, 3, 0, 0),
758 { }
759};
760
761static struct clk_rcg2 gp2_clk_src = {
762 .cmd_rcgr = 0x1944,
763 .mnd_width = 8,
764 .hid_width = 5,
765 .parent_map = gcc_xo_gpll0_map,
766 .freq_tbl = ftbl_gp2_clk_src,
767 .clkr.hw.init = &(struct clk_init_data)
768 {
769 .name = "gp2_clk_src",
770 .parent_names = gcc_xo_gpll0,
771 .num_parents = 2,
772 .ops = &clk_rcg2_ops,
773 },
774};
775
776static struct freq_tbl ftbl_gp3_clk_src[] = {
777 F(19200000, P_XO, 1, 0, 0),
778 F(100000000, P_GPLL0, 6, 0, 0),
779 F(200000000, P_GPLL0, 3, 0, 0),
780 { }
781};
782
783static struct clk_rcg2 gp3_clk_src = {
784 .cmd_rcgr = 0x1984,
785 .mnd_width = 8,
786 .hid_width = 5,
787 .parent_map = gcc_xo_gpll0_map,
788 .freq_tbl = ftbl_gp3_clk_src,
789 .clkr.hw.init = &(struct clk_init_data)
790 {
791 .name = "gp3_clk_src",
792 .parent_names = gcc_xo_gpll0,
793 .num_parents = 2,
794 .ops = &clk_rcg2_ops,
795 },
796};
797
798static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
799 F(1011000, P_XO, 1, 1, 19),
800 { }
801};
802
803static struct clk_rcg2 pcie_0_aux_clk_src = {
804 .cmd_rcgr = 0x1b00,
805 .mnd_width = 8,
806 .hid_width = 5,
807 .freq_tbl = ftbl_pcie_0_aux_clk_src,
808 .clkr.hw.init = &(struct clk_init_data)
809 {
810 .name = "pcie_0_aux_clk_src",
811 .parent_names = (const char *[]) { "xo" },
812 .num_parents = 1,
813 .ops = &clk_rcg2_ops,
814 },
815};
816
817static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
818 F(125000000, P_XO, 1, 0, 0),
819 { }
820};
821
822static struct clk_rcg2 pcie_0_pipe_clk_src = {
823 .cmd_rcgr = 0x1adc,
824 .hid_width = 5,
825 .freq_tbl = ftbl_pcie_pipe_clk_src,
826 .clkr.hw.init = &(struct clk_init_data)
827 {
828 .name = "pcie_0_pipe_clk_src",
829 .parent_names = (const char *[]) { "xo" },
830 .num_parents = 1,
831 .ops = &clk_rcg2_ops,
832 },
833};
834
835static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
836 F(1011000, P_XO, 1, 1, 19),
837 { }
838};
839
840static struct clk_rcg2 pcie_1_aux_clk_src = {
841 .cmd_rcgr = 0x1b80,
842 .mnd_width = 8,
843 .hid_width = 5,
844 .freq_tbl = ftbl_pcie_1_aux_clk_src,
845 .clkr.hw.init = &(struct clk_init_data)
846 {
847 .name = "pcie_1_aux_clk_src",
848 .parent_names = (const char *[]) { "xo" },
849 .num_parents = 1,
850 .ops = &clk_rcg2_ops,
851 },
852};
853
854static struct clk_rcg2 pcie_1_pipe_clk_src = {
855 .cmd_rcgr = 0x1b5c,
856 .hid_width = 5,
857 .freq_tbl = ftbl_pcie_pipe_clk_src,
858 .clkr.hw.init = &(struct clk_init_data)
859 {
860 .name = "pcie_1_pipe_clk_src",
861 .parent_names = (const char *[]) { "xo" },
862 .num_parents = 1,
863 .ops = &clk_rcg2_ops,
864 },
865};
866
867static struct freq_tbl ftbl_pdm2_clk_src[] = {
868 F(60000000, P_GPLL0, 10, 0, 0),
869 { }
870};
871
872static struct clk_rcg2 pdm2_clk_src = {
873 .cmd_rcgr = 0x0cd0,
874 .hid_width = 5,
875 .parent_map = gcc_xo_gpll0_map,
876 .freq_tbl = ftbl_pdm2_clk_src,
877 .clkr.hw.init = &(struct clk_init_data)
878 {
879 .name = "pdm2_clk_src",
880 .parent_names = gcc_xo_gpll0,
881 .num_parents = 2,
882 .ops = &clk_rcg2_ops,
883 },
884};
885
886static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
887 F(144000, P_XO, 16, 3, 25),
888 F(400000, P_XO, 12, 1, 4),
889 F(20000000, P_GPLL0, 15, 1, 2),
890 F(25000000, P_GPLL0, 12, 1, 2),
891 F(50000000, P_GPLL0, 12, 0, 0),
892 F(100000000, P_GPLL0, 6, 0, 0),
893 F(192000000, P_GPLL4, 2, 0, 0),
894 F(384000000, P_GPLL4, 1, 0, 0),
895 { }
896};
897
898static struct clk_rcg2 sdcc1_apps_clk_src = {
899 .cmd_rcgr = 0x04d0,
900 .mnd_width = 8,
901 .hid_width = 5,
902 .parent_map = gcc_xo_gpll0_gpll4_map,
903 .freq_tbl = ftbl_sdcc1_apps_clk_src,
904 .clkr.hw.init = &(struct clk_init_data)
905 {
906 .name = "sdcc1_apps_clk_src",
907 .parent_names = gcc_xo_gpll0_gpll4,
908 .num_parents = 3,
909 .ops = &clk_rcg2_floor_ops,
910 },
911};
912
913static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
914 F(144000, P_XO, 16, 3, 25),
915 F(400000, P_XO, 12, 1, 4),
916 F(20000000, P_GPLL0, 15, 1, 2),
917 F(25000000, P_GPLL0, 12, 1, 2),
918 F(50000000, P_GPLL0, 12, 0, 0),
919 F(100000000, P_GPLL0, 6, 0, 0),
920 F(200000000, P_GPLL0, 3, 0, 0),
921 { }
922};
923
924static struct clk_rcg2 sdcc2_apps_clk_src = {
925 .cmd_rcgr = 0x0510,
926 .mnd_width = 8,
927 .hid_width = 5,
928 .parent_map = gcc_xo_gpll0_map,
929 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
930 .clkr.hw.init = &(struct clk_init_data)
931 {
932 .name = "sdcc2_apps_clk_src",
933 .parent_names = gcc_xo_gpll0,
934 .num_parents = 2,
935 .ops = &clk_rcg2_floor_ops,
936 },
937};
938
939static struct clk_rcg2 sdcc3_apps_clk_src = {
940 .cmd_rcgr = 0x0550,
941 .mnd_width = 8,
942 .hid_width = 5,
943 .parent_map = gcc_xo_gpll0_map,
944 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
945 .clkr.hw.init = &(struct clk_init_data)
946 {
947 .name = "sdcc3_apps_clk_src",
948 .parent_names = gcc_xo_gpll0,
949 .num_parents = 2,
950 .ops = &clk_rcg2_floor_ops,
951 },
952};
953
954static struct clk_rcg2 sdcc4_apps_clk_src = {
955 .cmd_rcgr = 0x0590,
956 .mnd_width = 8,
957 .hid_width = 5,
958 .parent_map = gcc_xo_gpll0_map,
959 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
960 .clkr.hw.init = &(struct clk_init_data)
961 {
962 .name = "sdcc4_apps_clk_src",
963 .parent_names = gcc_xo_gpll0,
964 .num_parents = 2,
965 .ops = &clk_rcg2_floor_ops,
966 },
967};
968
969static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
970 F(105500, P_XO, 1, 1, 182),
971 { }
972};
973
974static struct clk_rcg2 tsif_ref_clk_src = {
975 .cmd_rcgr = 0x0d90,
976 .mnd_width = 8,
977 .hid_width = 5,
978 .freq_tbl = ftbl_tsif_ref_clk_src,
979 .clkr.hw.init = &(struct clk_init_data)
980 {
981 .name = "tsif_ref_clk_src",
982 .parent_names = (const char *[]) { "xo" },
983 .num_parents = 1,
984 .ops = &clk_rcg2_ops,
985 },
986};
987
988static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
989 F(19200000, P_XO, 1, 0, 0),
990 F(60000000, P_GPLL0, 10, 0, 0),
991 { }
992};
993
994static struct clk_rcg2 usb30_mock_utmi_clk_src = {
995 .cmd_rcgr = 0x03e8,
996 .hid_width = 5,
997 .parent_map = gcc_xo_gpll0_map,
998 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
999 .clkr.hw.init = &(struct clk_init_data)
1000 {
1001 .name = "usb30_mock_utmi_clk_src",
1002 .parent_names = gcc_xo_gpll0,
1003 .num_parents = 2,
1004 .ops = &clk_rcg2_ops,
1005 },
1006};
1007
1008static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1009 F(1200000, P_XO, 16, 0, 0),
1010 { }
1011};
1012
1013static struct clk_rcg2 usb3_phy_aux_clk_src = {
1014 .cmd_rcgr = 0x1414,
1015 .hid_width = 5,
1016 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1017 .clkr.hw.init = &(struct clk_init_data)
1018 {
1019 .name = "usb3_phy_aux_clk_src",
1020 .parent_names = (const char *[]) { "xo" },
1021 .num_parents = 1,
1022 .ops = &clk_rcg2_ops,
1023 },
1024};
1025
1026static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1027 F(75000000, P_GPLL0, 8, 0, 0),
1028 { }
1029};
1030
1031static struct clk_rcg2 usb_hs_system_clk_src = {
1032 .cmd_rcgr = 0x0490,
1033 .hid_width = 5,
1034 .parent_map = gcc_xo_gpll0_map,
1035 .freq_tbl = ftbl_usb_hs_system_clk_src,
1036 .clkr.hw.init = &(struct clk_init_data)
1037 {
1038 .name = "usb_hs_system_clk_src",
1039 .parent_names = gcc_xo_gpll0,
1040 .num_parents = 2,
1041 .ops = &clk_rcg2_ops,
1042 },
1043};
1044
1045static struct clk_branch gcc_blsp1_ahb_clk = {
1046 .halt_reg = 0x05c4,
1047 .halt_check = BRANCH_HALT_VOTED,
1048 .clkr = {
1049 .enable_reg = 0x1484,
1050 .enable_mask = BIT(17),
1051 .hw.init = &(struct clk_init_data)
1052 {
1053 .name = "gcc_blsp1_ahb_clk",
1054 .ops = &clk_branch2_ops,
1055 },
1056 },
1057};
1058
1059static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1060 .halt_reg = 0x0648,
1061 .clkr = {
1062 .enable_reg = 0x0648,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data)
1065 {
1066 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1067 .parent_names = (const char *[]) {
1068 "blsp1_qup1_i2c_apps_clk_src",
1069 },
1070 .num_parents = 1,
1071 .flags = CLK_SET_RATE_PARENT,
1072 .ops = &clk_branch2_ops,
1073 },
1074 },
1075};
1076
1077static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1078 .halt_reg = 0x0644,
1079 .clkr = {
1080 .enable_reg = 0x0644,
1081 .enable_mask = BIT(0),
1082 .hw.init = &(struct clk_init_data)
1083 {
1084 .name = "gcc_blsp1_qup1_spi_apps_clk",
1085 .parent_names = (const char *[]) {
1086 "blsp1_qup1_spi_apps_clk_src",
1087 },
1088 .num_parents = 1,
1089 .flags = CLK_SET_RATE_PARENT,
1090 .ops = &clk_branch2_ops,
1091 },
1092 },
1093};
1094
1095static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1096 .halt_reg = 0x06c8,
1097 .clkr = {
1098 .enable_reg = 0x06c8,
1099 .enable_mask = BIT(0),
1100 .hw.init = &(struct clk_init_data)
1101 {
1102 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1103 .parent_names = (const char *[]) {
1104 "blsp1_qup2_i2c_apps_clk_src",
1105 },
1106 .num_parents = 1,
1107 .flags = CLK_SET_RATE_PARENT,
1108 .ops = &clk_branch2_ops,
1109 },
1110 },
1111};
1112
1113static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1114 .halt_reg = 0x06c4,
1115 .clkr = {
1116 .enable_reg = 0x06c4,
1117 .enable_mask = BIT(0),
1118 .hw.init = &(struct clk_init_data)
1119 {
1120 .name = "gcc_blsp1_qup2_spi_apps_clk",
1121 .parent_names = (const char *[]) {
1122 "blsp1_qup2_spi_apps_clk_src",
1123 },
1124 .num_parents = 1,
1125 .flags = CLK_SET_RATE_PARENT,
1126 .ops = &clk_branch2_ops,
1127 },
1128 },
1129};
1130
1131static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1132 .halt_reg = 0x0748,
1133 .clkr = {
1134 .enable_reg = 0x0748,
1135 .enable_mask = BIT(0),
1136 .hw.init = &(struct clk_init_data)
1137 {
1138 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1139 .parent_names = (const char *[]) {
1140 "blsp1_qup3_i2c_apps_clk_src",
1141 },
1142 .num_parents = 1,
1143 .flags = CLK_SET_RATE_PARENT,
1144 .ops = &clk_branch2_ops,
1145 },
1146 },
1147};
1148
1149static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1150 .halt_reg = 0x0744,
1151 .clkr = {
1152 .enable_reg = 0x0744,
1153 .enable_mask = BIT(0),
1154 .hw.init = &(struct clk_init_data)
1155 {
1156 .name = "gcc_blsp1_qup3_spi_apps_clk",
1157 .parent_names = (const char *[]) {
1158 "blsp1_qup3_spi_apps_clk_src",
1159 },
1160 .num_parents = 1,
1161 .flags = CLK_SET_RATE_PARENT,
1162 .ops = &clk_branch2_ops,
1163 },
1164 },
1165};
1166
1167static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1168 .halt_reg = 0x07c8,
1169 .clkr = {
1170 .enable_reg = 0x07c8,
1171 .enable_mask = BIT(0),
1172 .hw.init = &(struct clk_init_data)
1173 {
1174 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1175 .parent_names = (const char *[]) {
1176 "blsp1_qup4_i2c_apps_clk_src",
1177 },
1178 .num_parents = 1,
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_branch2_ops,
1181 },
1182 },
1183};
1184
1185static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1186 .halt_reg = 0x07c4,
1187 .clkr = {
1188 .enable_reg = 0x07c4,
1189 .enable_mask = BIT(0),
1190 .hw.init = &(struct clk_init_data)
1191 {
1192 .name = "gcc_blsp1_qup4_spi_apps_clk",
1193 .parent_names = (const char *[]) {
1194 "blsp1_qup4_spi_apps_clk_src",
1195 },
1196 .num_parents = 1,
1197 .flags = CLK_SET_RATE_PARENT,
1198 .ops = &clk_branch2_ops,
1199 },
1200 },
1201};
1202
1203static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1204 .halt_reg = 0x0848,
1205 .clkr = {
1206 .enable_reg = 0x0848,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(struct clk_init_data)
1209 {
1210 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1211 .parent_names = (const char *[]) {
1212 "blsp1_qup5_i2c_apps_clk_src",
1213 },
1214 .num_parents = 1,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219};
1220
1221static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1222 .halt_reg = 0x0844,
1223 .clkr = {
1224 .enable_reg = 0x0844,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data)
1227 {
1228 .name = "gcc_blsp1_qup5_spi_apps_clk",
1229 .parent_names = (const char *[]) {
1230 "blsp1_qup5_spi_apps_clk_src",
1231 },
1232 .num_parents = 1,
1233 .flags = CLK_SET_RATE_PARENT,
1234 .ops = &clk_branch2_ops,
1235 },
1236 },
1237};
1238
1239static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1240 .halt_reg = 0x08c8,
1241 .clkr = {
1242 .enable_reg = 0x08c8,
1243 .enable_mask = BIT(0),
1244 .hw.init = &(struct clk_init_data)
1245 {
1246 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1247 .parent_names = (const char *[]) {
1248 "blsp1_qup6_i2c_apps_clk_src",
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1258 .halt_reg = 0x08c4,
1259 .clkr = {
1260 .enable_reg = 0x08c4,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data)
1263 {
1264 .name = "gcc_blsp1_qup6_spi_apps_clk",
1265 .parent_names = (const char *[]) {
1266 "blsp1_qup6_spi_apps_clk_src",
1267 },
1268 .num_parents = 1,
1269 .flags = CLK_SET_RATE_PARENT,
1270 .ops = &clk_branch2_ops,
1271 },
1272 },
1273};
1274
1275static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1276 .halt_reg = 0x0684,
1277 .clkr = {
1278 .enable_reg = 0x0684,
1279 .enable_mask = BIT(0),
1280 .hw.init = &(struct clk_init_data)
1281 {
1282 .name = "gcc_blsp1_uart1_apps_clk",
1283 .parent_names = (const char *[]) {
1284 "blsp1_uart1_apps_clk_src",
1285 },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1289 },
1290 },
1291};
1292
1293static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1294 .halt_reg = 0x0704,
1295 .clkr = {
1296 .enable_reg = 0x0704,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data)
1299 {
1300 .name = "gcc_blsp1_uart2_apps_clk",
1301 .parent_names = (const char *[]) {
1302 "blsp1_uart2_apps_clk_src",
1303 },
1304 .num_parents = 1,
1305 .flags = CLK_SET_RATE_PARENT,
1306 .ops = &clk_branch2_ops,
1307 },
1308 },
1309};
1310
1311static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1312 .halt_reg = 0x0784,
1313 .clkr = {
1314 .enable_reg = 0x0784,
1315 .enable_mask = BIT(0),
1316 .hw.init = &(struct clk_init_data)
1317 {
1318 .name = "gcc_blsp1_uart3_apps_clk",
1319 .parent_names = (const char *[]) {
1320 "blsp1_uart3_apps_clk_src",
1321 },
1322 .num_parents = 1,
1323 .flags = CLK_SET_RATE_PARENT,
1324 .ops = &clk_branch2_ops,
1325 },
1326 },
1327};
1328
1329static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1330 .halt_reg = 0x0804,
1331 .clkr = {
1332 .enable_reg = 0x0804,
1333 .enable_mask = BIT(0),
1334 .hw.init = &(struct clk_init_data)
1335 {
1336 .name = "gcc_blsp1_uart4_apps_clk",
1337 .parent_names = (const char *[]) {
1338 "blsp1_uart4_apps_clk_src",
1339 },
1340 .num_parents = 1,
1341 .flags = CLK_SET_RATE_PARENT,
1342 .ops = &clk_branch2_ops,
1343 },
1344 },
1345};
1346
1347static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1348 .halt_reg = 0x0884,
1349 .clkr = {
1350 .enable_reg = 0x0884,
1351 .enable_mask = BIT(0),
1352 .hw.init = &(struct clk_init_data)
1353 {
1354 .name = "gcc_blsp1_uart5_apps_clk",
1355 .parent_names = (const char *[]) {
1356 "blsp1_uart5_apps_clk_src",
1357 },
1358 .num_parents = 1,
1359 .flags = CLK_SET_RATE_PARENT,
1360 .ops = &clk_branch2_ops,
1361 },
1362 },
1363};
1364
1365static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1366 .halt_reg = 0x0904,
1367 .clkr = {
1368 .enable_reg = 0x0904,
1369 .enable_mask = BIT(0),
1370 .hw.init = &(struct clk_init_data)
1371 {
1372 .name = "gcc_blsp1_uart6_apps_clk",
1373 .parent_names = (const char *[]) {
1374 "blsp1_uart6_apps_clk_src",
1375 },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT,
1378 .ops = &clk_branch2_ops,
1379 },
1380 },
1381};
1382
1383static struct clk_branch gcc_blsp2_ahb_clk = {
1384 .halt_reg = 0x0944,
1385 .halt_check = BRANCH_HALT_VOTED,
1386 .clkr = {
1387 .enable_reg = 0x1484,
1388 .enable_mask = BIT(15),
1389 .hw.init = &(struct clk_init_data)
1390 {
1391 .name = "gcc_blsp2_ahb_clk",
1392 .ops = &clk_branch2_ops,
1393 },
1394 },
1395};
1396
1397static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1398 .halt_reg = 0x0988,
1399 .clkr = {
1400 .enable_reg = 0x0988,
1401 .enable_mask = BIT(0),
1402 .hw.init = &(struct clk_init_data)
1403 {
1404 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1405 .parent_names = (const char *[]) {
1406 "blsp2_qup1_i2c_apps_clk_src",
1407 },
1408 .num_parents = 1,
1409 .flags = CLK_SET_RATE_PARENT,
1410 .ops = &clk_branch2_ops,
1411 },
1412 },
1413};
1414
1415static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1416 .halt_reg = 0x0984,
1417 .clkr = {
1418 .enable_reg = 0x0984,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(struct clk_init_data)
1421 {
1422 .name = "gcc_blsp2_qup1_spi_apps_clk",
1423 .parent_names = (const char *[]) {
1424 "blsp2_qup1_spi_apps_clk_src",
1425 },
1426 .num_parents = 1,
1427 .flags = CLK_SET_RATE_PARENT,
1428 .ops = &clk_branch2_ops,
1429 },
1430 },
1431};
1432
1433static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1434 .halt_reg = 0x0a08,
1435 .clkr = {
1436 .enable_reg = 0x0a08,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(struct clk_init_data)
1439 {
1440 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1441 .parent_names = (const char *[]) {
1442 "blsp2_qup2_i2c_apps_clk_src",
1443 },
1444 .num_parents = 1,
1445 .flags = CLK_SET_RATE_PARENT,
1446 .ops = &clk_branch2_ops,
1447 },
1448 },
1449};
1450
1451static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1452 .halt_reg = 0x0a04,
1453 .clkr = {
1454 .enable_reg = 0x0a04,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(struct clk_init_data)
1457 {
1458 .name = "gcc_blsp2_qup2_spi_apps_clk",
1459 .parent_names = (const char *[]) {
1460 "blsp2_qup2_spi_apps_clk_src",
1461 },
1462 .num_parents = 1,
1463 .flags = CLK_SET_RATE_PARENT,
1464 .ops = &clk_branch2_ops,
1465 },
1466 },
1467};
1468
1469static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1470 .halt_reg = 0x0a88,
1471 .clkr = {
1472 .enable_reg = 0x0a88,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data)
1475 {
1476 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1477 .parent_names = (const char *[]) {
1478 "blsp2_qup3_i2c_apps_clk_src",
1479 },
1480 .num_parents = 1,
1481 .flags = CLK_SET_RATE_PARENT,
1482 .ops = &clk_branch2_ops,
1483 },
1484 },
1485};
1486
1487static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1488 .halt_reg = 0x0a84,
1489 .clkr = {
1490 .enable_reg = 0x0a84,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(struct clk_init_data)
1493 {
1494 .name = "gcc_blsp2_qup3_spi_apps_clk",
1495 .parent_names = (const char *[]) {
1496 "blsp2_qup3_spi_apps_clk_src",
1497 },
1498 .num_parents = 1,
1499 .flags = CLK_SET_RATE_PARENT,
1500 .ops = &clk_branch2_ops,
1501 },
1502 },
1503};
1504
1505static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1506 .halt_reg = 0x0b08,
1507 .clkr = {
1508 .enable_reg = 0x0b08,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data)
1511 {
1512 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1513 .parent_names = (const char *[]) {
1514 "blsp2_qup4_i2c_apps_clk_src",
1515 },
1516 .num_parents = 1,
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_branch2_ops,
1519 },
1520 },
1521};
1522
1523static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1524 .halt_reg = 0x0b04,
1525 .clkr = {
1526 .enable_reg = 0x0b04,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data)
1529 {
1530 .name = "gcc_blsp2_qup4_spi_apps_clk",
1531 .parent_names = (const char *[]) {
1532 "blsp2_qup4_spi_apps_clk_src",
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539};
1540
1541static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1542 .halt_reg = 0x0b88,
1543 .clkr = {
1544 .enable_reg = 0x0b88,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data)
1547 {
1548 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1549 .parent_names = (const char *[]) {
1550 "blsp2_qup5_i2c_apps_clk_src",
1551 },
1552 .num_parents = 1,
1553 .flags = CLK_SET_RATE_PARENT,
1554 .ops = &clk_branch2_ops,
1555 },
1556 },
1557};
1558
1559static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1560 .halt_reg = 0x0b84,
1561 .clkr = {
1562 .enable_reg = 0x0b84,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data)
1565 {
1566 .name = "gcc_blsp2_qup5_spi_apps_clk",
1567 .parent_names = (const char *[]) {
1568 "blsp2_qup5_spi_apps_clk_src",
1569 },
1570 .num_parents = 1,
1571 .flags = CLK_SET_RATE_PARENT,
1572 .ops = &clk_branch2_ops,
1573 },
1574 },
1575};
1576
1577static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1578 .halt_reg = 0x0c08,
1579 .clkr = {
1580 .enable_reg = 0x0c08,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(struct clk_init_data)
1583 {
1584 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1585 .parent_names = (const char *[]) {
1586 "blsp2_qup6_i2c_apps_clk_src",
1587 },
1588 .num_parents = 1,
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1591 },
1592 },
1593};
1594
1595static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1596 .halt_reg = 0x0c04,
1597 .clkr = {
1598 .enable_reg = 0x0c04,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data)
1601 {
1602 .name = "gcc_blsp2_qup6_spi_apps_clk",
1603 .parent_names = (const char *[]) {
1604 "blsp2_qup6_spi_apps_clk_src",
1605 },
1606 .num_parents = 1,
1607 .flags = CLK_SET_RATE_PARENT,
1608 .ops = &clk_branch2_ops,
1609 },
1610 },
1611};
1612
1613static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1614 .halt_reg = 0x09c4,
1615 .clkr = {
1616 .enable_reg = 0x09c4,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(struct clk_init_data)
1619 {
1620 .name = "gcc_blsp2_uart1_apps_clk",
1621 .parent_names = (const char *[]) {
1622 "blsp2_uart1_apps_clk_src",
1623 },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1632 .halt_reg = 0x0a44,
1633 .clkr = {
1634 .enable_reg = 0x0a44,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data)
1637 {
1638 .name = "gcc_blsp2_uart2_apps_clk",
1639 .parent_names = (const char *[]) {
1640 "blsp2_uart2_apps_clk_src",
1641 },
1642 .num_parents = 1,
1643 .flags = CLK_SET_RATE_PARENT,
1644 .ops = &clk_branch2_ops,
1645 },
1646 },
1647};
1648
1649static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1650 .halt_reg = 0x0ac4,
1651 .clkr = {
1652 .enable_reg = 0x0ac4,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(struct clk_init_data)
1655 {
1656 .name = "gcc_blsp2_uart3_apps_clk",
1657 .parent_names = (const char *[]) {
1658 "blsp2_uart3_apps_clk_src",
1659 },
1660 .num_parents = 1,
1661 .flags = CLK_SET_RATE_PARENT,
1662 .ops = &clk_branch2_ops,
1663 },
1664 },
1665};
1666
1667static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1668 .halt_reg = 0x0b44,
1669 .clkr = {
1670 .enable_reg = 0x0b44,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(struct clk_init_data)
1673 {
1674 .name = "gcc_blsp2_uart4_apps_clk",
1675 .parent_names = (const char *[]) {
1676 "blsp2_uart4_apps_clk_src",
1677 },
1678 .num_parents = 1,
1679 .flags = CLK_SET_RATE_PARENT,
1680 .ops = &clk_branch2_ops,
1681 },
1682 },
1683};
1684
1685static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1686 .halt_reg = 0x0bc4,
1687 .clkr = {
1688 .enable_reg = 0x0bc4,
1689 .enable_mask = BIT(0),
1690 .hw.init = &(struct clk_init_data)
1691 {
1692 .name = "gcc_blsp2_uart5_apps_clk",
1693 .parent_names = (const char *[]) {
1694 "blsp2_uart5_apps_clk_src",
1695 },
1696 .num_parents = 1,
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1699 },
1700 },
1701};
1702
1703static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1704 .halt_reg = 0x0c44,
1705 .clkr = {
1706 .enable_reg = 0x0c44,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(struct clk_init_data)
1709 {
1710 .name = "gcc_blsp2_uart6_apps_clk",
1711 .parent_names = (const char *[]) {
1712 "blsp2_uart6_apps_clk_src",
1713 },
1714 .num_parents = 1,
1715 .flags = CLK_SET_RATE_PARENT,
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719};
1720
1721static struct clk_branch gcc_gp1_clk = {
1722 .halt_reg = 0x1900,
1723 .clkr = {
1724 .enable_reg = 0x1900,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data)
1727 {
1728 .name = "gcc_gp1_clk",
1729 .parent_names = (const char *[]) {
1730 "gp1_clk_src",
1731 },
1732 .num_parents = 1,
1733 .flags = CLK_SET_RATE_PARENT,
1734 .ops = &clk_branch2_ops,
1735 },
1736 },
1737};
1738
1739static struct clk_branch gcc_gp2_clk = {
1740 .halt_reg = 0x1940,
1741 .clkr = {
1742 .enable_reg = 0x1940,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(struct clk_init_data)
1745 {
1746 .name = "gcc_gp2_clk",
1747 .parent_names = (const char *[]) {
1748 "gp2_clk_src",
1749 },
1750 .num_parents = 1,
1751 .flags = CLK_SET_RATE_PARENT,
1752 .ops = &clk_branch2_ops,
1753 },
1754 },
1755};
1756
1757static struct clk_branch gcc_gp3_clk = {
1758 .halt_reg = 0x1980,
1759 .clkr = {
1760 .enable_reg = 0x1980,
1761 .enable_mask = BIT(0),
1762 .hw.init = &(struct clk_init_data)
1763 {
1764 .name = "gcc_gp3_clk",
1765 .parent_names = (const char *[]) {
1766 "gp3_clk_src",
1767 },
1768 .num_parents = 1,
1769 .flags = CLK_SET_RATE_PARENT,
1770 .ops = &clk_branch2_ops,
1771 },
1772 },
1773};
1774
1775static struct clk_branch gcc_pcie_0_aux_clk = {
1776 .halt_reg = 0x1ad4,
1777 .clkr = {
1778 .enable_reg = 0x1ad4,
1779 .enable_mask = BIT(0),
1780 .hw.init = &(struct clk_init_data)
1781 {
1782 .name = "gcc_pcie_0_aux_clk",
1783 .parent_names = (const char *[]) {
1784 "pcie_0_aux_clk_src",
1785 },
1786 .num_parents = 1,
1787 .flags = CLK_SET_RATE_PARENT,
1788 .ops = &clk_branch2_ops,
1789 },
1790 },
1791};
1792
1793static struct clk_branch gcc_pcie_0_pipe_clk = {
1794 .halt_reg = 0x1ad8,
1795 .halt_check = BRANCH_HALT_DELAY,
1796 .clkr = {
1797 .enable_reg = 0x1ad8,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data)
1800 {
1801 .name = "gcc_pcie_0_pipe_clk",
1802 .parent_names = (const char *[]) {
1803 "pcie_0_pipe_clk_src",
1804 },
1805 .num_parents = 1,
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1808 },
1809 },
1810};
1811
1812static struct clk_branch gcc_pcie_1_aux_clk = {
1813 .halt_reg = 0x1b54,
1814 .clkr = {
1815 .enable_reg = 0x1b54,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data)
1818 {
1819 .name = "gcc_pcie_1_aux_clk",
1820 .parent_names = (const char *[]) {
1821 "pcie_1_aux_clk_src",
1822 },
1823 .num_parents = 1,
1824 .flags = CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1826 },
1827 },
1828};
1829
1830static struct clk_branch gcc_pcie_1_pipe_clk = {
1831 .halt_reg = 0x1b58,
1832 .halt_check = BRANCH_HALT_DELAY,
1833 .clkr = {
1834 .enable_reg = 0x1b58,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data)
1837 {
1838 .name = "gcc_pcie_1_pipe_clk",
1839 .parent_names = (const char *[]) {
1840 "pcie_1_pipe_clk_src",
1841 },
1842 .num_parents = 1,
1843 .flags = CLK_SET_RATE_PARENT,
1844 .ops = &clk_branch2_ops,
1845 },
1846 },
1847};
1848
1849static struct clk_branch gcc_pdm2_clk = {
1850 .halt_reg = 0x0ccc,
1851 .clkr = {
1852 .enable_reg = 0x0ccc,
1853 .enable_mask = BIT(0),
1854 .hw.init = &(struct clk_init_data)
1855 {
1856 .name = "gcc_pdm2_clk",
1857 .parent_names = (const char *[]) {
1858 "pdm2_clk_src",
1859 },
1860 .num_parents = 1,
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1863 },
1864 },
1865};
1866
1867static struct clk_branch gcc_sdcc1_apps_clk = {
1868 .halt_reg = 0x04c4,
1869 .clkr = {
1870 .enable_reg = 0x04c4,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data)
1873 {
1874 .name = "gcc_sdcc1_apps_clk",
1875 .parent_names = (const char *[]) {
1876 "sdcc1_apps_clk_src",
1877 },
1878 .num_parents = 1,
1879 .flags = CLK_SET_RATE_PARENT,
1880 .ops = &clk_branch2_ops,
1881 },
1882 },
1883};
1884
1885static struct clk_branch gcc_sdcc1_ahb_clk = {
1886 .halt_reg = 0x04c8,
1887 .clkr = {
1888 .enable_reg = 0x04c8,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data)
1891 {
1892 .name = "gcc_sdcc1_ahb_clk",
1893 .parent_names = (const char *[]){
1894 "periph_noc_clk_src",
1895 },
1896 .num_parents = 1,
1897 .ops = &clk_branch2_ops,
1898 },
1899 },
1900};
1901
1902static struct clk_branch gcc_sdcc2_apps_clk = {
1903 .halt_reg = 0x0504,
1904 .clkr = {
1905 .enable_reg = 0x0504,
1906 .enable_mask = BIT(0),
1907 .hw.init = &(struct clk_init_data)
1908 {
1909 .name = "gcc_sdcc2_apps_clk",
1910 .parent_names = (const char *[]) {
1911 "sdcc2_apps_clk_src",
1912 },
1913 .num_parents = 1,
1914 .flags = CLK_SET_RATE_PARENT,
1915 .ops = &clk_branch2_ops,
1916 },
1917 },
1918};
1919
1920static struct clk_branch gcc_sdcc3_apps_clk = {
1921 .halt_reg = 0x0544,
1922 .clkr = {
1923 .enable_reg = 0x0544,
1924 .enable_mask = BIT(0),
1925 .hw.init = &(struct clk_init_data)
1926 {
1927 .name = "gcc_sdcc3_apps_clk",
1928 .parent_names = (const char *[]) {
1929 "sdcc3_apps_clk_src",
1930 },
1931 .num_parents = 1,
1932 .flags = CLK_SET_RATE_PARENT,
1933 .ops = &clk_branch2_ops,
1934 },
1935 },
1936};
1937
1938static struct clk_branch gcc_sdcc4_apps_clk = {
1939 .halt_reg = 0x0584,
1940 .clkr = {
1941 .enable_reg = 0x0584,
1942 .enable_mask = BIT(0),
1943 .hw.init = &(struct clk_init_data)
1944 {
1945 .name = "gcc_sdcc4_apps_clk",
1946 .parent_names = (const char *[]) {
1947 "sdcc4_apps_clk_src",
1948 },
1949 .num_parents = 1,
1950 .flags = CLK_SET_RATE_PARENT,
1951 .ops = &clk_branch2_ops,
1952 },
1953 },
1954};
1955
1956static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1957 .halt_reg = 0x1d7c,
1958 .clkr = {
1959 .enable_reg = 0x1d7c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data)
1962 {
1963 .name = "gcc_sys_noc_ufs_axi_clk",
1964 .parent_names = (const char *[]) {
1965 "ufs_axi_clk_src",
1966 },
1967 .num_parents = 1,
1968 .flags = CLK_SET_RATE_PARENT,
1969 .ops = &clk_branch2_ops,
1970 },
1971 },
1972};
1973
1974static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1975 .halt_reg = 0x03fc,
1976 .clkr = {
1977 .enable_reg = 0x03fc,
1978 .enable_mask = BIT(0),
1979 .hw.init = &(struct clk_init_data)
1980 {
1981 .name = "gcc_sys_noc_usb3_axi_clk",
1982 .parent_names = (const char *[]) {
1983 "usb30_master_clk_src",
1984 },
1985 .num_parents = 1,
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1988 },
1989 },
1990};
1991
1992static struct clk_branch gcc_tsif_ref_clk = {
1993 .halt_reg = 0x0d88,
1994 .clkr = {
1995 .enable_reg = 0x0d88,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data)
1998 {
1999 .name = "gcc_tsif_ref_clk",
2000 .parent_names = (const char *[]) {
2001 "tsif_ref_clk_src",
2002 },
2003 .num_parents = 1,
2004 .flags = CLK_SET_RATE_PARENT,
2005 .ops = &clk_branch2_ops,
2006 },
2007 },
2008};
2009
2010static struct clk_branch gcc_ufs_axi_clk = {
2011 .halt_reg = 0x1d48,
2012 .clkr = {
2013 .enable_reg = 0x1d48,
2014 .enable_mask = BIT(0),
2015 .hw.init = &(struct clk_init_data)
2016 {
2017 .name = "gcc_ufs_axi_clk",
2018 .parent_names = (const char *[]) {
2019 "ufs_axi_clk_src",
2020 },
2021 .num_parents = 1,
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2024 },
2025 },
2026};
2027
2028static struct clk_branch gcc_ufs_rx_cfg_clk = {
2029 .halt_reg = 0x1d54,
2030 .clkr = {
2031 .enable_reg = 0x1d54,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data)
2034 {
2035 .name = "gcc_ufs_rx_cfg_clk",
2036 .parent_names = (const char *[]) {
2037 "ufs_axi_clk_src",
2038 },
2039 .num_parents = 1,
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2042 },
2043 },
2044};
2045
2046static struct clk_branch gcc_ufs_tx_cfg_clk = {
2047 .halt_reg = 0x1d50,
2048 .clkr = {
2049 .enable_reg = 0x1d50,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data)
2052 {
2053 .name = "gcc_ufs_tx_cfg_clk",
2054 .parent_names = (const char *[]) {
2055 "ufs_axi_clk_src",
2056 },
2057 .num_parents = 1,
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch gcc_usb30_master_clk = {
2065 .halt_reg = 0x03c8,
2066 .clkr = {
2067 .enable_reg = 0x03c8,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data)
2070 {
2071 .name = "gcc_usb30_master_clk",
2072 .parent_names = (const char *[]) {
2073 "usb30_master_clk_src",
2074 },
2075 .num_parents = 1,
2076 .flags = CLK_SET_RATE_PARENT,
2077 .ops = &clk_branch2_ops,
2078 },
2079 },
2080};
2081
2082static struct clk_branch gcc_usb30_mock_utmi_clk = {
2083 .halt_reg = 0x03d0,
2084 .clkr = {
2085 .enable_reg = 0x03d0,
2086 .enable_mask = BIT(0),
2087 .hw.init = &(struct clk_init_data)
2088 {
2089 .name = "gcc_usb30_mock_utmi_clk",
2090 .parent_names = (const char *[]) {
2091 "usb30_mock_utmi_clk_src",
2092 },
2093 .num_parents = 1,
2094 .flags = CLK_SET_RATE_PARENT,
2095 .ops = &clk_branch2_ops,
2096 },
2097 },
2098};
2099
2100static struct clk_branch gcc_usb3_phy_aux_clk = {
2101 .halt_reg = 0x1408,
2102 .clkr = {
2103 .enable_reg = 0x1408,
2104 .enable_mask = BIT(0),
2105 .hw.init = &(struct clk_init_data)
2106 {
2107 .name = "gcc_usb3_phy_aux_clk",
2108 .parent_names = (const char *[]) {
2109 "usb3_phy_aux_clk_src",
2110 },
2111 .num_parents = 1,
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2114 },
2115 },
2116};
2117
2118static struct clk_branch gcc_usb_hs_system_clk = {
2119 .halt_reg = 0x0484,
2120 .clkr = {
2121 .enable_reg = 0x0484,
2122 .enable_mask = BIT(0),
2123 .hw.init = &(struct clk_init_data)
2124 {
2125 .name = "gcc_usb_hs_system_clk",
2126 .parent_names = (const char *[]) {
2127 "usb_hs_system_clk_src",
2128 },
2129 .num_parents = 1,
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2132 },
2133 },
2134};
2135
2136static struct clk_regmap *gcc_msm8994_clocks[] = {
2137 [GPLL0_EARLY] = &gpll0_early.clkr,
2138 [GPLL0] = &gpll0.clkr,
2139 [GPLL4_EARLY] = &gpll4_early.clkr,
2140 [GPLL4] = &gpll4.clkr,
2141 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2142 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2143 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2144 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2145 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2146 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2147 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2148 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2149 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2150 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2151 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2152 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2153 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2154 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2155 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2156 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2157 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2158 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2159 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2160 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2161 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2162 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2163 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2164 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2165 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2166 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2167 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2168 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2169 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2170 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2171 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2172 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2173 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2174 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2175 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2176 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2177 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2178 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2179 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2180 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2181 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2182 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2183 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2184 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2185 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2186 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2187 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2188 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2189 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2190 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2191 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2192 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2193 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2194 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2195 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2196 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2197 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2198 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2199 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2200 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2201 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2202 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2203 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2204 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2205 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2206 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2207 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2208 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2209 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2210 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2211 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2212 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2213 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2214 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2215 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2216 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2217 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2218 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2219 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2220 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2221 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2222 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2223 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2224 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2225 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2226 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2227 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2228 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2229 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2230 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2231 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2232 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2233 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2234 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2235 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2236 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2237 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2238 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2239 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2240 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2241 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2242 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2243 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2244 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2245 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2246 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2247 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2248 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2249 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2250 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2251 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2252 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2253 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2254 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2255 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2256};
2257
2258static const struct regmap_config gcc_msm8994_regmap_config = {
2259 .reg_bits = 32,
2260 .reg_stride = 4,
2261 .val_bits = 32,
2262 .max_register = 0x2000,
2263 .fast_io = true,
2264};
2265
2266static const struct qcom_cc_desc gcc_msm8994_desc = {
2267 .config = &gcc_msm8994_regmap_config,
2268 .clks = gcc_msm8994_clocks,
2269 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2270};
2271
2272static const struct of_device_id gcc_msm8994_match_table[] = {
2273 { .compatible = "qcom,gcc-msm8994" },
2274 {}
2275};
2276MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2277
2278static int gcc_msm8994_probe(struct platform_device *pdev)
2279{
2280 struct device *dev = &pdev->dev;
2281 struct clk *clk;
2282
2283 clk = devm_clk_register(dev, &xo.hw);
2284 if (IS_ERR(clk))
2285 return PTR_ERR(clk);
2286
2287 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2288}
2289
2290static struct platform_driver gcc_msm8994_driver = {
2291 .probe = gcc_msm8994_probe,
2292 .driver = {
2293 .name = "gcc-msm8994",
2294 .of_match_table = gcc_msm8994_match_table,
2295 },
2296};
2297
2298static int __init gcc_msm8994_init(void)
2299{
2300 return platform_driver_register(&gcc_msm8994_driver);
2301}
2302core_initcall(gcc_msm8994_init);
2303
2304static void __exit gcc_msm8994_exit(void)
2305{
2306 platform_driver_unregister(&gcc_msm8994_driver);
2307}
2308module_exit(gcc_msm8994_exit);
2309
2310MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2311MODULE_LICENSE("GPL v2");
2312MODULE_ALIAS("platform:gcc-msm8994");