1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/bitops.h>
   8#include <linux/err.h>
   9#include <linux/platform_device.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/of_device.h>
  13#include <linux/clk-provider.h>
  14#include <linux/regmap.h>
  15#include <linux/reset-controller.h>
  16
  17#include <dt-bindings/clock/qcom,gcc-apq8084.h>
  18#include <dt-bindings/reset/qcom,gcc-apq8084.h>
  19
  20#include "common.h"
  21#include "clk-regmap.h"
  22#include "clk-pll.h"
  23#include "clk-rcg.h"
  24#include "clk-branch.h"
  25#include "reset.h"
  26#include "gdsc.h"
  27
  28enum {
  29	P_XO,
  30	P_GPLL0,
  31	P_GPLL1,
  32	P_GPLL4,
  33	P_PCIE_0_1_PIPE_CLK,
  34	P_SATA_ASIC0_CLK,
  35	P_SATA_RX_CLK,
  36	P_SLEEP_CLK,
  37};
  38
  39static const struct parent_map gcc_xo_gpll0_map[] = {
  40	{ P_XO, 0 },
  41	{ P_GPLL0, 1 }
  42};
  43
  44static const char * const gcc_xo_gpll0[] = {
  45	"xo",
  46	"gpll0_vote",
  47};
  48
  49static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  50	{ P_XO, 0 },
  51	{ P_GPLL0, 1 },
  52	{ P_GPLL4, 5 }
  53};
  54
  55static const char * const gcc_xo_gpll0_gpll4[] = {
  56	"xo",
  57	"gpll0_vote",
  58	"gpll4_vote",
  59};
  60
  61static const struct parent_map gcc_xo_sata_asic0_map[] = {
  62	{ P_XO, 0 },
  63	{ P_SATA_ASIC0_CLK, 2 }
  64};
  65
  66static const char * const gcc_xo_sata_asic0[] = {
  67	"xo",
  68	"sata_asic0_clk",
  69};
  70
  71static const struct parent_map gcc_xo_sata_rx_map[] = {
  72	{ P_XO, 0 },
  73	{ P_SATA_RX_CLK, 2}
  74};
  75
  76static const char * const gcc_xo_sata_rx[] = {
  77	"xo",
  78	"sata_rx_clk",
  79};
  80
  81static const struct parent_map gcc_xo_pcie_map[] = {
  82	{ P_XO, 0 },
  83	{ P_PCIE_0_1_PIPE_CLK, 2 }
  84};
  85
  86static const char * const gcc_xo_pcie[] = {
  87	"xo",
  88	"pcie_pipe",
  89};
  90
  91static const struct parent_map gcc_xo_pcie_sleep_map[] = {
  92	{ P_XO, 0 },
  93	{ P_SLEEP_CLK, 6 }
  94};
  95
  96static const char * const gcc_xo_pcie_sleep[] = {
  97	"xo",
  98	"sleep_clk_src",
  99};
 100
 101static struct clk_pll gpll0 = {
 102	.l_reg = 0x0004,
 103	.m_reg = 0x0008,
 104	.n_reg = 0x000c,
 105	.config_reg = 0x0014,
 106	.mode_reg = 0x0000,
 107	.status_reg = 0x001c,
 108	.status_bit = 17,
 109	.clkr.hw.init = &(struct clk_init_data){
 110		.name = "gpll0",
 111		.parent_names = (const char *[]){ "xo" },
 112		.num_parents = 1,
 113		.ops = &clk_pll_ops,
 114	},
 115};
 116
 117static struct clk_regmap gpll0_vote = {
 118	.enable_reg = 0x1480,
 119	.enable_mask = BIT(0),
 120	.hw.init = &(struct clk_init_data){
 121		.name = "gpll0_vote",
 122		.parent_names = (const char *[]){ "gpll0" },
 123		.num_parents = 1,
 124		.ops = &clk_pll_vote_ops,
 125	},
 126};
 127
 128static struct clk_rcg2 config_noc_clk_src = {
 129	.cmd_rcgr = 0x0150,
 130	.hid_width = 5,
 131	.parent_map = gcc_xo_gpll0_map,
 132	.clkr.hw.init = &(struct clk_init_data){
 133		.name = "config_noc_clk_src",
 134		.parent_names = gcc_xo_gpll0,
 135		.num_parents = 2,
 136		.ops = &clk_rcg2_ops,
 137	},
 138};
 139
 140static struct clk_rcg2 periph_noc_clk_src = {
 141	.cmd_rcgr = 0x0190,
 142	.hid_width = 5,
 143	.parent_map = gcc_xo_gpll0_map,
 144	.clkr.hw.init = &(struct clk_init_data){
 145		.name = "periph_noc_clk_src",
 146		.parent_names = gcc_xo_gpll0,
 147		.num_parents = 2,
 148		.ops = &clk_rcg2_ops,
 149	},
 150};
 151
 152static struct clk_rcg2 system_noc_clk_src = {
 153	.cmd_rcgr = 0x0120,
 154	.hid_width = 5,
 155	.parent_map = gcc_xo_gpll0_map,
 156	.clkr.hw.init = &(struct clk_init_data){
 157		.name = "system_noc_clk_src",
 158		.parent_names = gcc_xo_gpll0,
 159		.num_parents = 2,
 160		.ops = &clk_rcg2_ops,
 161	},
 162};
 163
 164static struct clk_pll gpll1 = {
 165	.l_reg = 0x0044,
 166	.m_reg = 0x0048,
 167	.n_reg = 0x004c,
 168	.config_reg = 0x0054,
 169	.mode_reg = 0x0040,
 170	.status_reg = 0x005c,
 171	.status_bit = 17,
 172	.clkr.hw.init = &(struct clk_init_data){
 173		.name = "gpll1",
 174		.parent_names = (const char *[]){ "xo" },
 175		.num_parents = 1,
 176		.ops = &clk_pll_ops,
 177	},
 178};
 179
 180static struct clk_regmap gpll1_vote = {
 181	.enable_reg = 0x1480,
 182	.enable_mask = BIT(1),
 183	.hw.init = &(struct clk_init_data){
 184		.name = "gpll1_vote",
 185		.parent_names = (const char *[]){ "gpll1" },
 186		.num_parents = 1,
 187		.ops = &clk_pll_vote_ops,
 188	},
 189};
 190
 191static struct clk_pll gpll4 = {
 192	.l_reg = 0x1dc4,
 193	.m_reg = 0x1dc8,
 194	.n_reg = 0x1dcc,
 195	.config_reg = 0x1dd4,
 196	.mode_reg = 0x1dc0,
 197	.status_reg = 0x1ddc,
 198	.status_bit = 17,
 199	.clkr.hw.init = &(struct clk_init_data){
 200		.name = "gpll4",
 201		.parent_names = (const char *[]){ "xo" },
 202		.num_parents = 1,
 203		.ops = &clk_pll_ops,
 204	},
 205};
 206
 207static struct clk_regmap gpll4_vote = {
 208	.enable_reg = 0x1480,
 209	.enable_mask = BIT(4),
 210	.hw.init = &(struct clk_init_data){
 211		.name = "gpll4_vote",
 212		.parent_names = (const char *[]){ "gpll4" },
 213		.num_parents = 1,
 214		.ops = &clk_pll_vote_ops,
 215	},
 216};
 217
 218static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
 219	F(100000000, P_GPLL0, 6, 0, 0),
 220	F(200000000, P_GPLL0, 3, 0, 0),
 221	F(240000000, P_GPLL0, 2.5, 0, 0),
 222	{ }
 223};
 224
 225static struct clk_rcg2 ufs_axi_clk_src = {
 226	.cmd_rcgr = 0x1d64,
 227	.mnd_width = 8,
 228	.hid_width = 5,
 229	.parent_map = gcc_xo_gpll0_map,
 230	.freq_tbl = ftbl_gcc_ufs_axi_clk,
 231	.clkr.hw.init = &(struct clk_init_data){
 232		.name = "ufs_axi_clk_src",
 233		.parent_names = gcc_xo_gpll0,
 234		.num_parents = 2,
 235		.ops = &clk_rcg2_ops,
 236	},
 237};
 238
 239static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
 240	F(125000000, P_GPLL0, 1, 5, 24),
 241	{ }
 242};
 243
 244static struct clk_rcg2 usb30_master_clk_src = {
 245	.cmd_rcgr = 0x03d4,
 246	.mnd_width = 8,
 247	.hid_width = 5,
 248	.parent_map = gcc_xo_gpll0_map,
 249	.freq_tbl = ftbl_gcc_usb30_master_clk,
 250	.clkr.hw.init = &(struct clk_init_data){
 251		.name = "usb30_master_clk_src",
 252		.parent_names = gcc_xo_gpll0,
 253		.num_parents = 2,
 254		.ops = &clk_rcg2_ops,
 255	},
 256};
 257
 258static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
 259	F(125000000, P_GPLL0, 1, 5, 24),
 260	{ }
 261};
 262
 263static struct clk_rcg2 usb30_sec_master_clk_src = {
 264	.cmd_rcgr = 0x1bd4,
 265	.mnd_width = 8,
 266	.hid_width = 5,
 267	.parent_map = gcc_xo_gpll0_map,
 268	.freq_tbl = ftbl_gcc_usb30_sec_master_clk,
 269	.clkr.hw.init = &(struct clk_init_data){
 270		.name = "usb30_sec_master_clk_src",
 271		.parent_names = gcc_xo_gpll0,
 272		.num_parents = 2,
 273		.ops = &clk_rcg2_ops,
 274	},
 275};
 276
 277static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
 278	.halt_reg = 0x1bd0,
 279	.clkr = {
 280		.enable_reg = 0x1bd0,
 281		.enable_mask = BIT(0),
 282		.hw.init = &(struct clk_init_data){
 283			.name = "gcc_usb30_sec_mock_utmi_clk",
 284			.parent_names = (const char *[]){
 285				"usb30_sec_mock_utmi_clk_src",
 286			},
 287			.num_parents = 1,
 288			.flags = CLK_SET_RATE_PARENT,
 289			.ops = &clk_branch2_ops,
 290		},
 291	},
 292};
 293
 294static struct clk_branch gcc_usb30_sec_sleep_clk = {
 295	.halt_reg = 0x1bcc,
 296	.clkr = {
 297		.enable_reg = 0x1bcc,
 298		.enable_mask = BIT(0),
 299		.hw.init = &(struct clk_init_data){
 300			.name = "gcc_usb30_sec_sleep_clk",
 301			.parent_names = (const char *[]){
 302				"sleep_clk_src",
 303			},
 304			.num_parents = 1,
 305			.flags = CLK_SET_RATE_PARENT,
 306			.ops = &clk_branch2_ops,
 307		},
 308	},
 309};
 310
 311static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
 312	F(19200000, P_XO, 1, 0, 0),
 313	F(50000000, P_GPLL0, 12, 0, 0),
 314	{ }
 315};
 316
 317static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 318	.cmd_rcgr = 0x0660,
 319	.hid_width = 5,
 320	.parent_map = gcc_xo_gpll0_map,
 321	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 322	.clkr.hw.init = &(struct clk_init_data){
 323		.name = "blsp1_qup1_i2c_apps_clk_src",
 324		.parent_names = gcc_xo_gpll0,
 325		.num_parents = 2,
 326		.ops = &clk_rcg2_ops,
 327	},
 328};
 329
 330static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
 331	F(960000, P_XO, 10, 1, 2),
 332	F(4800000, P_XO, 4, 0, 0),
 333	F(9600000, P_XO, 2, 0, 0),
 334	F(15000000, P_GPLL0, 10, 1, 4),
 335	F(19200000, P_XO, 1, 0, 0),
 336	F(25000000, P_GPLL0, 12, 1, 2),
 337	F(50000000, P_GPLL0, 12, 0, 0),
 338	{ }
 339};
 340
 341static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 342	.cmd_rcgr = 0x064c,
 343	.mnd_width = 8,
 344	.hid_width = 5,
 345	.parent_map = gcc_xo_gpll0_map,
 346	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 347	.clkr.hw.init = &(struct clk_init_data){
 348		.name = "blsp1_qup1_spi_apps_clk_src",
 349		.parent_names = gcc_xo_gpll0,
 350		.num_parents = 2,
 351		.ops = &clk_rcg2_ops,
 352	},
 353};
 354
 355static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 356	.cmd_rcgr = 0x06e0,
 357	.hid_width = 5,
 358	.parent_map = gcc_xo_gpll0_map,
 359	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 360	.clkr.hw.init = &(struct clk_init_data){
 361		.name = "blsp1_qup2_i2c_apps_clk_src",
 362		.parent_names = gcc_xo_gpll0,
 363		.num_parents = 2,
 364		.ops = &clk_rcg2_ops,
 365	},
 366};
 367
 368static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 369	.cmd_rcgr = 0x06cc,
 370	.mnd_width = 8,
 371	.hid_width = 5,
 372	.parent_map = gcc_xo_gpll0_map,
 373	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 374	.clkr.hw.init = &(struct clk_init_data){
 375		.name = "blsp1_qup2_spi_apps_clk_src",
 376		.parent_names = gcc_xo_gpll0,
 377		.num_parents = 2,
 378		.ops = &clk_rcg2_ops,
 379	},
 380};
 381
 382static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 383	.cmd_rcgr = 0x0760,
 384	.hid_width = 5,
 385	.parent_map = gcc_xo_gpll0_map,
 386	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 387	.clkr.hw.init = &(struct clk_init_data){
 388		.name = "blsp1_qup3_i2c_apps_clk_src",
 389		.parent_names = gcc_xo_gpll0,
 390		.num_parents = 2,
 391		.ops = &clk_rcg2_ops,
 392	},
 393};
 394
 395static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 396	.cmd_rcgr = 0x074c,
 397	.mnd_width = 8,
 398	.hid_width = 5,
 399	.parent_map = gcc_xo_gpll0_map,
 400	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 401	.clkr.hw.init = &(struct clk_init_data){
 402		.name = "blsp1_qup3_spi_apps_clk_src",
 403		.parent_names = gcc_xo_gpll0,
 404		.num_parents = 2,
 405		.ops = &clk_rcg2_ops,
 406	},
 407};
 408
 409static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 410	.cmd_rcgr = 0x07e0,
 411	.hid_width = 5,
 412	.parent_map = gcc_xo_gpll0_map,
 413	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 414	.clkr.hw.init = &(struct clk_init_data){
 415		.name = "blsp1_qup4_i2c_apps_clk_src",
 416		.parent_names = gcc_xo_gpll0,
 417		.num_parents = 2,
 418		.ops = &clk_rcg2_ops,
 419	},
 420};
 421
 422static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 423	.cmd_rcgr = 0x07cc,
 424	.mnd_width = 8,
 425	.hid_width = 5,
 426	.parent_map = gcc_xo_gpll0_map,
 427	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 428	.clkr.hw.init = &(struct clk_init_data){
 429		.name = "blsp1_qup4_spi_apps_clk_src",
 430		.parent_names = gcc_xo_gpll0,
 431		.num_parents = 2,
 432		.ops = &clk_rcg2_ops,
 433	},
 434};
 435
 436static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 437	.cmd_rcgr = 0x0860,
 438	.hid_width = 5,
 439	.parent_map = gcc_xo_gpll0_map,
 440	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 441	.clkr.hw.init = &(struct clk_init_data){
 442		.name = "blsp1_qup5_i2c_apps_clk_src",
 443		.parent_names = gcc_xo_gpll0,
 444		.num_parents = 2,
 445		.ops = &clk_rcg2_ops,
 446	},
 447};
 448
 449static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 450	.cmd_rcgr = 0x084c,
 451	.mnd_width = 8,
 452	.hid_width = 5,
 453	.parent_map = gcc_xo_gpll0_map,
 454	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 455	.clkr.hw.init = &(struct clk_init_data){
 456		.name = "blsp1_qup5_spi_apps_clk_src",
 457		.parent_names = gcc_xo_gpll0,
 458		.num_parents = 2,
 459		.ops = &clk_rcg2_ops,
 460	},
 461};
 462
 463static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 464	.cmd_rcgr = 0x08e0,
 465	.hid_width = 5,
 466	.parent_map = gcc_xo_gpll0_map,
 467	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 468	.clkr.hw.init = &(struct clk_init_data){
 469		.name = "blsp1_qup6_i2c_apps_clk_src",
 470		.parent_names = gcc_xo_gpll0,
 471		.num_parents = 2,
 472		.ops = &clk_rcg2_ops,
 473	},
 474};
 475
 476static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 477	.cmd_rcgr = 0x08cc,
 478	.mnd_width = 8,
 479	.hid_width = 5,
 480	.parent_map = gcc_xo_gpll0_map,
 481	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 482	.clkr.hw.init = &(struct clk_init_data){
 483		.name = "blsp1_qup6_spi_apps_clk_src",
 484		.parent_names = gcc_xo_gpll0,
 485		.num_parents = 2,
 486		.ops = &clk_rcg2_ops,
 487	},
 488};
 489
 490static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
 491	F(3686400, P_GPLL0, 1, 96, 15625),
 492	F(7372800, P_GPLL0, 1, 192, 15625),
 493	F(14745600, P_GPLL0, 1, 384, 15625),
 494	F(16000000, P_GPLL0, 5, 2, 15),
 495	F(19200000, P_XO, 1, 0, 0),
 496	F(24000000, P_GPLL0, 5, 1, 5),
 497	F(32000000, P_GPLL0, 1, 4, 75),
 498	F(40000000, P_GPLL0, 15, 0, 0),
 499	F(46400000, P_GPLL0, 1, 29, 375),
 500	F(48000000, P_GPLL0, 12.5, 0, 0),
 501	F(51200000, P_GPLL0, 1, 32, 375),
 502	F(56000000, P_GPLL0, 1, 7, 75),
 503	F(58982400, P_GPLL0, 1, 1536, 15625),
 504	F(60000000, P_GPLL0, 10, 0, 0),
 505	F(63160000, P_GPLL0, 9.5, 0, 0),
 506	{ }
 507};
 508
 509static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 510	.cmd_rcgr = 0x068c,
 511	.mnd_width = 16,
 512	.hid_width = 5,
 513	.parent_map = gcc_xo_gpll0_map,
 514	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 515	.clkr.hw.init = &(struct clk_init_data){
 516		.name = "blsp1_uart1_apps_clk_src",
 517		.parent_names = gcc_xo_gpll0,
 518		.num_parents = 2,
 519		.ops = &clk_rcg2_ops,
 520	},
 521};
 522
 523static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 524	.cmd_rcgr = 0x070c,
 525	.mnd_width = 16,
 526	.hid_width = 5,
 527	.parent_map = gcc_xo_gpll0_map,
 528	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 529	.clkr.hw.init = &(struct clk_init_data){
 530		.name = "blsp1_uart2_apps_clk_src",
 531		.parent_names = gcc_xo_gpll0,
 532		.num_parents = 2,
 533		.ops = &clk_rcg2_ops,
 534	},
 535};
 536
 537static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 538	.cmd_rcgr = 0x078c,
 539	.mnd_width = 16,
 540	.hid_width = 5,
 541	.parent_map = gcc_xo_gpll0_map,
 542	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 543	.clkr.hw.init = &(struct clk_init_data){
 544		.name = "blsp1_uart3_apps_clk_src",
 545		.parent_names = gcc_xo_gpll0,
 546		.num_parents = 2,
 547		.ops = &clk_rcg2_ops,
 548	},
 549};
 550
 551static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 552	.cmd_rcgr = 0x080c,
 553	.mnd_width = 16,
 554	.hid_width = 5,
 555	.parent_map = gcc_xo_gpll0_map,
 556	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 557	.clkr.hw.init = &(struct clk_init_data){
 558		.name = "blsp1_uart4_apps_clk_src",
 559		.parent_names = gcc_xo_gpll0,
 560		.num_parents = 2,
 561		.ops = &clk_rcg2_ops,
 562	},
 563};
 564
 565static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 566	.cmd_rcgr = 0x088c,
 567	.mnd_width = 16,
 568	.hid_width = 5,
 569	.parent_map = gcc_xo_gpll0_map,
 570	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 571	.clkr.hw.init = &(struct clk_init_data){
 572		.name = "blsp1_uart5_apps_clk_src",
 573		.parent_names = gcc_xo_gpll0,
 574		.num_parents = 2,
 575		.ops = &clk_rcg2_ops,
 576	},
 577};
 578
 579static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 580	.cmd_rcgr = 0x090c,
 581	.mnd_width = 16,
 582	.hid_width = 5,
 583	.parent_map = gcc_xo_gpll0_map,
 584	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 585	.clkr.hw.init = &(struct clk_init_data){
 586		.name = "blsp1_uart6_apps_clk_src",
 587		.parent_names = gcc_xo_gpll0,
 588		.num_parents = 2,
 589		.ops = &clk_rcg2_ops,
 590	},
 591};
 592
 593static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 594	.cmd_rcgr = 0x09a0,
 595	.hid_width = 5,
 596	.parent_map = gcc_xo_gpll0_map,
 597	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 598	.clkr.hw.init = &(struct clk_init_data){
 599		.name = "blsp2_qup1_i2c_apps_clk_src",
 600		.parent_names = gcc_xo_gpll0,
 601		.num_parents = 2,
 602		.ops = &clk_rcg2_ops,
 603	},
 604};
 605
 606static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 607	.cmd_rcgr = 0x098c,
 608	.mnd_width = 8,
 609	.hid_width = 5,
 610	.parent_map = gcc_xo_gpll0_map,
 611	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 612	.clkr.hw.init = &(struct clk_init_data){
 613		.name = "blsp2_qup1_spi_apps_clk_src",
 614		.parent_names = gcc_xo_gpll0,
 615		.num_parents = 2,
 616		.ops = &clk_rcg2_ops,
 617	},
 618};
 619
 620static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 621	.cmd_rcgr = 0x0a20,
 622	.hid_width = 5,
 623	.parent_map = gcc_xo_gpll0_map,
 624	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 625	.clkr.hw.init = &(struct clk_init_data){
 626		.name = "blsp2_qup2_i2c_apps_clk_src",
 627		.parent_names = gcc_xo_gpll0,
 628		.num_parents = 2,
 629		.ops = &clk_rcg2_ops,
 630	},
 631};
 632
 633static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 634	.cmd_rcgr = 0x0a0c,
 635	.mnd_width = 8,
 636	.hid_width = 5,
 637	.parent_map = gcc_xo_gpll0_map,
 638	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 639	.clkr.hw.init = &(struct clk_init_data){
 640		.name = "blsp2_qup2_spi_apps_clk_src",
 641		.parent_names = gcc_xo_gpll0,
 642		.num_parents = 2,
 643		.ops = &clk_rcg2_ops,
 644	},
 645};
 646
 647static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 648	.cmd_rcgr = 0x0aa0,
 649	.hid_width = 5,
 650	.parent_map = gcc_xo_gpll0_map,
 651	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 652	.clkr.hw.init = &(struct clk_init_data){
 653		.name = "blsp2_qup3_i2c_apps_clk_src",
 654		.parent_names = gcc_xo_gpll0,
 655		.num_parents = 2,
 656		.ops = &clk_rcg2_ops,
 657	},
 658};
 659
 660static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 661	.cmd_rcgr = 0x0a8c,
 662	.mnd_width = 8,
 663	.hid_width = 5,
 664	.parent_map = gcc_xo_gpll0_map,
 665	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 666	.clkr.hw.init = &(struct clk_init_data){
 667		.name = "blsp2_qup3_spi_apps_clk_src",
 668		.parent_names = gcc_xo_gpll0,
 669		.num_parents = 2,
 670		.ops = &clk_rcg2_ops,
 671	},
 672};
 673
 674static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 675	.cmd_rcgr = 0x0b20,
 676	.hid_width = 5,
 677	.parent_map = gcc_xo_gpll0_map,
 678	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 679	.clkr.hw.init = &(struct clk_init_data){
 680		.name = "blsp2_qup4_i2c_apps_clk_src",
 681		.parent_names = gcc_xo_gpll0,
 682		.num_parents = 2,
 683		.ops = &clk_rcg2_ops,
 684	},
 685};
 686
 687static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 688	.cmd_rcgr = 0x0b0c,
 689	.mnd_width = 8,
 690	.hid_width = 5,
 691	.parent_map = gcc_xo_gpll0_map,
 692	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 693	.clkr.hw.init = &(struct clk_init_data){
 694		.name = "blsp2_qup4_spi_apps_clk_src",
 695		.parent_names = gcc_xo_gpll0,
 696		.num_parents = 2,
 697		.ops = &clk_rcg2_ops,
 698	},
 699};
 700
 701static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 702	.cmd_rcgr = 0x0ba0,
 703	.hid_width = 5,
 704	.parent_map = gcc_xo_gpll0_map,
 705	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 706	.clkr.hw.init = &(struct clk_init_data){
 707		.name = "blsp2_qup5_i2c_apps_clk_src",
 708		.parent_names = gcc_xo_gpll0,
 709		.num_parents = 2,
 710		.ops = &clk_rcg2_ops,
 711	},
 712};
 713
 714static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 715	.cmd_rcgr = 0x0b8c,
 716	.mnd_width = 8,
 717	.hid_width = 5,
 718	.parent_map = gcc_xo_gpll0_map,
 719	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 720	.clkr.hw.init = &(struct clk_init_data){
 721		.name = "blsp2_qup5_spi_apps_clk_src",
 722		.parent_names = gcc_xo_gpll0,
 723		.num_parents = 2,
 724		.ops = &clk_rcg2_ops,
 725	},
 726};
 727
 728static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 729	.cmd_rcgr = 0x0c20,
 730	.hid_width = 5,
 731	.parent_map = gcc_xo_gpll0_map,
 732	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 733	.clkr.hw.init = &(struct clk_init_data){
 734		.name = "blsp2_qup6_i2c_apps_clk_src",
 735		.parent_names = gcc_xo_gpll0,
 736		.num_parents = 2,
 737		.ops = &clk_rcg2_ops,
 738	},
 739};
 740
 741static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 742	.cmd_rcgr = 0x0c0c,
 743	.mnd_width = 8,
 744	.hid_width = 5,
 745	.parent_map = gcc_xo_gpll0_map,
 746	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 747	.clkr.hw.init = &(struct clk_init_data){
 748		.name = "blsp2_qup6_spi_apps_clk_src",
 749		.parent_names = gcc_xo_gpll0,
 750		.num_parents = 2,
 751		.ops = &clk_rcg2_ops,
 752	},
 753};
 754
 755static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 756	.cmd_rcgr = 0x09cc,
 757	.mnd_width = 16,
 758	.hid_width = 5,
 759	.parent_map = gcc_xo_gpll0_map,
 760	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 761	.clkr.hw.init = &(struct clk_init_data){
 762		.name = "blsp2_uart1_apps_clk_src",
 763		.parent_names = gcc_xo_gpll0,
 764		.num_parents = 2,
 765		.ops = &clk_rcg2_ops,
 766	},
 767};
 768
 769static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 770	.cmd_rcgr = 0x0a4c,
 771	.mnd_width = 16,
 772	.hid_width = 5,
 773	.parent_map = gcc_xo_gpll0_map,
 774	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 775	.clkr.hw.init = &(struct clk_init_data){
 776		.name = "blsp2_uart2_apps_clk_src",
 777		.parent_names = gcc_xo_gpll0,
 778		.num_parents = 2,
 779		.ops = &clk_rcg2_ops,
 780	},
 781};
 782
 783static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 784	.cmd_rcgr = 0x0acc,
 785	.mnd_width = 16,
 786	.hid_width = 5,
 787	.parent_map = gcc_xo_gpll0_map,
 788	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 789	.clkr.hw.init = &(struct clk_init_data){
 790		.name = "blsp2_uart3_apps_clk_src",
 791		.parent_names = gcc_xo_gpll0,
 792		.num_parents = 2,
 793		.ops = &clk_rcg2_ops,
 794	},
 795};
 796
 797static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 798	.cmd_rcgr = 0x0b4c,
 799	.mnd_width = 16,
 800	.hid_width = 5,
 801	.parent_map = gcc_xo_gpll0_map,
 802	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 803	.clkr.hw.init = &(struct clk_init_data){
 804		.name = "blsp2_uart4_apps_clk_src",
 805		.parent_names = gcc_xo_gpll0,
 806		.num_parents = 2,
 807		.ops = &clk_rcg2_ops,
 808	},
 809};
 810
 811static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 812	.cmd_rcgr = 0x0bcc,
 813	.mnd_width = 16,
 814	.hid_width = 5,
 815	.parent_map = gcc_xo_gpll0_map,
 816	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 817	.clkr.hw.init = &(struct clk_init_data){
 818		.name = "blsp2_uart5_apps_clk_src",
 819		.parent_names = gcc_xo_gpll0,
 820		.num_parents = 2,
 821		.ops = &clk_rcg2_ops,
 822	},
 823};
 824
 825static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 826	.cmd_rcgr = 0x0c4c,
 827	.mnd_width = 16,
 828	.hid_width = 5,
 829	.parent_map = gcc_xo_gpll0_map,
 830	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 831	.clkr.hw.init = &(struct clk_init_data){
 832		.name = "blsp2_uart6_apps_clk_src",
 833		.parent_names = gcc_xo_gpll0,
 834		.num_parents = 2,
 835		.ops = &clk_rcg2_ops,
 836	},
 837};
 838
 839static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
 840	F(50000000, P_GPLL0, 12, 0, 0),
 841	F(85710000, P_GPLL0, 7, 0, 0),
 842	F(100000000, P_GPLL0, 6, 0, 0),
 843	F(171430000, P_GPLL0, 3.5, 0, 0),
 844	{ }
 845};
 846
 847static struct clk_rcg2 ce1_clk_src = {
 848	.cmd_rcgr = 0x1050,
 849	.hid_width = 5,
 850	.parent_map = gcc_xo_gpll0_map,
 851	.freq_tbl = ftbl_gcc_ce1_clk,
 852	.clkr.hw.init = &(struct clk_init_data){
 853		.name = "ce1_clk_src",
 854		.parent_names = gcc_xo_gpll0,
 855		.num_parents = 2,
 856		.ops = &clk_rcg2_ops,
 857	},
 858};
 859
 860static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
 861	F(50000000, P_GPLL0, 12, 0, 0),
 862	F(85710000, P_GPLL0, 7, 0, 0),
 863	F(100000000, P_GPLL0, 6, 0, 0),
 864	F(171430000, P_GPLL0, 3.5, 0, 0),
 865	{ }
 866};
 867
 868static struct clk_rcg2 ce2_clk_src = {
 869	.cmd_rcgr = 0x1090,
 870	.hid_width = 5,
 871	.parent_map = gcc_xo_gpll0_map,
 872	.freq_tbl = ftbl_gcc_ce2_clk,
 873	.clkr.hw.init = &(struct clk_init_data){
 874		.name = "ce2_clk_src",
 875		.parent_names = gcc_xo_gpll0,
 876		.num_parents = 2,
 877		.ops = &clk_rcg2_ops,
 878	},
 879};
 880
 881static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
 882	F(50000000, P_GPLL0, 12, 0, 0),
 883	F(85710000, P_GPLL0, 7, 0, 0),
 884	F(100000000, P_GPLL0, 6, 0, 0),
 885	F(171430000, P_GPLL0, 3.5, 0, 0),
 886	{ }
 887};
 888
 889static struct clk_rcg2 ce3_clk_src = {
 890	.cmd_rcgr = 0x1d10,
 891	.hid_width = 5,
 892	.parent_map = gcc_xo_gpll0_map,
 893	.freq_tbl = ftbl_gcc_ce3_clk,
 894	.clkr.hw.init = &(struct clk_init_data){
 895		.name = "ce3_clk_src",
 896		.parent_names = gcc_xo_gpll0,
 897		.num_parents = 2,
 898		.ops = &clk_rcg2_ops,
 899	},
 900};
 901
 902static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 903	F(19200000, P_XO, 1, 0, 0),
 904	F(100000000, P_GPLL0, 6, 0, 0),
 905	F(200000000, P_GPLL0, 3, 0, 0),
 906	{ }
 907};
 908
 909static struct clk_rcg2 gp1_clk_src = {
 910	.cmd_rcgr = 0x1904,
 911	.mnd_width = 8,
 912	.hid_width = 5,
 913	.parent_map = gcc_xo_gpll0_map,
 914	.freq_tbl = ftbl_gcc_gp_clk,
 915	.clkr.hw.init = &(struct clk_init_data){
 916		.name = "gp1_clk_src",
 917		.parent_names = gcc_xo_gpll0,
 918		.num_parents = 2,
 919		.ops = &clk_rcg2_ops,
 920	},
 921};
 922
 923static struct clk_rcg2 gp2_clk_src = {
 924	.cmd_rcgr = 0x1944,
 925	.mnd_width = 8,
 926	.hid_width = 5,
 927	.parent_map = gcc_xo_gpll0_map,
 928	.freq_tbl = ftbl_gcc_gp_clk,
 929	.clkr.hw.init = &(struct clk_init_data){
 930		.name = "gp2_clk_src",
 931		.parent_names = gcc_xo_gpll0,
 932		.num_parents = 2,
 933		.ops = &clk_rcg2_ops,
 934	},
 935};
 936
 937static struct clk_rcg2 gp3_clk_src = {
 938	.cmd_rcgr = 0x1984,
 939	.mnd_width = 8,
 940	.hid_width = 5,
 941	.parent_map = gcc_xo_gpll0_map,
 942	.freq_tbl = ftbl_gcc_gp_clk,
 943	.clkr.hw.init = &(struct clk_init_data){
 944		.name = "gp3_clk_src",
 945		.parent_names = gcc_xo_gpll0,
 946		.num_parents = 2,
 947		.ops = &clk_rcg2_ops,
 948	},
 949};
 950
 951static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
 952	F(1010000, P_XO, 1, 1, 19),
 953	{ }
 954};
 955
 956static struct clk_rcg2 pcie_0_aux_clk_src = {
 957	.cmd_rcgr = 0x1b2c,
 958	.mnd_width = 16,
 959	.hid_width = 5,
 960	.parent_map = gcc_xo_pcie_sleep_map,
 961	.freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
 962	.clkr.hw.init = &(struct clk_init_data){
 963		.name = "pcie_0_aux_clk_src",
 964		.parent_names = gcc_xo_pcie_sleep,
 965		.num_parents = 2,
 966		.ops = &clk_rcg2_ops,
 967	},
 968};
 969
 970static struct clk_rcg2 pcie_1_aux_clk_src = {
 971	.cmd_rcgr = 0x1bac,
 972	.mnd_width = 16,
 973	.hid_width = 5,
 974	.parent_map = gcc_xo_pcie_sleep_map,
 975	.freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
 976	.clkr.hw.init = &(struct clk_init_data){
 977		.name = "pcie_1_aux_clk_src",
 978		.parent_names = gcc_xo_pcie_sleep,
 979		.num_parents = 2,
 980		.ops = &clk_rcg2_ops,
 981	},
 982};
 983
 984static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
 985	F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
 986	F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
 987	{ }
 988};
 989
 990static struct clk_rcg2 pcie_0_pipe_clk_src = {
 991	.cmd_rcgr = 0x1b18,
 992	.hid_width = 5,
 993	.parent_map = gcc_xo_pcie_map,
 994	.freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
 995	.clkr.hw.init = &(struct clk_init_data){
 996		.name = "pcie_0_pipe_clk_src",
 997		.parent_names = gcc_xo_pcie,
 998		.num_parents = 2,
 999		.ops = &clk_rcg2_ops,
1000	},
1001};
1002
1003static struct clk_rcg2 pcie_1_pipe_clk_src = {
1004	.cmd_rcgr = 0x1b98,
1005	.hid_width = 5,
1006	.parent_map = gcc_xo_pcie_map,
1007	.freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1008	.clkr.hw.init = &(struct clk_init_data){
1009		.name = "pcie_1_pipe_clk_src",
1010		.parent_names = gcc_xo_pcie,
1011		.num_parents = 2,
1012		.ops = &clk_rcg2_ops,
1013	},
1014};
1015
1016static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1017	F(60000000, P_GPLL0, 10, 0, 0),
1018	{ }
1019};
1020
1021static struct clk_rcg2 pdm2_clk_src = {
1022	.cmd_rcgr = 0x0cd0,
1023	.hid_width = 5,
1024	.parent_map = gcc_xo_gpll0_map,
1025	.freq_tbl = ftbl_gcc_pdm2_clk,
1026	.clkr.hw.init = &(struct clk_init_data){
1027		.name = "pdm2_clk_src",
1028		.parent_names = gcc_xo_gpll0,
1029		.num_parents = 2,
1030		.ops = &clk_rcg2_ops,
1031	},
1032};
1033
1034static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
1035	F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1036	F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1037	F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1038	{ }
1039};
1040
1041static struct clk_rcg2 sata_asic0_clk_src = {
1042	.cmd_rcgr = 0x1c94,
1043	.hid_width = 5,
1044	.parent_map = gcc_xo_sata_asic0_map,
1045	.freq_tbl = ftbl_gcc_sata_asic0_clk,
1046	.clkr.hw.init = &(struct clk_init_data){
1047		.name = "sata_asic0_clk_src",
1048		.parent_names = gcc_xo_sata_asic0,
1049		.num_parents = 2,
1050		.ops = &clk_rcg2_ops,
1051	},
1052};
1053
1054static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
1055	F(19200000, P_XO, 1, 0, 0),
1056	F(50000000, P_GPLL0, 12, 0, 0),
1057	F(100000000, P_GPLL0, 6, 0, 0),
1058	{ }
1059};
1060
1061static struct clk_rcg2 sata_pmalive_clk_src = {
1062	.cmd_rcgr = 0x1c80,
1063	.hid_width = 5,
1064	.parent_map = gcc_xo_gpll0_map,
1065	.freq_tbl = ftbl_gcc_sata_pmalive_clk,
1066	.clkr.hw.init = &(struct clk_init_data){
1067		.name = "sata_pmalive_clk_src",
1068		.parent_names = gcc_xo_gpll0,
1069		.num_parents = 2,
1070		.ops = &clk_rcg2_ops,
1071	},
1072};
1073
1074static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
1075	F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1076	F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1077	F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1078	{ }
1079};
1080
1081static struct clk_rcg2 sata_rx_clk_src = {
1082	.cmd_rcgr = 0x1ca8,
1083	.hid_width = 5,
1084	.parent_map = gcc_xo_sata_rx_map,
1085	.freq_tbl = ftbl_gcc_sata_rx_clk,
1086	.clkr.hw.init = &(struct clk_init_data){
1087		.name = "sata_rx_clk_src",
1088		.parent_names = gcc_xo_sata_rx,
1089		.num_parents = 2,
1090		.ops = &clk_rcg2_ops,
1091	},
1092};
1093
1094static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
1095	F(100000000, P_GPLL0, 6, 0, 0),
1096	{ }
1097};
1098
1099static struct clk_rcg2 sata_rx_oob_clk_src = {
1100	.cmd_rcgr = 0x1c5c,
1101	.hid_width = 5,
1102	.parent_map = gcc_xo_gpll0_map,
1103	.freq_tbl = ftbl_gcc_sata_rx_oob_clk,
1104	.clkr.hw.init = &(struct clk_init_data){
1105		.name = "sata_rx_oob_clk_src",
1106		.parent_names = gcc_xo_gpll0,
1107		.num_parents = 2,
1108		.ops = &clk_rcg2_ops,
1109	},
1110};
1111
1112static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
1113	F(144000, P_XO, 16, 3, 25),
1114	F(400000, P_XO, 12, 1, 4),
1115	F(20000000, P_GPLL0, 15, 1, 2),
1116	F(25000000, P_GPLL0, 12, 1, 2),
1117	F(50000000, P_GPLL0, 12, 0, 0),
1118	F(100000000, P_GPLL0, 6, 0, 0),
1119	F(192000000, P_GPLL4, 4, 0, 0),
1120	F(200000000, P_GPLL0, 3, 0, 0),
1121	F(384000000, P_GPLL4, 2, 0, 0),
1122	{ }
1123};
1124
1125static struct clk_rcg2 sdcc1_apps_clk_src = {
1126	.cmd_rcgr = 0x04d0,
1127	.mnd_width = 8,
1128	.hid_width = 5,
1129	.parent_map = gcc_xo_gpll0_gpll4_map,
1130	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1131	.clkr.hw.init = &(struct clk_init_data){
1132		.name = "sdcc1_apps_clk_src",
1133		.parent_names = gcc_xo_gpll0_gpll4,
1134		.num_parents = 3,
1135		.ops = &clk_rcg2_floor_ops,
1136	},
1137};
1138
1139static struct clk_rcg2 sdcc2_apps_clk_src = {
1140	.cmd_rcgr = 0x0510,
1141	.mnd_width = 8,
1142	.hid_width = 5,
1143	.parent_map = gcc_xo_gpll0_map,
1144	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1145	.clkr.hw.init = &(struct clk_init_data){
1146		.name = "sdcc2_apps_clk_src",
1147		.parent_names = gcc_xo_gpll0,
1148		.num_parents = 2,
1149		.ops = &clk_rcg2_floor_ops,
1150	},
1151};
1152
1153static struct clk_rcg2 sdcc3_apps_clk_src = {
1154	.cmd_rcgr = 0x0550,
1155	.mnd_width = 8,
1156	.hid_width = 5,
1157	.parent_map = gcc_xo_gpll0_map,
1158	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1159	.clkr.hw.init = &(struct clk_init_data){
1160		.name = "sdcc3_apps_clk_src",
1161		.parent_names = gcc_xo_gpll0,
1162		.num_parents = 2,
1163		.ops = &clk_rcg2_floor_ops,
1164	},
1165};
1166
1167static struct clk_rcg2 sdcc4_apps_clk_src = {
1168	.cmd_rcgr = 0x0590,
1169	.mnd_width = 8,
1170	.hid_width = 5,
1171	.parent_map = gcc_xo_gpll0_map,
1172	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1173	.clkr.hw.init = &(struct clk_init_data){
1174		.name = "sdcc4_apps_clk_src",
1175		.parent_names = gcc_xo_gpll0,
1176		.num_parents = 2,
1177		.ops = &clk_rcg2_floor_ops,
1178	},
1179};
1180
1181static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
1182	F(105000, P_XO, 2, 1, 91),
1183	{ }
1184};
1185
1186static struct clk_rcg2 tsif_ref_clk_src = {
1187	.cmd_rcgr = 0x0d90,
1188	.mnd_width = 8,
1189	.hid_width = 5,
1190	.parent_map = gcc_xo_gpll0_map,
1191	.freq_tbl = ftbl_gcc_tsif_ref_clk,
1192	.clkr.hw.init = &(struct clk_init_data){
1193		.name = "tsif_ref_clk_src",
1194		.parent_names = gcc_xo_gpll0,
1195		.num_parents = 2,
1196		.ops = &clk_rcg2_ops,
1197	},
1198};
1199
1200static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1201	F(60000000, P_GPLL0, 10, 0, 0),
1202	{ }
1203};
1204
1205static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1206	.cmd_rcgr = 0x03e8,
1207	.hid_width = 5,
1208	.parent_map = gcc_xo_gpll0_map,
1209	.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1210	.clkr.hw.init = &(struct clk_init_data){
1211		.name = "usb30_mock_utmi_clk_src",
1212		.parent_names = gcc_xo_gpll0,
1213		.num_parents = 2,
1214		.ops = &clk_rcg2_ops,
1215	},
1216};
1217
1218static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1219	F(125000000, P_GPLL0, 1, 5, 24),
1220	{ }
1221};
1222
1223static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1224	.cmd_rcgr = 0x1be8,
1225	.hid_width = 5,
1226	.parent_map = gcc_xo_gpll0_map,
1227	.freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1228	.clkr.hw.init = &(struct clk_init_data){
1229		.name = "usb30_sec_mock_utmi_clk_src",
1230		.parent_names = gcc_xo_gpll0,
1231		.num_parents = 2,
1232		.ops = &clk_rcg2_ops,
1233	},
1234};
1235
1236static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1237	F(75000000, P_GPLL0, 8, 0, 0),
1238	{ }
1239};
1240
1241static struct clk_rcg2 usb_hs_system_clk_src = {
1242	.cmd_rcgr = 0x0490,
1243	.hid_width = 5,
1244	.parent_map = gcc_xo_gpll0_map,
1245	.freq_tbl = ftbl_gcc_usb_hs_system_clk,
1246	.clkr.hw.init = &(struct clk_init_data){
1247		.name = "usb_hs_system_clk_src",
1248		.parent_names = gcc_xo_gpll0,
1249		.num_parents = 2,
1250		.ops = &clk_rcg2_ops,
1251	},
1252};
1253
1254static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1255	F(480000000, P_GPLL1, 1, 0, 0),
1256	{ }
1257};
1258
1259static const struct parent_map usb_hsic_clk_src_map[] = {
1260	{ P_XO, 0 },
1261	{ P_GPLL1, 4 }
1262};
1263
1264static struct clk_rcg2 usb_hsic_clk_src = {
1265	.cmd_rcgr = 0x0440,
1266	.hid_width = 5,
1267	.parent_map = usb_hsic_clk_src_map,
1268	.freq_tbl = ftbl_gcc_usb_hsic_clk,
1269	.clkr.hw.init = &(struct clk_init_data){
1270		.name = "usb_hsic_clk_src",
1271		.parent_names = (const char *[]){
1272			"xo",
1273			"gpll1_vote",
1274		},
1275		.num_parents = 2,
1276		.ops = &clk_rcg2_ops,
1277	},
1278};
1279
1280static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1281	F(60000000, P_GPLL1, 8, 0, 0),
1282	{ }
1283};
1284
1285static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1286	.cmd_rcgr = 0x046c,
1287	.mnd_width = 8,
1288	.hid_width = 5,
1289	.parent_map = usb_hsic_clk_src_map,
1290	.freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1291	.clkr.hw.init = &(struct clk_init_data){
1292		.name = "usb_hsic_ahb_clk_src",
1293		.parent_names = (const char *[]){
1294			"xo",
1295			"gpll1_vote",
1296		},
1297		.num_parents = 2,
1298		.ops = &clk_rcg2_ops,
1299	},
1300};
1301
1302static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1303	F(9600000, P_XO, 2, 0, 0),
1304	{ }
1305};
1306
1307static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1308	.cmd_rcgr = 0x0458,
1309	.hid_width = 5,
1310	.parent_map = gcc_xo_gpll0_map,
1311	.freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1312	.clkr.hw.init = &(struct clk_init_data){
1313		.name = "usb_hsic_io_cal_clk_src",
1314		.parent_names = gcc_xo_gpll0,
1315		.num_parents = 1,
1316		.ops = &clk_rcg2_ops,
1317	},
1318};
1319
1320static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1321	.halt_reg = 0x1f14,
1322	.clkr = {
1323		.enable_reg = 0x1f14,
1324		.enable_mask = BIT(0),
1325		.hw.init = &(struct clk_init_data){
1326			.name = "gcc_usb_hsic_mock_utmi_clk",
1327			.parent_names = (const char *[]){
1328				"usb_hsic_mock_utmi_clk_src",
1329			},
1330			.num_parents = 1,
1331			.flags = CLK_SET_RATE_PARENT,
1332			.ops = &clk_branch2_ops,
1333		},
1334	},
1335};
1336
1337static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1338	F(60000000, P_GPLL0, 10, 0, 0),
1339	{ }
1340};
1341
1342static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1343	.cmd_rcgr = 0x1f00,
1344	.hid_width = 5,
1345	.parent_map = gcc_xo_gpll0_map,
1346	.freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1347	.clkr.hw.init = &(struct clk_init_data){
1348		.name = "usb_hsic_mock_utmi_clk_src",
1349		.parent_names = gcc_xo_gpll0,
1350		.num_parents = 1,
1351		.ops = &clk_rcg2_ops,
1352	},
1353};
1354
1355static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1356	F(75000000, P_GPLL0, 8, 0, 0),
1357	{ }
1358};
1359
1360static struct clk_rcg2 usb_hsic_system_clk_src = {
1361	.cmd_rcgr = 0x041c,
1362	.hid_width = 5,
1363	.parent_map = gcc_xo_gpll0_map,
1364	.freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1365	.clkr.hw.init = &(struct clk_init_data){
1366		.name = "usb_hsic_system_clk_src",
1367		.parent_names = gcc_xo_gpll0,
1368		.num_parents = 2,
1369		.ops = &clk_rcg2_ops,
1370	},
1371};
1372
1373static struct clk_branch gcc_bam_dma_ahb_clk = {
1374	.halt_reg = 0x0d44,
1375	.halt_check = BRANCH_HALT_VOTED,
1376	.clkr = {
1377		.enable_reg = 0x1484,
1378		.enable_mask = BIT(12),
1379		.hw.init = &(struct clk_init_data){
1380			.name = "gcc_bam_dma_ahb_clk",
1381			.parent_names = (const char *[]){
1382				"periph_noc_clk_src",
1383			},
1384			.num_parents = 1,
1385			.ops = &clk_branch2_ops,
1386		},
1387	},
1388};
1389
1390static struct clk_branch gcc_blsp1_ahb_clk = {
1391	.halt_reg = 0x05c4,
1392	.halt_check = BRANCH_HALT_VOTED,
1393	.clkr = {
1394		.enable_reg = 0x1484,
1395		.enable_mask = BIT(17),
1396		.hw.init = &(struct clk_init_data){
1397			.name = "gcc_blsp1_ahb_clk",
1398			.parent_names = (const char *[]){
1399				"periph_noc_clk_src",
1400			},
1401			.num_parents = 1,
1402			.ops = &clk_branch2_ops,
1403		},
1404	},
1405};
1406
1407static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1408	.halt_reg = 0x0648,
1409	.clkr = {
1410		.enable_reg = 0x0648,
1411		.enable_mask = BIT(0),
1412		.hw.init = &(struct clk_init_data){
1413			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1414			.parent_names = (const char *[]){
1415				"blsp1_qup1_i2c_apps_clk_src",
1416			},
1417			.num_parents = 1,
1418			.flags = CLK_SET_RATE_PARENT,
1419			.ops = &clk_branch2_ops,
1420		},
1421	},
1422};
1423
1424static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1425	.halt_reg = 0x0644,
1426	.clkr = {
1427		.enable_reg = 0x0644,
1428		.enable_mask = BIT(0),
1429		.hw.init = &(struct clk_init_data){
1430			.name = "gcc_blsp1_qup1_spi_apps_clk",
1431			.parent_names = (const char *[]){
1432				"blsp1_qup1_spi_apps_clk_src",
1433			},
1434			.num_parents = 1,
1435			.flags = CLK_SET_RATE_PARENT,
1436			.ops = &clk_branch2_ops,
1437		},
1438	},
1439};
1440
1441static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1442	.halt_reg = 0x06c8,
1443	.clkr = {
1444		.enable_reg = 0x06c8,
1445		.enable_mask = BIT(0),
1446		.hw.init = &(struct clk_init_data){
1447			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1448			.parent_names = (const char *[]){
1449				"blsp1_qup2_i2c_apps_clk_src",
1450			},
1451			.num_parents = 1,
1452			.flags = CLK_SET_RATE_PARENT,
1453			.ops = &clk_branch2_ops,
1454		},
1455	},
1456};
1457
1458static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1459	.halt_reg = 0x06c4,
1460	.clkr = {
1461		.enable_reg = 0x06c4,
1462		.enable_mask = BIT(0),
1463		.hw.init = &(struct clk_init_data){
1464			.name = "gcc_blsp1_qup2_spi_apps_clk",
1465			.parent_names = (const char *[]){
1466				"blsp1_qup2_spi_apps_clk_src",
1467			},
1468			.num_parents = 1,
1469			.flags = CLK_SET_RATE_PARENT,
1470			.ops = &clk_branch2_ops,
1471		},
1472	},
1473};
1474
1475static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1476	.halt_reg = 0x0748,
1477	.clkr = {
1478		.enable_reg = 0x0748,
1479		.enable_mask = BIT(0),
1480		.hw.init = &(struct clk_init_data){
1481			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1482			.parent_names = (const char *[]){
1483				"blsp1_qup3_i2c_apps_clk_src",
1484			},
1485			.num_parents = 1,
1486			.flags = CLK_SET_RATE_PARENT,
1487			.ops = &clk_branch2_ops,
1488		},
1489	},
1490};
1491
1492static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1493	.halt_reg = 0x0744,
1494	.clkr = {
1495		.enable_reg = 0x0744,
1496		.enable_mask = BIT(0),
1497		.hw.init = &(struct clk_init_data){
1498			.name = "gcc_blsp1_qup3_spi_apps_clk",
1499			.parent_names = (const char *[]){
1500				"blsp1_qup3_spi_apps_clk_src",
1501			},
1502			.num_parents = 1,
1503			.flags = CLK_SET_RATE_PARENT,
1504			.ops = &clk_branch2_ops,
1505		},
1506	},
1507};
1508
1509static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1510	.halt_reg = 0x07c8,
1511	.clkr = {
1512		.enable_reg = 0x07c8,
1513		.enable_mask = BIT(0),
1514		.hw.init = &(struct clk_init_data){
1515			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1516			.parent_names = (const char *[]){
1517				"blsp1_qup4_i2c_apps_clk_src",
1518			},
1519			.num_parents = 1,
1520			.flags = CLK_SET_RATE_PARENT,
1521			.ops = &clk_branch2_ops,
1522		},
1523	},
1524};
1525
1526static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1527	.halt_reg = 0x07c4,
1528	.clkr = {
1529		.enable_reg = 0x07c4,
1530		.enable_mask = BIT(0),
1531		.hw.init = &(struct clk_init_data){
1532			.name = "gcc_blsp1_qup4_spi_apps_clk",
1533			.parent_names = (const char *[]){
1534				"blsp1_qup4_spi_apps_clk_src",
1535			},
1536			.num_parents = 1,
1537			.flags = CLK_SET_RATE_PARENT,
1538			.ops = &clk_branch2_ops,
1539		},
1540	},
1541};
1542
1543static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1544	.halt_reg = 0x0848,
1545	.clkr = {
1546		.enable_reg = 0x0848,
1547		.enable_mask = BIT(0),
1548		.hw.init = &(struct clk_init_data){
1549			.name = "gcc_blsp1_qup5_i2c_apps_clk",
1550			.parent_names = (const char *[]){
1551				"blsp1_qup5_i2c_apps_clk_src",
1552			},
1553			.num_parents = 1,
1554			.flags = CLK_SET_RATE_PARENT,
1555			.ops = &clk_branch2_ops,
1556		},
1557	},
1558};
1559
1560static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1561	.halt_reg = 0x0844,
1562	.clkr = {
1563		.enable_reg = 0x0844,
1564		.enable_mask = BIT(0),
1565		.hw.init = &(struct clk_init_data){
1566			.name = "gcc_blsp1_qup5_spi_apps_clk",
1567			.parent_names = (const char *[]){
1568				"blsp1_qup5_spi_apps_clk_src",
1569			},
1570			.num_parents = 1,
1571			.flags = CLK_SET_RATE_PARENT,
1572			.ops = &clk_branch2_ops,
1573		},
1574	},
1575};
1576
1577static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1578	.halt_reg = 0x08c8,
1579	.clkr = {
1580		.enable_reg = 0x08c8,
1581		.enable_mask = BIT(0),
1582		.hw.init = &(struct clk_init_data){
1583			.name = "gcc_blsp1_qup6_i2c_apps_clk",
1584			.parent_names = (const char *[]){
1585				"blsp1_qup6_i2c_apps_clk_src",
1586			},
1587			.num_parents = 1,
1588			.flags = CLK_SET_RATE_PARENT,
1589			.ops = &clk_branch2_ops,
1590		},
1591	},
1592};
1593
1594static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1595	.halt_reg = 0x08c4,
1596	.clkr = {
1597		.enable_reg = 0x08c4,
1598		.enable_mask = BIT(0),
1599		.hw.init = &(struct clk_init_data){
1600			.name = "gcc_blsp1_qup6_spi_apps_clk",
1601			.parent_names = (const char *[]){
1602				"blsp1_qup6_spi_apps_clk_src",
1603			},
1604			.num_parents = 1,
1605			.flags = CLK_SET_RATE_PARENT,
1606			.ops = &clk_branch2_ops,
1607		},
1608	},
1609};
1610
1611static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1612	.halt_reg = 0x0684,
1613	.clkr = {
1614		.enable_reg = 0x0684,
1615		.enable_mask = BIT(0),
1616		.hw.init = &(struct clk_init_data){
1617			.name = "gcc_blsp1_uart1_apps_clk",
1618			.parent_names = (const char *[]){
1619				"blsp1_uart1_apps_clk_src",
1620			},
1621			.num_parents = 1,
1622			.flags = CLK_SET_RATE_PARENT,
1623			.ops = &clk_branch2_ops,
1624		},
1625	},
1626};
1627
1628static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1629	.halt_reg = 0x0704,
1630	.clkr = {
1631		.enable_reg = 0x0704,
1632		.enable_mask = BIT(0),
1633		.hw.init = &(struct clk_init_data){
1634			.name = "gcc_blsp1_uart2_apps_clk",
1635			.parent_names = (const char *[]){
1636				"blsp1_uart2_apps_clk_src",
1637			},
1638			.num_parents = 1,
1639			.flags = CLK_SET_RATE_PARENT,
1640			.ops = &clk_branch2_ops,
1641		},
1642	},
1643};
1644
1645static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1646	.halt_reg = 0x0784,
1647	.clkr = {
1648		.enable_reg = 0x0784,
1649		.enable_mask = BIT(0),
1650		.hw.init = &(struct clk_init_data){
1651			.name = "gcc_blsp1_uart3_apps_clk",
1652			.parent_names = (const char *[]){
1653				"blsp1_uart3_apps_clk_src",
1654			},
1655			.num_parents = 1,
1656			.flags = CLK_SET_RATE_PARENT,
1657			.ops = &clk_branch2_ops,
1658		},
1659	},
1660};
1661
1662static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1663	.halt_reg = 0x0804,
1664	.clkr = {
1665		.enable_reg = 0x0804,
1666		.enable_mask = BIT(0),
1667		.hw.init = &(struct clk_init_data){
1668			.name = "gcc_blsp1_uart4_apps_clk",
1669			.parent_names = (const char *[]){
1670				"blsp1_uart4_apps_clk_src",
1671			},
1672			.num_parents = 1,
1673			.flags = CLK_SET_RATE_PARENT,
1674			.ops = &clk_branch2_ops,
1675		},
1676	},
1677};
1678
1679static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1680	.halt_reg = 0x0884,
1681	.clkr = {
1682		.enable_reg = 0x0884,
1683		.enable_mask = BIT(0),
1684		.hw.init = &(struct clk_init_data){
1685			.name = "gcc_blsp1_uart5_apps_clk",
1686			.parent_names = (const char *[]){
1687				"blsp1_uart5_apps_clk_src",
1688			},
1689			.num_parents = 1,
1690			.flags = CLK_SET_RATE_PARENT,
1691			.ops = &clk_branch2_ops,
1692		},
1693	},
1694};
1695
1696static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1697	.halt_reg = 0x0904,
1698	.clkr = {
1699		.enable_reg = 0x0904,
1700		.enable_mask = BIT(0),
1701		.hw.init = &(struct clk_init_data){
1702			.name = "gcc_blsp1_uart6_apps_clk",
1703			.parent_names = (const char *[]){
1704				"blsp1_uart6_apps_clk_src",
1705			},
1706			.num_parents = 1,
1707			.flags = CLK_SET_RATE_PARENT,
1708			.ops = &clk_branch2_ops,
1709		},
1710	},
1711};
1712
1713static struct clk_branch gcc_blsp2_ahb_clk = {
1714	.halt_reg = 0x0944,
1715	.halt_check = BRANCH_HALT_VOTED,
1716	.clkr = {
1717		.enable_reg = 0x1484,
1718		.enable_mask = BIT(15),
1719		.hw.init = &(struct clk_init_data){
1720			.name = "gcc_blsp2_ahb_clk",
1721			.parent_names = (const char *[]){
1722				"periph_noc_clk_src",
1723			},
1724			.num_parents = 1,
1725			.ops = &clk_branch2_ops,
1726		},
1727	},
1728};
1729
1730static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1731	.halt_reg = 0x0988,
1732	.clkr = {
1733		.enable_reg = 0x0988,
1734		.enable_mask = BIT(0),
1735		.hw.init = &(struct clk_init_data){
1736			.name = "gcc_blsp2_qup1_i2c_apps_clk",
1737			.parent_names = (const char *[]){
1738				"blsp2_qup1_i2c_apps_clk_src",
1739			},
1740			.num_parents = 1,
1741			.flags = CLK_SET_RATE_PARENT,
1742			.ops = &clk_branch2_ops,
1743		},
1744	},
1745};
1746
1747static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1748	.halt_reg = 0x0984,
1749	.clkr = {
1750		.enable_reg = 0x0984,
1751		.enable_mask = BIT(0),
1752		.hw.init = &(struct clk_init_data){
1753			.name = "gcc_blsp2_qup1_spi_apps_clk",
1754			.parent_names = (const char *[]){
1755				"blsp2_qup1_spi_apps_clk_src",
1756			},
1757			.num_parents = 1,
1758			.flags = CLK_SET_RATE_PARENT,
1759			.ops = &clk_branch2_ops,
1760		},
1761	},
1762};
1763
1764static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1765	.halt_reg = 0x0a08,
1766	.clkr = {
1767		.enable_reg = 0x0a08,
1768		.enable_mask = BIT(0),
1769		.hw.init = &(struct clk_init_data){
1770			.name = "gcc_blsp2_qup2_i2c_apps_clk",
1771			.parent_names = (const char *[]){
1772				"blsp2_qup2_i2c_apps_clk_src",
1773			},
1774			.num_parents = 1,
1775			.flags = CLK_SET_RATE_PARENT,
1776			.ops = &clk_branch2_ops,
1777		},
1778	},
1779};
1780
1781static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1782	.halt_reg = 0x0a04,
1783	.clkr = {
1784		.enable_reg = 0x0a04,
1785		.enable_mask = BIT(0),
1786		.hw.init = &(struct clk_init_data){
1787			.name = "gcc_blsp2_qup2_spi_apps_clk",
1788			.parent_names = (const char *[]){
1789				"blsp2_qup2_spi_apps_clk_src",
1790			},
1791			.num_parents = 1,
1792			.flags = CLK_SET_RATE_PARENT,
1793			.ops = &clk_branch2_ops,
1794		},
1795	},
1796};
1797
1798static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1799	.halt_reg = 0x0a88,
1800	.clkr = {
1801		.enable_reg = 0x0a88,
1802		.enable_mask = BIT(0),
1803		.hw.init = &(struct clk_init_data){
1804			.name = "gcc_blsp2_qup3_i2c_apps_clk",
1805			.parent_names = (const char *[]){
1806				"blsp2_qup3_i2c_apps_clk_src",
1807			},
1808			.num_parents = 1,
1809			.flags = CLK_SET_RATE_PARENT,
1810			.ops = &clk_branch2_ops,
1811		},
1812	},
1813};
1814
1815static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1816	.halt_reg = 0x0a84,
1817	.clkr = {
1818		.enable_reg = 0x0a84,
1819		.enable_mask = BIT(0),
1820		.hw.init = &(struct clk_init_data){
1821			.name = "gcc_blsp2_qup3_spi_apps_clk",
1822			.parent_names = (const char *[]){
1823				"blsp2_qup3_spi_apps_clk_src",
1824			},
1825			.num_parents = 1,
1826			.flags = CLK_SET_RATE_PARENT,
1827			.ops = &clk_branch2_ops,
1828		},
1829	},
1830};
1831
1832static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1833	.halt_reg = 0x0b08,
1834	.clkr = {
1835		.enable_reg = 0x0b08,
1836		.enable_mask = BIT(0),
1837		.hw.init = &(struct clk_init_data){
1838			.name = "gcc_blsp2_qup4_i2c_apps_clk",
1839			.parent_names = (const char *[]){
1840				"blsp2_qup4_i2c_apps_clk_src",
1841			},
1842			.num_parents = 1,
1843			.flags = CLK_SET_RATE_PARENT,
1844			.ops = &clk_branch2_ops,
1845		},
1846	},
1847};
1848
1849static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1850	.halt_reg = 0x0b04,
1851	.clkr = {
1852		.enable_reg = 0x0b04,
1853		.enable_mask = BIT(0),
1854		.hw.init = &(struct clk_init_data){
1855			.name = "gcc_blsp2_qup4_spi_apps_clk",
1856			.parent_names = (const char *[]){
1857				"blsp2_qup4_spi_apps_clk_src",
1858			},
1859			.num_parents = 1,
1860			.flags = CLK_SET_RATE_PARENT,
1861			.ops = &clk_branch2_ops,
1862		},
1863	},
1864};
1865
1866static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1867	.halt_reg = 0x0b88,
1868	.clkr = {
1869		.enable_reg = 0x0b88,
1870		.enable_mask = BIT(0),
1871		.hw.init = &(struct clk_init_data){
1872			.name = "gcc_blsp2_qup5_i2c_apps_clk",
1873			.parent_names = (const char *[]){
1874				"blsp2_qup5_i2c_apps_clk_src",
1875			},
1876			.num_parents = 1,
1877			.flags = CLK_SET_RATE_PARENT,
1878			.ops = &clk_branch2_ops,
1879		},
1880	},
1881};
1882
1883static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1884	.halt_reg = 0x0b84,
1885	.clkr = {
1886		.enable_reg = 0x0b84,
1887		.enable_mask = BIT(0),
1888		.hw.init = &(struct clk_init_data){
1889			.name = "gcc_blsp2_qup5_spi_apps_clk",
1890			.parent_names = (const char *[]){
1891				"blsp2_qup5_spi_apps_clk_src",
1892			},
1893			.num_parents = 1,
1894			.flags = CLK_SET_RATE_PARENT,
1895			.ops = &clk_branch2_ops,
1896		},
1897	},
1898};
1899
1900static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1901	.halt_reg = 0x0c08,
1902	.clkr = {
1903		.enable_reg = 0x0c08,
1904		.enable_mask = BIT(0),
1905		.hw.init = &(struct clk_init_data){
1906			.name = "gcc_blsp2_qup6_i2c_apps_clk",
1907			.parent_names = (const char *[]){
1908				"blsp2_qup6_i2c_apps_clk_src",
1909			},
1910			.num_parents = 1,
1911			.flags = CLK_SET_RATE_PARENT,
1912			.ops = &clk_branch2_ops,
1913		},
1914	},
1915};
1916
1917static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1918	.halt_reg = 0x0c04,
1919	.clkr = {
1920		.enable_reg = 0x0c04,
1921		.enable_mask = BIT(0),
1922		.hw.init = &(struct clk_init_data){
1923			.name = "gcc_blsp2_qup6_spi_apps_clk",
1924			.parent_names = (const char *[]){
1925				"blsp2_qup6_spi_apps_clk_src",
1926			},
1927			.num_parents = 1,
1928			.flags = CLK_SET_RATE_PARENT,
1929			.ops = &clk_branch2_ops,
1930		},
1931	},
1932};
1933
1934static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1935	.halt_reg = 0x09c4,
1936	.clkr = {
1937		.enable_reg = 0x09c4,
1938		.enable_mask = BIT(0),
1939		.hw.init = &(struct clk_init_data){
1940			.name = "gcc_blsp2_uart1_apps_clk",
1941			.parent_names = (const char *[]){
1942				"blsp2_uart1_apps_clk_src",
1943			},
1944			.num_parents = 1,
1945			.flags = CLK_SET_RATE_PARENT,
1946			.ops = &clk_branch2_ops,
1947		},
1948	},
1949};
1950
1951static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1952	.halt_reg = 0x0a44,
1953	.clkr = {
1954		.enable_reg = 0x0a44,
1955		.enable_mask = BIT(0),
1956		.hw.init = &(struct clk_init_data){
1957			.name = "gcc_blsp2_uart2_apps_clk",
1958			.parent_names = (const char *[]){
1959				"blsp2_uart2_apps_clk_src",
1960			},
1961			.num_parents = 1,
1962			.flags = CLK_SET_RATE_PARENT,
1963			.ops = &clk_branch2_ops,
1964		},
1965	},
1966};
1967
1968static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1969	.halt_reg = 0x0ac4,
1970	.clkr = {
1971		.enable_reg = 0x0ac4,
1972		.enable_mask = BIT(0),
1973		.hw.init = &(struct clk_init_data){
1974			.name = "gcc_blsp2_uart3_apps_clk",
1975			.parent_names = (const char *[]){
1976				"blsp2_uart3_apps_clk_src",
1977			},
1978			.num_parents = 1,
1979			.flags = CLK_SET_RATE_PARENT,
1980			.ops = &clk_branch2_ops,
1981		},
1982	},
1983};
1984
1985static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1986	.halt_reg = 0x0b44,
1987	.clkr = {
1988		.enable_reg = 0x0b44,
1989		.enable_mask = BIT(0),
1990		.hw.init = &(struct clk_init_data){
1991			.name = "gcc_blsp2_uart4_apps_clk",
1992			.parent_names = (const char *[]){
1993				"blsp2_uart4_apps_clk_src",
1994			},
1995			.num_parents = 1,
1996			.flags = CLK_SET_RATE_PARENT,
1997			.ops = &clk_branch2_ops,
1998		},
1999	},
2000};
2001
2002static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2003	.halt_reg = 0x0bc4,
2004	.clkr = {
2005		.enable_reg = 0x0bc4,
2006		.enable_mask = BIT(0),
2007		.hw.init = &(struct clk_init_data){
2008			.name = "gcc_blsp2_uart5_apps_clk",
2009			.parent_names = (const char *[]){
2010				"blsp2_uart5_apps_clk_src",
2011			},
2012			.num_parents = 1,
2013			.flags = CLK_SET_RATE_PARENT,
2014			.ops = &clk_branch2_ops,
2015		},
2016	},
2017};
2018
2019static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2020	.halt_reg = 0x0c44,
2021	.clkr = {
2022		.enable_reg = 0x0c44,
2023		.enable_mask = BIT(0),
2024		.hw.init = &(struct clk_init_data){
2025			.name = "gcc_blsp2_uart6_apps_clk",
2026			.parent_names = (const char *[]){
2027				"blsp2_uart6_apps_clk_src",
2028			},
2029			.num_parents = 1,
2030			.flags = CLK_SET_RATE_PARENT,
2031			.ops = &clk_branch2_ops,
2032		},
2033	},
2034};
2035
2036static struct clk_branch gcc_boot_rom_ahb_clk = {
2037	.halt_reg = 0x0e04,
2038	.halt_check = BRANCH_HALT_VOTED,
2039	.clkr = {
2040		.enable_reg = 0x1484,
2041		.enable_mask = BIT(10),
2042		.hw.init = &(struct clk_init_data){
2043			.name = "gcc_boot_rom_ahb_clk",
2044			.parent_names = (const char *[]){
2045				"config_noc_clk_src",
2046			},
2047			.num_parents = 1,
2048			.ops = &clk_branch2_ops,
2049		},
2050	},
2051};
2052
2053static struct clk_branch gcc_ce1_ahb_clk = {
2054	.halt_reg = 0x104c,
2055	.halt_check = BRANCH_HALT_VOTED,
2056	.clkr = {
2057		.enable_reg = 0x1484,
2058		.enable_mask = BIT(3),
2059		.hw.init = &(struct clk_init_data){
2060			.name = "gcc_ce1_ahb_clk",
2061			.parent_names = (const char *[]){
2062				"config_noc_clk_src",
2063			},
2064			.num_parents = 1,
2065			.ops = &clk_branch2_ops,
2066		},
2067	},
2068};
2069
2070static struct clk_branch gcc_ce1_axi_clk = {
2071	.halt_reg = 0x1048,
2072	.halt_check = BRANCH_HALT_VOTED,
2073	.clkr = {
2074		.enable_reg = 0x1484,
2075		.enable_mask = BIT(4),
2076		.hw.init = &(struct clk_init_data){
2077			.name = "gcc_ce1_axi_clk",
2078			.parent_names = (const char *[]){
2079				"system_noc_clk_src",
2080			},
2081			.num_parents = 1,
2082			.ops = &clk_branch2_ops,
2083		},
2084	},
2085};
2086
2087static struct clk_branch gcc_ce1_clk = {
2088	.halt_reg = 0x1050,
2089	.halt_check = BRANCH_HALT_VOTED,
2090	.clkr = {
2091		.enable_reg = 0x1484,
2092		.enable_mask = BIT(5),
2093		.hw.init = &(struct clk_init_data){
2094			.name = "gcc_ce1_clk",
2095			.parent_names = (const char *[]){
2096				"ce1_clk_src",
2097			},
2098			.num_parents = 1,
2099			.flags = CLK_SET_RATE_PARENT,
2100			.ops = &clk_branch2_ops,
2101		},
2102	},
2103};
2104
2105static struct clk_branch gcc_ce2_ahb_clk = {
2106	.halt_reg = 0x108c,
2107	.halt_check = BRANCH_HALT_VOTED,
2108	.clkr = {
2109		.enable_reg = 0x1484,
2110		.enable_mask = BIT(0),
2111		.hw.init = &(struct clk_init_data){
2112			.name = "gcc_ce2_ahb_clk",
2113			.parent_names = (const char *[]){
2114				"config_noc_clk_src",
2115			},
2116			.num_parents = 1,
2117			.ops = &clk_branch2_ops,
2118		},
2119	},
2120};
2121
2122static struct clk_branch gcc_ce2_axi_clk = {
2123	.halt_reg = 0x1088,
2124	.halt_check = BRANCH_HALT_VOTED,
2125	.clkr = {
2126		.enable_reg = 0x1484,
2127		.enable_mask = BIT(1),
2128		.hw.init = &(struct clk_init_data){
2129			.name = "gcc_ce2_axi_clk",
2130			.parent_names = (const char *[]){
2131				"system_noc_clk_src",
2132			},
2133			.num_parents = 1,
2134			.ops = &clk_branch2_ops,
2135		},
2136	},
2137};
2138
2139static struct clk_branch gcc_ce2_clk = {
2140	.halt_reg = 0x1090,
2141	.halt_check = BRANCH_HALT_VOTED,
2142	.clkr = {
2143		.enable_reg = 0x1484,
2144		.enable_mask = BIT(2),
2145		.hw.init = &(struct clk_init_data){
2146			.name = "gcc_ce2_clk",
2147			.parent_names = (const char *[]){
2148				"ce2_clk_src",
2149			},
2150			.num_parents = 1,
2151			.flags = CLK_SET_RATE_PARENT,
2152			.ops = &clk_branch2_ops,
2153		},
2154	},
2155};
2156
2157static struct clk_branch gcc_ce3_ahb_clk = {
2158	.halt_reg = 0x1d0c,
2159	.halt_check = BRANCH_HALT_VOTED,
2160	.clkr = {
2161		.enable_reg = 0x1d0c,
2162		.enable_mask = BIT(0),
2163		.hw.init = &(struct clk_init_data){
2164			.name = "gcc_ce3_ahb_clk",
2165			.parent_names = (const char *[]){
2166				"config_noc_clk_src",
2167			},
2168			.num_parents = 1,
2169			.ops = &clk_branch2_ops,
2170		},
2171	},
2172};
2173
2174static struct clk_branch gcc_ce3_axi_clk = {
2175	.halt_reg = 0x1088,
2176	.halt_check = BRANCH_HALT_VOTED,
2177	.clkr = {
2178		.enable_reg = 0x1d08,
2179		.enable_mask = BIT(0),
2180		.hw.init = &(struct clk_init_data){
2181			.name = "gcc_ce3_axi_clk",
2182			.parent_names = (const char *[]){
2183				"system_noc_clk_src",
2184			},
2185			.num_parents = 1,
2186			.ops = &clk_branch2_ops,
2187		},
2188	},
2189};
2190
2191static struct clk_branch gcc_ce3_clk = {
2192	.halt_reg = 0x1090,
2193	.halt_check = BRANCH_HALT_VOTED,
2194	.clkr = {
2195		.enable_reg = 0x1d04,
2196		.enable_mask = BIT(0),
2197		.hw.init = &(struct clk_init_data){
2198			.name = "gcc_ce3_clk",
2199			.parent_names = (const char *[]){
2200				"ce3_clk_src",
2201			},
2202			.num_parents = 1,
2203			.flags = CLK_SET_RATE_PARENT,
2204			.ops = &clk_branch2_ops,
2205		},
2206	},
2207};
2208
2209static struct clk_branch gcc_gp1_clk = {
2210	.halt_reg = 0x1900,
2211	.clkr = {
2212		.enable_reg = 0x1900,
2213		.enable_mask = BIT(0),
2214		.hw.init = &(struct clk_init_data){
2215			.name = "gcc_gp1_clk",
2216			.parent_names = (const char *[]){
2217				"gp1_clk_src",
2218			},
2219			.num_parents = 1,
2220			.flags = CLK_SET_RATE_PARENT,
2221			.ops = &clk_branch2_ops,
2222		},
2223	},
2224};
2225
2226static struct clk_branch gcc_gp2_clk = {
2227	.halt_reg = 0x1940,
2228	.clkr = {
2229		.enable_reg = 0x1940,
2230		.enable_mask = BIT(0),
2231		.hw.init = &(struct clk_init_data){
2232			.name = "gcc_gp2_clk",
2233			.parent_names = (const char *[]){
2234				"gp2_clk_src",
2235			},
2236			.num_parents = 1,
2237			.flags = CLK_SET_RATE_PARENT,
2238			.ops = &clk_branch2_ops,
2239		},
2240	},
2241};
2242
2243static struct clk_branch gcc_gp3_clk = {
2244	.halt_reg = 0x1980,
2245	.clkr = {
2246		.enable_reg = 0x1980,
2247		.enable_mask = BIT(0),
2248		.hw.init = &(struct clk_init_data){
2249			.name = "gcc_gp3_clk",
2250			.parent_names = (const char *[]){
2251				"gp3_clk_src",
2252			},
2253			.num_parents = 1,
2254			.flags = CLK_SET_RATE_PARENT,
2255			.ops = &clk_branch2_ops,
2256		},
2257	},
2258};
2259
2260static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2261	.halt_reg = 0x0248,
2262	.clkr = {
2263		.enable_reg = 0x0248,
2264		.enable_mask = BIT(0),
2265		.hw.init = &(struct clk_init_data){
2266			.name = "gcc_ocmem_noc_cfg_ahb_clk",
2267			.parent_names = (const char *[]){
2268				"config_noc_clk_src",
2269			},
2270			.num_parents = 1,
2271			.ops = &clk_branch2_ops,
2272		},
2273	},
2274};
2275
2276static struct clk_branch gcc_pcie_0_aux_clk = {
2277	.halt_reg = 0x1b10,
2278	.clkr = {
2279		.enable_reg = 0x1b10,
2280		.enable_mask = BIT(0),
2281		.hw.init = &(struct clk_init_data){
2282			.name = "gcc_pcie_0_aux_clk",
2283			.parent_names = (const char *[]){
2284				"pcie_0_aux_clk_src",
2285			},
2286			.num_parents = 1,
2287			.flags = CLK_SET_RATE_PARENT,
2288			.ops = &clk_branch2_ops,
2289		},
2290	},
2291};
2292
2293static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2294	.halt_reg = 0x1b0c,
2295	.clkr = {
2296		.enable_reg = 0x1b0c,
2297		.enable_mask = BIT(0),
2298		.hw.init = &(struct clk_init_data){
2299			.name = "gcc_pcie_0_cfg_ahb_clk",
2300			.parent_names = (const char *[]){
2301				"config_noc_clk_src",
2302			},
2303			.num_parents = 1,
2304			.flags = CLK_SET_RATE_PARENT,
2305			.ops = &clk_branch2_ops,
2306		},
2307	},
2308};
2309
2310static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2311	.halt_reg = 0x1b08,
2312	.clkr = {
2313		.enable_reg = 0x1b08,
2314		.enable_mask = BIT(0),
2315		.hw.init = &(struct clk_init_data){
2316			.name = "gcc_pcie_0_mstr_axi_clk",
2317			.parent_names = (const char *[]){
2318				"config_noc_clk_src",
2319			},
2320			.num_parents = 1,
2321			.flags = CLK_SET_RATE_PARENT,
2322			.ops = &clk_branch2_ops,
2323		},
2324	},
2325};
2326
2327static struct clk_branch gcc_pcie_0_pipe_clk = {
2328	.halt_reg = 0x1b14,
2329	.clkr = {
2330		.enable_reg = 0x1b14,
2331		.enable_mask = BIT(0),
2332		.hw.init = &(struct clk_init_data){
2333			.name = "gcc_pcie_0_pipe_clk",
2334			.parent_names = (const char *[]){
2335				"pcie_0_pipe_clk_src",
2336			},
2337			.num_parents = 1,
2338			.flags = CLK_SET_RATE_PARENT,
2339			.ops = &clk_branch2_ops,
2340		},
2341	},
2342};
2343
2344static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2345	.halt_reg = 0x1b04,
2346	.clkr = {
2347		.enable_reg = 0x1b04,
2348		.enable_mask = BIT(0),
2349		.hw.init = &(struct clk_init_data){
2350			.name = "gcc_pcie_0_slv_axi_clk",
2351			.parent_names = (const char *[]){
2352				"config_noc_clk_src",
2353			},
2354			.num_parents = 1,
2355			.flags = CLK_SET_RATE_PARENT,
2356			.ops = &clk_branch2_ops,
2357		},
2358	},
2359};
2360
2361static struct clk_branch gcc_pcie_1_aux_clk = {
2362	.halt_reg = 0x1b90,
2363	.clkr = {
2364		.enable_reg = 0x1b90,
2365		.enable_mask = BIT(0),
2366		.hw.init = &(struct clk_init_data){
2367			.name = "gcc_pcie_1_aux_clk",
2368			.parent_names = (const char *[]){
2369				"pcie_1_aux_clk_src",
2370			},
2371			.num_parents = 1,
2372			.flags = CLK_SET_RATE_PARENT,
2373			.ops = &clk_branch2_ops,
2374		},
2375	},
2376};
2377
2378static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2379	.halt_reg = 0x1b8c,
2380	.clkr = {
2381		.enable_reg = 0x1b8c,
2382		.enable_mask = BIT(0),
2383		.hw.init = &(struct clk_init_data){
2384			.name = "gcc_pcie_1_cfg_ahb_clk",
2385			.parent_names = (const char *[]){
2386				"config_noc_clk_src",
2387			},
2388			.num_parents = 1,
2389			.flags = CLK_SET_RATE_PARENT,
2390			.ops = &clk_branch2_ops,
2391		},
2392	},
2393};
2394
2395static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2396	.halt_reg = 0x1b88,
2397	.clkr = {
2398		.enable_reg = 0x1b88,
2399		.enable_mask = BIT(0),
2400		.hw.init = &(struct clk_init_data){
2401			.name = "gcc_pcie_1_mstr_axi_clk",
2402			.parent_names = (const char *[]){
2403				"config_noc_clk_src",
2404			},
2405			.num_parents = 1,
2406			.flags = CLK_SET_RATE_PARENT,
2407			.ops = &clk_branch2_ops,
2408		},
2409	},
2410};
2411
2412static struct clk_branch gcc_pcie_1_pipe_clk = {
2413	.halt_reg = 0x1b94,
2414	.clkr = {
2415		.enable_reg = 0x1b94,
2416		.enable_mask = BIT(0),
2417		.hw.init = &(struct clk_init_data){
2418			.name = "gcc_pcie_1_pipe_clk",
2419			.parent_names = (const char *[]){
2420				"pcie_1_pipe_clk_src",
2421			},
2422			.num_parents = 1,
2423			.flags = CLK_SET_RATE_PARENT,
2424			.ops = &clk_branch2_ops,
2425		},
2426	},
2427};
2428
2429static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2430	.halt_reg = 0x1b84,
2431	.clkr = {
2432		.enable_reg = 0x1b84,
2433		.enable_mask = BIT(0),
2434		.hw.init = &(struct clk_init_data){
2435			.name = "gcc_pcie_1_slv_axi_clk",
2436			.parent_names = (const char *[]){
2437				"config_noc_clk_src",
2438			},
2439			.num_parents = 1,
2440			.flags = CLK_SET_RATE_PARENT,
2441			.ops = &clk_branch2_ops,
2442		},
2443	},
2444};
2445
2446static struct clk_branch gcc_pdm2_clk = {
2447	.halt_reg = 0x0ccc,
2448	.clkr = {
2449		.enable_reg = 0x0ccc,
2450		.enable_mask = BIT(0),
2451		.hw.init = &(struct clk_init_data){
2452			.name = "gcc_pdm2_clk",
2453			.parent_names = (const char *[]){
2454				"pdm2_clk_src",
2455			},
2456			.num_parents = 1,
2457			.flags = CLK_SET_RATE_PARENT,
2458			.ops = &clk_branch2_ops,
2459		},
2460	},
2461};
2462
2463static struct clk_branch gcc_pdm_ahb_clk = {
2464	.halt_reg = 0x0cc4,
2465	.clkr = {
2466		.enable_reg = 0x0cc4,
2467		.enable_mask = BIT(0),
2468		.hw.init = &(struct clk_init_data){
2469			.name = "gcc_pdm_ahb_clk",
2470			.parent_names = (const char *[]){
2471				"periph_noc_clk_src",
2472			},
2473			.num_parents = 1,
2474			.ops = &clk_branch2_ops,
2475		},
2476	},
2477};
2478
2479static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2480	.halt_reg = 0x01a4,
2481	.clkr = {
2482		.enable_reg = 0x01a4,
2483		.enable_mask = BIT(0),
2484		.hw.init = &(struct clk_init_data){
2485			.name = "gcc_periph_noc_usb_hsic_ahb_clk",
2486			.parent_names = (const char *[]){
2487				"usb_hsic_ahb_clk_src",
2488			},
2489			.num_parents = 1,
2490			.flags = CLK_SET_RATE_PARENT,
2491			.ops = &clk_branch2_ops,
2492		},
2493	},
2494};
2495
2496static struct clk_branch gcc_prng_ahb_clk = {
2497	.halt_reg = 0x0d04,
2498	.halt_check = BRANCH_HALT_VOTED,
2499	.clkr = {
2500		.enable_reg = 0x1484,
2501		.enable_mask = BIT(13),
2502		.hw.init = &(struct clk_init_data){
2503			.name = "gcc_prng_ahb_clk",
2504			.parent_names = (const char *[]){
2505				"periph_noc_clk_src",
2506			},
2507			.num_parents = 1,
2508			.ops = &clk_branch2_ops,
2509		},
2510	},
2511};
2512
2513static struct clk_branch gcc_sata_asic0_clk = {
2514	.halt_reg = 0x1c54,
2515	.clkr = {
2516		.enable_reg = 0x1c54,
2517		.enable_mask = BIT(0),
2518		.hw.init = &(struct clk_init_data){
2519			.name = "gcc_sata_asic0_clk",
2520			.parent_names = (const char *[]){
2521				"sata_asic0_clk_src",
2522			},
2523			.num_parents = 1,
2524			.flags = CLK_SET_RATE_PARENT,
2525			.ops = &clk_branch2_ops,
2526		},
2527	},
2528};
2529
2530static struct clk_branch gcc_sata_axi_clk = {
2531	.halt_reg = 0x1c44,
2532	.clkr = {
2533		.enable_reg = 0x1c44,
2534		.enable_mask = BIT(0),
2535		.hw.init = &(struct clk_init_data){
2536			.name = "gcc_sata_axi_clk",
2537			.parent_names = (const char *[]){
2538				"config_noc_clk_src",
2539			},
2540			.num_parents = 1,
2541			.flags = CLK_SET_RATE_PARENT,
2542			.ops = &clk_branch2_ops,
2543		},
2544	},
2545};
2546
2547static struct clk_branch gcc_sata_cfg_ahb_clk = {
2548	.halt_reg = 0x1c48,
2549	.clkr = {
2550		.enable_reg = 0x1c48,
2551		.enable_mask = BIT(0),
2552		.hw.init = &(struct clk_init_data){
2553			.name = "gcc_sata_cfg_ahb_clk",
2554			.parent_names = (const char *[]){
2555				"config_noc_clk_src",
2556			},
2557			.num_parents = 1,
2558			.flags = CLK_SET_RATE_PARENT,
2559			.ops = &clk_branch2_ops,
2560		},
2561	},
2562};
2563
2564static struct clk_branch gcc_sata_pmalive_clk = {
2565	.halt_reg = 0x1c50,
2566	.clkr = {
2567		.enable_reg = 0x1c50,
2568		.enable_mask = BIT(0),
2569		.hw.init = &(struct clk_init_data){
2570			.name = "gcc_sata_pmalive_clk",
2571			.parent_names = (const char *[]){
2572				"sata_pmalive_clk_src",
2573			},
2574			.num_parents = 1,
2575			.flags = CLK_SET_RATE_PARENT,
2576			.ops = &clk_branch2_ops,
2577		},
2578	},
2579};
2580
2581static struct clk_branch gcc_sata_rx_clk = {
2582	.halt_reg = 0x1c58,
2583	.clkr = {
2584		.enable_reg = 0x1c58,
2585		.enable_mask = BIT(0),
2586		.hw.init = &(struct clk_init_data){
2587			.name = "gcc_sata_rx_clk",
2588			.parent_names = (const char *[]){
2589				"sata_rx_clk_src",
2590			},
2591			.num_parents = 1,
2592			.flags = CLK_SET_RATE_PARENT,
2593			.ops = &clk_branch2_ops,
2594		},
2595	},
2596};
2597
2598static struct clk_branch gcc_sata_rx_oob_clk = {
2599	.halt_reg = 0x1c4c,
2600	.clkr = {
2601		.enable_reg = 0x1c4c,
2602		.enable_mask = BIT(0),
2603		.hw.init = &(struct clk_init_data){
2604			.name = "gcc_sata_rx_oob_clk",
2605			.parent_names = (const char *[]){
2606				"sata_rx_oob_clk_src",
2607			},
2608			.num_parents = 1,
2609			.flags = CLK_SET_RATE_PARENT,
2610			.ops = &clk_branch2_ops,
2611		},
2612	},
2613};
2614
2615static struct clk_branch gcc_sdcc1_ahb_clk = {
2616	.halt_reg = 0x04c8,
2617	.clkr = {
2618		.enable_reg = 0x04c8,
2619		.enable_mask = BIT(0),
2620		.hw.init = &(struct clk_init_data){
2621			.name = "gcc_sdcc1_ahb_clk",
2622			.parent_names = (const char *[]){
2623				"periph_noc_clk_src",
2624			},
2625			.num_parents = 1,
2626			.ops = &clk_branch2_ops,
2627		},
2628	},
2629};
2630
2631static struct clk_branch gcc_sdcc1_apps_clk = {
2632	.halt_reg = 0x04c4,
2633	.clkr = {
2634		.enable_reg = 0x04c4,
2635		.enable_mask = BIT(0),
2636		.hw.init = &(struct clk_init_data){
2637			.name = "gcc_sdcc1_apps_clk",
2638			.parent_names = (const char *[]){
2639				"sdcc1_apps_clk_src",
2640			},
2641			.num_parents = 1,
2642			.flags = CLK_SET_RATE_PARENT,
2643			.ops = &clk_branch2_ops,
2644		},
2645	},
2646};
2647
2648static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2649	.halt_reg = 0x04e8,
2650	.clkr = {
2651		.enable_reg = 0x04e8,
2652		.enable_mask = BIT(0),
2653		.hw.init = &(struct clk_init_data){
2654			.name = "gcc_sdcc1_cdccal_ff_clk",
2655			.parent_names = (const char *[]){
2656				"xo"
2657			},
2658			.num_parents = 1,
2659			.ops = &clk_branch2_ops,
2660		},
2661	},
2662};
2663
2664static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2665	.halt_reg = 0x04e4,
2666	.clkr = {
2667		.enable_reg = 0x04e4,
2668		.enable_mask = BIT(0),
2669		.hw.init = &(struct clk_init_data){
2670			.name = "gcc_sdcc1_cdccal_sleep_clk",
2671			.parent_names = (const char *[]){
2672				"sleep_clk_src"
2673			},
2674			.num_parents = 1,
2675			.ops = &clk_branch2_ops,
2676		},
2677	},
2678};
2679
2680static struct clk_branch gcc_sdcc2_ahb_clk = {
2681	.halt_reg = 0x0508,
2682	.clkr = {
2683		.enable_reg = 0x0508,
2684		.enable_mask = BIT(0),
2685		.hw.init = &(struct clk_init_data){
2686			.name = "gcc_sdcc2_ahb_clk",
2687			.parent_names = (const char *[]){
2688				"periph_noc_clk_src",
2689			},
2690			.num_parents = 1,
2691			.ops = &clk_branch2_ops,
2692		},
2693	},
2694};
2695
2696static struct clk_branch gcc_sdcc2_apps_clk = {
2697	.halt_reg = 0x0504,
2698	.clkr = {
2699		.enable_reg = 0x0504,
2700		.enable_mask = BIT(0),
2701		.hw.init = &(struct clk_init_data){
2702			.name = "gcc_sdcc2_apps_clk",
2703			.parent_names = (const char *[]){
2704				"sdcc2_apps_clk_src",
2705			},
2706			.num_parents = 1,
2707			.flags = CLK_SET_RATE_PARENT,
2708			.ops = &clk_branch2_ops,
2709		},
2710	},
2711};
2712
2713static struct clk_branch gcc_sdcc3_ahb_clk = {
2714	.halt_reg = 0x0548,
2715	.clkr = {
2716		.enable_reg = 0x0548,
2717		.enable_mask = BIT(0),
2718		.hw.init = &(struct clk_init_data){
2719			.name = "gcc_sdcc3_ahb_clk",
2720			.parent_names = (const char *[]){
2721				"periph_noc_clk_src",
2722			},
2723			.num_parents = 1,
2724			.ops = &clk_branch2_ops,
2725		},
2726	},
2727};
2728
2729static struct clk_branch gcc_sdcc3_apps_clk = {
2730	.halt_reg = 0x0544,
2731	.clkr = {
2732		.enable_reg = 0x0544,
2733		.enable_mask = BIT(0),
2734		.hw.init = &(struct clk_init_data){
2735			.name = "gcc_sdcc3_apps_clk",
2736			.parent_names = (const char *[]){
2737				"sdcc3_apps_clk_src",
2738			},
2739			.num_parents = 1,
2740			.flags = CLK_SET_RATE_PARENT,
2741			.ops = &clk_branch2_ops,
2742		},
2743	},
2744};
2745
2746static struct clk_branch gcc_sdcc4_ahb_clk = {
2747	.halt_reg = 0x0588,
2748	.clkr = {
2749		.enable_reg = 0x0588,
2750		.enable_mask = BIT(0),
2751		.hw.init = &(struct clk_init_data){
2752			.name = "gcc_sdcc4_ahb_clk",
2753			.parent_names = (const char *[]){
2754				"periph_noc_clk_src",
2755			},
2756			.num_parents = 1,
2757			.ops = &clk_branch2_ops,
2758		},
2759	},
2760};
2761
2762static struct clk_branch gcc_sdcc4_apps_clk = {
2763	.halt_reg = 0x0584,
2764	.clkr = {
2765		.enable_reg = 0x0584,
2766		.enable_mask = BIT(0),
2767		.hw.init = &(struct clk_init_data){
2768			.name = "gcc_sdcc4_apps_clk",
2769			.parent_names = (const char *[]){
2770				"sdcc4_apps_clk_src",
2771			},
2772			.num_parents = 1,
2773			.flags = CLK_SET_RATE_PARENT,
2774			.ops = &clk_branch2_ops,
2775		},
2776	},
2777};
2778
2779static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2780	.halt_reg = 0x013c,
2781	.clkr = {
2782		.enable_reg = 0x013c,
2783		.enable_mask = BIT(0),
2784		.hw.init = &(struct clk_init_data){
2785			.name = "gcc_sys_noc_ufs_axi_clk",
2786			.parent_names = (const char *[]){
2787				"ufs_axi_clk_src",
2788			},
2789			.num_parents = 1,
2790			.flags = CLK_SET_RATE_PARENT,
2791			.ops = &clk_branch2_ops,
2792		},
2793	},
2794};
2795
2796static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2797	.halt_reg = 0x0108,
2798	.clkr = {
2799		.enable_reg = 0x0108,
2800		.enable_mask = BIT(0),
2801		.hw.init = &(struct clk_init_data){
2802			.name = "gcc_sys_noc_usb3_axi_clk",
2803			.parent_names = (const char *[]){
2804				"usb30_master_clk_src",
2805			},
2806			.num_parents = 1,
2807			.flags = CLK_SET_RATE_PARENT,
2808			.ops = &clk_branch2_ops,
2809		},
2810	},
2811};
2812
2813static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2814	.halt_reg = 0x0138,
2815	.clkr = {
2816		.enable_reg = 0x0138,
2817		.enable_mask = BIT(0),
2818		.hw.init = &(struct clk_init_data){
2819			.name = "gcc_sys_noc_usb3_sec_axi_clk",
2820			.parent_names = (const char *[]){
2821				"usb30_sec_master_clk_src",
2822			},
2823			.num_parents = 1,
2824			.flags = CLK_SET_RATE_PARENT,
2825			.ops = &clk_branch2_ops,
2826		},
2827	},
2828};
2829
2830static struct clk_branch gcc_tsif_ahb_clk = {
2831	.halt_reg = 0x0d84,
2832	.clkr = {
2833		.enable_reg = 0x0d84,
2834		.enable_mask = BIT(0),
2835		.hw.init = &(struct clk_init_data){
2836			.name = "gcc_tsif_ahb_clk",
2837			.parent_names = (const char *[]){
2838				"periph_noc_clk_src",
2839			},
2840			.num_parents = 1,
2841			.ops = &clk_branch2_ops,
2842		},
2843	},
2844};
2845
2846static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2847	.halt_reg = 0x0d8c,
2848	.clkr = {
2849		.enable_reg = 0x0d8c,
2850		.enable_mask = BIT(0),
2851		.hw.init = &(struct clk_init_data){
2852			.name = "gcc_tsif_inactivity_timers_clk",
2853			.parent_names = (const char *[]){
2854				"sleep_clk_src",
2855			},
2856			.num_parents = 1,
2857			.flags = CLK_SET_RATE_PARENT,
2858			.ops = &clk_branch2_ops,
2859		},
2860	},
2861};
2862
2863static struct clk_branch gcc_tsif_ref_clk = {
2864	.halt_reg = 0x0d88,
2865	.clkr = {
2866		.enable_reg = 0x0d88,
2867		.enable_mask = BIT(0),
2868		.hw.init = &(struct clk_init_data){
2869			.name = "gcc_tsif_ref_clk",
2870			.parent_names = (const char *[]){
2871				"tsif_ref_clk_src",
2872			},
2873			.num_parents = 1,
2874			.flags = CLK_SET_RATE_PARENT,
2875			.ops = &clk_branch2_ops,
2876		},
2877	},
2878};
2879
2880static struct clk_branch gcc_ufs_ahb_clk = {
2881	.halt_reg = 0x1d48,
2882	.clkr = {
2883		.enable_reg = 0x1d48,
2884		.enable_mask = BIT(0),
2885		.hw.init = &(struct clk_init_data){
2886			.name = "gcc_ufs_ahb_clk",
2887			.parent_names = (const char *[]){
2888				"config_noc_clk_src",
2889			},
2890			.num_parents = 1,
2891			.flags = CLK_SET_RATE_PARENT,
2892			.ops = &clk_branch2_ops,
2893		},
2894	},
2895};
2896
2897static struct clk_branch gcc_ufs_axi_clk = {
2898	.halt_reg = 0x1d44,
2899	.clkr = {
2900		.enable_reg = 0x1d44,
2901		.enable_mask = BIT(0),
2902		.hw.init = &(struct clk_init_data){
2903			.name = "gcc_ufs_axi_clk",
2904			.parent_names = (const char *[]){
2905				"ufs_axi_clk_src",
2906			},
2907			.num_parents = 1,
2908			.flags = CLK_SET_RATE_PARENT,
2909			.ops = &clk_branch2_ops,
2910		},
2911	},
2912};
2913
2914static struct clk_branch gcc_ufs_rx_cfg_clk = {
2915	.halt_reg = 0x1d50,
2916	.clkr = {
2917		.enable_reg = 0x1d50,
2918		.enable_mask = BIT(0),
2919		.hw.init = &(struct clk_init_data){
2920			.name = "gcc_ufs_rx_cfg_clk",
2921			.parent_names = (const char *[]){
2922				"ufs_axi_clk_src",
2923			},
2924			.num_parents = 1,
2925			.flags = CLK_SET_RATE_PARENT,
2926			.ops = &clk_branch2_ops,
2927		},
2928	},
2929};
2930
2931static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2932	.halt_reg = 0x1d5c,
2933	.clkr = {
2934		.enable_reg = 0x1d5c,
2935		.enable_mask = BIT(0),
2936		.hw.init = &(struct clk_init_data){
2937			.name = "gcc_ufs_rx_symbol_0_clk",
2938			.parent_names = (const char *[]){
2939				"ufs_rx_symbol_0_clk_src",
2940			},
2941			.num_parents = 1,
2942			.flags = CLK_SET_RATE_PARENT,
2943			.ops = &clk_branch2_ops,
2944		},
2945	},
2946};
2947
2948static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2949	.halt_reg = 0x1d60,
2950	.clkr = {
2951		.enable_reg = 0x1d60,
2952		.enable_mask = BIT(0),
2953		.hw.init = &(struct clk_init_data){
2954			.name = "gcc_ufs_rx_symbol_1_clk",
2955			.parent_names = (const char *[]){
2956				"ufs_rx_symbol_1_clk_src",
2957			},
2958			.num_parents = 1,
2959			.flags = CLK_SET_RATE_PARENT,
2960			.ops = &clk_branch2_ops,
2961		},
2962	},
2963};
2964
2965static struct clk_branch gcc_ufs_tx_cfg_clk = {
2966	.halt_reg = 0x1d4c,
2967	.clkr = {
2968		.enable_reg = 0x1d4c,
2969		.enable_mask = BIT(0),
2970		.hw.init = &(struct clk_init_data){
2971			.name = "gcc_ufs_tx_cfg_clk",
2972			.parent_names = (const char *[]){
2973				"ufs_axi_clk_src",
2974			},
2975			.num_parents = 1,
2976			.flags = CLK_SET_RATE_PARENT,
2977			.ops = &clk_branch2_ops,
2978		},
2979	},
2980};
2981
2982static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2983	.halt_reg = 0x1d54,
2984	.clkr = {
2985		.enable_reg = 0x1d54,
2986		.enable_mask = BIT(0),
2987		.hw.init = &(struct clk_init_data){
2988			.name = "gcc_ufs_tx_symbol_0_clk",
2989			.parent_names = (const char *[]){
2990				"ufs_tx_symbol_0_clk_src",
2991			},
2992			.num_parents = 1,
2993			.flags = CLK_SET_RATE_PARENT,
2994			.ops = &clk_branch2_ops,
2995		},
2996	},
2997};
2998
2999static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
3000	.halt_reg = 0x1d58,
3001	.clkr = {
3002		.enable_reg = 0x1d58,
3003		.enable_mask = BIT(0),
3004		.hw.init = &(struct clk_init_data){
3005			.name = "gcc_ufs_tx_symbol_1_clk",
3006			.parent_names = (const char *[]){
3007				"ufs_tx_symbol_1_clk_src",
3008			},
3009			.num_parents = 1,
3010			.flags = CLK_SET_RATE_PARENT,
3011			.ops = &clk_branch2_ops,
3012		},
3013	},
3014};
3015
3016static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3017	.halt_reg = 0x04ac,
3018	.clkr = {
3019		.enable_reg = 0x04ac,
3020		.enable_mask = BIT(0),
3021		.hw.init = &(struct clk_init_data){
3022			.name = "gcc_usb2a_phy_sleep_clk",
3023			.parent_names = (const char *[]){
3024				"sleep_clk_src",
3025			},
3026			.num_parents = 1,
3027			.ops = &clk_branch2_ops,
3028		},
3029	},
3030};
3031
3032static struct clk_branch gcc_usb2b_phy_sleep_clk = {
3033	.halt_reg = 0x04b4,
3034	.clkr = {
3035		.enable_reg = 0x04b4,
3036		.enable_mask = BIT(0),
3037		.hw.init = &(struct clk_init_data){
3038			.name = "gcc_usb2b_phy_sleep_clk",
3039			.parent_names = (const char *[]){
3040				"sleep_clk_src",
3041			},
3042			.num_parents = 1,
3043			.ops = &clk_branch2_ops,
3044		},
3045	},
3046};
3047
3048static struct clk_branch gcc_usb30_master_clk = {
3049	.halt_reg = 0x03c8,
3050	.clkr = {
3051		.enable_reg = 0x03c8,
3052		.enable_mask = BIT(0),
3053		.hw.init = &(struct clk_init_data){
3054			.name = "gcc_usb30_master_clk",
3055			.parent_names = (const char *[]){
3056				"usb30_master_clk_src",
3057			},
3058			.num_parents = 1,
3059			.flags = CLK_SET_RATE_PARENT,
3060			.ops = &clk_branch2_ops,
3061		},
3062	},
3063};
3064
3065static struct clk_branch gcc_usb30_sec_master_clk = {
3066	.halt_reg = 0x1bc8,
3067	.clkr = {
3068		.enable_reg = 0x1bc8,
3069		.enable_mask = BIT(0),
3070		.hw.init = &(struct clk_init_data){
3071			.name = "gcc_usb30_sec_master_clk",
3072			.parent_names = (const char *[]){
3073				"usb30_sec_master_clk_src",
3074			},
3075			.num_parents = 1,
3076			.flags = CLK_SET_RATE_PARENT,
3077			.ops = &clk_branch2_ops,
3078		},
3079	},
3080};
3081
3082static struct clk_branch gcc_usb30_mock_utmi_clk = {
3083	.halt_reg = 0x03d0,
3084	.clkr = {
3085		.enable_reg = 0x03d0,
3086		.enable_mask = BIT(0),
3087		.hw.init = &(struct clk_init_data){
3088			.name = "gcc_usb30_mock_utmi_clk",
3089			.parent_names = (const char *[]){
3090				"usb30_mock_utmi_clk_src",
3091			},
3092			.num_parents = 1,
3093			.flags = CLK_SET_RATE_PARENT,
3094			.ops = &clk_branch2_ops,
3095		},
3096	},
3097};
3098
3099static struct clk_branch gcc_usb30_sleep_clk = {
3100	.halt_reg = 0x03cc,
3101	.clkr = {
3102		.enable_reg = 0x03cc,
3103		.enable_mask = BIT(0),
3104		.hw.init = &(struct clk_init_data){
3105			.name = "gcc_usb30_sleep_clk",
3106			.parent_names = (const char *[]){
3107				"sleep_clk_src",
3108			},
3109			.num_parents = 1,
3110			.ops = &clk_branch2_ops,
3111		},
3112	},
3113};
3114
3115static struct clk_branch gcc_usb_hs_ahb_clk = {
3116	.halt_reg = 0x0488,
3117	.clkr = {
3118		.enable_reg = 0x0488,
3119		.enable_mask = BIT(0),
3120		.hw.init = &(struct clk_init_data){
3121			.name = "gcc_usb_hs_ahb_clk",
3122			.parent_names = (const char *[]){
3123				"periph_noc_clk_src",
3124			},
3125			.num_parents = 1,
3126			.ops = &clk_branch2_ops,
3127		},
3128	},
3129};
3130
3131static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
3132	.halt_reg = 0x048c,
3133	.clkr = {
3134		.enable_reg = 0x048c,
3135		.enable_mask = BIT(0),
3136		.hw.init = &(struct clk_init_data){
3137			.name = "gcc_usb_hs_inactivity_timers_clk",
3138			.parent_names = (const char *[]){
3139				"sleep_clk_src",
3140			},
3141			.num_parents = 1,
3142			.flags = CLK_SET_RATE_PARENT,
3143			.ops = &clk_branch2_ops,
3144		},
3145	},
3146};
3147
3148static struct clk_branch gcc_usb_hs_system_clk = {
3149	.halt_reg = 0x0484,
3150	.clkr = {
3151		.enable_reg = 0x0484,
3152		.enable_mask = BIT(0),
3153		.hw.init = &(struct clk_init_data){
3154			.name = "gcc_usb_hs_system_clk",
3155			.parent_names = (const char *[]){
3156				"usb_hs_system_clk_src",
3157			},
3158			.num_parents = 1,
3159			.flags = CLK_SET_RATE_PARENT,
3160			.ops = &clk_branch2_ops,
3161		},
3162	},
3163};
3164
3165static struct clk_branch gcc_usb_hsic_ahb_clk = {
3166	.halt_reg = 0x0408,
3167	.clkr = {
3168		.enable_reg = 0x0408,
3169		.enable_mask = BIT(0),
3170		.hw.init = &(struct clk_init_data){
3171			.name = "gcc_usb_hsic_ahb_clk",
3172			.parent_names = (const char *[]){
3173				"periph_noc_clk_src",
3174			},
3175			.num_parents = 1,
3176			.ops = &clk_branch2_ops,
3177		},
3178	},
3179};
3180
3181static struct clk_branch gcc_usb_hsic_clk = {
3182	.halt_reg = 0x0410,
3183	.clkr = {
3184		.enable_reg = 0x0410,
3185		.enable_mask = BIT(0),
3186		.hw.init = &(struct clk_init_data){
3187			.name = "gcc_usb_hsic_clk",
3188			.parent_names = (const char *[]){
3189				"usb_hsic_clk_src",
3190			},
3191			.num_parents = 1,
3192			.flags = CLK_SET_RATE_PARENT,
3193			.ops = &clk_branch2_ops,
3194		},
3195	},
3196};
3197
3198static struct clk_branch gcc_usb_hsic_io_cal_clk = {
3199	.halt_reg = 0x0414,
3200	.clkr = {
3201		.enable_reg = 0x0414,
3202		.enable_mask = BIT(0),
3203		.hw.init = &(struct clk_init_data){
3204			.name = "gcc_usb_hsic_io_cal_clk",
3205			.parent_names = (const char *[]){
3206				"usb_hsic_io_cal_clk_src",
3207			},
3208			.num_parents = 1,
3209			.flags = CLK_SET_RATE_PARENT,
3210			.ops = &clk_branch2_ops,
3211		},
3212	},
3213};
3214
3215static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
3216	.halt_reg = 0x0418,
3217	.clkr = {
3218		.enable_reg = 0x0418,
3219		.enable_mask = BIT(0),
3220		.hw.init = &(struct clk_init_data){
3221			.name = "gcc_usb_hsic_io_cal_sleep_clk",
3222			.parent_names = (const char *[]){
3223				"sleep_clk_src",
3224			},
3225			.num_parents = 1,
3226			.ops = &clk_branch2_ops,
3227		},
3228	},
3229};
3230
3231static struct clk_branch gcc_usb_hsic_system_clk = {
3232	.halt_reg = 0x040c,
3233	.clkr = {
3234		.enable_reg = 0x040c,
3235		.enable_mask = BIT(0),
3236		.hw.init = &(struct clk_init_data){
3237			.name = "gcc_usb_hsic_system_clk",
3238			.parent_names = (const char *[]){
3239				"usb_hsic_system_clk_src",
3240			},
3241			.num_parents = 1,
3242			.flags = CLK_SET_RATE_PARENT,
3243			.ops = &clk_branch2_ops,
3244		},
3245	},
3246};
3247
3248static struct gdsc usb_hs_hsic_gdsc = {
3249	.gdscr = 0x404,
3250	.pd = {
3251		.name = "usb_hs_hsic",
3252	},
3253	.pwrsts = PWRSTS_OFF_ON,
3254};
3255
3256static struct gdsc pcie0_gdsc = {
3257	.gdscr = 0x1ac4,
3258	.pd = {
3259		.name = "pcie0",
3260	},
3261	.pwrsts = PWRSTS_OFF_ON,
3262};
3263
3264static struct gdsc pcie1_gdsc = {
3265	.gdscr = 0x1b44,
3266	.pd = {
3267		.name = "pcie1",
3268	},
3269	.pwrsts = PWRSTS_OFF_ON,
3270};
3271
3272static struct gdsc usb30_gdsc = {
3273	.gdscr = 0x1e84,
3274	.pd = {
3275		.name = "usb30",
3276	},
3277	.pwrsts = PWRSTS_OFF_ON,
3278};
3279
3280static struct clk_regmap *gcc_apq8084_clocks[] = {
3281	[GPLL0] = &gpll0.clkr,
3282	[GPLL0_VOTE] = &gpll0_vote,
3283	[GPLL1] = &gpll1.clkr,
3284	[GPLL1_VOTE] = &gpll1_vote,
3285	[GPLL4] = &gpll4.clkr,
3286	[GPLL4_VOTE] = &gpll4_vote,
3287	[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3288	[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3289	[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3290	[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3291	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3292	[USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
3293	[USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
3294	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3295	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3296	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3297	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3298	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3299	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3300	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3301	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3302	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3303	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3304	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3305	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3306	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3307	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3308	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3309	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3310	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3311	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3312	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3313	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3314	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3315	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3316	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3317	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3318	[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3319	[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3320	[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3321	[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3322	[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3323	[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3324	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3325	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3326	[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3327	[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3328	[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3329	[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3330	[CE1_CLK_SRC] = &ce1_clk_src.clkr,
3331	[CE2_CLK_SRC] = &ce2_clk_src.clkr,
3332	[CE3_CLK_SRC] = &ce3_clk_src.clkr,
3333	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3334	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3335	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3336	[PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
3337	[PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
3338	[PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
3339	[PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
3340	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3341	[SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
3342	[SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
3343	[SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
3344	[SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
3345	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3346	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3347	[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3348	[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3349	[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3350	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3351	[USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
3352	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3353	[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
3354	[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
3355	[USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
3356	[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
3357	[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
3358	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3359	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3360	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3361	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3362	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3363	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3364	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3365	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3366	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3367	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3368	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3369	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3370	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3371	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3372	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3373	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3374	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3375	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3376	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3377	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3378	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3379	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3380	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3381	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3382	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3383	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3384	[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3385	[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3386	[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3387	[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3388	[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3389	[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3390	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3391	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3392	[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3393	[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3394	[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3395	[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3396	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3397	[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3398	[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3399	[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3400	[GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
3401	[GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
3402	[GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
3403	[GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
3404	[GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
3405	[GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
3406	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3407	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3408	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3409	[GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
3410	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3411	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3412	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3413	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3414	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3415	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3416	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3417	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3418	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3419	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3420	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3421	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3422	[GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
3423	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3424	[GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
3425	[GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
3426	[GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
3427	[GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
3428	[GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
3429	[GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
3430	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3431	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3432	[GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
3433	[GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
3434	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3435	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3436	[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3437	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3438	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3439	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3440	[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3441	[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3442	[GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
3443	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3444	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3445	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3446	[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3447	[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3448	[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3449	[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3450	[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3451	[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3452	[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3453	[GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
3454	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3455	[GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
3456	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3457	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3458	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3459	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3460	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3461	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3462	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3463	[GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
3464	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3465	[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
3466	[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
3467	[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
3468	[GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
3469	[GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
3470	[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
3471};
3472
3473static struct gdsc *gcc_apq8084_gdscs[] = {
3474	[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
3475	[PCIE0_GDSC] = &pcie0_gdsc,
3476	[PCIE1_GDSC] = &pcie1_gdsc,
3477	[USB30_GDSC] = &usb30_gdsc,
3478};
3479
3480static const struct qcom_reset_map gcc_apq8084_resets[] = {
3481	[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3482	[GCC_CONFIG_NOC_BCR] = { 0x0140 },
3483	[GCC_PERIPH_NOC_BCR] = { 0x0180 },
3484	[GCC_IMEM_BCR] = { 0x0200 },
3485	[GCC_MMSS_BCR] = { 0x0240 },
3486	[GCC_QDSS_BCR] = { 0x0300 },
3487	[GCC_USB_30_BCR] = { 0x03c0 },
3488	[GCC_USB3_PHY_BCR] = { 0x03fc },
3489	[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3490	[GCC_USB_HS_BCR] = { 0x0480 },
3491	[GCC_USB2A_PHY_BCR] = { 0x04a8 },
3492	[GCC_USB2B_PHY_BCR] = { 0x04b0 },
3493	[GCC_SDCC1_BCR] = { 0x04c0 },
3494	[GCC_SDCC2_BCR] = { 0x0500 },
3495	[GCC_SDCC3_BCR] = { 0x0540 },
3496	[GCC_SDCC4_BCR] = { 0x0580 },
3497	[GCC_BLSP1_BCR] = { 0x05c0 },
3498	[GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3499	[GCC_BLSP1_UART1_BCR] = { 0x0680 },
3500	[GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3501	[GCC_BLSP1_UART2_BCR] = { 0x0700 },
3502	[GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3503	[GCC_BLSP1_UART3_BCR] = { 0x0780 },
3504	[GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3505	[GCC_BLSP1_UART4_BCR] = { 0x0800 },
3506	[GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3507	[GCC_BLSP1_UART5_BCR] = { 0x0880 },
3508	[GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3509	[GCC_BLSP1_UART6_BCR] = { 0x0900 },
3510	[GCC_BLSP2_BCR] = { 0x0940 },
3511	[GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3512	[GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3513	[GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3514	[GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3515	[GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3516	[GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3517	[GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3518	[GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3519	[GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3520	[GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3521	[GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3522	[GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3523	[GCC_PDM_BCR] = { 0x0cc0 },
3524	[GCC_PRNG_BCR] = { 0x0d00 },
3525	[GCC_BAM_DMA_BCR] = { 0x0d40 },
3526	[GCC_TSIF_BCR] = { 0x0d80 },
3527	[GCC_TCSR_BCR] = { 0x0dc0 },
3528	[GCC_BOOT_ROM_BCR] = { 0x0e00 },
3529	[GCC_MSG_RAM_BCR] = { 0x0e40 },
3530	[GCC_TLMM_BCR] = { 0x0e80 },
3531	[GCC_MPM_BCR] = { 0x0ec0 },
3532	[GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3533	[GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3534	[GCC_SEC_CTRL_BCR] = { 0x0f40 },
3535	[GCC_SPMI_BCR] = { 0x0fc0 },
3536	[GCC_SPDM_BCR] = { 0x1000 },
3537	[GCC_CE1_BCR] = { 0x1040 },
3538	[GCC_CE2_BCR] = { 0x1080 },
3539	[GCC_BIMC_BCR] = { 0x1100 },
3540	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3541	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3542	[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3543	[GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3544	[GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3545	[GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3546	[GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3547	[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3548	[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3549	[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3550	[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3551	[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3552	[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3553	[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3554	[GCC_DEHR_BCR] = { 0x1300 },
3555	[GCC_RBCPR_BCR] = { 0x1380 },
3556	[GCC_MSS_RESTART] = { 0x1680 },
3557	[GCC_LPASS_RESTART] = { 0x16c0 },
3558	[GCC_WCSS_RESTART] = { 0x1700 },
3559	[GCC_VENUS_RESTART] = { 0x1740 },
3560	[GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3561	[GCC_SPSS_BCR] = { 0x1a80 },
3562	[GCC_PCIE_0_BCR] = { 0x1ac0 },
3563	[GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3564	[GCC_PCIE_1_BCR] = { 0x1b40 },
3565	[GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3566	[GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3567	[GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3568	[GCC_SATA_BCR] = { 0x1c40 },
3569	[GCC_CE3_BCR] = { 0x1d00 },
3570	[GCC_UFS_BCR] = { 0x1d40 },
3571	[GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3572};
3573
3574static const struct regmap_config gcc_apq8084_regmap_config = {
3575	.reg_bits	= 32,
3576	.reg_stride	= 4,
3577	.val_bits	= 32,
3578	.max_register	= 0x1fc0,
3579	.fast_io	= true,
3580};
3581
3582static const struct qcom_cc_desc gcc_apq8084_desc = {
3583	.config = &gcc_apq8084_regmap_config,
3584	.clks = gcc_apq8084_clocks,
3585	.num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
3586	.resets = gcc_apq8084_resets,
3587	.num_resets = ARRAY_SIZE(gcc_apq8084_resets),
3588	.gdscs = gcc_apq8084_gdscs,
3589	.num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
3590};
3591
3592static const struct of_device_id gcc_apq8084_match_table[] = {
3593	{ .compatible = "qcom,gcc-apq8084" },
3594	{ }
3595};
3596MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3597
3598static int gcc_apq8084_probe(struct platform_device *pdev)
3599{
3600	int ret;
3601	struct device *dev = &pdev->dev;
3602
3603	ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3604	if (ret)
3605		return ret;
3606
3607	ret = qcom_cc_register_sleep_clk(dev);
3608	if (ret)
3609		return ret;
3610
3611	return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3612}
3613
3614static struct platform_driver gcc_apq8084_driver = {
3615	.probe		= gcc_apq8084_probe,
3616	.driver		= {
3617		.name	= "gcc-apq8084",
3618		.of_match_table = gcc_apq8084_match_table,
3619	},
3620};
3621
3622static int __init gcc_apq8084_init(void)
3623{
3624	return platform_driver_register(&gcc_apq8084_driver);
3625}
3626core_initcall(gcc_apq8084_init);
3627
3628static void __exit gcc_apq8084_exit(void)
3629{
3630	platform_driver_unregister(&gcc_apq8084_driver);
3631}
3632module_exit(gcc_apq8084_exit);
3633
3634MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3635MODULE_LICENSE("GPL v2");
3636MODULE_ALIAS("platform:gcc-apq8084");