1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * HEART IRQ defines
 4 *
 5 * Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de>
 6 *		 2014-2016 Joshua Kinard <kumba@gentoo.org>
 7 *
 8 */
 9
10#ifndef __ASM_MACH_IP30_IRQ_H
11#define __ASM_MACH_IP30_IRQ_H
12
13/*
14 * HEART has 64 hardware interrupts, but use 128 to leave room for a few
15 * software interrupts as well (such as the CPU timer interrupt.
16 */
17#define NR_IRQS				128
18
19extern void __init ip30_install_ipi(void);
20
21/*
22 * HEART has 64 interrupt vectors available to it, subdivided into five
23 * priority levels.  They are numbered 0 to 63.
24 */
25#define HEART_NUM_IRQS			64
26
27/*
28 * These are the five interrupt priority levels and their corresponding
29 * CPU IPx interrupt pins.
30 *
31 * Level 4 - Error Interrupts.
32 * Level 3 - HEART timer interrupt.
33 * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
34 * Level 1 - General device interrupts.
35 * Level 0 - General device GFX flow control interrupts.
36 */
37#define HEART_L4_INT_MASK		0xfff8000000000000ULL	/* IP6 */
38#define HEART_L3_INT_MASK		0x0004000000000000ULL	/* IP5 */
39#define HEART_L2_INT_MASK		0x0003ffff00000000ULL	/* IP4 */
40#define HEART_L1_INT_MASK		0x00000000ffff0000ULL	/* IP3 */
41#define HEART_L0_INT_MASK		0x000000000000ffffULL	/* IP2 */
42
43/* HEART L0 Interrupts (Low Priority) */
44#define HEART_L0_INT_GENERIC		 0
45#define HEART_L0_INT_FLOW_CTRL_HWTR_0	 1
46#define HEART_L0_INT_FLOW_CTRL_HWTR_1	 2
47
48/* HEART L2 Interrupts (High Priority) */
49#define HEART_L2_INT_RESCHED_CPU_0	46
50#define HEART_L2_INT_RESCHED_CPU_1	47
51#define HEART_L2_INT_CALL_CPU_0		48
52#define HEART_L2_INT_CALL_CPU_1		49
53
54/* HEART L3 Interrupts (Compare/Counter Timer) */
55#define HEART_L3_INT_TIMER		50
56
57/* HEART L4 Interrupts (Errors) */
58#define HEART_L4_INT_XWID_ERR_9		51
59#define HEART_L4_INT_XWID_ERR_A		52
60#define HEART_L4_INT_XWID_ERR_B		53
61#define HEART_L4_INT_XWID_ERR_C		54
62#define HEART_L4_INT_XWID_ERR_D		55
63#define HEART_L4_INT_XWID_ERR_E		56
64#define HEART_L4_INT_XWID_ERR_F		57
65#define HEART_L4_INT_XWID_ERR_XBOW	58
66#define HEART_L4_INT_CPU_BUS_ERR_0	59
67#define HEART_L4_INT_CPU_BUS_ERR_1	60
68#define HEART_L4_INT_CPU_BUS_ERR_2	61
69#define HEART_L4_INT_CPU_BUS_ERR_3	62
70#define HEART_L4_INT_HEART_EXCP		63
71
72/*
73 * Power Switch is wired via BaseIO BRIDGE slot #6.
74 *
75 * ACFail is wired via BaseIO BRIDGE slot #7.
76 */
77#define IP30_POWER_IRQ		HEART_L2_INT_POWER_BTN
78
79#include <asm/mach-generic/irq.h>
80
81#define IP30_HEART_L0_IRQ	(MIPS_CPU_IRQ_BASE + 2)
82#define IP30_HEART_L1_IRQ	(MIPS_CPU_IRQ_BASE + 3)
83#define IP30_HEART_L2_IRQ	(MIPS_CPU_IRQ_BASE + 4)
84#define IP30_HEART_TIMER_IRQ	(MIPS_CPU_IRQ_BASE + 5)
85#define IP30_HEART_ERR_IRQ	(MIPS_CPU_IRQ_BASE + 6)
86
87#endif /* __ASM_MACH_IP30_IRQ_H */