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1/*
2 * OMAP44xx PRCM MPU instance offset macros
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22 * or "OMAP4430".
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
27
28#define OMAP4430_PRCM_MPU_BASE 0x48243000
29
30#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
32
33/* PRCM_MPU instances */
34#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
35#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
36#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
37#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
38
39/* PRCM_MPU clockdomain register offsets (from instance start) */
40#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
41#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
42
43
44/*
45 * PRCM_MPU
46 *
47 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
48 * point of view the PRCM_MPU is a single entity. It shares the same
49 * programming model as the global PRCM and thus can be assimilate as two new
50 * MOD inside the PRCM
51 */
52
53/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
54#define OMAP4_REVISION_PRCM_OFFSET 0x0000
55#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
56
57/* PRCM_MPU.DEVICE_PRM register offsets */
58#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
59#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
60#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
61#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
62
63/* PRCM_MPU.CPU0 register offsets */
64#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
65#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
66#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
67#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
68#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
69#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
70#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
71#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
72#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
73#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
74#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
75#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
76#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
77#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
78
79/* PRCM_MPU.CPU1 register offsets */
80#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
81#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
82#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
83#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
84#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
85#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
86#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
87#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
88#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
89#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
90#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
91#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
92#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
93#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
94
95/* Function prototypes */
96# ifndef __ASSEMBLER__
97extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
98extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
99extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
100 s16 idx);
101# endif
102
103#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * OMAP44xx PRCM MPU instance offset macros
4 *
5 * Copyright (C) 2010, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2010 Nokia Corporation
7 *
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
19 * or "OMAP4430".
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
24
25#include "prcm_mpu_44xx_54xx.h"
26
27#define OMAP4430_PRCM_MPU_BASE 0x48243000
28
29#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
31
32/* PRCM_MPU instances */
33#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
37
38/* PRCM_MPU clockdomain register offsets (from instance start) */
39#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
41
42
43/*
44 * PRCM_MPU
45 *
46 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
47 * point of view the PRCM_MPU is a single entity. It shares the same
48 * programming model as the global PRCM and thus can be assimilate as two new
49 * MOD inside the PRCM
50 */
51
52/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
53#define OMAP4_REVISION_PRCM_OFFSET 0x0000
54#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
55
56/* PRCM_MPU.DEVICE_PRM register offsets */
57#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
58#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
59#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
60#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
61
62/* PRCM_MPU.CPU0 register offsets */
63#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
64#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
65#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
66#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
67#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
68#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
69#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
70#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
71#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
72#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
73#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
74#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
75#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
76#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
77
78/* PRCM_MPU.CPU1 register offsets */
79#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
80#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
81#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
82#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
83#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
84#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
85#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
86#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
87#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
88#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
89#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
90#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
91#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
92#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
93
94#endif