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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Hardware modules present on the OMAP54xx chips
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 */
16
17#include <linux/io.h>
18#include <linux/power/smartreflex.h>
19
20#include "omap_hwmod.h"
21#include "omap_hwmod_common_data.h"
22#include "cm1_54xx.h"
23#include "cm2_54xx.h"
24#include "prm54xx.h"
25
26/* Base offset for all OMAP5 interrupts external to MPUSS */
27#define OMAP54XX_IRQ_GIC_START 32
28
29/*
30 * IP blocks
31 */
32
33/*
34 * 'dmm' class
35 * instance(s): dmm
36 */
37static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
38 .name = "dmm",
39};
40
41/* dmm */
42static struct omap_hwmod omap54xx_dmm_hwmod = {
43 .name = "dmm",
44 .class = &omap54xx_dmm_hwmod_class,
45 .clkdm_name = "emif_clkdm",
46 .prcm = {
47 .omap4 = {
48 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
49 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
50 },
51 },
52};
53
54/*
55 * 'l3' class
56 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
57 */
58static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
59 .name = "l3",
60};
61
62/* l3_instr */
63static struct omap_hwmod omap54xx_l3_instr_hwmod = {
64 .name = "l3_instr",
65 .class = &omap54xx_l3_hwmod_class,
66 .clkdm_name = "l3instr_clkdm",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
70 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
71 .modulemode = MODULEMODE_HWCTRL,
72 },
73 },
74};
75
76/* l3_main_1 */
77static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
78 .name = "l3_main_1",
79 .class = &omap54xx_l3_hwmod_class,
80 .clkdm_name = "l3main1_clkdm",
81 .prcm = {
82 .omap4 = {
83 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
84 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
85 },
86 },
87};
88
89/* l3_main_2 */
90static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
91 .name = "l3_main_2",
92 .class = &omap54xx_l3_hwmod_class,
93 .clkdm_name = "l3main2_clkdm",
94 .prcm = {
95 .omap4 = {
96 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
97 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
98 },
99 },
100};
101
102/* l3_main_3 */
103static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
104 .name = "l3_main_3",
105 .class = &omap54xx_l3_hwmod_class,
106 .clkdm_name = "l3instr_clkdm",
107 .prcm = {
108 .omap4 = {
109 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
110 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
111 .modulemode = MODULEMODE_HWCTRL,
112 },
113 },
114};
115
116/*
117 * 'l4' class
118 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
119 */
120static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
121 .name = "l4",
122};
123
124/* l4_abe */
125static struct omap_hwmod omap54xx_l4_abe_hwmod = {
126 .name = "l4_abe",
127 .class = &omap54xx_l4_hwmod_class,
128 .clkdm_name = "abe_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
132 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
133 },
134 },
135};
136
137/* l4_cfg */
138static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
139 .name = "l4_cfg",
140 .class = &omap54xx_l4_hwmod_class,
141 .clkdm_name = "l4cfg_clkdm",
142 .prcm = {
143 .omap4 = {
144 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
145 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
146 },
147 },
148};
149
150/* l4_per */
151static struct omap_hwmod omap54xx_l4_per_hwmod = {
152 .name = "l4_per",
153 .class = &omap54xx_l4_hwmod_class,
154 .clkdm_name = "l4per_clkdm",
155 .prcm = {
156 .omap4 = {
157 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
158 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
159 },
160 },
161};
162
163/* l4_wkup */
164static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
165 .name = "l4_wkup",
166 .class = &omap54xx_l4_hwmod_class,
167 .clkdm_name = "wkupaon_clkdm",
168 .prcm = {
169 .omap4 = {
170 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
171 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
172 },
173 },
174};
175
176/*
177 * 'mpu_bus' class
178 * instance(s): mpu_private
179 */
180static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
181 .name = "mpu_bus",
182};
183
184/* mpu_private */
185static struct omap_hwmod omap54xx_mpu_private_hwmod = {
186 .name = "mpu_private",
187 .class = &omap54xx_mpu_bus_hwmod_class,
188 .clkdm_name = "mpu_clkdm",
189 .prcm = {
190 .omap4 = {
191 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
192 },
193 },
194};
195
196/*
197 * 'emif' class
198 * external memory interface no1 (wrapper)
199 */
200
201static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
202 .rev_offs = 0x0000,
203};
204
205static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
206 .name = "emif",
207 .sysc = &omap54xx_emif_sysc,
208};
209
210/* emif1 */
211static struct omap_hwmod omap54xx_emif1_hwmod = {
212 .name = "emif1",
213 .class = &omap54xx_emif_hwmod_class,
214 .clkdm_name = "emif_clkdm",
215 .flags = HWMOD_INIT_NO_IDLE,
216 .main_clk = "dpll_core_h11x2_ck",
217 .prcm = {
218 .omap4 = {
219 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
220 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
221 .modulemode = MODULEMODE_HWCTRL,
222 },
223 },
224};
225
226/* emif2 */
227static struct omap_hwmod omap54xx_emif2_hwmod = {
228 .name = "emif2",
229 .class = &omap54xx_emif_hwmod_class,
230 .clkdm_name = "emif_clkdm",
231 .flags = HWMOD_INIT_NO_IDLE,
232 .main_clk = "dpll_core_h11x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
236 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
238 },
239 },
240};
241
242
243
244
245/*
246 * 'mpu' class
247 * mpu sub-system
248 */
249
250static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
251 .name = "mpu",
252};
253
254/* mpu */
255static struct omap_hwmod omap54xx_mpu_hwmod = {
256 .name = "mpu",
257 .class = &omap54xx_mpu_hwmod_class,
258 .clkdm_name = "mpu_clkdm",
259 .flags = HWMOD_INIT_NO_IDLE,
260 .main_clk = "dpll_mpu_m2_ck",
261 .prcm = {
262 .omap4 = {
263 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
264 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
265 },
266 },
267};
268
269/*
270 * 'sata' class
271 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
272 */
273
274static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
275 .rev_offs = 0x00fc,
276 .sysc_offs = 0x0000,
277 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
278 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
279 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
280 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
281 .sysc_fields = &omap_hwmod_sysc_type2,
282};
283
284static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
285 .name = "sata",
286 .sysc = &omap54xx_sata_sysc,
287};
288
289/* sata */
290static struct omap_hwmod omap54xx_sata_hwmod = {
291 .name = "sata",
292 .class = &omap54xx_sata_hwmod_class,
293 .clkdm_name = "l3init_clkdm",
294 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
295 .main_clk = "func_48m_fclk",
296 .mpu_rt_idx = 1,
297 .prcm = {
298 .omap4 = {
299 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
300 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
301 .modulemode = MODULEMODE_SWCTRL,
302 },
303 },
304};
305
306/* l4_cfg -> sata */
307static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
308 .master = &omap54xx_l4_cfg_hwmod,
309 .slave = &omap54xx_sata_hwmod,
310 .clk = "l3_iclk_div",
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
312};
313
314/*
315 * Interfaces
316 */
317
318/* l3_main_1 -> dmm */
319static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
320 .master = &omap54xx_l3_main_1_hwmod,
321 .slave = &omap54xx_dmm_hwmod,
322 .clk = "l3_iclk_div",
323 .user = OCP_USER_SDMA,
324};
325
326/* l3_main_3 -> l3_instr */
327static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
328 .master = &omap54xx_l3_main_3_hwmod,
329 .slave = &omap54xx_l3_instr_hwmod,
330 .clk = "l3_iclk_div",
331 .user = OCP_USER_MPU | OCP_USER_SDMA,
332};
333
334/* l3_main_2 -> l3_main_1 */
335static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
336 .master = &omap54xx_l3_main_2_hwmod,
337 .slave = &omap54xx_l3_main_1_hwmod,
338 .clk = "l3_iclk_div",
339 .user = OCP_USER_MPU | OCP_USER_SDMA,
340};
341
342/* l4_cfg -> l3_main_1 */
343static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
344 .master = &omap54xx_l4_cfg_hwmod,
345 .slave = &omap54xx_l3_main_1_hwmod,
346 .clk = "l3_iclk_div",
347 .user = OCP_USER_MPU | OCP_USER_SDMA,
348};
349
350/* mpu -> l3_main_1 */
351static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
352 .master = &omap54xx_mpu_hwmod,
353 .slave = &omap54xx_l3_main_1_hwmod,
354 .clk = "l3_iclk_div",
355 .user = OCP_USER_MPU,
356};
357
358/* l3_main_1 -> l3_main_2 */
359static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
360 .master = &omap54xx_l3_main_1_hwmod,
361 .slave = &omap54xx_l3_main_2_hwmod,
362 .clk = "l3_iclk_div",
363 .user = OCP_USER_MPU,
364};
365
366/* l4_cfg -> l3_main_2 */
367static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
368 .master = &omap54xx_l4_cfg_hwmod,
369 .slave = &omap54xx_l3_main_2_hwmod,
370 .clk = "l3_iclk_div",
371 .user = OCP_USER_MPU | OCP_USER_SDMA,
372};
373
374/* l3_main_1 -> l3_main_3 */
375static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
376 .master = &omap54xx_l3_main_1_hwmod,
377 .slave = &omap54xx_l3_main_3_hwmod,
378 .clk = "l3_iclk_div",
379 .user = OCP_USER_MPU,
380};
381
382/* l3_main_2 -> l3_main_3 */
383static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
384 .master = &omap54xx_l3_main_2_hwmod,
385 .slave = &omap54xx_l3_main_3_hwmod,
386 .clk = "l3_iclk_div",
387 .user = OCP_USER_MPU | OCP_USER_SDMA,
388};
389
390/* l4_cfg -> l3_main_3 */
391static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
392 .master = &omap54xx_l4_cfg_hwmod,
393 .slave = &omap54xx_l3_main_3_hwmod,
394 .clk = "l3_iclk_div",
395 .user = OCP_USER_MPU | OCP_USER_SDMA,
396};
397
398/* l3_main_1 -> l4_abe */
399static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
400 .master = &omap54xx_l3_main_1_hwmod,
401 .slave = &omap54xx_l4_abe_hwmod,
402 .clk = "abe_iclk",
403 .user = OCP_USER_MPU | OCP_USER_SDMA,
404};
405
406/* mpu -> l4_abe */
407static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
408 .master = &omap54xx_mpu_hwmod,
409 .slave = &omap54xx_l4_abe_hwmod,
410 .clk = "abe_iclk",
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412};
413
414/* l3_main_1 -> l4_cfg */
415static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
416 .master = &omap54xx_l3_main_1_hwmod,
417 .slave = &omap54xx_l4_cfg_hwmod,
418 .clk = "l4_root_clk_div",
419 .user = OCP_USER_MPU | OCP_USER_SDMA,
420};
421
422/* l3_main_2 -> l4_per */
423static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
424 .master = &omap54xx_l3_main_2_hwmod,
425 .slave = &omap54xx_l4_per_hwmod,
426 .clk = "l4_root_clk_div",
427 .user = OCP_USER_MPU | OCP_USER_SDMA,
428};
429
430/* l3_main_1 -> l4_wkup */
431static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
432 .master = &omap54xx_l3_main_1_hwmod,
433 .slave = &omap54xx_l4_wkup_hwmod,
434 .clk = "wkupaon_iclk_mux",
435 .user = OCP_USER_MPU | OCP_USER_SDMA,
436};
437
438/* mpu -> mpu_private */
439static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
440 .master = &omap54xx_mpu_hwmod,
441 .slave = &omap54xx_mpu_private_hwmod,
442 .clk = "l3_iclk_div",
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
444};
445
446/* mpu -> emif1 */
447static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
448 .master = &omap54xx_mpu_hwmod,
449 .slave = &omap54xx_emif1_hwmod,
450 .clk = "dpll_core_h11x2_ck",
451 .user = OCP_USER_MPU | OCP_USER_SDMA,
452};
453
454/* mpu -> emif2 */
455static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
456 .master = &omap54xx_mpu_hwmod,
457 .slave = &omap54xx_emif2_hwmod,
458 .clk = "dpll_core_h11x2_ck",
459 .user = OCP_USER_MPU | OCP_USER_SDMA,
460};
461
462/* l4_cfg -> mpu */
463static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
464 .master = &omap54xx_l4_cfg_hwmod,
465 .slave = &omap54xx_mpu_hwmod,
466 .clk = "l4_root_clk_div",
467 .user = OCP_USER_MPU | OCP_USER_SDMA,
468};
469
470static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
471 &omap54xx_l3_main_1__dmm,
472 &omap54xx_l3_main_3__l3_instr,
473 &omap54xx_l3_main_2__l3_main_1,
474 &omap54xx_l4_cfg__l3_main_1,
475 &omap54xx_mpu__l3_main_1,
476 &omap54xx_l3_main_1__l3_main_2,
477 &omap54xx_l4_cfg__l3_main_2,
478 &omap54xx_l3_main_1__l3_main_3,
479 &omap54xx_l3_main_2__l3_main_3,
480 &omap54xx_l4_cfg__l3_main_3,
481 &omap54xx_l3_main_1__l4_abe,
482 &omap54xx_mpu__l4_abe,
483 &omap54xx_l3_main_1__l4_cfg,
484 &omap54xx_l3_main_2__l4_per,
485 &omap54xx_l3_main_1__l4_wkup,
486 &omap54xx_mpu__mpu_private,
487 &omap54xx_mpu__emif1,
488 &omap54xx_mpu__emif2,
489 &omap54xx_l4_cfg__mpu,
490 &omap54xx_l4_cfg__sata,
491 NULL,
492};
493
494int __init omap54xx_hwmod_init(void)
495{
496 omap_hwmod_init();
497 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
498}