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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * DRA7xx CM2 instance offset macros
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Generated by code originally written by:
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
20#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
21
22/* CM2 base address */
23#define DRA7XX_CM_CORE_BASE 0x4a008000
24
25#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
26 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
27
28/* CM_CORE instances */
29#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31#define DRA7XX_CM_CORE_COREAON_INST 0x0600
32#define DRA7XX_CM_CORE_CORE_INST 0x0700
33#define DRA7XX_CM_CORE_IVA_INST 0x0f00
34#define DRA7XX_CM_CORE_CAM_INST 0x1000
35#define DRA7XX_CM_CORE_DSS_INST 0x1100
36#define DRA7XX_CM_CORE_GPU_INST 0x1200
37#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
38#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
39#define DRA7XX_CM_CORE_L4PER_INST 0x1700
40#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
41
42/* CM_CORE clockdomain register offsets (from instance start) */
43#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
44#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
45#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
46#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
47#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
48#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
49#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
50#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
51#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
52#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
53#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
54#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
55#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
56#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
57#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
58#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
61#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
62#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
63
64/* CM_CORE */
65
66/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
67#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
68#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
69#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
70#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
71
72/* CM_CORE.CKGEN_CM_CORE register offsets */
73#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
74#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
75#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
76#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
77#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
78#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
79#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
80#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
81#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
82#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
83#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
84#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
85#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
86#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
87#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
88#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
89#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
90#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
91#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
92#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
93#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
94#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
95#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
96#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
97#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
98#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
99#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
100#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
101#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
102#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
103#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
104#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
105#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
106#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
107#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
108#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
109#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
110#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
111#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
112#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
113#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
114#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
115#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
116#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
117#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
118#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
119#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
120#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
121#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
122#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
123#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
124#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
125#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
126#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
127#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
128#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
129#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
130#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
131
132/* CM_CORE.COREAON_CM_CORE register offsets */
133#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
134#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
135#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
136#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
137#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
138#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
139#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
140#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
141#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
142#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
143#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
144#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
145#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
146#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
147#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
148#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
149#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
150#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
151#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
152#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
153#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
154#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
155#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
156#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
157#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
158#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
159#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
160
161/* CM_CORE.CORE_CM_CORE register offsets */
162#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
163#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
164#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
165#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
166#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
167#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
168#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
169#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
170#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
171#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
172#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
173#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
174#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
175#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
176#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
177#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
178#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
179#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
180#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
181#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
182#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
183#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
184#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
185#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
186#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
187#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
188#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
189#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
190#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
191#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
192#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
193#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
194#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
195#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
196#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
197#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
198#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
199#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
200#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
201#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
202#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
203#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
204#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
205#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
206#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
207#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
208#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
209#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
210#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
211#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
212#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
213#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
214#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
215#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
216#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
217#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
218#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
219#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
220#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
221#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
222#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
223#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
224#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
225#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
226#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
227#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
228#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
229#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
230#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
231#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
232#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
233#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
234#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
235#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
236#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
237#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
238#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
239#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
240#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
241#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
242#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
243#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
244#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
245#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
246#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
247#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
248#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
249#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
250#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
251#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
252#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
253#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
254#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
255#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
256#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
257#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
258#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
259#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
260#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
261#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
262#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
263#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
264#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
265#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
266#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
267#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
268#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
269#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
270#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
271#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
272#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
273#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
274#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
275#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
276#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
277#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
278#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
279#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
280#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
281#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
282#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
283#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
284#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
285#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
286#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
287#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
288#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
289
290/* CM_CORE.IVA_CM_CORE register offsets */
291#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
292#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
293#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
294#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
295#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
296#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
297#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
298
299/* CM_CORE.CAM_CM_CORE register offsets */
300#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
301#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
302#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
303#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
304#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
305#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
306#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
307#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
308#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
309#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
310#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
311#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
312#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
313#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
314
315/* CM_CORE.DSS_CM_CORE register offsets */
316#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
317#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
318#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
319#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
320#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
321#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
322#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
323#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
324#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
325
326/* CM_CORE.GPU_CM_CORE register offsets */
327#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
328#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
329#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
330#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
331#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
332
333/* CM_CORE.L3INIT_CM_CORE register offsets */
334#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
335#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
336#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
337#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
338#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
339#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
340#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
341#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
342#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
343#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
344#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
345#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
346#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
347#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
348#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
349#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
350#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
351#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
352#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
353#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
354#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
355#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
356#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
357#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
358#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
359#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
360#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
361#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
362#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
363#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
364#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
365#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
366#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
367#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
368#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
369#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
370
371/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
372#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
373#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
374#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
375
376/* CM_CORE.L4PER_CM_CORE register offsets */
377#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
378#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
379#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
380#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
381#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
382#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
383#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
384#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
385#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
386#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
387#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
388#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
389#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
390#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
391#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
392#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
393#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
394#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
395#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
396#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
397#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
398#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
399#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
400#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
401#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
402#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
403#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
404#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
405#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
406#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
407#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
408#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
409#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
410#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
411#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
412#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
413#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
414#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
415#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
416#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
417#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
418#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
419#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
420#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
421#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
422#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
423#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
424#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
425#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
426#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
427#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
428#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
429#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
430#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
431#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
432#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
433#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
434#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
435#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
436#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
437#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
438#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
439#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
440#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
441#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
442#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
443#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
444#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
445#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
446#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
447#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
448#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
449#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
450#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
451#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
452#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
453#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
454#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
455#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
456#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
457#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
458#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
459#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
460#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
461#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
462#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
463#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
464#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
465#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
466#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
467#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
468#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
469#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
470#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
471#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
472#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
473#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
474#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
475#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
476#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
477#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
478#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
479#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
480#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
481#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
482#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
483#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
484#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
485#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
486#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
487#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
488#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
489#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
490#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
491#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
492#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
493#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
494#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
495#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
496#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
497#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
498#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
499#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
500#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
501#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
502#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
503#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
504#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
505#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
506#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
507#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
508#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
509#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
510#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
511
512#endif