1/*
  2 * pxa910 clock framework source file
  3 *
  4 * Copyright (C) 2012 Marvell
  5 * Chao Xie <xiechao.mail@gmail.com>
  6 *
  7 * This file is licensed under the terms of the GNU General Public
  8 * License version 2. This program is licensed "as is" without any
  9 * warranty of any kind, whether express or implied.
 10 */
 11
 12#include <linux/module.h>
 13#include <linux/kernel.h>
 14#include <linux/spinlock.h>
 15#include <linux/io.h>
 16#include <linux/delay.h>
 17#include <linux/err.h>
 18#include <linux/of_address.h>
 19
 20#include <dt-bindings/clock/marvell,pxa910.h>
 21
 22#include "clk.h"
 23#include "reset.h"
 24
 25#define APBC_RTC	0x28
 26#define APBC_TWSI0	0x2c
 27#define APBC_KPC	0x18
 28#define APBC_UART0	0x0
 29#define APBC_UART1	0x4
 30#define APBC_GPIO	0x8
 31#define APBC_PWM0	0xc
 32#define APBC_PWM1	0x10
 33#define APBC_PWM2	0x14
 34#define APBC_PWM3	0x18
 35#define APBC_SSP0	0x1c
 36#define APBC_SSP1	0x20
 37#define APBC_SSP2	0x4c
 38#define APBC_TIMER0	0x30
 39#define APBC_TIMER1	0x44
 40#define APBCP_TWSI1	0x28
 41#define APBCP_UART2	0x1c
 42#define APMU_SDH0	0x54
 43#define APMU_SDH1	0x58
 44#define APMU_USB	0x5c
 45#define APMU_DISP0	0x4c
 46#define APMU_CCIC0	0x50
 47#define APMU_DFC	0x60
 48#define MPMU_UART_PLL	0x14
 49
 50struct pxa910_clk_unit {
 51	struct mmp_clk_unit unit;
 52	void __iomem *mpmu_base;
 53	void __iomem *apmu_base;
 54	void __iomem *apbc_base;
 55	void __iomem *apbcp_base;
 56};
 57
 58static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
 59	{PXA910_CLK_CLK32, "clk32", NULL, 0, 32768},
 60	{PXA910_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
 61	{PXA910_CLK_PLL1, "pll1", NULL, 0, 624000000},
 62	{PXA910_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
 63};
 64
 65static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
 66	{PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
 67	{PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
 68	{PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
 69	{PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
 70	{PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
 71	{PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
 72	{PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
 73	{PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
 74	{PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
 75	{PXA910_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
 76	{PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
 77	{PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
 78	{PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
 79	{PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
 80};
 81
 82static struct mmp_clk_factor_masks uart_factor_masks = {
 83	.factor = 2,
 84	.num_mask = 0x1fff,
 85	.den_mask = 0x1fff,
 86	.num_shift = 16,
 87	.den_shift = 0,
 88};
 89
 90static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
 91	{.num = 8125, .den = 1536},	/*14.745MHZ */
 92};
 93
 94static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
 95{
 96	struct clk *clk;
 97	struct mmp_clk_unit *unit = &pxa_unit->unit;
 98
 99	mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
100					ARRAY_SIZE(fixed_rate_clks));
101
102	mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
103					ARRAY_SIZE(fixed_factor_clks));
104
105	clk = mmp_clk_register_factor("uart_pll", "pll1_4",
106				CLK_SET_RATE_PARENT,
107				pxa_unit->mpmu_base + MPMU_UART_PLL,
108				&uart_factor_masks, uart_factor_tbl,
109				ARRAY_SIZE(uart_factor_tbl), NULL);
110	mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
111}
112
113static DEFINE_SPINLOCK(uart0_lock);
114static DEFINE_SPINLOCK(uart1_lock);
115static DEFINE_SPINLOCK(uart2_lock);
116static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
117
118static DEFINE_SPINLOCK(ssp0_lock);
119static DEFINE_SPINLOCK(ssp1_lock);
120static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
121
122static DEFINE_SPINLOCK(timer0_lock);
123static DEFINE_SPINLOCK(timer1_lock);
124static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96"};
125
126static DEFINE_SPINLOCK(reset_lock);
127
128static struct mmp_param_mux_clk apbc_mux_clks[] = {
129	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
130	{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
131	{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
132	{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
133	{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock},
134	{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock},
135};
136
137static struct mmp_param_mux_clk apbcp_mux_clks[] = {
138	{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
139};
140
141static struct mmp_param_gate_clk apbc_gate_clks[] = {
142	{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
143	{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
144	{PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
145	{PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
146	{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
147	{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
148	{PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
149	{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
150	/* The gate clocks has mux parent. */
151	{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
152	{PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
153	{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
154	{PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
155	{PXA910_CLK_TIMER0, "timer0_clk", "timer0_mux", CLK_SET_RATE_PARENT, APBC_TIMER0, 0x3, 0x3, 0x0, 0, &timer0_lock},
156	{PXA910_CLK_TIMER1, "timer1_clk", "timer1_mux", CLK_SET_RATE_PARENT, APBC_TIMER1, 0x3, 0x3, 0x0, 0, &timer1_lock},
157};
158
159static struct mmp_param_gate_clk apbcp_gate_clks[] = {
160	{PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
161	/* The gate clocks has mux parent. */
162	{PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
163};
164
165static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
166{
167	struct mmp_clk_unit *unit = &pxa_unit->unit;
168
169	mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
170				ARRAY_SIZE(apbc_mux_clks));
171
172	mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
173				ARRAY_SIZE(apbcp_mux_clks));
174
175	mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
176				ARRAY_SIZE(apbc_gate_clks));
177
178	mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
179				ARRAY_SIZE(apbcp_gate_clks));
180}
181
182static DEFINE_SPINLOCK(sdh0_lock);
183static DEFINE_SPINLOCK(sdh1_lock);
184static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
185
186static DEFINE_SPINLOCK(usb_lock);
187
188static DEFINE_SPINLOCK(disp0_lock);
189static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
190
191static DEFINE_SPINLOCK(ccic0_lock);
192static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
193static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
194
195static struct mmp_param_mux_clk apmu_mux_clks[] = {
196	{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
197	{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
198	{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
199	{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
200	{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
201};
202
203static struct mmp_param_div_clk apmu_div_clks[] = {
204	{0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
205};
206
207static struct mmp_param_gate_clk apmu_gate_clks[] = {
208	{PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
209	{PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
210	{PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
211	/* The gate clocks has mux parent. */
212	{PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
213	{PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
214	{PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
215	{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
216	{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
217	{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
218};
219
220static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
221{
222	struct mmp_clk_unit *unit = &pxa_unit->unit;
223
224	mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
225				ARRAY_SIZE(apmu_mux_clks));
226
227	mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
228				ARRAY_SIZE(apmu_div_clks));
229
230	mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
231				ARRAY_SIZE(apmu_gate_clks));
232}
233
234static void pxa910_clk_reset_init(struct device_node *np,
235				struct pxa910_clk_unit *pxa_unit)
236{
237	struct mmp_clk_reset_cell *cells;
238	int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
239
240	nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
241	nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
242	nr_resets = nr_resets_apbc + nr_resets_apbcp;
243	cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
244	if (!cells)
245		return;
246
247	base = 0;
248	for (i = 0; i < nr_resets_apbc; i++) {
249		cells[base + i].clk_id = apbc_gate_clks[i].id;
250		cells[base + i].reg =
251			pxa_unit->apbc_base + apbc_gate_clks[i].offset;
252		cells[base + i].flags = 0;
253		cells[base + i].lock = apbc_gate_clks[i].lock;
254		cells[base + i].bits = 0x4;
255	}
256
257	base = nr_resets_apbc;
258	for (i = 0; i < nr_resets_apbcp; i++) {
259		cells[base + i].clk_id = apbcp_gate_clks[i].id;
260		cells[base + i].reg =
261			pxa_unit->apbc_base + apbc_gate_clks[i].offset;
262		cells[base + i].flags = 0;
263		cells[base + i].lock = apbc_gate_clks[i].lock;
264		cells[base + i].bits = 0x4;
265	}
266
267	mmp_clk_reset_register(np, cells, nr_resets);
268}
269
270static void __init pxa910_clk_init(struct device_node *np)
271{
272	struct pxa910_clk_unit *pxa_unit;
273
274	pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
275	if (!pxa_unit)
276		return;
277
278	pxa_unit->mpmu_base = of_iomap(np, 0);
279	if (!pxa_unit->mpmu_base) {
280		pr_err("failed to map mpmu registers\n");
281		goto free_memory;
282	}
283
284	pxa_unit->apmu_base = of_iomap(np, 1);
285	if (!pxa_unit->apmu_base) {
286		pr_err("failed to map apmu registers\n");
287		goto unmap_mpmu_region;
288	}
289
290	pxa_unit->apbc_base = of_iomap(np, 2);
291	if (!pxa_unit->apbc_base) {
292		pr_err("failed to map apbc registers\n");
293		goto unmap_apmu_region;
294	}
295
296	pxa_unit->apbcp_base = of_iomap(np, 3);
297	if (!pxa_unit->apbcp_base) {
298		pr_err("failed to map apbcp registers\n");
299		goto unmap_apbc_region;
300	}
301
302	mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
303
304	pxa910_pll_init(pxa_unit);
305
306	pxa910_apb_periph_clk_init(pxa_unit);
307
308	pxa910_axi_periph_clk_init(pxa_unit);
309
310	pxa910_clk_reset_init(np, pxa_unit);
311
312	return;
313
314unmap_apbc_region:
315	iounmap(pxa_unit->apbc_base);
316unmap_apmu_region:
317	iounmap(pxa_unit->apmu_base);
318unmap_mpmu_region:
319	iounmap(pxa_unit->mpmu_base);
320free_memory:
321	kfree(pxa_unit);
322}
323
324CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);