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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 */
5#include <linux/mm.h>
6#include <linux/delay.h>
7#include <linux/clk.h>
8#include <linux/io.h>
9#include <linux/clkdev.h>
10#include <linux/of.h>
11#include <linux/err.h>
12#include <soc/imx/revision.h>
13#include <soc/imx/timer.h>
14#include <asm/irq.h>
15
16#include "clk.h"
17
18#define MX35_CCM_BASE_ADDR 0x53f80000
19#define MX35_GPT1_BASE_ADDR 0x53f90000
20#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
21
22#define MXC_CCM_PDR0 0x04
23#define MX35_CCM_PDR2 0x0c
24#define MX35_CCM_PDR3 0x10
25#define MX35_CCM_PDR4 0x14
26#define MX35_CCM_MPCTL 0x1c
27#define MX35_CCM_PPCTL 0x20
28#define MX35_CCM_CGR0 0x2c
29#define MX35_CCM_CGR1 0x30
30#define MX35_CCM_CGR2 0x34
31#define MX35_CCM_CGR3 0x38
32
33struct arm_ahb_div {
34 unsigned char arm, ahb, sel;
35};
36
37static struct arm_ahb_div clk_consumer[] = {
38 { .arm = 1, .ahb = 4, .sel = 0},
39 { .arm = 1, .ahb = 3, .sel = 1},
40 { .arm = 2, .ahb = 2, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44 { .arm = 4, .ahb = 1, .sel = 0},
45 { .arm = 1, .ahb = 5, .sel = 0},
46 { .arm = 1, .ahb = 8, .sel = 0},
47 { .arm = 1, .ahb = 6, .sel = 1},
48 { .arm = 2, .ahb = 4, .sel = 0},
49 { .arm = 0, .ahb = 0, .sel = 0},
50 { .arm = 0, .ahb = 0, .sel = 0},
51 { .arm = 0, .ahb = 0, .sel = 0},
52 { .arm = 4, .ahb = 2, .sel = 0},
53 { .arm = 0, .ahb = 0, .sel = 0},
54};
55
56static char hsp_div_532[] = { 4, 8, 3, 0 };
57static char hsp_div_400[] = { 3, 6, 3, 0 };
58
59static struct clk_onecell_data clk_data;
60
61static const char *std_sel[] = {"ppll", "arm"};
62static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
63
64enum mx35_clks {
65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
66 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div,
67 /* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel,
68 /* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre,
69 /* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div,
70 /* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate,
71 /* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate,
72 /* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
73 /* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate,
74 /* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate,
75 /* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate,
76 /* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate,
77 /* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate,
78 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate,
79 /* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
80 /* 81 */ gpu2d_gate, ckil, clk_max
81};
82
83static struct clk *clk[clk_max];
84
85static struct clk ** const uart_clks[] __initconst = {
86 &clk[ipg],
87 &clk[uart1_gate],
88 &clk[uart2_gate],
89 &clk[uart3_gate],
90 NULL
91};
92
93static void __init _mx35_clocks_init(void)
94{
95 void __iomem *base;
96 u32 pdr0, consumer_sel, hsp_sel;
97 struct arm_ahb_div *aad;
98 unsigned char *hsp_div;
99
100 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K);
101 BUG_ON(!base);
102
103 pdr0 = __raw_readl(base + MXC_CCM_PDR0);
104 consumer_sel = (pdr0 >> 16) & 0xf;
105 aad = &clk_consumer[consumer_sel];
106 if (!aad->arm) {
107 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
108 /*
109 * We are basically stuck. Continue with a default entry and hope we
110 * get far enough to actually show the above message
111 */
112 aad = &clk_consumer[0];
113 }
114
115 clk[ckih] = imx_clk_fixed("ckih", 24000000);
116 clk[ckil] = imx_clk_fixed("ckil", 32768);
117 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
118 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
119
120 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
121
122 if (aad->sel)
123 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
124 else
125 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
126
127 if (clk_get_rate(clk[arm]) > 400000000)
128 hsp_div = hsp_div_532;
129 else
130 hsp_div = hsp_div_400;
131
132 hsp_sel = (pdr0 >> 20) & 0x3;
133 if (!hsp_div[hsp_sel]) {
134 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
135 hsp_sel = 0;
136 }
137
138 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
139
140 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
141 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
142
143 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
144 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
145 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
146
147 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
148 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
149
150 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
151 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
152 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
153 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
154
155 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
156 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */
157 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
158
159 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
160 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
161 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
162 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
163 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
164
165 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
166 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
167
168 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
169
170 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
171 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
172
173 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
174 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
175 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
176 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6);
177 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8);
178 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
179 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
180 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
181 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16);
182 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
183 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
184 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
185 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24);
186 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
187 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
188 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
189
190 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0);
191 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2);
192 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4);
193 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6);
194 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8);
195 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
196 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
197 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
198 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
199 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
200 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
201 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
202 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
203 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
204 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
205 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
206
207 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0);
208 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2);
209 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4);
210 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6);
211 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8);
212 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
213 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
214 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
215 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
216 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
217 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
218 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
219 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
220 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
221 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
222
223 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
224 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
225 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
226
227 imx_check_clocks(clk, ARRAY_SIZE(clk));
228
229 clk_prepare_enable(clk[spba_gate]);
230 clk_prepare_enable(clk[gpio1_gate]);
231 clk_prepare_enable(clk[gpio2_gate]);
232 clk_prepare_enable(clk[gpio3_gate]);
233 clk_prepare_enable(clk[iim_gate]);
234 clk_prepare_enable(clk[emi_gate]);
235 clk_prepare_enable(clk[max_gate]);
236 clk_prepare_enable(clk[iomuxc_gate]);
237
238 /*
239 * SCC is needed to boot via mmc after a watchdog reset. The clock code
240 * before conversion to common clk also enabled UART1 (which isn't
241 * handled here and not needed for mmc) and IIM (which is enabled
242 * unconditionally above).
243 */
244 clk_prepare_enable(clk[scc_gate]);
245
246 imx_register_uart_clocks(uart_clks);
247
248 imx_print_silicon_rev("i.MX35", mx35_revision());
249}
250
251int __init mx35_clocks_init(void)
252{
253 _mx35_clocks_init();
254
255 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
256 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
257 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
258 clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
259 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
260 clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
261 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
262 clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
263 clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
264 clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
265 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
266 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
267 clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
268 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
269 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
270 clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
271 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
272 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
273 /* i.mx35 has the i.mx27 type fec */
274 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
275 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
276 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
277 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
278 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
279 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
280 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
281 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
282 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
283 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
284 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
285 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
286 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
287 /* i.mx35 has the i.mx21 type uart */
288 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
289 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
290 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
291 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
292 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
293 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
294 /* i.mx35 has the i.mx21 type rtc */
295 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
296 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
297 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
298 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
299 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
300 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
301 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
302 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
303 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
304 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
305 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
306 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
307 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
308 clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27");
309 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
310 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
311 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
312 clk_register_clkdev(clk[admux_gate], "audmux", NULL);
313
314 mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
315
316 return 0;
317}
318
319static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
320{
321 _mx35_clocks_init();
322
323 clk_data.clks = clk;
324 clk_data.clk_num = ARRAY_SIZE(clk);
325 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
326}
327CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);