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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Hardware modules present on the DRA7xx chips
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 */
16
17#include <linux/io.h>
18
19#include "omap_hwmod.h"
20#include "omap_hwmod_common_data.h"
21#include "cm1_7xx.h"
22#include "cm2_7xx.h"
23#include "prm7xx.h"
24#include "soc.h"
25
26/* Base offset for all DRA7XX interrupts external to MPUSS */
27#define DRA7XX_IRQ_GIC_START 32
28
29/*
30 * IP blocks
31 */
32
33/*
34 * 'dmm' class
35 * instance(s): dmm
36 */
37static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
38 .name = "dmm",
39};
40
41/* dmm */
42static struct omap_hwmod dra7xx_dmm_hwmod = {
43 .name = "dmm",
44 .class = &dra7xx_dmm_hwmod_class,
45 .clkdm_name = "emif_clkdm",
46 .prcm = {
47 .omap4 = {
48 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
49 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
50 },
51 },
52};
53
54/*
55 * 'l3' class
56 * instance(s): l3_instr, l3_main_1, l3_main_2
57 */
58static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
59 .name = "l3",
60};
61
62/* l3_instr */
63static struct omap_hwmod dra7xx_l3_instr_hwmod = {
64 .name = "l3_instr",
65 .class = &dra7xx_l3_hwmod_class,
66 .clkdm_name = "l3instr_clkdm",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
70 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
71 .modulemode = MODULEMODE_HWCTRL,
72 },
73 },
74};
75
76/* l3_main_1 */
77static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
78 .name = "l3_main_1",
79 .class = &dra7xx_l3_hwmod_class,
80 .clkdm_name = "l3main1_clkdm",
81 .prcm = {
82 .omap4 = {
83 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
84 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
85 },
86 },
87};
88
89/* l3_main_2 */
90static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
91 .name = "l3_main_2",
92 .class = &dra7xx_l3_hwmod_class,
93 .clkdm_name = "l3instr_clkdm",
94 .prcm = {
95 .omap4 = {
96 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
97 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
98 .modulemode = MODULEMODE_HWCTRL,
99 },
100 },
101};
102
103/*
104 * 'l4' class
105 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
106 */
107static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
108 .name = "l4",
109};
110
111/* l4_cfg */
112static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
113 .name = "l4_cfg",
114 .class = &dra7xx_l4_hwmod_class,
115 .clkdm_name = "l4cfg_clkdm",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
119 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
120 },
121 },
122};
123
124/* l4_per1 */
125static struct omap_hwmod dra7xx_l4_per1_hwmod = {
126 .name = "l4_per1",
127 .class = &dra7xx_l4_hwmod_class,
128 .clkdm_name = "l4per_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
132 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
133 },
134 },
135};
136
137/* l4_per2 */
138static struct omap_hwmod dra7xx_l4_per2_hwmod = {
139 .name = "l4_per2",
140 .class = &dra7xx_l4_hwmod_class,
141 .clkdm_name = "l4per2_clkdm",
142 .prcm = {
143 .omap4 = {
144 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
145 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
146 },
147 },
148};
149
150/* l4_per3 */
151static struct omap_hwmod dra7xx_l4_per3_hwmod = {
152 .name = "l4_per3",
153 .class = &dra7xx_l4_hwmod_class,
154 .clkdm_name = "l4per3_clkdm",
155 .prcm = {
156 .omap4 = {
157 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
158 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
159 },
160 },
161};
162
163/* l4_wkup */
164static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
165 .name = "l4_wkup",
166 .class = &dra7xx_l4_hwmod_class,
167 .clkdm_name = "wkupaon_clkdm",
168 .prcm = {
169 .omap4 = {
170 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
171 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
172 },
173 },
174};
175
176/*
177 * 'atl' class
178 *
179 */
180
181static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
182 .name = "atl",
183};
184
185/* atl */
186static struct omap_hwmod dra7xx_atl_hwmod = {
187 .name = "atl",
188 .class = &dra7xx_atl_hwmod_class,
189 .clkdm_name = "atl_clkdm",
190 .main_clk = "atl_gfclk_mux",
191 .prcm = {
192 .omap4 = {
193 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
194 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
195 .modulemode = MODULEMODE_SWCTRL,
196 },
197 },
198};
199
200/*
201 * 'bb2d' class
202 *
203 */
204
205static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
206 .name = "bb2d",
207};
208
209/* bb2d */
210static struct omap_hwmod dra7xx_bb2d_hwmod = {
211 .name = "bb2d",
212 .class = &dra7xx_bb2d_hwmod_class,
213 .clkdm_name = "dss_clkdm",
214 .main_clk = "dpll_core_h24x2_ck",
215 .prcm = {
216 .omap4 = {
217 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
218 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
219 .modulemode = MODULEMODE_SWCTRL,
220 },
221 },
222};
223
224/*
225 * 'ctrl_module' class
226 *
227 */
228
229static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
230 .name = "ctrl_module",
231};
232
233/* ctrl_module_wkup */
234static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
235 .name = "ctrl_module_wkup",
236 .class = &dra7xx_ctrl_module_hwmod_class,
237 .clkdm_name = "wkupaon_clkdm",
238 .prcm = {
239 .omap4 = {
240 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
241 },
242 },
243};
244
245/*
246 * 'gpmc' class
247 *
248 */
249
250static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
251 .rev_offs = 0x0000,
252 .sysc_offs = 0x0010,
253 .syss_offs = 0x0014,
254 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
255 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
257 .sysc_fields = &omap_hwmod_sysc_type1,
258};
259
260static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
261 .name = "gpmc",
262 .sysc = &dra7xx_gpmc_sysc,
263};
264
265/* gpmc */
266
267static struct omap_hwmod dra7xx_gpmc_hwmod = {
268 .name = "gpmc",
269 .class = &dra7xx_gpmc_hwmod_class,
270 .clkdm_name = "l3main1_clkdm",
271 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
272 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
273 .main_clk = "l3_iclk_div",
274 .prcm = {
275 .omap4 = {
276 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
277 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
278 .modulemode = MODULEMODE_HWCTRL,
279 },
280 },
281};
282
283
284
285/*
286 * 'mpu' class
287 *
288 */
289
290static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
291 .name = "mpu",
292};
293
294/* mpu */
295static struct omap_hwmod dra7xx_mpu_hwmod = {
296 .name = "mpu",
297 .class = &dra7xx_mpu_hwmod_class,
298 .clkdm_name = "mpu_clkdm",
299 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
300 .main_clk = "dpll_mpu_m2_ck",
301 .prcm = {
302 .omap4 = {
303 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
304 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
305 },
306 },
307};
308
309
310/*
311 * 'PCIE' class
312 *
313 */
314
315/*
316 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
317 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
318 * associated with an IP automatically leaving the driver to handle that
319 * by itself. This does not work for PCIeSS which needs the reset lines
320 * deasserted for the driver to start accessing registers.
321 *
322 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
323 * lines after asserting them.
324 */
325int dra7xx_pciess_reset(struct omap_hwmod *oh)
326{
327 int i;
328
329 for (i = 0; i < oh->rst_lines_cnt; i++) {
330 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
331 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
332 }
333
334 return 0;
335}
336
337static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
338 .name = "pcie",
339 .reset = dra7xx_pciess_reset,
340};
341
342/* pcie1 */
343static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
344 { .name = "pcie", .rst_shift = 0 },
345};
346
347static struct omap_hwmod dra7xx_pciess1_hwmod = {
348 .name = "pcie1",
349 .class = &dra7xx_pciess_hwmod_class,
350 .clkdm_name = "pcie_clkdm",
351 .rst_lines = dra7xx_pciess1_resets,
352 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
353 .main_clk = "l4_root_clk_div",
354 .prcm = {
355 .omap4 = {
356 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
357 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
358 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
359 .modulemode = MODULEMODE_SWCTRL,
360 },
361 },
362};
363
364/* pcie2 */
365static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
366 { .name = "pcie", .rst_shift = 1 },
367};
368
369/* pcie2 */
370static struct omap_hwmod dra7xx_pciess2_hwmod = {
371 .name = "pcie2",
372 .class = &dra7xx_pciess_hwmod_class,
373 .clkdm_name = "pcie_clkdm",
374 .rst_lines = dra7xx_pciess2_resets,
375 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
376 .main_clk = "l4_root_clk_div",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
380 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
381 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
382 .modulemode = MODULEMODE_SWCTRL,
383 },
384 },
385};
386
387/*
388 * 'qspi' class
389 *
390 */
391
392static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
393 .rev_offs = 0,
394 .sysc_offs = 0x0010,
395 .sysc_flags = SYSC_HAS_SIDLEMODE,
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
397 SIDLE_SMART_WKUP),
398 .sysc_fields = &omap_hwmod_sysc_type2,
399};
400
401static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
402 .name = "qspi",
403 .sysc = &dra7xx_qspi_sysc,
404};
405
406/* qspi */
407static struct omap_hwmod dra7xx_qspi_hwmod = {
408 .name = "qspi",
409 .class = &dra7xx_qspi_hwmod_class,
410 .clkdm_name = "l4per2_clkdm",
411 .main_clk = "qspi_gfclk_div",
412 .prcm = {
413 .omap4 = {
414 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
415 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
416 .modulemode = MODULEMODE_SWCTRL,
417 },
418 },
419};
420
421/*
422 * 'rtcss' class
423 *
424 */
425static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
426 .rev_offs = 0x0074,
427 .sysc_offs = 0x0078,
428 .sysc_flags = SYSC_HAS_SIDLEMODE,
429 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
430 SIDLE_SMART_WKUP),
431 .sysc_fields = &omap_hwmod_sysc_type3,
432};
433
434static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
435 .name = "rtcss",
436 .sysc = &dra7xx_rtcss_sysc,
437 .unlock = &omap_hwmod_rtc_unlock,
438 .lock = &omap_hwmod_rtc_lock,
439};
440
441/* rtcss */
442static struct omap_hwmod dra7xx_rtcss_hwmod = {
443 .name = "rtcss",
444 .class = &dra7xx_rtcss_hwmod_class,
445 .clkdm_name = "rtc_clkdm",
446 .main_clk = "sys_32k_ck",
447 .prcm = {
448 .omap4 = {
449 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
450 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
451 .modulemode = MODULEMODE_SWCTRL,
452 },
453 },
454};
455
456/*
457 * 'sata' class
458 *
459 */
460
461static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
462 .rev_offs = 0x00fc,
463 .sysc_offs = 0x0000,
464 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
465 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
466 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
467 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
468 .sysc_fields = &omap_hwmod_sysc_type2,
469};
470
471static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
472 .name = "sata",
473 .sysc = &dra7xx_sata_sysc,
474};
475
476/* sata */
477
478static struct omap_hwmod dra7xx_sata_hwmod = {
479 .name = "sata",
480 .class = &dra7xx_sata_hwmod_class,
481 .clkdm_name = "l3init_clkdm",
482 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
483 .main_clk = "func_48m_fclk",
484 .mpu_rt_idx = 1,
485 .prcm = {
486 .omap4 = {
487 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
488 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
489 .modulemode = MODULEMODE_SWCTRL,
490 },
491 },
492};
493
494/*
495 * 'vcp' class
496 *
497 */
498
499static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
500 .name = "vcp",
501};
502
503/* vcp1 */
504static struct omap_hwmod dra7xx_vcp1_hwmod = {
505 .name = "vcp1",
506 .class = &dra7xx_vcp_hwmod_class,
507 .clkdm_name = "l3main1_clkdm",
508 .main_clk = "l3_iclk_div",
509 .prcm = {
510 .omap4 = {
511 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
512 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
513 },
514 },
515};
516
517/* vcp2 */
518static struct omap_hwmod dra7xx_vcp2_hwmod = {
519 .name = "vcp2",
520 .class = &dra7xx_vcp_hwmod_class,
521 .clkdm_name = "l3main1_clkdm",
522 .main_clk = "l3_iclk_div",
523 .prcm = {
524 .omap4 = {
525 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
526 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
527 },
528 },
529};
530
531
532
533/*
534 * Interfaces
535 */
536
537/* l3_main_1 -> dmm */
538static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
539 .master = &dra7xx_l3_main_1_hwmod,
540 .slave = &dra7xx_dmm_hwmod,
541 .clk = "l3_iclk_div",
542 .user = OCP_USER_SDMA,
543};
544
545/* l3_main_2 -> l3_instr */
546static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
547 .master = &dra7xx_l3_main_2_hwmod,
548 .slave = &dra7xx_l3_instr_hwmod,
549 .clk = "l3_iclk_div",
550 .user = OCP_USER_MPU | OCP_USER_SDMA,
551};
552
553/* l4_cfg -> l3_main_1 */
554static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
555 .master = &dra7xx_l4_cfg_hwmod,
556 .slave = &dra7xx_l3_main_1_hwmod,
557 .clk = "l3_iclk_div",
558 .user = OCP_USER_MPU | OCP_USER_SDMA,
559};
560
561/* mpu -> l3_main_1 */
562static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
563 .master = &dra7xx_mpu_hwmod,
564 .slave = &dra7xx_l3_main_1_hwmod,
565 .clk = "l3_iclk_div",
566 .user = OCP_USER_MPU,
567};
568
569/* l3_main_1 -> l3_main_2 */
570static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
571 .master = &dra7xx_l3_main_1_hwmod,
572 .slave = &dra7xx_l3_main_2_hwmod,
573 .clk = "l3_iclk_div",
574 .user = OCP_USER_MPU,
575};
576
577/* l4_cfg -> l3_main_2 */
578static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
579 .master = &dra7xx_l4_cfg_hwmod,
580 .slave = &dra7xx_l3_main_2_hwmod,
581 .clk = "l3_iclk_div",
582 .user = OCP_USER_MPU | OCP_USER_SDMA,
583};
584
585/* l3_main_1 -> l4_cfg */
586static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
587 .master = &dra7xx_l3_main_1_hwmod,
588 .slave = &dra7xx_l4_cfg_hwmod,
589 .clk = "l3_iclk_div",
590 .user = OCP_USER_MPU | OCP_USER_SDMA,
591};
592
593/* l3_main_1 -> l4_per1 */
594static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
595 .master = &dra7xx_l3_main_1_hwmod,
596 .slave = &dra7xx_l4_per1_hwmod,
597 .clk = "l3_iclk_div",
598 .user = OCP_USER_MPU | OCP_USER_SDMA,
599};
600
601/* l3_main_1 -> l4_per2 */
602static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
603 .master = &dra7xx_l3_main_1_hwmod,
604 .slave = &dra7xx_l4_per2_hwmod,
605 .clk = "l3_iclk_div",
606 .user = OCP_USER_MPU | OCP_USER_SDMA,
607};
608
609/* l3_main_1 -> l4_per3 */
610static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
611 .master = &dra7xx_l3_main_1_hwmod,
612 .slave = &dra7xx_l4_per3_hwmod,
613 .clk = "l3_iclk_div",
614 .user = OCP_USER_MPU | OCP_USER_SDMA,
615};
616
617/* l3_main_1 -> l4_wkup */
618static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
619 .master = &dra7xx_l3_main_1_hwmod,
620 .slave = &dra7xx_l4_wkup_hwmod,
621 .clk = "wkupaon_iclk_mux",
622 .user = OCP_USER_MPU | OCP_USER_SDMA,
623};
624
625/* l4_per2 -> atl */
626static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
627 .master = &dra7xx_l4_per2_hwmod,
628 .slave = &dra7xx_atl_hwmod,
629 .clk = "l3_iclk_div",
630 .user = OCP_USER_MPU | OCP_USER_SDMA,
631};
632
633/* l3_main_1 -> bb2d */
634static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
635 .master = &dra7xx_l3_main_1_hwmod,
636 .slave = &dra7xx_bb2d_hwmod,
637 .clk = "l3_iclk_div",
638 .user = OCP_USER_MPU | OCP_USER_SDMA,
639};
640
641/* l4_wkup -> ctrl_module_wkup */
642static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
643 .master = &dra7xx_l4_wkup_hwmod,
644 .slave = &dra7xx_ctrl_module_wkup_hwmod,
645 .clk = "wkupaon_iclk_mux",
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
647};
648
649/* l3_main_1 -> gpmc */
650static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
651 .master = &dra7xx_l3_main_1_hwmod,
652 .slave = &dra7xx_gpmc_hwmod,
653 .clk = "l3_iclk_div",
654 .user = OCP_USER_MPU | OCP_USER_SDMA,
655};
656
657/* l4_cfg -> mpu */
658static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
659 .master = &dra7xx_l4_cfg_hwmod,
660 .slave = &dra7xx_mpu_hwmod,
661 .clk = "l3_iclk_div",
662 .user = OCP_USER_MPU | OCP_USER_SDMA,
663};
664
665/* l3_main_1 -> pciess1 */
666static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
667 .master = &dra7xx_l3_main_1_hwmod,
668 .slave = &dra7xx_pciess1_hwmod,
669 .clk = "l3_iclk_div",
670 .user = OCP_USER_MPU | OCP_USER_SDMA,
671};
672
673/* l4_cfg -> pciess1 */
674static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
675 .master = &dra7xx_l4_cfg_hwmod,
676 .slave = &dra7xx_pciess1_hwmod,
677 .clk = "l4_root_clk_div",
678 .user = OCP_USER_MPU | OCP_USER_SDMA,
679};
680
681/* l3_main_1 -> pciess2 */
682static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
683 .master = &dra7xx_l3_main_1_hwmod,
684 .slave = &dra7xx_pciess2_hwmod,
685 .clk = "l3_iclk_div",
686 .user = OCP_USER_MPU | OCP_USER_SDMA,
687};
688
689/* l4_cfg -> pciess2 */
690static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
691 .master = &dra7xx_l4_cfg_hwmod,
692 .slave = &dra7xx_pciess2_hwmod,
693 .clk = "l4_root_clk_div",
694 .user = OCP_USER_MPU | OCP_USER_SDMA,
695};
696
697/* l3_main_1 -> qspi */
698static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
699 .master = &dra7xx_l3_main_1_hwmod,
700 .slave = &dra7xx_qspi_hwmod,
701 .clk = "l3_iclk_div",
702 .user = OCP_USER_MPU | OCP_USER_SDMA,
703};
704
705/* l4_per3 -> rtcss */
706static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
707 .master = &dra7xx_l4_per3_hwmod,
708 .slave = &dra7xx_rtcss_hwmod,
709 .clk = "l4_root_clk_div",
710 .user = OCP_USER_MPU | OCP_USER_SDMA,
711};
712
713/* l4_cfg -> sata */
714static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
715 .master = &dra7xx_l4_cfg_hwmod,
716 .slave = &dra7xx_sata_hwmod,
717 .clk = "l3_iclk_div",
718 .user = OCP_USER_MPU | OCP_USER_SDMA,
719};
720
721/* l3_main_1 -> vcp1 */
722static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
723 .master = &dra7xx_l3_main_1_hwmod,
724 .slave = &dra7xx_vcp1_hwmod,
725 .clk = "l3_iclk_div",
726 .user = OCP_USER_MPU | OCP_USER_SDMA,
727};
728
729/* l4_per2 -> vcp1 */
730static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
731 .master = &dra7xx_l4_per2_hwmod,
732 .slave = &dra7xx_vcp1_hwmod,
733 .clk = "l3_iclk_div",
734 .user = OCP_USER_MPU | OCP_USER_SDMA,
735};
736
737/* l3_main_1 -> vcp2 */
738static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
739 .master = &dra7xx_l3_main_1_hwmod,
740 .slave = &dra7xx_vcp2_hwmod,
741 .clk = "l3_iclk_div",
742 .user = OCP_USER_MPU | OCP_USER_SDMA,
743};
744
745/* l4_per2 -> vcp2 */
746static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
747 .master = &dra7xx_l4_per2_hwmod,
748 .slave = &dra7xx_vcp2_hwmod,
749 .clk = "l3_iclk_div",
750 .user = OCP_USER_MPU | OCP_USER_SDMA,
751};
752
753static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
754 &dra7xx_l3_main_1__dmm,
755 &dra7xx_l3_main_2__l3_instr,
756 &dra7xx_l4_cfg__l3_main_1,
757 &dra7xx_mpu__l3_main_1,
758 &dra7xx_l3_main_1__l3_main_2,
759 &dra7xx_l4_cfg__l3_main_2,
760 &dra7xx_l3_main_1__l4_cfg,
761 &dra7xx_l3_main_1__l4_per1,
762 &dra7xx_l3_main_1__l4_per2,
763 &dra7xx_l3_main_1__l4_per3,
764 &dra7xx_l3_main_1__l4_wkup,
765 &dra7xx_l4_per2__atl,
766 &dra7xx_l3_main_1__bb2d,
767 &dra7xx_l4_wkup__ctrl_module_wkup,
768 &dra7xx_l3_main_1__gpmc,
769 &dra7xx_l4_cfg__mpu,
770 &dra7xx_l3_main_1__pciess1,
771 &dra7xx_l4_cfg__pciess1,
772 &dra7xx_l3_main_1__pciess2,
773 &dra7xx_l4_cfg__pciess2,
774 &dra7xx_l3_main_1__qspi,
775 &dra7xx_l4_cfg__sata,
776 &dra7xx_l3_main_1__vcp1,
777 &dra7xx_l4_per2__vcp1,
778 &dra7xx_l3_main_1__vcp2,
779 &dra7xx_l4_per2__vcp2,
780 NULL,
781};
782
783/* SoC variant specific hwmod links */
784static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
785 NULL,
786};
787
788static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
789 &dra7xx_l4_per3__rtcss,
790 NULL,
791};
792
793int __init dra7xx_hwmod_init(void)
794{
795 int ret;
796
797 omap_hwmod_init();
798 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
799
800 if (!ret && soc_is_dra74x()) {
801 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
802 } else if (!ret && soc_is_dra72x()) {
803 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
804 if (!ret && !of_machine_is_compatible("ti,dra718"))
805 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
806 } else if (!ret && soc_is_dra76x()) {
807 if (!ret && soc_is_dra76x_abz())
808 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
809 }
810
811 return ret;
812}