1#ifndef __ASMARM_ARCH_TIMER_H
 2#define __ASMARM_ARCH_TIMER_H
 3
 
 
 
 
 
 
 
 
 
 4#ifdef CONFIG_ARM_ARCH_TIMER
 5int arch_timer_of_register(void);
 6int arch_timer_sched_clock_init(void);
 7#else
 8static inline int arch_timer_of_register(void)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 9{
10	return -ENXIO;
11}
12
13static inline int arch_timer_sched_clock_init(void)
14{
15	return -ENXIO;
16}
17#endif
18
19#endif

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __ASMARM_ARCH_TIMER_H
  3#define __ASMARM_ARCH_TIMER_H
  4
  5#include <asm/barrier.h>
  6#include <asm/errno.h>
  7#include <asm/hwcap.h>
  8#include <linux/clocksource.h>
  9#include <linux/init.h>
 10#include <linux/types.h>
 11
 12#include <clocksource/arm_arch_timer.h>
 13
 14#ifdef CONFIG_ARM_ARCH_TIMER
 15/* 32bit ARM doesn't know anything about timer errata... */
 16#define has_erratum_handler(h)		(false)
 17#define erratum_handler(h)		(arch_timer_##h)
 18
 19int arch_timer_arch_init(void);
 20
 21/*
 22 * These register accessors are marked inline so the compiler can
 23 * nicely work out which register we want, and chuck away the rest of
 24 * the code. At least it does so with a recent GCC (4.6.3).
 25 */
 26static __always_inline
 27void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
 28{
 29	if (access == ARCH_TIMER_PHYS_ACCESS) {
 30		switch (reg) {
 31		case ARCH_TIMER_REG_CTRL:
 32			asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
 33			break;
 34		case ARCH_TIMER_REG_TVAL:
 35			asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
 36			break;
 37		}
 38	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
 39		switch (reg) {
 40		case ARCH_TIMER_REG_CTRL:
 41			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
 42			break;
 43		case ARCH_TIMER_REG_TVAL:
 44			asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
 45			break;
 46		}
 47	}
 48
 49	isb();
 50}
 51
 52static __always_inline
 53u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 54{
 55	u32 val = 0;
 56
 57	if (access == ARCH_TIMER_PHYS_ACCESS) {
 58		switch (reg) {
 59		case ARCH_TIMER_REG_CTRL:
 60			asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
 61			break;
 62		case ARCH_TIMER_REG_TVAL:
 63			asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
 64			break;
 65		}
 66	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
 67		switch (reg) {
 68		case ARCH_TIMER_REG_CTRL:
 69			asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
 70			break;
 71		case ARCH_TIMER_REG_TVAL:
 72			asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
 73			break;
 74		}
 75	}
 76
 77	return val;
 78}
 79
 80static inline u32 arch_timer_get_cntfrq(void)
 81{
 82	u32 val;
 83	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
 84	return val;
 85}
 86
 87static inline u64 __arch_counter_get_cntpct(void)
 88{
 89	u64 cval;
 90
 91	isb();
 92	asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
 93	return cval;
 94}
 95
 96static inline u64 __arch_counter_get_cntpct_stable(void)
 97{
 98	return __arch_counter_get_cntpct();
 99}
100
101static inline u64 __arch_counter_get_cntvct(void)
102{
103	u64 cval;
104
105	isb();
106	asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
107	return cval;
108}
109
110static inline u64 __arch_counter_get_cntvct_stable(void)
111{
112	return __arch_counter_get_cntvct();
113}
114
115static inline u32 arch_timer_get_cntkctl(void)
116{
117	u32 cntkctl;
118	asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
119	return cntkctl;
120}
121
122static inline void arch_timer_set_cntkctl(u32 cntkctl)
123{
124	asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
125	isb();
126}
127
128static inline void arch_timer_set_evtstrm_feature(void)
129{
130	elf_hwcap |= HWCAP_EVTSTRM;
131}
132
133static inline bool arch_timer_have_evtstrm_feature(void)
134{
135	return elf_hwcap & HWCAP_EVTSTRM;
136}
137#endif
138
139#endif