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1/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
15#define _DRIVERS_MMC_SDHCI_ESDHC_H
16
17/*
18 * Ops and quirks for the Freescale eSDHC controller.
19 */
20
21#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
22 SDHCI_QUIRK_NO_BUSY_IRQ | \
23 SDHCI_QUIRK_NONSTANDARD_CLOCK | \
24 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
25 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
26 SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
27
28#define ESDHC_SYSTEM_CONTROL 0x2c
29#define ESDHC_CLOCK_MASK 0x0000fff0
30#define ESDHC_PREDIV_SHIFT 8
31#define ESDHC_DIVIDER_SHIFT 4
32#define ESDHC_CLOCK_PEREN 0x00000004
33#define ESDHC_CLOCK_HCKEN 0x00000002
34#define ESDHC_CLOCK_IPGEN 0x00000001
35
36/* pltfm-specific */
37#define ESDHC_HOST_CONTROL_LE 0x20
38
39/* OF-specific */
40#define ESDHC_DMA_SYSCTL 0x40c
41#define ESDHC_DMA_SNOOP 0x00000040
42
43#define ESDHC_HOST_CONTROL_RES 0x05
44
45static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
46{
47 int pre_div = 2;
48 int div = 1;
49 u32 temp;
50
51 if (clock == 0)
52 goto out;
53
54 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
55 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
56 | ESDHC_CLOCK_MASK);
57 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
58
59 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
60 pre_div *= 2;
61
62 while (host->max_clk / pre_div / div > clock && div < 16)
63 div++;
64
65 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
66 clock, host->max_clk / pre_div / div);
67
68 pre_div >>= 1;
69 div--;
70
71 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
72 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
73 | (div << ESDHC_DIVIDER_SHIFT)
74 | (pre_div << ESDHC_PREDIV_SHIFT));
75 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
76 mdelay(1);
77out:
78 host->clock = clock;
79}
80
81#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Freescale eSDHC controller driver generics for OF and pltfm.
4 *
5 * Copyright (c) 2007 Freescale Semiconductor, Inc.
6 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <w.sang@pengutronix.de>
9 */
10
11#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
12#define _DRIVERS_MMC_SDHCI_ESDHC_H
13
14/*
15 * Ops and quirks for the Freescale eSDHC controller.
16 */
17
18#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
19 SDHCI_QUIRK_32BIT_DMA_ADDR | \
20 SDHCI_QUIRK_NO_BUSY_IRQ | \
21 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
22 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
23 SDHCI_QUIRK_NO_HISPD_BIT)
24
25/* pltfm-specific */
26#define ESDHC_HOST_CONTROL_LE 0x20
27
28/*
29 * eSDHC register definition
30 */
31
32/* Present State Register */
33#define ESDHC_PRSSTAT 0x24
34#define ESDHC_CLOCK_STABLE 0x00000008
35
36/* Protocol Control Register */
37#define ESDHC_PROCTL 0x28
38#define ESDHC_VOLT_SEL 0x00000400
39#define ESDHC_CTRL_4BITBUS (0x1 << 1)
40#define ESDHC_CTRL_8BITBUS (0x2 << 1)
41#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
42#define ESDHC_HOST_CONTROL_RES 0x01
43
44/* System Control Register */
45#define ESDHC_SYSTEM_CONTROL 0x2c
46#define ESDHC_CLOCK_MASK 0x0000fff0
47#define ESDHC_PREDIV_SHIFT 8
48#define ESDHC_DIVIDER_SHIFT 4
49#define ESDHC_CLOCK_SDCLKEN 0x00000008
50#define ESDHC_CLOCK_PEREN 0x00000004
51#define ESDHC_CLOCK_HCKEN 0x00000002
52#define ESDHC_CLOCK_IPGEN 0x00000001
53
54/* Host Controller Capabilities Register 2 */
55#define ESDHC_CAPABILITIES_1 0x114
56
57/* Tuning Block Control Register */
58#define ESDHC_TBCTL 0x120
59#define ESDHC_HS400_WNDW_ADJUST 0x00000040
60#define ESDHC_HS400_MODE 0x00000010
61#define ESDHC_TB_EN 0x00000004
62#define ESDHC_TBPTR 0x128
63
64/* SD Clock Control Register */
65#define ESDHC_SDCLKCTL 0x144
66#define ESDHC_LPBK_CLK_SEL 0x80000000
67#define ESDHC_CMD_CLK_CTL 0x00008000
68
69/* SD Timing Control Register */
70#define ESDHC_SDTIMNGCTL 0x148
71#define ESDHC_FLW_CTL_BG 0x00008000
72
73/* DLL Config 0 Register */
74#define ESDHC_DLLCFG0 0x160
75#define ESDHC_DLL_ENABLE 0x80000000
76#define ESDHC_DLL_FREQ_SEL 0x08000000
77
78/* DLL Config 1 Register */
79#define ESDHC_DLLCFG1 0x164
80#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
81
82/* DLL Status 0 Register */
83#define ESDHC_DLLSTAT0 0x170
84#define ESDHC_DLL_STS_SLV_LOCK 0x08000000
85
86/* Control Register for DMA transfer */
87#define ESDHC_DMA_SYSCTL 0x40c
88#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
89#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
90#define ESDHC_DMA_SNOOP 0x00000040
91
92#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */