1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2015 MediaTek Inc.
   4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
   5 */
   6
   7#include <linux/module.h>
   8#include <linux/clk.h>
   9#include <linux/delay.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/ioport.h>
  12#include <linux/irq.h>
  13#include <linux/of_address.h>
  14#include <linux/of_device.h>
  15#include <linux/of_irq.h>
  16#include <linux/of_gpio.h>
  17#include <linux/pinctrl/consumer.h>
  18#include <linux/platform_device.h>
  19#include <linux/pm.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/regulator/consumer.h>
  22#include <linux/slab.h>
  23#include <linux/spinlock.h>
  24#include <linux/interrupt.h>
  25
  26#include <linux/mmc/card.h>
  27#include <linux/mmc/core.h>
  28#include <linux/mmc/host.h>
  29#include <linux/mmc/mmc.h>
  30#include <linux/mmc/sd.h>
  31#include <linux/mmc/sdio.h>
  32#include <linux/mmc/slot-gpio.h>
  33
  34#define MAX_BD_NUM          1024
  35
  36/*--------------------------------------------------------------------------*/
  37/* Common Definition                                                        */
  38/*--------------------------------------------------------------------------*/
  39#define MSDC_BUS_1BITS          0x0
  40#define MSDC_BUS_4BITS          0x1
  41#define MSDC_BUS_8BITS          0x2
  42
  43#define MSDC_BURST_64B          0x6
  44
  45/*--------------------------------------------------------------------------*/
  46/* Register Offset                                                          */
  47/*--------------------------------------------------------------------------*/
  48#define MSDC_CFG         0x0
  49#define MSDC_IOCON       0x04
  50#define MSDC_PS          0x08
  51#define MSDC_INT         0x0c
  52#define MSDC_INTEN       0x10
  53#define MSDC_FIFOCS      0x14
  54#define SDC_CFG          0x30
  55#define SDC_CMD          0x34
  56#define SDC_ARG          0x38
  57#define SDC_STS          0x3c
  58#define SDC_RESP0        0x40
  59#define SDC_RESP1        0x44
  60#define SDC_RESP2        0x48
  61#define SDC_RESP3        0x4c
  62#define SDC_BLK_NUM      0x50
  63#define SDC_ADV_CFG0     0x64
  64#define EMMC_IOCON       0x7c
  65#define SDC_ACMD_RESP    0x80
  66#define DMA_SA_H4BIT     0x8c
  67#define MSDC_DMA_SA      0x90
  68#define MSDC_DMA_CTRL    0x98
  69#define MSDC_DMA_CFG     0x9c
  70#define MSDC_PATCH_BIT   0xb0
  71#define MSDC_PATCH_BIT1  0xb4
  72#define MSDC_PATCH_BIT2  0xb8
  73#define MSDC_PAD_TUNE    0xec
  74#define MSDC_PAD_TUNE0   0xf0
  75#define PAD_DS_TUNE      0x188
  76#define PAD_CMD_TUNE     0x18c
  77#define EMMC50_CFG0      0x208
  78#define EMMC50_CFG3      0x220
  79#define SDC_FIFO_CFG     0x228
  80
  81/*--------------------------------------------------------------------------*/
  82/* Top Pad Register Offset                                                  */
  83/*--------------------------------------------------------------------------*/
  84#define EMMC_TOP_CONTROL	0x00
  85#define EMMC_TOP_CMD		0x04
  86#define EMMC50_PAD_DS_TUNE	0x0c
  87
  88/*--------------------------------------------------------------------------*/
  89/* Register Mask                                                            */
  90/*--------------------------------------------------------------------------*/
  91
  92/* MSDC_CFG mask */
  93#define MSDC_CFG_MODE           (0x1 << 0)	/* RW */
  94#define MSDC_CFG_CKPDN          (0x1 << 1)	/* RW */
  95#define MSDC_CFG_RST            (0x1 << 2)	/* RW */
  96#define MSDC_CFG_PIO            (0x1 << 3)	/* RW */
  97#define MSDC_CFG_CKDRVEN        (0x1 << 4)	/* RW */
  98#define MSDC_CFG_BV18SDT        (0x1 << 5)	/* RW */
  99#define MSDC_CFG_BV18PSS        (0x1 << 6)	/* R  */
 100#define MSDC_CFG_CKSTB          (0x1 << 7)	/* R  */
 101#define MSDC_CFG_CKDIV          (0xff << 8)	/* RW */
 102#define MSDC_CFG_CKMOD          (0x3 << 16)	/* RW */
 103#define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)	/* RW */
 104#define MSDC_CFG_HS400_CK_MODE_EXTRA  (0x1 << 22)	/* RW */
 105#define MSDC_CFG_CKDIV_EXTRA    (0xfff << 8)	/* RW */
 106#define MSDC_CFG_CKMOD_EXTRA    (0x3 << 20)	/* RW */
 107
 108/* MSDC_IOCON mask */
 109#define MSDC_IOCON_SDR104CKS    (0x1 << 0)	/* RW */
 110#define MSDC_IOCON_RSPL         (0x1 << 1)	/* RW */
 111#define MSDC_IOCON_DSPL         (0x1 << 2)	/* RW */
 112#define MSDC_IOCON_DDLSEL       (0x1 << 3)	/* RW */
 113#define MSDC_IOCON_DDR50CKD     (0x1 << 4)	/* RW */
 114#define MSDC_IOCON_DSPLSEL      (0x1 << 5)	/* RW */
 115#define MSDC_IOCON_W_DSPL       (0x1 << 8)	/* RW */
 116#define MSDC_IOCON_D0SPL        (0x1 << 16)	/* RW */
 117#define MSDC_IOCON_D1SPL        (0x1 << 17)	/* RW */
 118#define MSDC_IOCON_D2SPL        (0x1 << 18)	/* RW */
 119#define MSDC_IOCON_D3SPL        (0x1 << 19)	/* RW */
 120#define MSDC_IOCON_D4SPL        (0x1 << 20)	/* RW */
 121#define MSDC_IOCON_D5SPL        (0x1 << 21)	/* RW */
 122#define MSDC_IOCON_D6SPL        (0x1 << 22)	/* RW */
 123#define MSDC_IOCON_D7SPL        (0x1 << 23)	/* RW */
 124#define MSDC_IOCON_RISCSZ       (0x3 << 24)	/* RW */
 125
 126/* MSDC_PS mask */
 127#define MSDC_PS_CDEN            (0x1 << 0)	/* RW */
 128#define MSDC_PS_CDSTS           (0x1 << 1)	/* R  */
 129#define MSDC_PS_CDDEBOUNCE      (0xf << 12)	/* RW */
 130#define MSDC_PS_DAT             (0xff << 16)	/* R  */
 131#define MSDC_PS_CMD             (0x1 << 24)	/* R  */
 132#define MSDC_PS_WP              (0x1 << 31)	/* R  */
 133
 134/* MSDC_INT mask */
 135#define MSDC_INT_MMCIRQ         (0x1 << 0)	/* W1C */
 136#define MSDC_INT_CDSC           (0x1 << 1)	/* W1C */
 137#define MSDC_INT_ACMDRDY        (0x1 << 3)	/* W1C */
 138#define MSDC_INT_ACMDTMO        (0x1 << 4)	/* W1C */
 139#define MSDC_INT_ACMDCRCERR     (0x1 << 5)	/* W1C */
 140#define MSDC_INT_DMAQ_EMPTY     (0x1 << 6)	/* W1C */
 141#define MSDC_INT_SDIOIRQ        (0x1 << 7)	/* W1C */
 142#define MSDC_INT_CMDRDY         (0x1 << 8)	/* W1C */
 143#define MSDC_INT_CMDTMO         (0x1 << 9)	/* W1C */
 144#define MSDC_INT_RSPCRCERR      (0x1 << 10)	/* W1C */
 145#define MSDC_INT_CSTA           (0x1 << 11)	/* R */
 146#define MSDC_INT_XFER_COMPL     (0x1 << 12)	/* W1C */
 147#define MSDC_INT_DXFER_DONE     (0x1 << 13)	/* W1C */
 148#define MSDC_INT_DATTMO         (0x1 << 14)	/* W1C */
 149#define MSDC_INT_DATCRCERR      (0x1 << 15)	/* W1C */
 150#define MSDC_INT_ACMD19_DONE    (0x1 << 16)	/* W1C */
 151#define MSDC_INT_DMA_BDCSERR    (0x1 << 17)	/* W1C */
 152#define MSDC_INT_DMA_GPDCSERR   (0x1 << 18)	/* W1C */
 153#define MSDC_INT_DMA_PROTECT    (0x1 << 19)	/* W1C */
 154
 155/* MSDC_INTEN mask */
 156#define MSDC_INTEN_MMCIRQ       (0x1 << 0)	/* RW */
 157#define MSDC_INTEN_CDSC         (0x1 << 1)	/* RW */
 158#define MSDC_INTEN_ACMDRDY      (0x1 << 3)	/* RW */
 159#define MSDC_INTEN_ACMDTMO      (0x1 << 4)	/* RW */
 160#define MSDC_INTEN_ACMDCRCERR   (0x1 << 5)	/* RW */
 161#define MSDC_INTEN_DMAQ_EMPTY   (0x1 << 6)	/* RW */
 162#define MSDC_INTEN_SDIOIRQ      (0x1 << 7)	/* RW */
 163#define MSDC_INTEN_CMDRDY       (0x1 << 8)	/* RW */
 164#define MSDC_INTEN_CMDTMO       (0x1 << 9)	/* RW */
 165#define MSDC_INTEN_RSPCRCERR    (0x1 << 10)	/* RW */
 166#define MSDC_INTEN_CSTA         (0x1 << 11)	/* RW */
 167#define MSDC_INTEN_XFER_COMPL   (0x1 << 12)	/* RW */
 168#define MSDC_INTEN_DXFER_DONE   (0x1 << 13)	/* RW */
 169#define MSDC_INTEN_DATTMO       (0x1 << 14)	/* RW */
 170#define MSDC_INTEN_DATCRCERR    (0x1 << 15)	/* RW */
 171#define MSDC_INTEN_ACMD19_DONE  (0x1 << 16)	/* RW */
 172#define MSDC_INTEN_DMA_BDCSERR  (0x1 << 17)	/* RW */
 173#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18)	/* RW */
 174#define MSDC_INTEN_DMA_PROTECT  (0x1 << 19)	/* RW */
 175
 176/* MSDC_FIFOCS mask */
 177#define MSDC_FIFOCS_RXCNT       (0xff << 0)	/* R */
 178#define MSDC_FIFOCS_TXCNT       (0xff << 16)	/* R */
 179#define MSDC_FIFOCS_CLR         (0x1 << 31)	/* RW */
 180
 181/* SDC_CFG mask */
 182#define SDC_CFG_SDIOINTWKUP     (0x1 << 0)	/* RW */
 183#define SDC_CFG_INSWKUP         (0x1 << 1)	/* RW */
 184#define SDC_CFG_BUSWIDTH        (0x3 << 16)	/* RW */
 185#define SDC_CFG_SDIO            (0x1 << 19)	/* RW */
 186#define SDC_CFG_SDIOIDE         (0x1 << 20)	/* RW */
 187#define SDC_CFG_INTATGAP        (0x1 << 21)	/* RW */
 188#define SDC_CFG_DTOC            (0xff << 24)	/* RW */
 189
 190/* SDC_STS mask */
 191#define SDC_STS_SDCBUSY         (0x1 << 0)	/* RW */
 192#define SDC_STS_CMDBUSY         (0x1 << 1)	/* RW */
 193#define SDC_STS_SWR_COMPL       (0x1 << 31)	/* RW */
 194
 195#define SDC_DAT1_IRQ_TRIGGER	(0x1 << 19)	/* RW */
 196/* SDC_ADV_CFG0 mask */
 197#define SDC_RX_ENHANCE_EN	(0x1 << 20)	/* RW */
 198
 199/* DMA_SA_H4BIT mask */
 200#define DMA_ADDR_HIGH_4BIT      (0xf << 0)      /* RW */
 201
 202/* MSDC_DMA_CTRL mask */
 203#define MSDC_DMA_CTRL_START     (0x1 << 0)	/* W */
 204#define MSDC_DMA_CTRL_STOP      (0x1 << 1)	/* W */
 205#define MSDC_DMA_CTRL_RESUME    (0x1 << 2)	/* W */
 206#define MSDC_DMA_CTRL_MODE      (0x1 << 8)	/* RW */
 207#define MSDC_DMA_CTRL_LASTBUF   (0x1 << 10)	/* RW */
 208#define MSDC_DMA_CTRL_BRUSTSZ   (0x7 << 12)	/* RW */
 209
 210/* MSDC_DMA_CFG mask */
 211#define MSDC_DMA_CFG_STS        (0x1 << 0)	/* R */
 212#define MSDC_DMA_CFG_DECSEN     (0x1 << 1)	/* RW */
 213#define MSDC_DMA_CFG_AHBHPROT2  (0x2 << 8)	/* RW */
 214#define MSDC_DMA_CFG_ACTIVEEN   (0x2 << 12)	/* RW */
 215#define MSDC_DMA_CFG_CS12B16B   (0x1 << 16)	/* RW */
 216
 217/* MSDC_PATCH_BIT mask */
 218#define MSDC_PATCH_BIT_ODDSUPP    (0x1 <<  1)	/* RW */
 219#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 <<  7)
 220#define MSDC_CKGEN_MSDC_DLY_SEL   (0x1f << 10)
 221#define MSDC_PATCH_BIT_IODSSEL    (0x1 << 16)	/* RW */
 222#define MSDC_PATCH_BIT_IOINTSEL   (0x1 << 17)	/* RW */
 223#define MSDC_PATCH_BIT_BUSYDLY    (0xf << 18)	/* RW */
 224#define MSDC_PATCH_BIT_WDOD       (0xf << 22)	/* RW */
 225#define MSDC_PATCH_BIT_IDRTSEL    (0x1 << 26)	/* RW */
 226#define MSDC_PATCH_BIT_CMDFSEL    (0x1 << 27)	/* RW */
 227#define MSDC_PATCH_BIT_INTDLSEL   (0x1 << 28)	/* RW */
 228#define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)	/* RW */
 229#define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)	/* RW */
 230
 231#define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */
 232
 233#define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
 234#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
 235#define MSDC_PB2_SUPPORT_64G      (0x1 << 1)    /* RW */
 236#define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
 237#define MSDC_PB2_RESPSTSENSEL     (0x7 << 16)   /* RW */
 238#define MSDC_PB2_CRCSTSENSEL      (0x7 << 29)   /* RW */
 239
 240#define MSDC_PAD_TUNE_DATWRDLY	  (0x1f <<  0)	/* RW */
 241#define MSDC_PAD_TUNE_DATRRDLY	  (0x1f <<  8)	/* RW */
 242#define MSDC_PAD_TUNE_CMDRDLY	  (0x1f << 16)  /* RW */
 243#define MSDC_PAD_TUNE_CMDRRDLY	  (0x1f << 22)	/* RW */
 244#define MSDC_PAD_TUNE_CLKTDLY	  (0x1f << 27)  /* RW */
 245#define MSDC_PAD_TUNE_RXDLYSEL	  (0x1 << 15)   /* RW */
 246#define MSDC_PAD_TUNE_RD_SEL	  (0x1 << 13)   /* RW */
 247#define MSDC_PAD_TUNE_CMD_SEL	  (0x1 << 21)   /* RW */
 248
 249#define PAD_DS_TUNE_DLY1	  (0x1f << 2)   /* RW */
 250#define PAD_DS_TUNE_DLY2	  (0x1f << 7)   /* RW */
 251#define PAD_DS_TUNE_DLY3	  (0x1f << 12)  /* RW */
 252
 253#define PAD_CMD_TUNE_RX_DLY3	  (0x1f << 1)  /* RW */
 254
 255#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)   /* RW */
 256#define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
 257#define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
 258
 259#define EMMC50_CFG3_OUTS_WR       (0x1f << 0)  /* RW */
 260
 261#define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
 262#define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
 263
 264/* EMMC_TOP_CONTROL mask */
 265#define PAD_RXDLY_SEL           (0x1 << 0)      /* RW */
 266#define DELAY_EN                (0x1 << 1)      /* RW */
 267#define PAD_DAT_RD_RXDLY2       (0x1f << 2)     /* RW */
 268#define PAD_DAT_RD_RXDLY        (0x1f << 7)     /* RW */
 269#define PAD_DAT_RD_RXDLY2_SEL   (0x1 << 12)     /* RW */
 270#define PAD_DAT_RD_RXDLY_SEL    (0x1 << 13)     /* RW */
 271#define DATA_K_VALUE_SEL        (0x1 << 14)     /* RW */
 272#define SDC_RX_ENH_EN           (0x1 << 15)     /* TW */
 273
 274/* EMMC_TOP_CMD mask */
 275#define PAD_CMD_RXDLY2          (0x1f << 0)     /* RW */
 276#define PAD_CMD_RXDLY           (0x1f << 5)     /* RW */
 277#define PAD_CMD_RD_RXDLY2_SEL   (0x1 << 10)     /* RW */
 278#define PAD_CMD_RD_RXDLY_SEL    (0x1 << 11)     /* RW */
 279#define PAD_CMD_TX_DLY          (0x1f << 12)    /* RW */
 280
 281#define REQ_CMD_EIO  (0x1 << 0)
 282#define REQ_CMD_TMO  (0x1 << 1)
 283#define REQ_DAT_ERR  (0x1 << 2)
 284#define REQ_STOP_EIO (0x1 << 3)
 285#define REQ_STOP_TMO (0x1 << 4)
 286#define REQ_CMD_BUSY (0x1 << 5)
 287
 288#define MSDC_PREPARE_FLAG (0x1 << 0)
 289#define MSDC_ASYNC_FLAG (0x1 << 1)
 290#define MSDC_MMAP_FLAG (0x1 << 2)
 291
 292#define MTK_MMC_AUTOSUSPEND_DELAY	50
 293#define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
 294#define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
 295
 296#define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
 297
 298#define PAD_DELAY_MAX	32 /* PAD delay cells */
 299/*--------------------------------------------------------------------------*/
 300/* Descriptor Structure                                                     */
 301/*--------------------------------------------------------------------------*/
 302struct mt_gpdma_desc {
 303	u32 gpd_info;
 304#define GPDMA_DESC_HWO		(0x1 << 0)
 305#define GPDMA_DESC_BDP		(0x1 << 1)
 306#define GPDMA_DESC_CHECKSUM	(0xff << 8) /* bit8 ~ bit15 */
 307#define GPDMA_DESC_INT		(0x1 << 16)
 308#define GPDMA_DESC_NEXT_H4	(0xf << 24)
 309#define GPDMA_DESC_PTR_H4	(0xf << 28)
 310	u32 next;
 311	u32 ptr;
 312	u32 gpd_data_len;
 313#define GPDMA_DESC_BUFLEN	(0xffff) /* bit0 ~ bit15 */
 314#define GPDMA_DESC_EXTLEN	(0xff << 16) /* bit16 ~ bit23 */
 315	u32 arg;
 316	u32 blknum;
 317	u32 cmd;
 318};
 319
 320struct mt_bdma_desc {
 321	u32 bd_info;
 322#define BDMA_DESC_EOL		(0x1 << 0)
 323#define BDMA_DESC_CHECKSUM	(0xff << 8) /* bit8 ~ bit15 */
 324#define BDMA_DESC_BLKPAD	(0x1 << 17)
 325#define BDMA_DESC_DWPAD		(0x1 << 18)
 326#define BDMA_DESC_NEXT_H4	(0xf << 24)
 327#define BDMA_DESC_PTR_H4	(0xf << 28)
 328	u32 next;
 329	u32 ptr;
 330	u32 bd_data_len;
 331#define BDMA_DESC_BUFLEN	(0xffff) /* bit0 ~ bit15 */
 332#define BDMA_DESC_BUFLEN_EXT	(0xffffff) /* bit0 ~ bit23 */
 333};
 334
 335struct msdc_dma {
 336	struct scatterlist *sg;	/* I/O scatter list */
 337	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
 338	struct mt_bdma_desc *bd;		/* pointer to bd array */
 339	dma_addr_t gpd_addr;	/* the physical address of gpd array */
 340	dma_addr_t bd_addr;	/* the physical address of bd array */
 341};
 342
 343struct msdc_save_para {
 344	u32 msdc_cfg;
 345	u32 iocon;
 346	u32 sdc_cfg;
 347	u32 pad_tune;
 348	u32 patch_bit0;
 349	u32 patch_bit1;
 350	u32 patch_bit2;
 351	u32 pad_ds_tune;
 352	u32 pad_cmd_tune;
 353	u32 emmc50_cfg0;
 354	u32 emmc50_cfg3;
 355	u32 sdc_fifo_cfg;
 356	u32 emmc_top_control;
 357	u32 emmc_top_cmd;
 358	u32 emmc50_pad_ds_tune;
 359};
 360
 361struct mtk_mmc_compatible {
 362	u8 clk_div_bits;
 363	bool hs400_tune; /* only used for MT8173 */
 364	u32 pad_tune_reg;
 365	bool async_fifo;
 366	bool data_tune;
 367	bool busy_check;
 368	bool stop_clk_fix;
 369	bool enhance_rx;
 370	bool support_64g;
 371	bool use_internal_cd;
 372};
 373
 374struct msdc_tune_para {
 375	u32 iocon;
 376	u32 pad_tune;
 377	u32 pad_cmd_tune;
 378	u32 emmc_top_control;
 379	u32 emmc_top_cmd;
 380};
 381
 382struct msdc_delay_phase {
 383	u8 maxlen;
 384	u8 start;
 385	u8 final_phase;
 386};
 387
 388struct msdc_host {
 389	struct device *dev;
 390	const struct mtk_mmc_compatible *dev_comp;
 391	struct mmc_host *mmc;	/* mmc structure */
 392	int cmd_rsp;
 393
 394	spinlock_t lock;
 395	struct mmc_request *mrq;
 396	struct mmc_command *cmd;
 397	struct mmc_data *data;
 398	int error;
 399
 400	void __iomem *base;		/* host base address */
 401	void __iomem *top_base;		/* host top register base address */
 402
 403	struct msdc_dma dma;	/* dma channel */
 404	u64 dma_mask;
 405
 406	u32 timeout_ns;		/* data timeout ns */
 407	u32 timeout_clks;	/* data timeout clks */
 408
 409	struct pinctrl *pinctrl;
 410	struct pinctrl_state *pins_default;
 411	struct pinctrl_state *pins_uhs;
 412	struct delayed_work req_timeout;
 413	int irq;		/* host interrupt */
 414
 415	struct clk *src_clk;	/* msdc source clock */
 416	struct clk *h_clk;      /* msdc h_clk */
 417	struct clk *bus_clk;	/* bus clock which used to access register */
 418	struct clk *src_clk_cg; /* msdc source clock control gate */
 419	u32 mclk;		/* mmc subsystem clock frequency */
 420	u32 src_clk_freq;	/* source clock frequency */
 421	unsigned char timing;
 422	bool vqmmc_enabled;
 423	u32 latch_ck;
 424	u32 hs400_ds_delay;
 425	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
 426	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
 427	bool hs400_cmd_resp_sel_rising;
 428				 /* cmd response sample selection for HS400 */
 429	bool hs400_mode;	/* current eMMC will run at hs400 mode */
 430	bool internal_cd;	/* Use internal card-detect logic */
 431	struct msdc_save_para save_para; /* used when gate HCLK */
 432	struct msdc_tune_para def_tune_para; /* default tune setting */
 433	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
 434};
 435
 436static const struct mtk_mmc_compatible mt8135_compat = {
 437	.clk_div_bits = 8,
 438	.hs400_tune = false,
 439	.pad_tune_reg = MSDC_PAD_TUNE,
 440	.async_fifo = false,
 441	.data_tune = false,
 442	.busy_check = false,
 443	.stop_clk_fix = false,
 444	.enhance_rx = false,
 445	.support_64g = false,
 446};
 447
 448static const struct mtk_mmc_compatible mt8173_compat = {
 449	.clk_div_bits = 8,
 450	.hs400_tune = true,
 451	.pad_tune_reg = MSDC_PAD_TUNE,
 452	.async_fifo = false,
 453	.data_tune = false,
 454	.busy_check = false,
 455	.stop_clk_fix = false,
 456	.enhance_rx = false,
 457	.support_64g = false,
 458};
 459
 460static const struct mtk_mmc_compatible mt8183_compat = {
 461	.clk_div_bits = 12,
 462	.hs400_tune = false,
 463	.pad_tune_reg = MSDC_PAD_TUNE0,
 464	.async_fifo = true,
 465	.data_tune = true,
 466	.busy_check = true,
 467	.stop_clk_fix = true,
 468	.enhance_rx = true,
 469	.support_64g = true,
 470};
 471
 472static const struct mtk_mmc_compatible mt2701_compat = {
 473	.clk_div_bits = 12,
 474	.hs400_tune = false,
 475	.pad_tune_reg = MSDC_PAD_TUNE0,
 476	.async_fifo = true,
 477	.data_tune = true,
 478	.busy_check = false,
 479	.stop_clk_fix = false,
 480	.enhance_rx = false,
 481	.support_64g = false,
 482};
 483
 484static const struct mtk_mmc_compatible mt2712_compat = {
 485	.clk_div_bits = 12,
 486	.hs400_tune = false,
 487	.pad_tune_reg = MSDC_PAD_TUNE0,
 488	.async_fifo = true,
 489	.data_tune = true,
 490	.busy_check = true,
 491	.stop_clk_fix = true,
 492	.enhance_rx = true,
 493	.support_64g = true,
 494};
 495
 496static const struct mtk_mmc_compatible mt7622_compat = {
 497	.clk_div_bits = 12,
 498	.hs400_tune = false,
 499	.pad_tune_reg = MSDC_PAD_TUNE0,
 500	.async_fifo = true,
 501	.data_tune = true,
 502	.busy_check = true,
 503	.stop_clk_fix = true,
 504	.enhance_rx = true,
 505	.support_64g = false,
 506};
 507
 508static const struct mtk_mmc_compatible mt8516_compat = {
 509	.clk_div_bits = 12,
 510	.hs400_tune = false,
 511	.pad_tune_reg = MSDC_PAD_TUNE0,
 512	.async_fifo = true,
 513	.data_tune = true,
 514	.busy_check = true,
 515	.stop_clk_fix = true,
 516};
 517
 518static const struct mtk_mmc_compatible mt7620_compat = {
 519	.clk_div_bits = 8,
 520	.hs400_tune = false,
 521	.pad_tune_reg = MSDC_PAD_TUNE,
 522	.async_fifo = false,
 523	.data_tune = false,
 524	.busy_check = false,
 525	.stop_clk_fix = false,
 526	.enhance_rx = false,
 527	.use_internal_cd = true,
 528};
 529
 530static const struct of_device_id msdc_of_ids[] = {
 531	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
 532	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
 533	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
 534	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
 535	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
 536	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
 537	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
 538	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
 539	{}
 540};
 541MODULE_DEVICE_TABLE(of, msdc_of_ids);
 542
 543static void sdr_set_bits(void __iomem *reg, u32 bs)
 544{
 545	u32 val = readl(reg);
 546
 547	val |= bs;
 548	writel(val, reg);
 549}
 550
 551static void sdr_clr_bits(void __iomem *reg, u32 bs)
 552{
 553	u32 val = readl(reg);
 554
 555	val &= ~bs;
 556	writel(val, reg);
 557}
 558
 559static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
 560{
 561	unsigned int tv = readl(reg);
 562
 563	tv &= ~field;
 564	tv |= ((val) << (ffs((unsigned int)field) - 1));
 565	writel(tv, reg);
 566}
 567
 568static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
 569{
 570	unsigned int tv = readl(reg);
 571
 572	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
 573}
 574
 575static void msdc_reset_hw(struct msdc_host *host)
 576{
 577	u32 val;
 578
 579	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
 580	while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
 581		cpu_relax();
 582
 583	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
 584	while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
 585		cpu_relax();
 586
 587	val = readl(host->base + MSDC_INT);
 588	writel(val, host->base + MSDC_INT);
 589}
 590
 591static void msdc_cmd_next(struct msdc_host *host,
 592		struct mmc_request *mrq, struct mmc_command *cmd);
 593
 594static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
 595			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
 596			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
 597static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
 598			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
 599			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
 600
 601static u8 msdc_dma_calcs(u8 *buf, u32 len)
 602{
 603	u32 i, sum = 0;
 604
 605	for (i = 0; i < len; i++)
 606		sum += buf[i];
 607	return 0xff - (u8) sum;
 608}
 609
 610static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
 611		struct mmc_data *data)
 612{
 613	unsigned int j, dma_len;
 614	dma_addr_t dma_address;
 615	u32 dma_ctrl;
 616	struct scatterlist *sg;
 617	struct mt_gpdma_desc *gpd;
 618	struct mt_bdma_desc *bd;
 619
 620	sg = data->sg;
 621
 622	gpd = dma->gpd;
 623	bd = dma->bd;
 624
 625	/* modify gpd */
 626	gpd->gpd_info |= GPDMA_DESC_HWO;
 627	gpd->gpd_info |= GPDMA_DESC_BDP;
 628	/* need to clear first. use these bits to calc checksum */
 629	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
 630	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
 631
 632	/* modify bd */
 633	for_each_sg(data->sg, sg, data->sg_count, j) {
 634		dma_address = sg_dma_address(sg);
 635		dma_len = sg_dma_len(sg);
 636
 637		/* init bd */
 638		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
 639		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
 640		bd[j].ptr = lower_32_bits(dma_address);
 641		if (host->dev_comp->support_64g) {
 642			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
 643			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
 644					 << 28;
 645		}
 646
 647		if (host->dev_comp->support_64g) {
 648			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
 649			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
 650		} else {
 651			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
 652			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
 653		}
 654
 655		if (j == data->sg_count - 1) /* the last bd */
 656			bd[j].bd_info |= BDMA_DESC_EOL;
 657		else
 658			bd[j].bd_info &= ~BDMA_DESC_EOL;
 659
 660		/* checksume need to clear first */
 661		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
 662		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
 663	}
 664
 665	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
 666	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
 667	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
 668	dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
 669	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
 670	if (host->dev_comp->support_64g)
 671		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
 672			      upper_32_bits(dma->gpd_addr) & 0xf);
 673	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
 674}
 675
 676static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
 677{
 678	struct mmc_data *data = mrq->data;
 679
 680	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
 681		data->host_cookie |= MSDC_PREPARE_FLAG;
 682		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
 683					    mmc_get_dma_dir(data));
 684	}
 685}
 686
 687static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
 688{
 689	struct mmc_data *data = mrq->data;
 690
 691	if (data->host_cookie & MSDC_ASYNC_FLAG)
 692		return;
 693
 694	if (data->host_cookie & MSDC_PREPARE_FLAG) {
 695		dma_unmap_sg(host->dev, data->sg, data->sg_len,
 696			     mmc_get_dma_dir(data));
 697		data->host_cookie &= ~MSDC_PREPARE_FLAG;
 698	}
 699}
 700
 701/* clock control primitives */
 702static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
 703{
 704	u32 timeout, clk_ns;
 705	u32 mode = 0;
 706
 707	host->timeout_ns = ns;
 708	host->timeout_clks = clks;
 709	if (host->mmc->actual_clock == 0) {
 710		timeout = 0;
 711	} else {
 712		clk_ns  = 1000000000UL / host->mmc->actual_clock;
 713		timeout = (ns + clk_ns - 1) / clk_ns + clks;
 714		/* in 1048576 sclk cycle unit */
 715		timeout = (timeout + (0x1 << 20) - 1) >> 20;
 716		if (host->dev_comp->clk_div_bits == 8)
 717			sdr_get_field(host->base + MSDC_CFG,
 718				      MSDC_CFG_CKMOD, &mode);
 719		else
 720			sdr_get_field(host->base + MSDC_CFG,
 721				      MSDC_CFG_CKMOD_EXTRA, &mode);
 722		/*DDR mode will double the clk cycles for data timeout */
 723		timeout = mode >= 2 ? timeout * 2 : timeout;
 724		timeout = timeout > 1 ? timeout - 1 : 0;
 725		timeout = timeout > 255 ? 255 : timeout;
 726	}
 727	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
 728}
 729
 730static void msdc_gate_clock(struct msdc_host *host)
 731{
 732	clk_disable_unprepare(host->src_clk_cg);
 733	clk_disable_unprepare(host->src_clk);
 734	clk_disable_unprepare(host->bus_clk);
 735	clk_disable_unprepare(host->h_clk);
 736}
 737
 738static void msdc_ungate_clock(struct msdc_host *host)
 739{
 740	clk_prepare_enable(host->h_clk);
 741	clk_prepare_enable(host->bus_clk);
 742	clk_prepare_enable(host->src_clk);
 743	clk_prepare_enable(host->src_clk_cg);
 744	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 745		cpu_relax();
 746}
 747
 748static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
 749{
 750	u32 mode;
 751	u32 flags;
 752	u32 div;
 753	u32 sclk;
 754	u32 tune_reg = host->dev_comp->pad_tune_reg;
 755
 756	if (!hz) {
 757		dev_dbg(host->dev, "set mclk to 0\n");
 758		host->mclk = 0;
 759		host->mmc->actual_clock = 0;
 760		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 761		return;
 762	}
 763
 764	flags = readl(host->base + MSDC_INTEN);
 765	sdr_clr_bits(host->base + MSDC_INTEN, flags);
 766	if (host->dev_comp->clk_div_bits == 8)
 767		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
 768	else
 769		sdr_clr_bits(host->base + MSDC_CFG,
 770			     MSDC_CFG_HS400_CK_MODE_EXTRA);
 771	if (timing == MMC_TIMING_UHS_DDR50 ||
 772	    timing == MMC_TIMING_MMC_DDR52 ||
 773	    timing == MMC_TIMING_MMC_HS400) {
 774		if (timing == MMC_TIMING_MMC_HS400)
 775			mode = 0x3;
 776		else
 777			mode = 0x2; /* ddr mode and use divisor */
 778
 779		if (hz >= (host->src_clk_freq >> 2)) {
 780			div = 0; /* mean div = 1/4 */
 781			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
 782		} else {
 783			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
 784			sclk = (host->src_clk_freq >> 2) / div;
 785			div = (div >> 1);
 786		}
 787
 788		if (timing == MMC_TIMING_MMC_HS400 &&
 789		    hz >= (host->src_clk_freq >> 1)) {
 790			if (host->dev_comp->clk_div_bits == 8)
 791				sdr_set_bits(host->base + MSDC_CFG,
 792					     MSDC_CFG_HS400_CK_MODE);
 793			else
 794				sdr_set_bits(host->base + MSDC_CFG,
 795					     MSDC_CFG_HS400_CK_MODE_EXTRA);
 796			sclk = host->src_clk_freq >> 1;
 797			div = 0; /* div is ignore when bit18 is set */
 798		}
 799	} else if (hz >= host->src_clk_freq) {
 800		mode = 0x1; /* no divisor */
 801		div = 0;
 802		sclk = host->src_clk_freq;
 803	} else {
 804		mode = 0x0; /* use divisor */
 805		if (hz >= (host->src_clk_freq >> 1)) {
 806			div = 0; /* mean div = 1/2 */
 807			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
 808		} else {
 809			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
 810			sclk = (host->src_clk_freq >> 2) / div;
 811		}
 812	}
 813	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 814	/*
 815	 * As src_clk/HCLK use the same bit to gate/ungate,
 816	 * So if want to only gate src_clk, need gate its parent(mux).
 817	 */
 818	if (host->src_clk_cg)
 819		clk_disable_unprepare(host->src_clk_cg);
 820	else
 821		clk_disable_unprepare(clk_get_parent(host->src_clk));
 822	if (host->dev_comp->clk_div_bits == 8)
 823		sdr_set_field(host->base + MSDC_CFG,
 824			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
 825			      (mode << 8) | div);
 826	else
 827		sdr_set_field(host->base + MSDC_CFG,
 828			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
 829			      (mode << 12) | div);
 830	if (host->src_clk_cg)
 831		clk_prepare_enable(host->src_clk_cg);
 832	else
 833		clk_prepare_enable(clk_get_parent(host->src_clk));
 834
 835	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
 836		cpu_relax();
 837	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
 838	host->mmc->actual_clock = sclk;
 839	host->mclk = hz;
 840	host->timing = timing;
 841	/* need because clk changed. */
 842	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
 843	sdr_set_bits(host->base + MSDC_INTEN, flags);
 844
 845	/*
 846	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
 847	 * tune result of hs200/200Mhz is not suitable for 50Mhz
 848	 */
 849	if (host->mmc->actual_clock <= 52000000) {
 850		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
 851		if (host->top_base) {
 852			writel(host->def_tune_para.emmc_top_control,
 853			       host->top_base + EMMC_TOP_CONTROL);
 854			writel(host->def_tune_para.emmc_top_cmd,
 855			       host->top_base + EMMC_TOP_CMD);
 856		} else {
 857			writel(host->def_tune_para.pad_tune,
 858			       host->base + tune_reg);
 859		}
 860	} else {
 861		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
 862		writel(host->saved_tune_para.pad_cmd_tune,
 863		       host->base + PAD_CMD_TUNE);
 864		if (host->top_base) {
 865			writel(host->saved_tune_para.emmc_top_control,
 866			       host->top_base + EMMC_TOP_CONTROL);
 867			writel(host->saved_tune_para.emmc_top_cmd,
 868			       host->top_base + EMMC_TOP_CMD);
 869		} else {
 870			writel(host->saved_tune_para.pad_tune,
 871			       host->base + tune_reg);
 872		}
 873	}
 874
 875	if (timing == MMC_TIMING_MMC_HS400 &&
 876	    host->dev_comp->hs400_tune)
 877		sdr_set_field(host->base + tune_reg,
 878			      MSDC_PAD_TUNE_CMDRRDLY,
 879			      host->hs400_cmd_int_delay);
 880	dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock,
 881		timing);
 882}
 883
 884static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
 885		struct mmc_request *mrq, struct mmc_command *cmd)
 886{
 887	u32 resp;
 888
 889	switch (mmc_resp_type(cmd)) {
 890		/* Actually, R1, R5, R6, R7 are the same */
 891	case MMC_RSP_R1:
 892		resp = 0x1;
 893		break;
 894	case MMC_RSP_R1B:
 895		resp = 0x7;
 896		break;
 897	case MMC_RSP_R2:
 898		resp = 0x2;
 899		break;
 900	case MMC_RSP_R3:
 901		resp = 0x3;
 902		break;
 903	case MMC_RSP_NONE:
 904	default:
 905		resp = 0x0;
 906		break;
 907	}
 908
 909	return resp;
 910}
 911
 912static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
 913		struct mmc_request *mrq, struct mmc_command *cmd)
 914{
 915	/* rawcmd :
 916	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
 917	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
 918	 */
 919	u32 opcode = cmd->opcode;
 920	u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
 921	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
 922
 923	host->cmd_rsp = resp;
 924
 925	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
 926	    opcode == MMC_STOP_TRANSMISSION)
 927		rawcmd |= (0x1 << 14);
 928	else if (opcode == SD_SWITCH_VOLTAGE)
 929		rawcmd |= (0x1 << 30);
 930	else if (opcode == SD_APP_SEND_SCR ||
 931		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
 932		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
 933		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
 934		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
 935		rawcmd |= (0x1 << 11);
 936
 937	if (cmd->data) {
 938		struct mmc_data *data = cmd->data;
 939
 940		if (mmc_op_multi(opcode)) {
 941			if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
 942			    !(mrq->sbc->arg & 0xFFFF0000))
 943				rawcmd |= 0x2 << 28; /* AutoCMD23 */
 944		}
 945
 946		rawcmd |= ((data->blksz & 0xFFF) << 16);
 947		if (data->flags & MMC_DATA_WRITE)
 948			rawcmd |= (0x1 << 13);
 949		if (data->blocks > 1)
 950			rawcmd |= (0x2 << 11);
 951		else
 952			rawcmd |= (0x1 << 11);
 953		/* Always use dma mode */
 954		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
 955
 956		if (host->timeout_ns != data->timeout_ns ||
 957		    host->timeout_clks != data->timeout_clks)
 958			msdc_set_timeout(host, data->timeout_ns,
 959					data->timeout_clks);
 960
 961		writel(data->blocks, host->base + SDC_BLK_NUM);
 962	}
 963	return rawcmd;
 964}
 965
 966static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
 967			    struct mmc_command *cmd, struct mmc_data *data)
 968{
 969	bool read;
 970
 971	WARN_ON(host->data);
 972	host->data = data;
 973	read = data->flags & MMC_DATA_READ;
 974
 975	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
 976	msdc_dma_setup(host, &host->dma, data);
 977	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
 978	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
 979	dev_dbg(host->dev, "DMA start\n");
 980	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
 981			__func__, cmd->opcode, data->blocks, read);
 982}
 983
 984static int msdc_auto_cmd_done(struct msdc_host *host, int events,
 985		struct mmc_command *cmd)
 986{
 987	u32 *rsp = cmd->resp;
 988
 989	rsp[0] = readl(host->base + SDC_ACMD_RESP);
 990
 991	if (events & MSDC_INT_ACMDRDY) {
 992		cmd->error = 0;
 993	} else {
 994		msdc_reset_hw(host);
 995		if (events & MSDC_INT_ACMDCRCERR) {
 996			cmd->error = -EILSEQ;
 997			host->error |= REQ_STOP_EIO;
 998		} else if (events & MSDC_INT_ACMDTMO) {
 999			cmd->error = -ETIMEDOUT;
1000			host->error |= REQ_STOP_TMO;
1001		}
1002		dev_err(host->dev,
1003			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1004			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1005	}
1006	return cmd->error;
1007}
1008
1009static void msdc_track_cmd_data(struct msdc_host *host,
1010				struct mmc_command *cmd, struct mmc_data *data)
1011{
1012	if (host->error)
1013		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1014			__func__, cmd->opcode, cmd->arg, host->error);
1015}
1016
1017static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1018{
1019	unsigned long flags;
1020	bool ret;
1021
1022	ret = cancel_delayed_work(&host->req_timeout);
1023	if (!ret) {
1024		/* delay work already running */
1025		return;
1026	}
1027	spin_lock_irqsave(&host->lock, flags);
1028	host->mrq = NULL;
1029	spin_unlock_irqrestore(&host->lock, flags);
1030
1031	msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1032	if (mrq->data)
1033		msdc_unprepare_data(host, mrq);
1034	if (host->error)
1035		msdc_reset_hw(host);
1036	mmc_request_done(host->mmc, mrq);
1037}
1038
1039/* returns true if command is fully handled; returns false otherwise */
1040static bool msdc_cmd_done(struct msdc_host *host, int events,
1041			  struct mmc_request *mrq, struct mmc_command *cmd)
1042{
1043	bool done = false;
1044	bool sbc_error;
1045	unsigned long flags;
1046	u32 *rsp = cmd->resp;
1047
1048	if (mrq->sbc && cmd == mrq->cmd &&
1049	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1050				   | MSDC_INT_ACMDTMO)))
1051		msdc_auto_cmd_done(host, events, mrq->sbc);
1052
1053	sbc_error = mrq->sbc && mrq->sbc->error;
1054
1055	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1056					| MSDC_INT_RSPCRCERR
1057					| MSDC_INT_CMDTMO)))
1058		return done;
1059
1060	spin_lock_irqsave(&host->lock, flags);
1061	done = !host->cmd;
1062	host->cmd = NULL;
1063	spin_unlock_irqrestore(&host->lock, flags);
1064
1065	if (done)
1066		return true;
1067
1068	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1069
1070	if (cmd->flags & MMC_RSP_PRESENT) {
1071		if (cmd->flags & MMC_RSP_136) {
1072			rsp[0] = readl(host->base + SDC_RESP3);
1073			rsp[1] = readl(host->base + SDC_RESP2);
1074			rsp[2] = readl(host->base + SDC_RESP1);
1075			rsp[3] = readl(host->base + SDC_RESP0);
1076		} else {
1077			rsp[0] = readl(host->base + SDC_RESP0);
1078		}
1079	}
1080
1081	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1082		if (events & MSDC_INT_CMDTMO ||
1083		    (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1084		     cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1085			/*
1086			 * should not clear fifo/interrupt as the tune data
1087			 * may have alreay come when cmd19/cmd21 gets response
1088			 * CRC error.
1089			 */
1090			msdc_reset_hw(host);
1091		if (events & MSDC_INT_RSPCRCERR) {
1092			cmd->error = -EILSEQ;
1093			host->error |= REQ_CMD_EIO;
1094		} else if (events & MSDC_INT_CMDTMO) {
1095			cmd->error = -ETIMEDOUT;
1096			host->error |= REQ_CMD_TMO;
1097		}
1098	}
1099	if (cmd->error)
1100		dev_dbg(host->dev,
1101				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1102				__func__, cmd->opcode, cmd->arg, rsp[0],
1103				cmd->error);
1104
1105	msdc_cmd_next(host, mrq, cmd);
1106	return true;
1107}
1108
1109/* It is the core layer's responsibility to ensure card status
1110 * is correct before issue a request. but host design do below
1111 * checks recommended.
1112 */
1113static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1114		struct mmc_request *mrq, struct mmc_command *cmd)
1115{
1116	/* The max busy time we can endure is 20ms */
1117	unsigned long tmo = jiffies + msecs_to_jiffies(20);
1118
1119	while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1120			time_before(jiffies, tmo))
1121		cpu_relax();
1122	if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1123		dev_err(host->dev, "CMD bus busy detected\n");
1124		host->error |= REQ_CMD_BUSY;
1125		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1126		return false;
1127	}
1128
1129	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1130		tmo = jiffies + msecs_to_jiffies(20);
1131		/* R1B or with data, should check SDCBUSY */
1132		while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1133				time_before(jiffies, tmo))
1134			cpu_relax();
1135		if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1136			dev_err(host->dev, "Controller busy detected\n");
1137			host->error |= REQ_CMD_BUSY;
1138			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1139			return false;
1140		}
1141	}
1142	return true;
1143}
1144
1145static void msdc_start_command(struct msdc_host *host,
1146		struct mmc_request *mrq, struct mmc_command *cmd)
1147{
1148	u32 rawcmd;
1149	unsigned long flags;
1150
1151	WARN_ON(host->cmd);
1152	host->cmd = cmd;
1153
1154	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1155	if (!msdc_cmd_is_ready(host, mrq, cmd))
1156		return;
1157
1158	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1159	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1160		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1161		msdc_reset_hw(host);
1162	}
1163
1164	cmd->error = 0;
1165	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1166
1167	spin_lock_irqsave(&host->lock, flags);
1168	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1169	spin_unlock_irqrestore(&host->lock, flags);
1170
1171	writel(cmd->arg, host->base + SDC_ARG);
1172	writel(rawcmd, host->base + SDC_CMD);
1173}
1174
1175static void msdc_cmd_next(struct msdc_host *host,
1176		struct mmc_request *mrq, struct mmc_command *cmd)
1177{
1178	if ((cmd->error &&
1179	    !(cmd->error == -EILSEQ &&
1180	      (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1181	       cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1182	    (mrq->sbc && mrq->sbc->error))
1183		msdc_request_done(host, mrq);
1184	else if (cmd == mrq->sbc)
1185		msdc_start_command(host, mrq, mrq->cmd);
1186	else if (!cmd->data)
1187		msdc_request_done(host, mrq);
1188	else
1189		msdc_start_data(host, mrq, cmd, cmd->data);
1190}
1191
1192static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1193{
1194	struct msdc_host *host = mmc_priv(mmc);
1195
1196	host->error = 0;
1197	WARN_ON(host->mrq);
1198	host->mrq = mrq;
1199
1200	if (mrq->data)
1201		msdc_prepare_data(host, mrq);
1202
1203	/* if SBC is required, we have HW option and SW option.
1204	 * if HW option is enabled, and SBC does not have "special" flags,
1205	 * use HW option,  otherwise use SW option
1206	 */
1207	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1208	    (mrq->sbc->arg & 0xFFFF0000)))
1209		msdc_start_command(host, mrq, mrq->sbc);
1210	else
1211		msdc_start_command(host, mrq, mrq->cmd);
1212}
1213
1214static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1215{
1216	struct msdc_host *host = mmc_priv(mmc);
1217	struct mmc_data *data = mrq->data;
1218
1219	if (!data)
1220		return;
1221
1222	msdc_prepare_data(host, mrq);
1223	data->host_cookie |= MSDC_ASYNC_FLAG;
1224}
1225
1226static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1227		int err)
1228{
1229	struct msdc_host *host = mmc_priv(mmc);
1230	struct mmc_data *data;
1231
1232	data = mrq->data;
1233	if (!data)
1234		return;
1235	if (data->host_cookie) {
1236		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1237		msdc_unprepare_data(host, mrq);
1238	}
1239}
1240
1241static void msdc_data_xfer_next(struct msdc_host *host,
1242				struct mmc_request *mrq, struct mmc_data *data)
1243{
1244	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1245	    !mrq->sbc)
1246		msdc_start_command(host, mrq, mrq->stop);
1247	else
1248		msdc_request_done(host, mrq);
1249}
1250
1251static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1252				struct mmc_request *mrq, struct mmc_data *data)
1253{
1254	struct mmc_command *stop = data->stop;
1255	unsigned long flags;
1256	bool done;
1257	unsigned int check_data = events &
1258	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1259	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1260	     | MSDC_INT_DMA_PROTECT);
1261
1262	spin_lock_irqsave(&host->lock, flags);
1263	done = !host->data;
1264	if (check_data)
1265		host->data = NULL;
1266	spin_unlock_irqrestore(&host->lock, flags);
1267
1268	if (done)
1269		return true;
1270
1271	if (check_data || (stop && stop->error)) {
1272		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1273				readl(host->base + MSDC_DMA_CFG));
1274		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1275				1);
1276		while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1277			cpu_relax();
1278		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1279		dev_dbg(host->dev, "DMA stop\n");
1280
1281		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1282			data->bytes_xfered = data->blocks * data->blksz;
1283		} else {
1284			dev_dbg(host->dev, "interrupt events: %x\n", events);
1285			msdc_reset_hw(host);
1286			host->error |= REQ_DAT_ERR;
1287			data->bytes_xfered = 0;
1288
1289			if (events & MSDC_INT_DATTMO)
1290				data->error = -ETIMEDOUT;
1291			else if (events & MSDC_INT_DATCRCERR)
1292				data->error = -EILSEQ;
1293
1294			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1295				__func__, mrq->cmd->opcode, data->blocks);
1296			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1297				(int)data->error, data->bytes_xfered);
1298		}
1299
1300		msdc_data_xfer_next(host, mrq, data);
1301		done = true;
1302	}
1303	return done;
1304}
1305
1306static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1307{
1308	u32 val = readl(host->base + SDC_CFG);
1309
1310	val &= ~SDC_CFG_BUSWIDTH;
1311
1312	switch (width) {
1313	default:
1314	case MMC_BUS_WIDTH_1:
1315		val |= (MSDC_BUS_1BITS << 16);
1316		break;
1317	case MMC_BUS_WIDTH_4:
1318		val |= (MSDC_BUS_4BITS << 16);
1319		break;
1320	case MMC_BUS_WIDTH_8:
1321		val |= (MSDC_BUS_8BITS << 16);
1322		break;
1323	}
1324
1325	writel(val, host->base + SDC_CFG);
1326	dev_dbg(host->dev, "Bus Width = %d", width);
1327}
1328
1329static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1330{
1331	struct msdc_host *host = mmc_priv(mmc);
1332	int ret = 0;
1333
1334	if (!IS_ERR(mmc->supply.vqmmc)) {
1335		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1336		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1337			dev_err(host->dev, "Unsupported signal voltage!\n");
1338			return -EINVAL;
1339		}
1340
1341		ret = mmc_regulator_set_vqmmc(mmc, ios);
1342		if (ret) {
1343			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1344				ret, ios->signal_voltage);
1345		} else {
1346			/* Apply different pinctrl settings for different signal voltage */
1347			if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1348				pinctrl_select_state(host->pinctrl, host->pins_uhs);
1349			else
1350				pinctrl_select_state(host->pinctrl, host->pins_default);
1351		}
1352	}
1353	return ret;
1354}
1355
1356static int msdc_card_busy(struct mmc_host *mmc)
1357{
1358	struct msdc_host *host = mmc_priv(mmc);
1359	u32 status = readl(host->base + MSDC_PS);
1360
1361	/* only check if data0 is low */
1362	return !(status & BIT(16));
1363}
1364
1365static void msdc_request_timeout(struct work_struct *work)
1366{
1367	struct msdc_host *host = container_of(work, struct msdc_host,
1368			req_timeout.work);
1369
1370	/* simulate HW timeout status */
1371	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1372	if (host->mrq) {
1373		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1374				host->mrq, host->mrq->cmd->opcode);
1375		if (host->cmd) {
1376			dev_err(host->dev, "%s: aborting cmd=%d\n",
1377					__func__, host->cmd->opcode);
1378			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1379					host->cmd);
1380		} else if (host->data) {
1381			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1382					__func__, host->mrq->cmd->opcode,
1383					host->data->blocks);
1384			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1385					host->data);
1386		}
1387	}
1388}
1389
1390static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1391{
1392	if (enb) {
1393		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1394		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1395	} else {
1396		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1397		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1398	}
1399}
1400
1401static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1402{
1403	unsigned long flags;
1404	struct msdc_host *host = mmc_priv(mmc);
1405
1406	spin_lock_irqsave(&host->lock, flags);
1407	__msdc_enable_sdio_irq(host, enb);
1408	spin_unlock_irqrestore(&host->lock, flags);
1409
1410	if (enb)
1411		pm_runtime_get_noresume(host->dev);
1412	else
1413		pm_runtime_put_noidle(host->dev);
1414}
1415
1416static irqreturn_t msdc_irq(int irq, void *dev_id)
1417{
1418	struct msdc_host *host = (struct msdc_host *) dev_id;
1419
1420	while (true) {
1421		unsigned long flags;
1422		struct mmc_request *mrq;
1423		struct mmc_command *cmd;
1424		struct mmc_data *data;
1425		u32 events, event_mask;
1426
1427		spin_lock_irqsave(&host->lock, flags);
1428		events = readl(host->base + MSDC_INT);
1429		event_mask = readl(host->base + MSDC_INTEN);
1430		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1431			__msdc_enable_sdio_irq(host, 0);
1432		/* clear interrupts */
1433		writel(events & event_mask, host->base + MSDC_INT);
1434
1435		mrq = host->mrq;
1436		cmd = host->cmd;
1437		data = host->data;
1438		spin_unlock_irqrestore(&host->lock, flags);
1439
1440		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1441			sdio_signal_irq(host->mmc);
1442
1443		if ((events & event_mask) & MSDC_INT_CDSC) {
1444			if (host->internal_cd)
1445				mmc_detect_change(host->mmc, msecs_to_jiffies(20));
1446			events &= ~MSDC_INT_CDSC;
1447		}
1448
1449		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1450			break;
1451
1452		if (!mrq) {
1453			dev_err(host->dev,
1454				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1455				__func__, events, event_mask);
1456			WARN_ON(1);
1457			break;
1458		}
1459
1460		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1461
1462		if (cmd)
1463			msdc_cmd_done(host, events, mrq, cmd);
1464		else if (data)
1465			msdc_data_xfer_done(host, events, mrq, data);
1466	}
1467
1468	return IRQ_HANDLED;
1469}
1470
1471static void msdc_init_hw(struct msdc_host *host)
1472{
1473	u32 val;
1474	u32 tune_reg = host->dev_comp->pad_tune_reg;
1475
1476	/* Configure to MMC/SD mode, clock free running */
1477	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1478
1479	/* Reset */
1480	msdc_reset_hw(host);
1481
1482	/* Disable and clear all interrupts */
1483	writel(0, host->base + MSDC_INTEN);
1484	val = readl(host->base + MSDC_INT);
1485	writel(val, host->base + MSDC_INT);
1486
1487	/* Configure card detection */
1488	if (host->internal_cd) {
1489		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1490			      DEFAULT_DEBOUNCE);
1491		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1492		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1493		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1494	} else {
1495		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1496		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1497		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1498	}
1499
1500	if (host->top_base) {
1501		writel(0, host->top_base + EMMC_TOP_CONTROL);
1502		writel(0, host->top_base + EMMC_TOP_CMD);
1503	} else {
1504		writel(0, host->base + tune_reg);
1505	}
1506	writel(0, host->base + MSDC_IOCON);
1507	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1508	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1509	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1510	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1511	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1512
1513	if (host->dev_comp->stop_clk_fix) {
1514		sdr_set_field(host->base + MSDC_PATCH_BIT1,
1515			      MSDC_PATCH_BIT1_STOP_DLY, 3);
1516		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1517			     SDC_FIFO_CFG_WRVALIDSEL);
1518		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1519			     SDC_FIFO_CFG_RDVALIDSEL);
1520	}
1521
1522	if (host->dev_comp->busy_check)
1523		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1524
1525	if (host->dev_comp->async_fifo) {
1526		sdr_set_field(host->base + MSDC_PATCH_BIT2,
1527			      MSDC_PB2_RESPWAIT, 3);
1528		if (host->dev_comp->enhance_rx) {
1529			if (host->top_base)
1530				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1531					     SDC_RX_ENH_EN);
1532			else
1533				sdr_set_bits(host->base + SDC_ADV_CFG0,
1534					     SDC_RX_ENHANCE_EN);
1535		} else {
1536			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1537				      MSDC_PB2_RESPSTSENSEL, 2);
1538			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1539				      MSDC_PB2_CRCSTSENSEL, 2);
1540		}
1541		/* use async fifo, then no need tune internal delay */
1542		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1543			     MSDC_PATCH_BIT2_CFGRESP);
1544		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1545			     MSDC_PATCH_BIT2_CFGCRCSTS);
1546	}
1547
1548	if (host->dev_comp->support_64g)
1549		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1550			     MSDC_PB2_SUPPORT_64G);
1551	if (host->dev_comp->data_tune) {
1552		if (host->top_base) {
1553			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1554				     PAD_DAT_RD_RXDLY_SEL);
1555			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1556				     DATA_K_VALUE_SEL);
1557			sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1558				     PAD_CMD_RD_RXDLY_SEL);
1559		} else {
1560			sdr_set_bits(host->base + tune_reg,
1561				     MSDC_PAD_TUNE_RD_SEL |
1562				     MSDC_PAD_TUNE_CMD_SEL);
1563		}
1564	} else {
1565		/* choose clock tune */
1566		if (host->top_base)
1567			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1568				     PAD_RXDLY_SEL);
1569		else
1570			sdr_set_bits(host->base + tune_reg,
1571				     MSDC_PAD_TUNE_RXDLYSEL);
1572	}
1573
1574	/* Configure to enable SDIO mode.
1575	 * it's must otherwise sdio cmd5 failed
1576	 */
1577	sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1578
1579	/* Config SDIO device detect interrupt function */
1580	sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1581	sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1582
1583	/* Configure to default data timeout */
1584	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1585
1586	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1587	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1588	if (host->top_base) {
1589		host->def_tune_para.emmc_top_control =
1590			readl(host->top_base + EMMC_TOP_CONTROL);
1591		host->def_tune_para.emmc_top_cmd =
1592			readl(host->top_base + EMMC_TOP_CMD);
1593		host->saved_tune_para.emmc_top_control =
1594			readl(host->top_base + EMMC_TOP_CONTROL);
1595		host->saved_tune_para.emmc_top_cmd =
1596			readl(host->top_base + EMMC_TOP_CMD);
1597	} else {
1598		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1599		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1600	}
1601	dev_dbg(host->dev, "init hardware done!");
1602}
1603
1604static void msdc_deinit_hw(struct msdc_host *host)
1605{
1606	u32 val;
1607
1608	if (host->internal_cd) {
1609		/* Disabled card-detect */
1610		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1611		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1612	}
1613
1614	/* Disable and clear all interrupts */
1615	writel(0, host->base + MSDC_INTEN);
1616
1617	val = readl(host->base + MSDC_INT);
1618	writel(val, host->base + MSDC_INT);
1619}
1620
1621/* init gpd and bd list in msdc_drv_probe */
1622static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1623{
1624	struct mt_gpdma_desc *gpd = dma->gpd;
1625	struct mt_bdma_desc *bd = dma->bd;
1626	dma_addr_t dma_addr;
1627	int i;
1628
1629	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1630
1631	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1632	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1633	/* gpd->next is must set for desc DMA
1634	 * That's why must alloc 2 gpd structure.
1635	 */
1636	gpd->next = lower_32_bits(dma_addr);
1637	if (host->dev_comp->support_64g)
1638		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1639
1640	dma_addr = dma->bd_addr;
1641	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1642	if (host->dev_comp->support_64g)
1643		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1644
1645	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1646	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1647		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1648		bd[i].next = lower_32_bits(dma_addr);
1649		if (host->dev_comp->support_64g)
1650			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1651	}
1652}
1653
1654static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1655{
1656	struct msdc_host *host = mmc_priv(mmc);
1657	int ret;
1658
1659	msdc_set_buswidth(host, ios->bus_width);
1660
1661	/* Suspend/Resume will do power off/on */
1662	switch (ios->power_mode) {
1663	case MMC_POWER_UP:
1664		if (!IS_ERR(mmc->supply.vmmc)) {
1665			msdc_init_hw(host);
1666			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1667					ios->vdd);
1668			if (ret) {
1669				dev_err(host->dev, "Failed to set vmmc power!\n");
1670				return;
1671			}
1672		}
1673		break;
1674	case MMC_POWER_ON:
1675		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1676			ret = regulator_enable(mmc->supply.vqmmc);
1677			if (ret)
1678				dev_err(host->dev, "Failed to set vqmmc power!\n");
1679			else
1680				host->vqmmc_enabled = true;
1681		}
1682		break;
1683	case MMC_POWER_OFF:
1684		if (!IS_ERR(mmc->supply.vmmc))
1685			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1686
1687		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1688			regulator_disable(mmc->supply.vqmmc);
1689			host->vqmmc_enabled = false;
1690		}
1691		break;
1692	default:
1693		break;
1694	}
1695
1696	if (host->mclk != ios->clock || host->timing != ios->timing)
1697		msdc_set_mclk(host, ios->timing, ios->clock);
1698}
1699
1700static u32 test_delay_bit(u32 delay, u32 bit)
1701{
1702	bit %= PAD_DELAY_MAX;
1703	return delay & (1 << bit);
1704}
1705
1706static int get_delay_len(u32 delay, u32 start_bit)
1707{
1708	int i;
1709
1710	for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1711		if (test_delay_bit(delay, start_bit + i) == 0)
1712			return i;
1713	}
1714	return PAD_DELAY_MAX - start_bit;
1715}
1716
1717static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1718{
1719	int start = 0, len = 0;
1720	int start_final = 0, len_final = 0;
1721	u8 final_phase = 0xff;
1722	struct msdc_delay_phase delay_phase = { 0, };
1723
1724	if (delay == 0) {
1725		dev_err(host->dev, "phase error: [map:%x]\n", delay);
1726		delay_phase.final_phase = final_phase;
1727		return delay_phase;
1728	}
1729
1730	while (start < PAD_DELAY_MAX) {
1731		len = get_delay_len(delay, start);
1732		if (len_final < len) {
1733			start_final = start;
1734			len_final = len;
1735		}
1736		start += len ? len : 1;
1737		if (len >= 12 && start_final < 4)
1738			break;
1739	}
1740
1741	/* The rule is that to find the smallest delay cell */
1742	if (start_final == 0)
1743		final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1744	else
1745		final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1746	dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1747		 delay, len_final, final_phase);
1748
1749	delay_phase.maxlen = len_final;
1750	delay_phase.start = start_final;
1751	delay_phase.final_phase = final_phase;
1752	return delay_phase;
1753}
1754
1755static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1756{
1757	u32 tune_reg = host->dev_comp->pad_tune_reg;
1758
1759	if (host->top_base)
1760		sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1761			      value);
1762	else
1763		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1764			      value);
1765}
1766
1767static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1768{
1769	u32 tune_reg = host->dev_comp->pad_tune_reg;
1770
1771	if (host->top_base)
1772		sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1773			      PAD_DAT_RD_RXDLY, value);
1774	else
1775		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1776			      value);
1777}
1778
1779static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1780{
1781	struct msdc_host *host = mmc_priv(mmc);
1782	u32 rise_delay = 0, fall_delay = 0;
1783	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1784	struct msdc_delay_phase internal_delay_phase;
1785	u8 final_delay, final_maxlen;
1786	u32 internal_delay = 0;
1787	u32 tune_reg = host->dev_comp->pad_tune_reg;
1788	int cmd_err;
1789	int i, j;
1790
1791	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1792	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1793		sdr_set_field(host->base + tune_reg,
1794			      MSDC_PAD_TUNE_CMDRRDLY,
1795			      host->hs200_cmd_int_delay);
1796
1797	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1798	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1799		msdc_set_cmd_delay(host, i);
1800		/*
1801		 * Using the same parameters, it may sometimes pass the test,
1802		 * but sometimes it may fail. To make sure the parameters are
1803		 * more stable, we test each set of parameters 3 times.
1804		 */
1805		for (j = 0; j < 3; j++) {
1806			mmc_send_tuning(mmc, opcode, &cmd_err);
1807			if (!cmd_err) {
1808				rise_delay |= (1 << i);
1809			} else {
1810				rise_delay &= ~(1 << i);
1811				break;
1812			}
1813		}
1814	}
1815	final_rise_delay = get_best_delay(host, rise_delay);
1816	/* if rising edge has enough margin, then do not scan falling edge */
1817	if (final_rise_delay.maxlen >= 12 ||
1818	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1819		goto skip_fall;
1820
1821	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1822	for (i = 0; i < PAD_DELAY_MAX; i++) {
1823		msdc_set_cmd_delay(host, i);
1824		/*
1825		 * Using the same parameters, it may sometimes pass the test,
1826		 * but sometimes it may fail. To make sure the parameters are
1827		 * more stable, we test each set of parameters 3 times.
1828		 */
1829		for (j = 0; j < 3; j++) {
1830			mmc_send_tuning(mmc, opcode, &cmd_err);
1831			if (!cmd_err) {
1832				fall_delay |= (1 << i);
1833			} else {
1834				fall_delay &= ~(1 << i);
1835				break;
1836			}
1837		}
1838	}
1839	final_fall_delay = get_best_delay(host, fall_delay);
1840
1841skip_fall:
1842	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1843	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1844		final_maxlen = final_fall_delay.maxlen;
1845	if (final_maxlen == final_rise_delay.maxlen) {
1846		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1847		final_delay = final_rise_delay.final_phase;
1848	} else {
1849		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1850		final_delay = final_fall_delay.final_phase;
1851	}
1852	msdc_set_cmd_delay(host, final_delay);
1853
1854	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1855		goto skip_internal;
1856
1857	for (i = 0; i < PAD_DELAY_MAX; i++) {
1858		sdr_set_field(host->base + tune_reg,
1859			      MSDC_PAD_TUNE_CMDRRDLY, i);
1860		mmc_send_tuning(mmc, opcode, &cmd_err);
1861		if (!cmd_err)
1862			internal_delay |= (1 << i);
1863	}
1864	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1865	internal_delay_phase = get_best_delay(host, internal_delay);
1866	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
1867		      internal_delay_phase.final_phase);
1868skip_internal:
1869	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1870	return final_delay == 0xff ? -EIO : 0;
1871}
1872
1873static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1874{
1875	struct msdc_host *host = mmc_priv(mmc);
1876	u32 cmd_delay = 0;
1877	struct msdc_delay_phase final_cmd_delay = { 0,};
1878	u8 final_delay;
1879	int cmd_err;
1880	int i, j;
1881
1882	/* select EMMC50 PAD CMD tune */
1883	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1884
1885	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1886	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1887		sdr_set_field(host->base + MSDC_PAD_TUNE,
1888			      MSDC_PAD_TUNE_CMDRRDLY,
1889			      host->hs200_cmd_int_delay);
1890
1891	if (host->hs400_cmd_resp_sel_rising)
1892		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1893	else
1894		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1895	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1896		sdr_set_field(host->base + PAD_CMD_TUNE,
1897			      PAD_CMD_TUNE_RX_DLY3, i);
1898		/*
1899		 * Using the same parameters, it may sometimes pass the test,
1900		 * but sometimes it may fail. To make sure the parameters are
1901		 * more stable, we test each set of parameters 3 times.
1902		 */
1903		for (j = 0; j < 3; j++) {
1904			mmc_send_tuning(mmc, opcode, &cmd_err);
1905			if (!cmd_err) {
1906				cmd_delay |= (1 << i);
1907			} else {
1908				cmd_delay &= ~(1 << i);
1909				break;
1910			}
1911		}
1912	}
1913	final_cmd_delay = get_best_delay(host, cmd_delay);
1914	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1915		      final_cmd_delay.final_phase);
1916	final_delay = final_cmd_delay.final_phase;
1917
1918	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1919	return final_delay == 0xff ? -EIO : 0;
1920}
1921
1922static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1923{
1924	struct msdc_host *host = mmc_priv(mmc);
1925	u32 rise_delay = 0, fall_delay = 0;
1926	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1927	u8 final_delay, final_maxlen;
1928	int i, ret;
1929
1930	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1931		      host->latch_ck);
1932	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1933	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1934	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1935		msdc_set_data_delay(host, i);
1936		ret = mmc_send_tuning(mmc, opcode, NULL);
1937		if (!ret)
1938			rise_delay |= (1 << i);
1939	}
1940	final_rise_delay = get_best_delay(host, rise_delay);
1941	/* if rising edge has enough margin, then do not scan falling edge */
1942	if (final_rise_delay.maxlen >= 12 ||
1943	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1944		goto skip_fall;
1945
1946	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1947	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1948	for (i = 0; i < PAD_DELAY_MAX; i++) {
1949		msdc_set_data_delay(host, i);
1950		ret = mmc_send_tuning(mmc, opcode, NULL);
1951		if (!ret)
1952			fall_delay |= (1 << i);
1953	}
1954	final_fall_delay = get_best_delay(host, fall_delay);
1955
1956skip_fall:
1957	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1958	if (final_maxlen == final_rise_delay.maxlen) {
1959		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1960		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1961		final_delay = final_rise_delay.final_phase;
1962	} else {
1963		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1964		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1965		final_delay = final_fall_delay.final_phase;
1966	}
1967	msdc_set_data_delay(host, final_delay);
1968
1969	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1970	return final_delay == 0xff ? -EIO : 0;
1971}
1972
1973/*
1974 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1975 * together, which can save the tuning time.
1976 */
1977static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
1978{
1979	struct msdc_host *host = mmc_priv(mmc);
1980	u32 rise_delay = 0, fall_delay = 0;
1981	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1982	u8 final_delay, final_maxlen;
1983	int i, ret;
1984
1985	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1986		      host->latch_ck);
1987
1988	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1989	sdr_clr_bits(host->base + MSDC_IOCON,
1990		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1991	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1992		msdc_set_cmd_delay(host, i);
1993		msdc_set_data_delay(host, i);
1994		ret = mmc_send_tuning(mmc, opcode, NULL);
1995		if (!ret)
1996			rise_delay |= (1 << i);
1997	}
1998	final_rise_delay = get_best_delay(host, rise_delay);
1999	/* if rising edge has enough margin, then do not scan falling edge */
2000	if (final_rise_delay.maxlen >= 12 ||
2001	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2002		goto skip_fall;
2003
2004	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2005	sdr_set_bits(host->base + MSDC_IOCON,
2006		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2007	for (i = 0; i < PAD_DELAY_MAX; i++) {
2008		msdc_set_cmd_delay(host, i);
2009		msdc_set_data_delay(host, i);
2010		ret = mmc_send_tuning(mmc, opcode, NULL);
2011		if (!ret)
2012			fall_delay |= (1 << i);
2013	}
2014	final_fall_delay = get_best_delay(host, fall_delay);
2015
2016skip_fall:
2017	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2018	if (final_maxlen == final_rise_delay.maxlen) {
2019		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2020		sdr_clr_bits(host->base + MSDC_IOCON,
2021			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2022		final_delay = final_rise_delay.final_phase;
2023	} else {
2024		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2025		sdr_set_bits(host->base + MSDC_IOCON,
2026			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2027		final_delay = final_fall_delay.final_phase;
2028	}
2029
2030	msdc_set_cmd_delay(host, final_delay);
2031	msdc_set_data_delay(host, final_delay);
2032
2033	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2034	return final_delay == 0xff ? -EIO : 0;
2035}
2036
2037static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2038{
2039	struct msdc_host *host = mmc_priv(mmc);
2040	int ret;
2041	u32 tune_reg = host->dev_comp->pad_tune_reg;
2042
2043	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2044		ret = msdc_tune_together(mmc, opcode);
2045		if (host->hs400_mode) {
2046			sdr_clr_bits(host->base + MSDC_IOCON,
2047				     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2048			msdc_set_data_delay(host, 0);
2049		}
2050		goto tune_done;
2051	}
2052	if (host->hs400_mode &&
2053	    host->dev_comp->hs400_tune)
2054		ret = hs400_tune_response(mmc, opcode);
2055	else
2056		ret = msdc_tune_response(mmc, opcode);
2057	if (ret == -EIO) {
2058		dev_err(host->dev, "Tune response fail!\n");
2059		return ret;
2060	}
2061	if (host->hs400_mode == false) {
2062		ret = msdc_tune_data(mmc, opcode);
2063		if (ret == -EIO)
2064			dev_err(host->dev, "Tune data fail!\n");
2065	}
2066
2067tune_done:
2068	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2069	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2070	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2071	if (host->top_base) {
2072		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2073				EMMC_TOP_CONTROL);
2074		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2075				EMMC_TOP_CMD);
2076	}
2077	return ret;
2078}
2079
2080static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2081{
2082	struct msdc_host *host = mmc_priv(mmc);
2083	host->hs400_mode = true;
2084
2085	if (host->top_base)
2086		writel(host->hs400_ds_delay,
2087		       host->top_base + EMMC50_PAD_DS_TUNE);
2088	else
2089		writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2090	/* hs400 mode must set it to 0 */
2091	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2092	/* to improve read performance, set outstanding to 2 */
2093	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2094
2095	return 0;
2096}
2097
2098static void msdc_hw_reset(struct mmc_host *mmc)
2099{
2100	struct msdc_host *host = mmc_priv(mmc);
2101
2102	sdr_set_bits(host->base + EMMC_IOCON, 1);
2103	udelay(10); /* 10us is enough */
2104	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2105}
2106
2107static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2108{
2109	unsigned long flags;
2110	struct msdc_host *host = mmc_priv(mmc);
2111
2112	spin_lock_irqsave(&host->lock, flags);
2113	__msdc_enable_sdio_irq(host, 1);
2114	spin_unlock_irqrestore(&host->lock, flags);
2115}
2116
2117static int msdc_get_cd(struct mmc_host *mmc)
2118{
2119	struct msdc_host *host = mmc_priv(mmc);
2120	int val;
2121
2122	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2123		return 1;
2124
2125	if (!host->internal_cd)
2126		return mmc_gpio_get_cd(mmc);
2127
2128	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2129	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2130		return !!val;
2131	else
2132		return !val;
2133}
2134
2135static const struct mmc_host_ops mt_msdc_ops = {
2136	.post_req = msdc_post_req,
2137	.pre_req = msdc_pre_req,
2138	.request = msdc_ops_request,
2139	.set_ios = msdc_ops_set_ios,
2140	.get_ro = mmc_gpio_get_ro,
2141	.get_cd = msdc_get_cd,
2142	.enable_sdio_irq = msdc_enable_sdio_irq,
2143	.ack_sdio_irq = msdc_ack_sdio_irq,
2144	.start_signal_voltage_switch = msdc_ops_switch_volt,
2145	.card_busy = msdc_card_busy,
2146	.execute_tuning = msdc_execute_tuning,
2147	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2148	.hw_reset = msdc_hw_reset,
2149};
2150
2151static void msdc_of_property_parse(struct platform_device *pdev,
2152				   struct msdc_host *host)
2153{
2154	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2155			     &host->latch_ck);
2156
2157	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2158			     &host->hs400_ds_delay);
2159
2160	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2161			     &host->hs200_cmd_int_delay);
2162
2163	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2164			     &host->hs400_cmd_int_delay);
2165
2166	if (of_property_read_bool(pdev->dev.of_node,
2167				  "mediatek,hs400-cmd-resp-sel-rising"))
2168		host->hs400_cmd_resp_sel_rising = true;
2169	else
2170		host->hs400_cmd_resp_sel_rising = false;
2171}
2172
2173static int msdc_drv_probe(struct platform_device *pdev)
2174{
2175	struct mmc_host *mmc;
2176	struct msdc_host *host;
2177	struct resource *res;
2178	int ret;
2179
2180	if (!pdev->dev.of_node) {
2181		dev_err(&pdev->dev, "No DT found\n");
2182		return -EINVAL;
2183	}
2184
2185	/* Allocate MMC host for this device */
2186	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2187	if (!mmc)
2188		return -ENOMEM;
2189
2190	host = mmc_priv(mmc);
2191	ret = mmc_of_parse(mmc);
2192	if (ret)
2193		goto host_free;
2194
2195	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2196	host->base = devm_ioremap_resource(&pdev->dev, res);
2197	if (IS_ERR(host->base)) {
2198		ret = PTR_ERR(host->base);
2199		goto host_free;
2200	}
2201
2202	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2203	if (res) {
2204		host->top_base = devm_ioremap_resource(&pdev->dev, res);
2205		if (IS_ERR(host->top_base))
2206			host->top_base = NULL;
2207	}
2208
2209	ret = mmc_regulator_get_supply(mmc);
2210	if (ret)
2211		goto host_free;
2212
2213	host->src_clk = devm_clk_get(&pdev->dev, "source");
2214	if (IS_ERR(host->src_clk)) {
2215		ret = PTR_ERR(host->src_clk);
2216		goto host_free;
2217	}
2218
2219	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2220	if (IS_ERR(host->h_clk)) {
2221		ret = PTR_ERR(host->h_clk);
2222		goto host_free;
2223	}
2224
2225	host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
2226	if (IS_ERR(host->bus_clk))
2227		host->bus_clk = NULL;
2228	/*source clock control gate is optional clock*/
2229	host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
2230	if (IS_ERR(host->src_clk_cg))
2231		host->src_clk_cg = NULL;
2232
2233	host->irq = platform_get_irq(pdev, 0);
2234	if (host->irq < 0) {
2235		ret = -EINVAL;
2236		goto host_free;
2237	}
2238
2239	host->pinctrl = devm_pinctrl_get(&pdev->dev);
2240	if (IS_ERR(host->pinctrl)) {
2241		ret = PTR_ERR(host->pinctrl);
2242		dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2243		goto host_free;
2244	}
2245
2246	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2247	if (IS_ERR(host->pins_default)) {
2248		ret = PTR_ERR(host->pins_default);
2249		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2250		goto host_free;
2251	}
2252
2253	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2254	if (IS_ERR(host->pins_uhs)) {
2255		ret = PTR_ERR(host->pins_uhs);
2256		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2257		goto host_free;
2258	}
2259
2260	msdc_of_property_parse(pdev, host);
2261
2262	host->dev = &pdev->dev;
2263	host->dev_comp = of_device_get_match_data(&pdev->dev);
2264	host->mmc = mmc;
2265	host->src_clk_freq = clk_get_rate(host->src_clk);
2266	/* Set host parameters to mmc */
2267	mmc->ops = &mt_msdc_ops;
2268	if (host->dev_comp->clk_div_bits == 8)
2269		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2270	else
2271		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2272
2273	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2274	    !mmc_can_gpio_cd(mmc) &&
2275	    host->dev_comp->use_internal_cd) {
2276		/*
2277		 * Is removable but no GPIO declared, so
2278		 * use internal functionality.
2279		 */
2280		host->internal_cd = true;
2281	}
2282
2283	if (mmc->caps & MMC_CAP_SDIO_IRQ)
2284		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2285
2286	mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
2287	/* MMC core transfer sizes tunable parameters */
2288	mmc->max_segs = MAX_BD_NUM;
2289	if (host->dev_comp->support_64g)
2290		mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2291	else
2292		mmc->max_seg_size = BDMA_DESC_BUFLEN;
2293	mmc->max_blk_size = 2048;
2294	mmc->max_req_size = 512 * 1024;
2295	mmc->max_blk_count = mmc->max_req_size / 512;
2296	if (host->dev_comp->support_64g)
2297		host->dma_mask = DMA_BIT_MASK(36);
2298	else
2299		host->dma_mask = DMA_BIT_MASK(32);
2300	mmc_dev(mmc)->dma_mask = &host->dma_mask;
2301
2302	host->timeout_clks = 3 * 1048576;
2303	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2304				2 * sizeof(struct mt_gpdma_desc),
2305				&host->dma.gpd_addr, GFP_KERNEL);
2306	host->dma.bd = dma_alloc_coherent(&pdev->dev,
2307				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2308				&host->dma.bd_addr, GFP_KERNEL);
2309	if (!host->dma.gpd || !host->dma.bd) {
2310		ret = -ENOMEM;
2311		goto release_mem;
2312	}
2313	msdc_init_gpd_bd(host, &host->dma);
2314	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2315	spin_lock_init(&host->lock);
2316
2317	platform_set_drvdata(pdev, mmc);
2318	msdc_ungate_clock(host);
2319	msdc_init_hw(host);
2320
2321	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2322			       IRQF_TRIGGER_NONE, pdev->name, host);
2323	if (ret)
2324		goto release;
2325
2326	pm_runtime_set_active(host->dev);
2327	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2328	pm_runtime_use_autosuspend(host->dev);
2329	pm_runtime_enable(host->dev);
2330	ret = mmc_add_host(mmc);
2331
2332	if (ret)
2333		goto end;
2334
2335	return 0;
2336end:
2337	pm_runtime_disable(host->dev);
2338release:
2339	platform_set_drvdata(pdev, NULL);
2340	msdc_deinit_hw(host);
2341	msdc_gate_clock(host);
2342release_mem:
2343	if (host->dma.gpd)
2344		dma_free_coherent(&pdev->dev,
2345			2 * sizeof(struct mt_gpdma_desc),
2346			host->dma.gpd, host->dma.gpd_addr);
2347	if (host->dma.bd)
2348		dma_free_coherent(&pdev->dev,
2349			MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2350			host->dma.bd, host->dma.bd_addr);
2351host_free:
2352	mmc_free_host(mmc);
2353
2354	return ret;
2355}
2356
2357static int msdc_drv_remove(struct platform_device *pdev)
2358{
2359	struct mmc_host *mmc;
2360	struct msdc_host *host;
2361
2362	mmc = platform_get_drvdata(pdev);
2363	host = mmc_priv(mmc);
2364
2365	pm_runtime_get_sync(host->dev);
2366
2367	platform_set_drvdata(pdev, NULL);
2368	mmc_remove_host(host->mmc);
2369	msdc_deinit_hw(host);
2370	msdc_gate_clock(host);
2371
2372	pm_runtime_disable(host->dev);
2373	pm_runtime_put_noidle(host->dev);
2374	dma_free_coherent(&pdev->dev,
2375			2 * sizeof(struct mt_gpdma_desc),
2376			host->dma.gpd, host->dma.gpd_addr);
2377	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2378			host->dma.bd, host->dma.bd_addr);
2379
2380	mmc_free_host(host->mmc);
2381
2382	return 0;
2383}
2384
2385#ifdef CONFIG_PM
2386static void msdc_save_reg(struct msdc_host *host)
2387{
2388	u32 tune_reg = host->dev_comp->pad_tune_reg;
2389
2390	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2391	host->save_para.iocon = readl(host->base + MSDC_IOCON);
2392	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2393	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2394	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2395	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2396	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2397	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2398	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2399	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2400	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2401	if (host->top_base) {
2402		host->save_para.emmc_top_control =
2403			readl(host->top_base + EMMC_TOP_CONTROL);
2404		host->save_para.emmc_top_cmd =
2405			readl(host->top_base + EMMC_TOP_CMD);
2406		host->save_para.emmc50_pad_ds_tune =
2407			readl(host->top_base + EMMC50_PAD_DS_TUNE);
2408	} else {
2409		host->save_para.pad_tune = readl(host->base + tune_reg);
2410	}
2411}
2412
2413static void msdc_restore_reg(struct msdc_host *host)
2414{
2415	u32 tune_reg = host->dev_comp->pad_tune_reg;
2416
2417	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2418	writel(host->save_para.iocon, host->base + MSDC_IOCON);
2419	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2420	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2421	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2422	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2423	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2424	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2425	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2426	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2427	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2428	if (host->top_base) {
2429		writel(host->save_para.emmc_top_control,
2430		       host->top_base + EMMC_TOP_CONTROL);
2431		writel(host->save_para.emmc_top_cmd,
2432		       host->top_base + EMMC_TOP_CMD);
2433		writel(host->save_para.emmc50_pad_ds_tune,
2434		       host->top_base + EMMC50_PAD_DS_TUNE);
2435	} else {
2436		writel(host->save_para.pad_tune, host->base + tune_reg);
2437	}
2438
2439	if (sdio_irq_claimed(host->mmc))
2440		__msdc_enable_sdio_irq(host, 1);
2441}
2442
2443static int msdc_runtime_suspend(struct device *dev)
2444{
2445	struct mmc_host *mmc = dev_get_drvdata(dev);
2446	struct msdc_host *host = mmc_priv(mmc);
2447
2448	msdc_save_reg(host);
2449	msdc_gate_clock(host);
2450	return 0;
2451}
2452
2453static int msdc_runtime_resume(struct device *dev)
2454{
2455	struct mmc_host *mmc = dev_get_drvdata(dev);
2456	struct msdc_host *host = mmc_priv(mmc);
2457
2458	msdc_ungate_clock(host);
2459	msdc_restore_reg(host);
2460	return 0;
2461}
2462#endif
2463
2464static const struct dev_pm_ops msdc_dev_pm_ops = {
2465	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2466				pm_runtime_force_resume)
2467	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2468};
2469
2470static struct platform_driver mt_msdc_driver = {
2471	.probe = msdc_drv_probe,
2472	.remove = msdc_drv_remove,
2473	.driver = {
2474		.name = "mtk-msdc",
2475		.of_match_table = msdc_of_ids,
2476		.pm = &msdc_dev_pm_ops,
2477	},
2478};
2479
2480module_platform_driver(mt_msdc_driver);
2481MODULE_LICENSE("GPL v2");
2482MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");