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1/*
2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#define MMCIPOWER 0x000
11#define MCI_PWR_OFF 0x00
12#define MCI_PWR_UP 0x02
13#define MCI_PWR_ON 0x03
14#define MCI_OD (1 << 6)
15#define MCI_ROD (1 << 7)
16
17#define MMCICLOCK 0x004
18#define MCI_CLK_ENABLE (1 << 8)
19#define MCI_CLK_PWRSAVE (1 << 9)
20#define MCI_CLK_BYPASS (1 << 10)
21#define MCI_4BIT_BUS (1 << 11)
22/*
23 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
24 * supported in ST Micro U300 and Ux500 versions
25 */
26#define MCI_ST_8BIT_BUS (1 << 12)
27#define MCI_ST_U300_HWFCEN (1 << 13)
28#define MCI_ST_UX500_NEG_EDGE (1 << 13)
29#define MCI_ST_UX500_HWFCEN (1 << 14)
30#define MCI_ST_UX500_CLK_INV (1 << 15)
31
32#define MMCIARGUMENT 0x008
33#define MMCICOMMAND 0x00c
34#define MCI_CPSM_RESPONSE (1 << 6)
35#define MCI_CPSM_LONGRSP (1 << 7)
36#define MCI_CPSM_INTERRUPT (1 << 8)
37#define MCI_CPSM_PENDING (1 << 9)
38#define MCI_CPSM_ENABLE (1 << 10)
39#define MCI_SDIO_SUSP (1 << 11)
40#define MCI_ENCMD_COMPL (1 << 12)
41#define MCI_NIEN (1 << 13)
42#define MCI_CE_ATACMD (1 << 14)
43
44#define MMCIRESPCMD 0x010
45#define MMCIRESPONSE0 0x014
46#define MMCIRESPONSE1 0x018
47#define MMCIRESPONSE2 0x01c
48#define MMCIRESPONSE3 0x020
49#define MMCIDATATIMER 0x024
50#define MMCIDATALENGTH 0x028
51#define MMCIDATACTRL 0x02c
52#define MCI_DPSM_ENABLE (1 << 0)
53#define MCI_DPSM_DIRECTION (1 << 1)
54#define MCI_DPSM_MODE (1 << 2)
55#define MCI_DPSM_DMAENABLE (1 << 3)
56#define MCI_DPSM_BLOCKSIZE (1 << 4)
57/* Control register extensions in the ST Micro U300 and Ux500 versions */
58#define MCI_ST_DPSM_RWSTART (1 << 8)
59#define MCI_ST_DPSM_RWSTOP (1 << 9)
60#define MCI_ST_DPSM_RWMOD (1 << 10)
61#define MCI_ST_DPSM_SDIOEN (1 << 11)
62/* Control register extensions in the ST Micro Ux500 versions */
63#define MCI_ST_DPSM_DMAREQCTL (1 << 12)
64#define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
65#define MCI_ST_DPSM_BUSYMODE (1 << 14)
66#define MCI_ST_DPSM_DDRMODE (1 << 15)
67
68#define MMCIDATACNT 0x030
69#define MMCISTATUS 0x034
70#define MCI_CMDCRCFAIL (1 << 0)
71#define MCI_DATACRCFAIL (1 << 1)
72#define MCI_CMDTIMEOUT (1 << 2)
73#define MCI_DATATIMEOUT (1 << 3)
74#define MCI_TXUNDERRUN (1 << 4)
75#define MCI_RXOVERRUN (1 << 5)
76#define MCI_CMDRESPEND (1 << 6)
77#define MCI_CMDSENT (1 << 7)
78#define MCI_DATAEND (1 << 8)
79#define MCI_STARTBITERR (1 << 9)
80#define MCI_DATABLOCKEND (1 << 10)
81#define MCI_CMDACTIVE (1 << 11)
82#define MCI_TXACTIVE (1 << 12)
83#define MCI_RXACTIVE (1 << 13)
84#define MCI_TXFIFOHALFEMPTY (1 << 14)
85#define MCI_RXFIFOHALFFULL (1 << 15)
86#define MCI_TXFIFOFULL (1 << 16)
87#define MCI_RXFIFOFULL (1 << 17)
88#define MCI_TXFIFOEMPTY (1 << 18)
89#define MCI_RXFIFOEMPTY (1 << 19)
90#define MCI_TXDATAAVLBL (1 << 20)
91#define MCI_RXDATAAVLBL (1 << 21)
92/* Extended status bits for the ST Micro variants */
93#define MCI_ST_SDIOIT (1 << 22)
94#define MCI_ST_CEATAEND (1 << 23)
95
96#define MMCICLEAR 0x038
97#define MCI_CMDCRCFAILCLR (1 << 0)
98#define MCI_DATACRCFAILCLR (1 << 1)
99#define MCI_CMDTIMEOUTCLR (1 << 2)
100#define MCI_DATATIMEOUTCLR (1 << 3)
101#define MCI_TXUNDERRUNCLR (1 << 4)
102#define MCI_RXOVERRUNCLR (1 << 5)
103#define MCI_CMDRESPENDCLR (1 << 6)
104#define MCI_CMDSENTCLR (1 << 7)
105#define MCI_DATAENDCLR (1 << 8)
106#define MCI_STARTBITERRCLR (1 << 9)
107#define MCI_DATABLOCKENDCLR (1 << 10)
108/* Extended status bits for the ST Micro variants */
109#define MCI_ST_SDIOITC (1 << 22)
110#define MCI_ST_CEATAENDC (1 << 23)
111
112#define MMCIMASK0 0x03c
113#define MCI_CMDCRCFAILMASK (1 << 0)
114#define MCI_DATACRCFAILMASK (1 << 1)
115#define MCI_CMDTIMEOUTMASK (1 << 2)
116#define MCI_DATATIMEOUTMASK (1 << 3)
117#define MCI_TXUNDERRUNMASK (1 << 4)
118#define MCI_RXOVERRUNMASK (1 << 5)
119#define MCI_CMDRESPENDMASK (1 << 6)
120#define MCI_CMDSENTMASK (1 << 7)
121#define MCI_DATAENDMASK (1 << 8)
122#define MCI_STARTBITERRMASK (1 << 9)
123#define MCI_DATABLOCKENDMASK (1 << 10)
124#define MCI_CMDACTIVEMASK (1 << 11)
125#define MCI_TXACTIVEMASK (1 << 12)
126#define MCI_RXACTIVEMASK (1 << 13)
127#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
128#define MCI_RXFIFOHALFFULLMASK (1 << 15)
129#define MCI_TXFIFOFULLMASK (1 << 16)
130#define MCI_RXFIFOFULLMASK (1 << 17)
131#define MCI_TXFIFOEMPTYMASK (1 << 18)
132#define MCI_RXFIFOEMPTYMASK (1 << 19)
133#define MCI_TXDATAAVLBLMASK (1 << 20)
134#define MCI_RXDATAAVLBLMASK (1 << 21)
135/* Extended status bits for the ST Micro variants */
136#define MCI_ST_SDIOITMASK (1 << 22)
137#define MCI_ST_CEATAENDMASK (1 << 23)
138
139#define MMCIMASK1 0x040
140#define MMCIFIFOCNT 0x048
141#define MMCIFIFO 0x080 /* to 0x0bc */
142
143#define MCI_IRQENABLE \
144 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
145 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
146 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)
147
148/* These interrupts are directed to IRQ1 when two IRQ lines are available */
149#define MCI_IRQ1MASK \
150 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
151 MCI_TXFIFOHALFEMPTYMASK)
152
153#define NR_SG 128
154
155struct clk;
156struct variant_data;
157struct dma_chan;
158
159struct mmci_host_next {
160 struct dma_async_tx_descriptor *dma_desc;
161 struct dma_chan *dma_chan;
162 s32 cookie;
163};
164
165struct mmci_host {
166 phys_addr_t phybase;
167 void __iomem *base;
168 struct mmc_request *mrq;
169 struct mmc_command *cmd;
170 struct mmc_data *data;
171 struct mmc_host *mmc;
172 struct clk *clk;
173 int gpio_cd;
174 int gpio_wp;
175 int gpio_cd_irq;
176 bool singleirq;
177
178 spinlock_t lock;
179
180 unsigned int mclk;
181 unsigned int cclk;
182 u32 pwr_reg;
183 u32 clk_reg;
184 struct mmci_platform_data *plat;
185 struct variant_data *variant;
186
187 u8 hw_designer;
188 u8 hw_revision:4;
189
190 struct timer_list timer;
191 unsigned int oldstat;
192
193 /* pio stuff */
194 struct sg_mapping_iter sg_miter;
195 unsigned int size;
196 struct regulator *vcc;
197
198#ifdef CONFIG_DMA_ENGINE
199 /* DMA stuff */
200 struct dma_chan *dma_current;
201 struct dma_chan *dma_rx_channel;
202 struct dma_chan *dma_tx_channel;
203 struct dma_async_tx_descriptor *dma_desc_current;
204 struct mmci_host_next next_data;
205
206#define dma_inprogress(host) ((host)->dma_current)
207#else
208#define dma_inprogress(host) (0)
209#endif
210};
211
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
4 *
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 */
7#define MMCIPOWER 0x000
8#define MCI_PWR_OFF 0x00
9#define MCI_PWR_UP 0x02
10#define MCI_PWR_ON 0x03
11#define MCI_OD (1 << 6)
12#define MCI_ROD (1 << 7)
13/*
14 * The ST Micro version does not have ROD and reuse the voltage registers for
15 * direction settings.
16 */
17#define MCI_ST_DATA2DIREN (1 << 2)
18#define MCI_ST_CMDDIREN (1 << 3)
19#define MCI_ST_DATA0DIREN (1 << 4)
20#define MCI_ST_DATA31DIREN (1 << 5)
21#define MCI_ST_FBCLKEN (1 << 7)
22#define MCI_ST_DATA74DIREN (1 << 8)
23/*
24 * The STM32 sdmmc does not have PWR_UP/OD/ROD
25 * and uses the power register for
26 */
27#define MCI_STM32_PWR_CYC 0x02
28#define MCI_STM32_VSWITCH BIT(2)
29#define MCI_STM32_VSWITCHEN BIT(3)
30#define MCI_STM32_DIRPOL BIT(4)
31
32#define MMCICLOCK 0x004
33#define MCI_CLK_ENABLE (1 << 8)
34#define MCI_CLK_PWRSAVE (1 << 9)
35#define MCI_CLK_BYPASS (1 << 10)
36#define MCI_4BIT_BUS (1 << 11)
37/*
38 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
39 * supported in ST Micro U300 and Ux500 versions
40 */
41#define MCI_ST_8BIT_BUS (1 << 12)
42#define MCI_ST_U300_HWFCEN (1 << 13)
43#define MCI_ST_UX500_NEG_EDGE (1 << 13)
44#define MCI_ST_UX500_HWFCEN (1 << 14)
45#define MCI_ST_UX500_CLK_INV (1 << 15)
46/* Modified PL180 on Versatile Express platform */
47#define MCI_ARM_HWFCEN (1 << 12)
48
49/* Modified on Qualcomm Integrations */
50#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11))
51#define MCI_QCOM_CLK_FLOWENA BIT(12)
52#define MCI_QCOM_CLK_INVERTOUT BIT(13)
53
54/* select in latch data and command in */
55#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
56#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
57
58/* Modified on STM32 sdmmc */
59#define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
60#define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
61#define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
62#define MCI_STM32_CLK_NEGEDGE BIT(16)
63#define MCI_STM32_CLK_HWFCEN BIT(17)
64#define MCI_STM32_CLK_DDR BIT(18)
65#define MCI_STM32_CLK_BUSSPEED BIT(19)
66#define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
67#define MCI_STM32_CLK_SELCK (0 << 20)
68#define MCI_STM32_CLK_SELCKIN (1 << 20)
69#define MCI_STM32_CLK_SELFBCK (2 << 20)
70
71#define MMCIARGUMENT 0x008
72
73/* The command register controls the Command Path State Machine (CPSM) */
74#define MMCICOMMAND 0x00c
75#define MCI_CPSM_RESPONSE BIT(6)
76#define MCI_CPSM_LONGRSP BIT(7)
77#define MCI_CPSM_INTERRUPT BIT(8)
78#define MCI_CPSM_PENDING BIT(9)
79#define MCI_CPSM_ENABLE BIT(10)
80/* Command register flag extenstions in the ST Micro versions */
81#define MCI_CPSM_ST_SDIO_SUSP BIT(11)
82#define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
83#define MCI_CPSM_ST_NIEN BIT(13)
84#define MCI_CPSM_ST_CE_ATACMD BIT(14)
85/* Command register flag extensions in the Qualcomm versions */
86#define MCI_CPSM_QCOM_PROGENA BIT(11)
87#define MCI_CPSM_QCOM_DATCMD BIT(12)
88#define MCI_CPSM_QCOM_MCIABORT BIT(13)
89#define MCI_CPSM_QCOM_CCSENABLE BIT(14)
90#define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
91#define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
92#define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
93/* Command register in STM32 sdmmc versions */
94#define MCI_CPSM_STM32_CMDTRANS BIT(6)
95#define MCI_CPSM_STM32_CMDSTOP BIT(7)
96#define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
97#define MCI_CPSM_STM32_NORSP (0 << 8)
98#define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
99#define MCI_CPSM_STM32_SRSP (2 << 8)
100#define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
101#define MCI_CPSM_STM32_ENABLE BIT(12)
102
103#define MMCIRESPCMD 0x010
104#define MMCIRESPONSE0 0x014
105#define MMCIRESPONSE1 0x018
106#define MMCIRESPONSE2 0x01c
107#define MMCIRESPONSE3 0x020
108#define MMCIDATATIMER 0x024
109#define MMCIDATALENGTH 0x028
110
111/* The data control register controls the Data Path State Machine (DPSM) */
112#define MMCIDATACTRL 0x02c
113#define MCI_DPSM_ENABLE BIT(0)
114#define MCI_DPSM_DIRECTION BIT(1)
115#define MCI_DPSM_MODE BIT(2)
116#define MCI_DPSM_DMAENABLE BIT(3)
117#define MCI_DPSM_BLOCKSIZE BIT(4)
118/* Control register extensions in the ST Micro U300 and Ux500 versions */
119#define MCI_DPSM_ST_RWSTART BIT(8)
120#define MCI_DPSM_ST_RWSTOP BIT(9)
121#define MCI_DPSM_ST_RWMOD BIT(10)
122#define MCI_DPSM_ST_SDIOEN BIT(11)
123/* Control register extensions in the ST Micro Ux500 versions */
124#define MCI_DPSM_ST_DMAREQCTL BIT(12)
125#define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
126#define MCI_DPSM_ST_BUSYMODE BIT(14)
127#define MCI_DPSM_ST_DDRMODE BIT(15)
128/* Control register extensions in the Qualcomm versions */
129#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
130#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
131/* Control register extensions in STM32 versions */
132#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2)
133#define MCI_DPSM_STM32_MODE_SDIO (1 << 2)
134#define MCI_DPSM_STM32_MODE_STREAM (2 << 2)
135#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2)
136
137#define MMCIDATACNT 0x030
138#define MMCISTATUS 0x034
139#define MCI_CMDCRCFAIL (1 << 0)
140#define MCI_DATACRCFAIL (1 << 1)
141#define MCI_CMDTIMEOUT (1 << 2)
142#define MCI_DATATIMEOUT (1 << 3)
143#define MCI_TXUNDERRUN (1 << 4)
144#define MCI_RXOVERRUN (1 << 5)
145#define MCI_CMDRESPEND (1 << 6)
146#define MCI_CMDSENT (1 << 7)
147#define MCI_DATAEND (1 << 8)
148#define MCI_STARTBITERR (1 << 9)
149#define MCI_DATABLOCKEND (1 << 10)
150#define MCI_CMDACTIVE (1 << 11)
151#define MCI_TXACTIVE (1 << 12)
152#define MCI_RXACTIVE (1 << 13)
153#define MCI_TXFIFOHALFEMPTY (1 << 14)
154#define MCI_RXFIFOHALFFULL (1 << 15)
155#define MCI_TXFIFOFULL (1 << 16)
156#define MCI_RXFIFOFULL (1 << 17)
157#define MCI_TXFIFOEMPTY (1 << 18)
158#define MCI_RXFIFOEMPTY (1 << 19)
159#define MCI_TXDATAAVLBL (1 << 20)
160#define MCI_RXDATAAVLBL (1 << 21)
161/* Extended status bits for the ST Micro variants */
162#define MCI_ST_SDIOIT (1 << 22)
163#define MCI_ST_CEATAEND (1 << 23)
164#define MCI_ST_CARDBUSY (1 << 24)
165/* Extended status bits for the STM32 variants */
166#define MCI_STM32_BUSYD0 BIT(20)
167
168#define MMCICLEAR 0x038
169#define MCI_CMDCRCFAILCLR (1 << 0)
170#define MCI_DATACRCFAILCLR (1 << 1)
171#define MCI_CMDTIMEOUTCLR (1 << 2)
172#define MCI_DATATIMEOUTCLR (1 << 3)
173#define MCI_TXUNDERRUNCLR (1 << 4)
174#define MCI_RXOVERRUNCLR (1 << 5)
175#define MCI_CMDRESPENDCLR (1 << 6)
176#define MCI_CMDSENTCLR (1 << 7)
177#define MCI_DATAENDCLR (1 << 8)
178#define MCI_STARTBITERRCLR (1 << 9)
179#define MCI_DATABLOCKENDCLR (1 << 10)
180/* Extended status bits for the ST Micro variants */
181#define MCI_ST_SDIOITC (1 << 22)
182#define MCI_ST_CEATAENDC (1 << 23)
183#define MCI_ST_BUSYENDC (1 << 24)
184
185#define MMCIMASK0 0x03c
186#define MCI_CMDCRCFAILMASK (1 << 0)
187#define MCI_DATACRCFAILMASK (1 << 1)
188#define MCI_CMDTIMEOUTMASK (1 << 2)
189#define MCI_DATATIMEOUTMASK (1 << 3)
190#define MCI_TXUNDERRUNMASK (1 << 4)
191#define MCI_RXOVERRUNMASK (1 << 5)
192#define MCI_CMDRESPENDMASK (1 << 6)
193#define MCI_CMDSENTMASK (1 << 7)
194#define MCI_DATAENDMASK (1 << 8)
195#define MCI_STARTBITERRMASK (1 << 9)
196#define MCI_DATABLOCKENDMASK (1 << 10)
197#define MCI_CMDACTIVEMASK (1 << 11)
198#define MCI_TXACTIVEMASK (1 << 12)
199#define MCI_RXACTIVEMASK (1 << 13)
200#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
201#define MCI_RXFIFOHALFFULLMASK (1 << 15)
202#define MCI_TXFIFOFULLMASK (1 << 16)
203#define MCI_RXFIFOFULLMASK (1 << 17)
204#define MCI_TXFIFOEMPTYMASK (1 << 18)
205#define MCI_RXFIFOEMPTYMASK (1 << 19)
206#define MCI_TXDATAAVLBLMASK (1 << 20)
207#define MCI_RXDATAAVLBLMASK (1 << 21)
208/* Extended status bits for the ST Micro variants */
209#define MCI_ST_SDIOITMASK (1 << 22)
210#define MCI_ST_CEATAENDMASK (1 << 23)
211#define MCI_ST_BUSYENDMASK (1 << 24)
212/* Extended status bits for the STM32 variants */
213#define MCI_STM32_BUSYD0ENDMASK BIT(21)
214
215#define MMCIMASK1 0x040
216#define MMCIFIFOCNT 0x048
217#define MMCIFIFO 0x080 /* to 0x0bc */
218
219/* STM32 sdmmc registers for IDMA (Internal DMA) */
220#define MMCI_STM32_IDMACTRLR 0x050
221#define MMCI_STM32_IDMAEN BIT(0)
222#define MMCI_STM32_IDMALLIEN BIT(1)
223
224#define MMCI_STM32_IDMABSIZER 0x054
225#define MMCI_STM32_IDMABNDT_SHIFT 5
226#define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
227
228#define MMCI_STM32_IDMABASE0R 0x058
229
230#define MMCI_STM32_IDMALAR 0x64
231#define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
232#define MMCI_STM32_ABR BIT(29)
233#define MMCI_STM32_ULS BIT(30)
234#define MMCI_STM32_ULA BIT(31)
235
236#define MMCI_STM32_IDMABAR 0x68
237
238#define MCI_IRQENABLE \
239 (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
240 MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
241 MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
242
243/* These interrupts are directed to IRQ1 when two IRQ lines are available */
244#define MCI_IRQ_PIO_MASK \
245 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
246 MCI_TXFIFOHALFEMPTYMASK)
247
248#define MCI_IRQ_PIO_STM32_MASK \
249 (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
250
251#define NR_SG 128
252
253#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
254
255struct clk;
256struct dma_chan;
257struct mmci_host;
258
259/**
260 * struct variant_data - MMCI variant-specific quirks
261 * @clkreg: default value for MCICLOCK register
262 * @clkreg_enable: enable value for MMCICLOCK register
263 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
264 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
265 * @cmdreg_cpsm_enable: enable value for CPSM
266 * @cmdreg_lrsp_crc: enable value for long response with crc
267 * @cmdreg_srsp_crc: enable value for short response with crc
268 * @cmdreg_srsp: enable value for short response without crc
269 * @cmdreg_stop: enable value for stop and abort transmission
270 * @datalength_bits: number of bits in the MMCIDATALENGTH register
271 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
272 * is asserted (likewise for RX)
273 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
274 * is asserted (likewise for RX)
275 * @data_cmd_enable: enable value for data commands.
276 * @st_sdio: enable ST specific SDIO logic
277 * @st_clkdiv: true if using a ST-specific clock divider algorithm
278 * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
279 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
280 * @datactrl_mask_sdio: SDIO enable mask in datactrl register
281 * @datactrl_blksz: block size in power of two
282 * @datactrl_first: true if data must be setup before send command
283 * @datacnt_useless: true if you could not use datacnt register to read
284 * remaining data
285 * @pwrreg_powerup: power up value for MMCIPOWER register
286 * @f_max: maximum clk frequency supported by the controller.
287 * @signal_direction: input/out direction of bus signals can be indicated
288 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
289 * @busy_detect: true if the variant supports busy detection on DAT0.
290 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
291 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
292 * indicating that the card is busy
293 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
294 * getting busy end detection interrupts
295 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
296 * @explicit_mclk_control: enable explicit mclk control in driver.
297 * @qcom_fifo: enables qcom specific fifo pio read logic.
298 * @qcom_dml: enables qcom specific dma glue for dma transfers.
299 * @reversed_irq_handling: handle data irq before cmd irq.
300 * @mmcimask1: true if variant have a MMCIMASK1 register.
301 * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
302 * register
303 * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
304 * register.
305 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
306 * @dma_lli: true if variant has dma link list feature.
307 * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
308 */
309struct variant_data {
310 unsigned int clkreg;
311 unsigned int clkreg_enable;
312 unsigned int clkreg_8bit_bus_enable;
313 unsigned int clkreg_neg_edge_enable;
314 unsigned int cmdreg_cpsm_enable;
315 unsigned int cmdreg_lrsp_crc;
316 unsigned int cmdreg_srsp_crc;
317 unsigned int cmdreg_srsp;
318 unsigned int cmdreg_stop;
319 unsigned int datalength_bits;
320 unsigned int fifosize;
321 unsigned int fifohalfsize;
322 unsigned int data_cmd_enable;
323 unsigned int datactrl_mask_ddrmode;
324 unsigned int datactrl_mask_sdio;
325 unsigned int datactrl_blocksz;
326 u8 datactrl_first:1;
327 u8 datacnt_useless:1;
328 u8 st_sdio:1;
329 u8 st_clkdiv:1;
330 u8 stm32_clkdiv:1;
331 u32 pwrreg_powerup;
332 u32 f_max;
333 u8 signal_direction:1;
334 u8 pwrreg_clkgate:1;
335 u8 busy_detect:1;
336 u32 busy_dpsm_flag;
337 u32 busy_detect_flag;
338 u32 busy_detect_mask;
339 u8 pwrreg_nopower:1;
340 u8 explicit_mclk_control:1;
341 u8 qcom_fifo:1;
342 u8 qcom_dml:1;
343 u8 reversed_irq_handling:1;
344 u8 mmcimask1:1;
345 unsigned int irq_pio_mask;
346 u32 start_err;
347 u32 opendrain;
348 u8 dma_lli:1;
349 u32 stm32_idmabsize_mask;
350 void (*init)(struct mmci_host *host);
351};
352
353/* mmci variant callbacks */
354struct mmci_host_ops {
355 int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
356 int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
357 bool next);
358 void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
359 int err);
360 u32 (*get_datactrl_cfg)(struct mmci_host *host);
361 void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
362 int (*dma_setup)(struct mmci_host *host);
363 void (*dma_release)(struct mmci_host *host);
364 int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
365 void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
366 void (*dma_error)(struct mmci_host *host);
367 void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
368 void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
369};
370
371struct mmci_host {
372 phys_addr_t phybase;
373 void __iomem *base;
374 struct mmc_request *mrq;
375 struct mmc_command *cmd;
376 struct mmc_command stop_abort;
377 struct mmc_data *data;
378 struct mmc_host *mmc;
379 struct clk *clk;
380 u8 singleirq:1;
381
382 struct reset_control *rst;
383
384 spinlock_t lock;
385
386 unsigned int mclk;
387 /* cached value of requested clk in set_ios */
388 unsigned int clock_cache;
389 unsigned int cclk;
390 u32 pwr_reg;
391 u32 pwr_reg_add;
392 u32 clk_reg;
393 u32 clk_reg_add;
394 u32 datactrl_reg;
395 u32 busy_status;
396 u32 mask1_reg;
397 u8 vqmmc_enabled:1;
398 struct mmci_platform_data *plat;
399 struct mmci_host_ops *ops;
400 struct variant_data *variant;
401 struct pinctrl *pinctrl;
402 struct pinctrl_state *pins_default;
403 struct pinctrl_state *pins_opendrain;
404
405 u8 hw_designer;
406 u8 hw_revision:4;
407
408 struct timer_list timer;
409 unsigned int oldstat;
410
411 /* pio stuff */
412 struct sg_mapping_iter sg_miter;
413 unsigned int size;
414 int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
415
416 u8 use_dma:1;
417 u8 dma_in_progress:1;
418 void *dma_priv;
419
420 s32 next_cookie;
421};
422
423#define dma_inprogress(host) ((host)->dma_in_progress)
424
425void mmci_write_clkreg(struct mmci_host *host, u32 clk);
426void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
427
428static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
429{
430 return (ffs(host->data->blksz) - 1) << 4;
431}
432
433#ifdef CONFIG_DMA_ENGINE
434int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
435 bool next);
436void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
437 int err);
438void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
439int mmci_dmae_setup(struct mmci_host *host);
440void mmci_dmae_release(struct mmci_host *host);
441int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
442void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
443void mmci_dmae_error(struct mmci_host *host);
444#endif
445
446#ifdef CONFIG_MMC_QCOM_DML
447void qcom_variant_init(struct mmci_host *host);
448#else
449static inline void qcom_variant_init(struct mmci_host *host) {}
450#endif
451
452#ifdef CONFIG_MMC_STM32_SDMMC
453void sdmmc_variant_init(struct mmci_host *host);
454#else
455static inline void sdmmc_variant_init(struct mmci_host *host) {}
456#endif