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1/*
2 * Copyright (C) 2008, 2009 Provigent Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
9 *
10 * Data sheet: ARM DDI 0190B, September 2000
11 */
12#include <linux/spinlock.h>
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/bitops.h>
19#include <linux/workqueue.h>
20#include <linux/gpio.h>
21#include <linux/device.h>
22#include <linux/amba/bus.h>
23#include <linux/amba/pl061.h>
24#include <linux/slab.h>
25#include <linux/pm.h>
26#include <asm/mach/irq.h>
27
28#define GPIODIR 0x400
29#define GPIOIS 0x404
30#define GPIOIBE 0x408
31#define GPIOIEV 0x40C
32#define GPIOIE 0x410
33#define GPIORIS 0x414
34#define GPIOMIS 0x418
35#define GPIOIC 0x41C
36
37#define PL061_GPIO_NR 8
38
39#ifdef CONFIG_PM
40struct pl061_context_save_regs {
41 u8 gpio_data;
42 u8 gpio_dir;
43 u8 gpio_is;
44 u8 gpio_ibe;
45 u8 gpio_iev;
46 u8 gpio_ie;
47};
48#endif
49
50struct pl061_gpio {
51 /* Each of the two spinlocks protects a different set of hardware
52 * regiters and data structurs. This decouples the code of the IRQ from
53 * the GPIO code. This also makes the case of a GPIO routine call from
54 * the IRQ code simpler.
55 */
56 spinlock_t lock; /* GPIO registers */
57
58 void __iomem *base;
59 int irq_base;
60 struct irq_chip_generic *irq_gc;
61 struct gpio_chip gc;
62
63#ifdef CONFIG_PM
64 struct pl061_context_save_regs csave_regs;
65#endif
66};
67
68static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
69{
70 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
71 unsigned long flags;
72 unsigned char gpiodir;
73
74 if (offset >= gc->ngpio)
75 return -EINVAL;
76
77 spin_lock_irqsave(&chip->lock, flags);
78 gpiodir = readb(chip->base + GPIODIR);
79 gpiodir &= ~(1 << offset);
80 writeb(gpiodir, chip->base + GPIODIR);
81 spin_unlock_irqrestore(&chip->lock, flags);
82
83 return 0;
84}
85
86static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
87 int value)
88{
89 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
90 unsigned long flags;
91 unsigned char gpiodir;
92
93 if (offset >= gc->ngpio)
94 return -EINVAL;
95
96 spin_lock_irqsave(&chip->lock, flags);
97 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
98 gpiodir = readb(chip->base + GPIODIR);
99 gpiodir |= 1 << offset;
100 writeb(gpiodir, chip->base + GPIODIR);
101
102 /*
103 * gpio value is set again, because pl061 doesn't allow to set value of
104 * a gpio pin before configuring it in OUT mode.
105 */
106 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
107 spin_unlock_irqrestore(&chip->lock, flags);
108
109 return 0;
110}
111
112static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
113{
114 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
115
116 return !!readb(chip->base + (1 << (offset + 2)));
117}
118
119static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
120{
121 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
122
123 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
124}
125
126static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
127{
128 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
129
130 if (chip->irq_base <= 0)
131 return -EINVAL;
132
133 return chip->irq_base + offset;
134}
135
136static int pl061_irq_type(struct irq_data *d, unsigned trigger)
137{
138 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
139 struct pl061_gpio *chip = gc->private;
140 int offset = d->irq - chip->irq_base;
141 unsigned long flags;
142 u8 gpiois, gpioibe, gpioiev;
143
144 if (offset < 0 || offset >= PL061_GPIO_NR)
145 return -EINVAL;
146
147 raw_spin_lock_irqsave(&gc->lock, flags);
148
149 gpioiev = readb(chip->base + GPIOIEV);
150
151 gpiois = readb(chip->base + GPIOIS);
152 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
153 gpiois |= 1 << offset;
154 if (trigger & IRQ_TYPE_LEVEL_HIGH)
155 gpioiev |= 1 << offset;
156 else
157 gpioiev &= ~(1 << offset);
158 } else
159 gpiois &= ~(1 << offset);
160 writeb(gpiois, chip->base + GPIOIS);
161
162 gpioibe = readb(chip->base + GPIOIBE);
163 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
164 gpioibe |= 1 << offset;
165 else {
166 gpioibe &= ~(1 << offset);
167 if (trigger & IRQ_TYPE_EDGE_RISING)
168 gpioiev |= 1 << offset;
169 else if (trigger & IRQ_TYPE_EDGE_FALLING)
170 gpioiev &= ~(1 << offset);
171 }
172 writeb(gpioibe, chip->base + GPIOIBE);
173
174 writeb(gpioiev, chip->base + GPIOIEV);
175
176 raw_spin_unlock_irqrestore(&gc->lock, flags);
177
178 return 0;
179}
180
181static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
182{
183 unsigned long pending;
184 int offset;
185 struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
186 struct irq_chip *irqchip = irq_desc_get_chip(desc);
187
188 chained_irq_enter(irqchip, desc);
189
190 pending = readb(chip->base + GPIOMIS);
191 writeb(pending, chip->base + GPIOIC);
192 if (pending) {
193 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
194 generic_handle_irq(pl061_to_irq(&chip->gc, offset));
195 }
196
197 chained_irq_exit(irqchip, desc);
198}
199
200static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
201{
202 struct irq_chip_type *ct;
203
204 chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
205 chip->base, handle_simple_irq);
206 chip->irq_gc->private = chip;
207
208 ct = chip->irq_gc->chip_types;
209 ct->chip.irq_mask = irq_gc_mask_clr_bit;
210 ct->chip.irq_unmask = irq_gc_mask_set_bit;
211 ct->chip.irq_set_type = pl061_irq_type;
212 ct->chip.irq_set_wake = irq_gc_set_wake;
213 ct->regs.mask = GPIOIE;
214
215 irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
216 IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
217}
218
219static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
220{
221 struct pl061_platform_data *pdata;
222 struct pl061_gpio *chip;
223 int ret, irq, i;
224
225 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
226 if (chip == NULL)
227 return -ENOMEM;
228
229 pdata = dev->dev.platform_data;
230 if (pdata) {
231 chip->gc.base = pdata->gpio_base;
232 chip->irq_base = pdata->irq_base;
233 } else if (dev->dev.of_node) {
234 chip->gc.base = -1;
235 chip->irq_base = 0;
236 } else {
237 ret = -ENODEV;
238 goto free_mem;
239 }
240
241 if (!request_mem_region(dev->res.start,
242 resource_size(&dev->res), "pl061")) {
243 ret = -EBUSY;
244 goto free_mem;
245 }
246
247 chip->base = ioremap(dev->res.start, resource_size(&dev->res));
248 if (chip->base == NULL) {
249 ret = -ENOMEM;
250 goto release_region;
251 }
252
253 spin_lock_init(&chip->lock);
254
255 chip->gc.direction_input = pl061_direction_input;
256 chip->gc.direction_output = pl061_direction_output;
257 chip->gc.get = pl061_get_value;
258 chip->gc.set = pl061_set_value;
259 chip->gc.to_irq = pl061_to_irq;
260 chip->gc.ngpio = PL061_GPIO_NR;
261 chip->gc.label = dev_name(&dev->dev);
262 chip->gc.dev = &dev->dev;
263 chip->gc.owner = THIS_MODULE;
264
265 ret = gpiochip_add(&chip->gc);
266 if (ret)
267 goto iounmap;
268
269 /*
270 * irq_chip support
271 */
272
273 if (chip->irq_base <= 0)
274 return 0;
275
276 pl061_init_gc(chip, chip->irq_base);
277
278 writeb(0, chip->base + GPIOIE); /* disable irqs */
279 irq = dev->irq[0];
280 if (irq < 0) {
281 ret = -ENODEV;
282 goto iounmap;
283 }
284 irq_set_chained_handler(irq, pl061_irq_handler);
285 irq_set_handler_data(irq, chip);
286
287 for (i = 0; i < PL061_GPIO_NR; i++) {
288 if (pdata) {
289 if (pdata->directions & (1 << i))
290 pl061_direction_output(&chip->gc, i,
291 pdata->values & (1 << i));
292 else
293 pl061_direction_input(&chip->gc, i);
294 }
295 }
296
297 amba_set_drvdata(dev, chip);
298
299 return 0;
300
301iounmap:
302 iounmap(chip->base);
303release_region:
304 release_mem_region(dev->res.start, resource_size(&dev->res));
305free_mem:
306 kfree(chip);
307
308 return ret;
309}
310
311#ifdef CONFIG_PM
312static int pl061_suspend(struct device *dev)
313{
314 struct pl061_gpio *chip = dev_get_drvdata(dev);
315 int offset;
316
317 chip->csave_regs.gpio_data = 0;
318 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
319 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
320 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
321 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
322 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
323
324 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
325 if (chip->csave_regs.gpio_dir & (1 << offset))
326 chip->csave_regs.gpio_data |=
327 pl061_get_value(&chip->gc, offset) << offset;
328 }
329
330 return 0;
331}
332
333static int pl061_resume(struct device *dev)
334{
335 struct pl061_gpio *chip = dev_get_drvdata(dev);
336 int offset;
337
338 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
339 if (chip->csave_regs.gpio_dir & (1 << offset))
340 pl061_direction_output(&chip->gc, offset,
341 chip->csave_regs.gpio_data &
342 (1 << offset));
343 else
344 pl061_direction_input(&chip->gc, offset);
345 }
346
347 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
348 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
349 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
350 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
351
352 return 0;
353}
354
355static const struct dev_pm_ops pl061_dev_pm_ops = {
356 .suspend = pl061_suspend,
357 .resume = pl061_resume,
358 .freeze = pl061_suspend,
359 .restore = pl061_resume,
360};
361#endif
362
363static struct amba_id pl061_ids[] = {
364 {
365 .id = 0x00041061,
366 .mask = 0x000fffff,
367 },
368 { 0, 0 },
369};
370
371MODULE_DEVICE_TABLE(amba, pl061_ids);
372
373static struct amba_driver pl061_gpio_driver = {
374 .drv = {
375 .name = "pl061_gpio",
376#ifdef CONFIG_PM
377 .pm = &pl061_dev_pm_ops,
378#endif
379 },
380 .id_table = pl061_ids,
381 .probe = pl061_probe,
382};
383
384static int __init pl061_gpio_init(void)
385{
386 return amba_driver_register(&pl061_gpio_driver);
387}
388subsys_initcall(pl061_gpio_init);
389
390MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
391MODULE_DESCRIPTION("PL061 GPIO driver");
392MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2008, 2009 Provigent Ltd.
4 *
5 * Author: Baruch Siach <baruch@tkos.co.il>
6 *
7 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
8 *
9 * Data sheet: ARM DDI 0190B, September 2000
10 */
11#include <linux/spinlock.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/bitops.h>
20#include <linux/gpio/driver.h>
21#include <linux/device.h>
22#include <linux/amba/bus.h>
23#include <linux/slab.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/pm.h>
26
27#define GPIODIR 0x400
28#define GPIOIS 0x404
29#define GPIOIBE 0x408
30#define GPIOIEV 0x40C
31#define GPIOIE 0x410
32#define GPIORIS 0x414
33#define GPIOMIS 0x418
34#define GPIOIC 0x41C
35
36#define PL061_GPIO_NR 8
37
38#ifdef CONFIG_PM
39struct pl061_context_save_regs {
40 u8 gpio_data;
41 u8 gpio_dir;
42 u8 gpio_is;
43 u8 gpio_ibe;
44 u8 gpio_iev;
45 u8 gpio_ie;
46};
47#endif
48
49struct pl061 {
50 raw_spinlock_t lock;
51
52 void __iomem *base;
53 struct gpio_chip gc;
54 struct irq_chip irq_chip;
55 int parent_irq;
56
57#ifdef CONFIG_PM
58 struct pl061_context_save_regs csave_regs;
59#endif
60};
61
62static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
63{
64 struct pl061 *pl061 = gpiochip_get_data(gc);
65
66 return !(readb(pl061->base + GPIODIR) & BIT(offset));
67}
68
69static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
70{
71 struct pl061 *pl061 = gpiochip_get_data(gc);
72 unsigned long flags;
73 unsigned char gpiodir;
74
75 raw_spin_lock_irqsave(&pl061->lock, flags);
76 gpiodir = readb(pl061->base + GPIODIR);
77 gpiodir &= ~(BIT(offset));
78 writeb(gpiodir, pl061->base + GPIODIR);
79 raw_spin_unlock_irqrestore(&pl061->lock, flags);
80
81 return 0;
82}
83
84static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
85 int value)
86{
87 struct pl061 *pl061 = gpiochip_get_data(gc);
88 unsigned long flags;
89 unsigned char gpiodir;
90
91 raw_spin_lock_irqsave(&pl061->lock, flags);
92 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
93 gpiodir = readb(pl061->base + GPIODIR);
94 gpiodir |= BIT(offset);
95 writeb(gpiodir, pl061->base + GPIODIR);
96
97 /*
98 * gpio value is set again, because pl061 doesn't allow to set value of
99 * a gpio pin before configuring it in OUT mode.
100 */
101 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
102 raw_spin_unlock_irqrestore(&pl061->lock, flags);
103
104 return 0;
105}
106
107static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
108{
109 struct pl061 *pl061 = gpiochip_get_data(gc);
110
111 return !!readb(pl061->base + (BIT(offset + 2)));
112}
113
114static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
115{
116 struct pl061 *pl061 = gpiochip_get_data(gc);
117
118 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
119}
120
121static int pl061_irq_type(struct irq_data *d, unsigned trigger)
122{
123 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
124 struct pl061 *pl061 = gpiochip_get_data(gc);
125 int offset = irqd_to_hwirq(d);
126 unsigned long flags;
127 u8 gpiois, gpioibe, gpioiev;
128 u8 bit = BIT(offset);
129
130 if (offset < 0 || offset >= PL061_GPIO_NR)
131 return -EINVAL;
132
133 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
134 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
135 {
136 dev_err(gc->parent,
137 "trying to configure line %d for both level and edge "
138 "detection, choose one!\n",
139 offset);
140 return -EINVAL;
141 }
142
143
144 raw_spin_lock_irqsave(&pl061->lock, flags);
145
146 gpioiev = readb(pl061->base + GPIOIEV);
147 gpiois = readb(pl061->base + GPIOIS);
148 gpioibe = readb(pl061->base + GPIOIBE);
149
150 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
151 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
152
153 /* Disable edge detection */
154 gpioibe &= ~bit;
155 /* Enable level detection */
156 gpiois |= bit;
157 /* Select polarity */
158 if (polarity)
159 gpioiev |= bit;
160 else
161 gpioiev &= ~bit;
162 irq_set_handler_locked(d, handle_level_irq);
163 dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
164 offset,
165 polarity ? "HIGH" : "LOW");
166 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
167 /* Disable level detection */
168 gpiois &= ~bit;
169 /* Select both edges, setting this makes GPIOEV be ignored */
170 gpioibe |= bit;
171 irq_set_handler_locked(d, handle_edge_irq);
172 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
173 } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
174 (trigger & IRQ_TYPE_EDGE_FALLING)) {
175 bool rising = trigger & IRQ_TYPE_EDGE_RISING;
176
177 /* Disable level detection */
178 gpiois &= ~bit;
179 /* Clear detection on both edges */
180 gpioibe &= ~bit;
181 /* Select edge */
182 if (rising)
183 gpioiev |= bit;
184 else
185 gpioiev &= ~bit;
186 irq_set_handler_locked(d, handle_edge_irq);
187 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
188 offset,
189 rising ? "RISING" : "FALLING");
190 } else {
191 /* No trigger: disable everything */
192 gpiois &= ~bit;
193 gpioibe &= ~bit;
194 gpioiev &= ~bit;
195 irq_set_handler_locked(d, handle_bad_irq);
196 dev_warn(gc->parent, "no trigger selected for line %d\n",
197 offset);
198 }
199
200 writeb(gpiois, pl061->base + GPIOIS);
201 writeb(gpioibe, pl061->base + GPIOIBE);
202 writeb(gpioiev, pl061->base + GPIOIEV);
203
204 raw_spin_unlock_irqrestore(&pl061->lock, flags);
205
206 return 0;
207}
208
209static void pl061_irq_handler(struct irq_desc *desc)
210{
211 unsigned long pending;
212 int offset;
213 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
214 struct pl061 *pl061 = gpiochip_get_data(gc);
215 struct irq_chip *irqchip = irq_desc_get_chip(desc);
216
217 chained_irq_enter(irqchip, desc);
218
219 pending = readb(pl061->base + GPIOMIS);
220 if (pending) {
221 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
222 generic_handle_irq(irq_find_mapping(gc->irq.domain,
223 offset));
224 }
225
226 chained_irq_exit(irqchip, desc);
227}
228
229static void pl061_irq_mask(struct irq_data *d)
230{
231 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
232 struct pl061 *pl061 = gpiochip_get_data(gc);
233 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
234 u8 gpioie;
235
236 raw_spin_lock(&pl061->lock);
237 gpioie = readb(pl061->base + GPIOIE) & ~mask;
238 writeb(gpioie, pl061->base + GPIOIE);
239 raw_spin_unlock(&pl061->lock);
240}
241
242static void pl061_irq_unmask(struct irq_data *d)
243{
244 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245 struct pl061 *pl061 = gpiochip_get_data(gc);
246 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
247 u8 gpioie;
248
249 raw_spin_lock(&pl061->lock);
250 gpioie = readb(pl061->base + GPIOIE) | mask;
251 writeb(gpioie, pl061->base + GPIOIE);
252 raw_spin_unlock(&pl061->lock);
253}
254
255/**
256 * pl061_irq_ack() - ACK an edge IRQ
257 * @d: IRQ data for this IRQ
258 *
259 * This gets called from the edge IRQ handler to ACK the edge IRQ
260 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
261 * not needed: these go away when the level signal goes away.
262 */
263static void pl061_irq_ack(struct irq_data *d)
264{
265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
266 struct pl061 *pl061 = gpiochip_get_data(gc);
267 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
268
269 raw_spin_lock(&pl061->lock);
270 writeb(mask, pl061->base + GPIOIC);
271 raw_spin_unlock(&pl061->lock);
272}
273
274static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
275{
276 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
277 struct pl061 *pl061 = gpiochip_get_data(gc);
278
279 return irq_set_irq_wake(pl061->parent_irq, state);
280}
281
282static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
283{
284 struct device *dev = &adev->dev;
285 struct pl061 *pl061;
286 struct gpio_irq_chip *girq;
287 int ret, irq;
288
289 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
290 if (pl061 == NULL)
291 return -ENOMEM;
292
293 pl061->base = devm_ioremap_resource(dev, &adev->res);
294 if (IS_ERR(pl061->base))
295 return PTR_ERR(pl061->base);
296
297 raw_spin_lock_init(&pl061->lock);
298 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
299 pl061->gc.request = gpiochip_generic_request;
300 pl061->gc.free = gpiochip_generic_free;
301 }
302
303 pl061->gc.base = -1;
304 pl061->gc.get_direction = pl061_get_direction;
305 pl061->gc.direction_input = pl061_direction_input;
306 pl061->gc.direction_output = pl061_direction_output;
307 pl061->gc.get = pl061_get_value;
308 pl061->gc.set = pl061_set_value;
309 pl061->gc.ngpio = PL061_GPIO_NR;
310 pl061->gc.label = dev_name(dev);
311 pl061->gc.parent = dev;
312 pl061->gc.owner = THIS_MODULE;
313
314 /*
315 * irq_chip support
316 */
317 pl061->irq_chip.name = dev_name(dev);
318 pl061->irq_chip.irq_ack = pl061_irq_ack;
319 pl061->irq_chip.irq_mask = pl061_irq_mask;
320 pl061->irq_chip.irq_unmask = pl061_irq_unmask;
321 pl061->irq_chip.irq_set_type = pl061_irq_type;
322 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
323
324 writeb(0, pl061->base + GPIOIE); /* disable irqs */
325 irq = adev->irq[0];
326 if (irq < 0) {
327 dev_err(&adev->dev, "invalid IRQ\n");
328 return -ENODEV;
329 }
330 pl061->parent_irq = irq;
331
332 girq = &pl061->gc.irq;
333 girq->chip = &pl061->irq_chip;
334 girq->parent_handler = pl061_irq_handler;
335 girq->num_parents = 1;
336 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
337 GFP_KERNEL);
338 if (!girq->parents)
339 return -ENOMEM;
340 girq->parents[0] = irq;
341 girq->default_type = IRQ_TYPE_NONE;
342 girq->handler = handle_bad_irq;
343
344 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
345 if (ret)
346 return ret;
347
348 amba_set_drvdata(adev, pl061);
349 dev_info(dev, "PL061 GPIO chip registered\n");
350
351 return 0;
352}
353
354#ifdef CONFIG_PM
355static int pl061_suspend(struct device *dev)
356{
357 struct pl061 *pl061 = dev_get_drvdata(dev);
358 int offset;
359
360 pl061->csave_regs.gpio_data = 0;
361 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
362 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
363 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
364 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
365 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
366
367 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
368 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
369 pl061->csave_regs.gpio_data |=
370 pl061_get_value(&pl061->gc, offset) << offset;
371 }
372
373 return 0;
374}
375
376static int pl061_resume(struct device *dev)
377{
378 struct pl061 *pl061 = dev_get_drvdata(dev);
379 int offset;
380
381 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
382 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
383 pl061_direction_output(&pl061->gc, offset,
384 pl061->csave_regs.gpio_data &
385 (BIT(offset)));
386 else
387 pl061_direction_input(&pl061->gc, offset);
388 }
389
390 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
391 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
392 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
393 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
394
395 return 0;
396}
397
398static const struct dev_pm_ops pl061_dev_pm_ops = {
399 .suspend = pl061_suspend,
400 .resume = pl061_resume,
401 .freeze = pl061_suspend,
402 .restore = pl061_resume,
403};
404#endif
405
406static const struct amba_id pl061_ids[] = {
407 {
408 .id = 0x00041061,
409 .mask = 0x000fffff,
410 },
411 { 0, 0 },
412};
413
414static struct amba_driver pl061_gpio_driver = {
415 .drv = {
416 .name = "pl061_gpio",
417#ifdef CONFIG_PM
418 .pm = &pl061_dev_pm_ops,
419#endif
420 },
421 .id_table = pl061_ids,
422 .probe = pl061_probe,
423};
424
425static int __init pl061_gpio_init(void)
426{
427 return amba_driver_register(&pl061_gpio_driver);
428}
429device_initcall(pl061_gpio_init);