Loading...
Note: File does not exist in v5.4.
1/*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15#include <linux/perf_event.h>
16
17/*
18 * | NHM/WSM | SNB |
19 * register -------------------------------
20 * | HT | no HT | HT | no HT |
21 *-----------------------------------------
22 * offcore | core | core | cpu | core |
23 * lbr_sel | core | core | cpu | core |
24 * ld_lat | cpu | core | cpu | core |
25 *-----------------------------------------
26 *
27 * Given that there is a small number of shared regs,
28 * we can pre-allocate their slot in the per-cpu
29 * per-core reg tables.
30 */
31enum extra_reg_type {
32 EXTRA_REG_NONE = -1, /* not used */
33
34 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
35 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
36 EXTRA_REG_LBR = 2, /* lbr_select */
37
38 EXTRA_REG_MAX /* number of entries needed */
39};
40
41struct event_constraint {
42 union {
43 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
44 u64 idxmsk64;
45 };
46 u64 code;
47 u64 cmask;
48 int weight;
49 int overlap;
50};
51
52struct amd_nb {
53 int nb_id; /* NorthBridge id */
54 int refcnt; /* reference count */
55 struct perf_event *owners[X86_PMC_IDX_MAX];
56 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
57};
58
59/* The maximal number of PEBS events: */
60#define MAX_PEBS_EVENTS 4
61
62/*
63 * A debug store configuration.
64 *
65 * We only support architectures that use 64bit fields.
66 */
67struct debug_store {
68 u64 bts_buffer_base;
69 u64 bts_index;
70 u64 bts_absolute_maximum;
71 u64 bts_interrupt_threshold;
72 u64 pebs_buffer_base;
73 u64 pebs_index;
74 u64 pebs_absolute_maximum;
75 u64 pebs_interrupt_threshold;
76 u64 pebs_event_reset[MAX_PEBS_EVENTS];
77};
78
79/*
80 * Per register state.
81 */
82struct er_account {
83 raw_spinlock_t lock; /* per-core: protect structure */
84 u64 config; /* extra MSR config */
85 u64 reg; /* extra MSR number */
86 atomic_t ref; /* reference count */
87};
88
89/*
90 * Per core/cpu state
91 *
92 * Used to coordinate shared registers between HT threads or
93 * among events on a single PMU.
94 */
95struct intel_shared_regs {
96 struct er_account regs[EXTRA_REG_MAX];
97 int refcnt; /* per-core: #HT threads */
98 unsigned core_id; /* per-core: core id */
99};
100
101#define MAX_LBR_ENTRIES 16
102
103struct cpu_hw_events {
104 /*
105 * Generic x86 PMC bits
106 */
107 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
108 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
109 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
110 int enabled;
111
112 int n_events;
113 int n_added;
114 int n_txn;
115 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
116 u64 tags[X86_PMC_IDX_MAX];
117 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
118
119 unsigned int group_flag;
120 int is_fake;
121
122 /*
123 * Intel DebugStore bits
124 */
125 struct debug_store *ds;
126 u64 pebs_enabled;
127
128 /*
129 * Intel LBR bits
130 */
131 int lbr_users;
132 void *lbr_context;
133 struct perf_branch_stack lbr_stack;
134 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
135 struct er_account *lbr_sel;
136 u64 br_sel;
137
138 /*
139 * Intel host/guest exclude bits
140 */
141 u64 intel_ctrl_guest_mask;
142 u64 intel_ctrl_host_mask;
143 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
144
145 /*
146 * manage shared (per-core, per-cpu) registers
147 * used on Intel NHM/WSM/SNB
148 */
149 struct intel_shared_regs *shared_regs;
150
151 /*
152 * AMD specific bits
153 */
154 struct amd_nb *amd_nb;
155 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
156 u64 perf_ctr_virt_mask;
157
158 void *kfree_on_online;
159};
160
161#define __EVENT_CONSTRAINT(c, n, m, w, o) {\
162 { .idxmsk64 = (n) }, \
163 .code = (c), \
164 .cmask = (m), \
165 .weight = (w), \
166 .overlap = (o), \
167}
168
169#define EVENT_CONSTRAINT(c, n, m) \
170 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
171
172/*
173 * The overlap flag marks event constraints with overlapping counter
174 * masks. This is the case if the counter mask of such an event is not
175 * a subset of any other counter mask of a constraint with an equal or
176 * higher weight, e.g.:
177 *
178 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
179 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
180 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
181 *
182 * The event scheduler may not select the correct counter in the first
183 * cycle because it needs to know which subsequent events will be
184 * scheduled. It may fail to schedule the events then. So we set the
185 * overlap flag for such constraints to give the scheduler a hint which
186 * events to select for counter rescheduling.
187 *
188 * Care must be taken as the rescheduling algorithm is O(n!) which
189 * will increase scheduling cycles for an over-commited system
190 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
191 * and its counter masks must be kept at a minimum.
192 */
193#define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
194 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
195
196/*
197 * Constraint on the Event code.
198 */
199#define INTEL_EVENT_CONSTRAINT(c, n) \
200 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
201
202/*
203 * Constraint on the Event code + UMask + fixed-mask
204 *
205 * filter mask to validate fixed counter events.
206 * the following filters disqualify for fixed counters:
207 * - inv
208 * - edge
209 * - cnt-mask
210 * The other filters are supported by fixed counters.
211 * The any-thread option is supported starting with v3.
212 */
213#define FIXED_EVENT_CONSTRAINT(c, n) \
214 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
215
216/*
217 * Constraint on the Event code + UMask
218 */
219#define INTEL_UEVENT_CONSTRAINT(c, n) \
220 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
221
222#define EVENT_CONSTRAINT_END \
223 EVENT_CONSTRAINT(0, 0, 0)
224
225#define for_each_event_constraint(e, c) \
226 for ((e) = (c); (e)->weight; (e)++)
227
228/*
229 * Extra registers for specific events.
230 *
231 * Some events need large masks and require external MSRs.
232 * Those extra MSRs end up being shared for all events on
233 * a PMU and sometimes between PMU of sibling HT threads.
234 * In either case, the kernel needs to handle conflicting
235 * accesses to those extra, shared, regs. The data structure
236 * to manage those registers is stored in cpu_hw_event.
237 */
238struct extra_reg {
239 unsigned int event;
240 unsigned int msr;
241 u64 config_mask;
242 u64 valid_mask;
243 int idx; /* per_xxx->regs[] reg index */
244};
245
246#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
247 .event = (e), \
248 .msr = (ms), \
249 .config_mask = (m), \
250 .valid_mask = (vm), \
251 .idx = EXTRA_REG_##i \
252 }
253
254#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
255 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
256
257#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
258
259union perf_capabilities {
260 struct {
261 u64 lbr_format:6;
262 u64 pebs_trap:1;
263 u64 pebs_arch_reg:1;
264 u64 pebs_format:4;
265 u64 smm_freeze:1;
266 };
267 u64 capabilities;
268};
269
270struct x86_pmu_quirk {
271 struct x86_pmu_quirk *next;
272 void (*func)(void);
273};
274
275union x86_pmu_config {
276 struct {
277 u64 event:8,
278 umask:8,
279 usr:1,
280 os:1,
281 edge:1,
282 pc:1,
283 interrupt:1,
284 __reserved1:1,
285 en:1,
286 inv:1,
287 cmask:8,
288 event2:4,
289 __reserved2:4,
290 go:1,
291 ho:1;
292 } bits;
293 u64 value;
294};
295
296#define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
297
298/*
299 * struct x86_pmu - generic x86 pmu
300 */
301struct x86_pmu {
302 /*
303 * Generic x86 PMC bits
304 */
305 const char *name;
306 int version;
307 int (*handle_irq)(struct pt_regs *);
308 void (*disable_all)(void);
309 void (*enable_all)(int added);
310 void (*enable)(struct perf_event *);
311 void (*disable)(struct perf_event *);
312 int (*hw_config)(struct perf_event *event);
313 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
314 unsigned eventsel;
315 unsigned perfctr;
316 u64 (*event_map)(int);
317 int max_events;
318 int num_counters;
319 int num_counters_fixed;
320 int cntval_bits;
321 u64 cntval_mask;
322 union {
323 unsigned long events_maskl;
324 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
325 };
326 int events_mask_len;
327 int apic;
328 u64 max_period;
329 struct event_constraint *
330 (*get_event_constraints)(struct cpu_hw_events *cpuc,
331 struct perf_event *event);
332
333 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
334 struct perf_event *event);
335 struct event_constraint *event_constraints;
336 struct x86_pmu_quirk *quirks;
337 int perfctr_second_write;
338
339 /*
340 * sysfs attrs
341 */
342 int attr_rdpmc;
343 struct attribute **format_attrs;
344
345 /*
346 * CPU Hotplug hooks
347 */
348 int (*cpu_prepare)(int cpu);
349 void (*cpu_starting)(int cpu);
350 void (*cpu_dying)(int cpu);
351 void (*cpu_dead)(int cpu);
352 void (*flush_branch_stack)(void);
353
354 /*
355 * Intel Arch Perfmon v2+
356 */
357 u64 intel_ctrl;
358 union perf_capabilities intel_cap;
359
360 /*
361 * Intel DebugStore bits
362 */
363 int bts, pebs;
364 int bts_active, pebs_active;
365 int pebs_record_size;
366 void (*drain_pebs)(struct pt_regs *regs);
367 struct event_constraint *pebs_constraints;
368 void (*pebs_aliases)(struct perf_event *event);
369
370 /*
371 * Intel LBR
372 */
373 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
374 int lbr_nr; /* hardware stack size */
375 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
376 const int *lbr_sel_map; /* lbr_select mappings */
377
378 /*
379 * Extra registers for events
380 */
381 struct extra_reg *extra_regs;
382 unsigned int er_flags;
383
384 /*
385 * Intel host/guest support (KVM)
386 */
387 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
388};
389
390#define x86_add_quirk(func_) \
391do { \
392 static struct x86_pmu_quirk __quirk __initdata = { \
393 .func = func_, \
394 }; \
395 __quirk.next = x86_pmu.quirks; \
396 x86_pmu.quirks = &__quirk; \
397} while (0)
398
399#define ERF_NO_HT_SHARING 1
400#define ERF_HAS_RSP_1 2
401
402extern struct x86_pmu x86_pmu __read_mostly;
403
404DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
405
406int x86_perf_event_set_period(struct perf_event *event);
407
408/*
409 * Generalized hw caching related hw_event table, filled
410 * in on a per model basis. A value of 0 means
411 * 'not supported', -1 means 'hw_event makes no sense on
412 * this CPU', any other value means the raw hw_event
413 * ID.
414 */
415
416#define C(x) PERF_COUNT_HW_CACHE_##x
417
418extern u64 __read_mostly hw_cache_event_ids
419 [PERF_COUNT_HW_CACHE_MAX]
420 [PERF_COUNT_HW_CACHE_OP_MAX]
421 [PERF_COUNT_HW_CACHE_RESULT_MAX];
422extern u64 __read_mostly hw_cache_extra_regs
423 [PERF_COUNT_HW_CACHE_MAX]
424 [PERF_COUNT_HW_CACHE_OP_MAX]
425 [PERF_COUNT_HW_CACHE_RESULT_MAX];
426
427u64 x86_perf_event_update(struct perf_event *event);
428
429static inline int x86_pmu_addr_offset(int index)
430{
431 int offset;
432
433 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
434 alternative_io(ASM_NOP2,
435 "shll $1, %%eax",
436 X86_FEATURE_PERFCTR_CORE,
437 "=a" (offset),
438 "a" (index));
439
440 return offset;
441}
442
443static inline unsigned int x86_pmu_config_addr(int index)
444{
445 return x86_pmu.eventsel + x86_pmu_addr_offset(index);
446}
447
448static inline unsigned int x86_pmu_event_addr(int index)
449{
450 return x86_pmu.perfctr + x86_pmu_addr_offset(index);
451}
452
453int x86_setup_perfctr(struct perf_event *event);
454
455int x86_pmu_hw_config(struct perf_event *event);
456
457void x86_pmu_disable_all(void);
458
459static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
460 u64 enable_mask)
461{
462 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
463
464 if (hwc->extra_reg.reg)
465 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
466 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
467}
468
469void x86_pmu_enable_all(int added);
470
471int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
472
473void x86_pmu_stop(struct perf_event *event, int flags);
474
475static inline void x86_pmu_disable_event(struct perf_event *event)
476{
477 struct hw_perf_event *hwc = &event->hw;
478
479 wrmsrl(hwc->config_base, hwc->config);
480}
481
482void x86_pmu_enable_event(struct perf_event *event);
483
484int x86_pmu_handle_irq(struct pt_regs *regs);
485
486extern struct event_constraint emptyconstraint;
487
488extern struct event_constraint unconstrained;
489
490static inline bool kernel_ip(unsigned long ip)
491{
492#ifdef CONFIG_X86_32
493 return ip > PAGE_OFFSET;
494#else
495 return (long)ip < 0;
496#endif
497}
498
499#ifdef CONFIG_CPU_SUP_AMD
500
501int amd_pmu_init(void);
502
503#else /* CONFIG_CPU_SUP_AMD */
504
505static inline int amd_pmu_init(void)
506{
507 return 0;
508}
509
510#endif /* CONFIG_CPU_SUP_AMD */
511
512#ifdef CONFIG_CPU_SUP_INTEL
513
514int intel_pmu_save_and_restart(struct perf_event *event);
515
516struct event_constraint *
517x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
518
519struct intel_shared_regs *allocate_shared_regs(int cpu);
520
521int intel_pmu_init(void);
522
523void init_debug_store_on_cpu(int cpu);
524
525void fini_debug_store_on_cpu(int cpu);
526
527void release_ds_buffers(void);
528
529void reserve_ds_buffers(void);
530
531extern struct event_constraint bts_constraint;
532
533void intel_pmu_enable_bts(u64 config);
534
535void intel_pmu_disable_bts(void);
536
537int intel_pmu_drain_bts_buffer(void);
538
539extern struct event_constraint intel_core2_pebs_event_constraints[];
540
541extern struct event_constraint intel_atom_pebs_event_constraints[];
542
543extern struct event_constraint intel_nehalem_pebs_event_constraints[];
544
545extern struct event_constraint intel_westmere_pebs_event_constraints[];
546
547extern struct event_constraint intel_snb_pebs_event_constraints[];
548
549struct event_constraint *intel_pebs_constraints(struct perf_event *event);
550
551void intel_pmu_pebs_enable(struct perf_event *event);
552
553void intel_pmu_pebs_disable(struct perf_event *event);
554
555void intel_pmu_pebs_enable_all(void);
556
557void intel_pmu_pebs_disable_all(void);
558
559void intel_ds_init(void);
560
561void intel_pmu_lbr_reset(void);
562
563void intel_pmu_lbr_enable(struct perf_event *event);
564
565void intel_pmu_lbr_disable(struct perf_event *event);
566
567void intel_pmu_lbr_enable_all(void);
568
569void intel_pmu_lbr_disable_all(void);
570
571void intel_pmu_lbr_read(void);
572
573void intel_pmu_lbr_init_core(void);
574
575void intel_pmu_lbr_init_nhm(void);
576
577void intel_pmu_lbr_init_atom(void);
578
579void intel_pmu_lbr_init_snb(void);
580
581int intel_pmu_setup_lbr_filter(struct perf_event *event);
582
583int p4_pmu_init(void);
584
585int p6_pmu_init(void);
586
587#else /* CONFIG_CPU_SUP_INTEL */
588
589static inline void reserve_ds_buffers(void)
590{
591}
592
593static inline void release_ds_buffers(void)
594{
595}
596
597static inline int intel_pmu_init(void)
598{
599 return 0;
600}
601
602static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
603{
604 return NULL;
605}
606
607#endif /* CONFIG_CPU_SUP_INTEL */