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1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
3 *
4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
5 *
6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of_platform.h>
26#include <asm/io.h>
27
28#include "fsl_85xx_cache_ctlr.h"
29
30static char *sram_size;
31static char *sram_offset;
32struct mpc85xx_l2ctlr __iomem *l2ctlr;
33
34static long get_cache_sram_size(void)
35{
36 unsigned long val;
37
38 if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
39 return -EINVAL;
40
41 return val;
42}
43
44static long get_cache_sram_offset(void)
45{
46 unsigned long val;
47
48 if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
49 return -EINVAL;
50
51 return val;
52}
53
54static int __init get_size_from_cmdline(char *str)
55{
56 if (!str)
57 return 0;
58
59 sram_size = str;
60 return 1;
61}
62
63static int __init get_offset_from_cmdline(char *str)
64{
65 if (!str)
66 return 0;
67
68 sram_offset = str;
69 return 1;
70}
71
72__setup("cache-sram-size=", get_size_from_cmdline);
73__setup("cache-sram-offset=", get_offset_from_cmdline);
74
75static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
76{
77 long rval;
78 unsigned int rem;
79 unsigned char ways;
80 const unsigned int *prop;
81 unsigned int l2cache_size;
82 struct sram_parameters sram_params;
83
84 if (!dev->dev.of_node) {
85 dev_err(&dev->dev, "Device's OF-node is NULL\n");
86 return -EINVAL;
87 }
88
89 prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
90 if (!prop) {
91 dev_err(&dev->dev, "Missing L2 cache-size\n");
92 return -EINVAL;
93 }
94 l2cache_size = *prop;
95
96 sram_params.sram_size = get_cache_sram_size();
97 if ((int)sram_params.sram_size <= 0) {
98 dev_err(&dev->dev,
99 "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
100 return -EINVAL;
101 }
102
103 sram_params.sram_offset = get_cache_sram_offset();
104 if ((int64_t)sram_params.sram_offset <= 0) {
105 dev_err(&dev->dev,
106 "Entire L2 as cache, provide a valid sram offset\n");
107 return -EINVAL;
108 }
109
110
111 rem = l2cache_size % sram_params.sram_size;
112 ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
113 if (rem || (ways & (ways - 1))) {
114 dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
115 return -EINVAL;
116 }
117
118 l2ctlr = of_iomap(dev->dev.of_node, 0);
119 if (!l2ctlr) {
120 dev_err(&dev->dev, "Can't map L2 controller\n");
121 return -EINVAL;
122 }
123
124 /*
125 * Write bits[0-17] to srbar0
126 */
127 out_be32(&l2ctlr->srbar0,
128 sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
129
130 /*
131 * Write bits[18-21] to srbare0
132 */
133#ifdef CONFIG_PHYS_64BIT
134 out_be32(&l2ctlr->srbarea0,
135 (sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
136#endif
137
138 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
139
140 switch (ways) {
141 case LOCK_WAYS_EIGHTH:
142 setbits32(&l2ctlr->ctl,
143 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
144 break;
145
146 case LOCK_WAYS_TWO_EIGHTH:
147 setbits32(&l2ctlr->ctl,
148 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
149 break;
150
151 case LOCK_WAYS_HALF:
152 setbits32(&l2ctlr->ctl,
153 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
154 break;
155
156 case LOCK_WAYS_FULL:
157 default:
158 setbits32(&l2ctlr->ctl,
159 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
160 break;
161 }
162 eieio();
163
164 rval = instantiate_cache_sram(dev, sram_params);
165 if (rval < 0) {
166 dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
167 iounmap(l2ctlr);
168 return -EINVAL;
169 }
170
171 return 0;
172}
173
174static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
175{
176 BUG_ON(!l2ctlr);
177
178 iounmap(l2ctlr);
179 remove_cache_sram(dev);
180 dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
181
182 return 0;
183}
184
185static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
186 {
187 .compatible = "fsl,p2020-l2-cache-controller",
188 },
189 {
190 .compatible = "fsl,p2010-l2-cache-controller",
191 },
192 {
193 .compatible = "fsl,p1020-l2-cache-controller",
194 },
195 {
196 .compatible = "fsl,p1011-l2-cache-controller",
197 },
198 {
199 .compatible = "fsl,p1013-l2-cache-controller",
200 },
201 {
202 .compatible = "fsl,p1022-l2-cache-controller",
203 },
204 {
205 .compatible = "fsl,mpc8548-l2-cache-controller",
206 },
207 {},
208};
209
210static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
211 .driver = {
212 .name = "fsl-l2ctlr",
213 .owner = THIS_MODULE,
214 .of_match_table = mpc85xx_l2ctlr_of_match,
215 },
216 .probe = mpc85xx_l2ctlr_of_probe,
217 .remove = __devexit_p(mpc85xx_l2ctlr_of_remove),
218};
219
220static __init int mpc85xx_l2ctlr_of_init(void)
221{
222 return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
223}
224
225static void __exit mpc85xx_l2ctlr_of_exit(void)
226{
227 platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
228}
229
230subsys_initcall(mpc85xx_l2ctlr_of_init);
231module_exit(mpc85xx_l2ctlr_of_exit);
232
233MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
234MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
4 *
5 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
6 *
7 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_platform.h>
13#include <asm/io.h>
14
15#include "fsl_85xx_cache_ctlr.h"
16
17static char *sram_size;
18static char *sram_offset;
19struct mpc85xx_l2ctlr __iomem *l2ctlr;
20
21static int get_cache_sram_params(struct sram_parameters *sram_params)
22{
23 unsigned long long addr;
24 unsigned int size;
25
26 if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
27 return -EINVAL;
28
29 if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
30 return -EINVAL;
31
32 sram_params->sram_offset = addr;
33 sram_params->sram_size = size;
34
35 return 0;
36}
37
38static int __init get_size_from_cmdline(char *str)
39{
40 if (!str)
41 return 0;
42
43 sram_size = str;
44 return 1;
45}
46
47static int __init get_offset_from_cmdline(char *str)
48{
49 if (!str)
50 return 0;
51
52 sram_offset = str;
53 return 1;
54}
55
56__setup("cache-sram-size=", get_size_from_cmdline);
57__setup("cache-sram-offset=", get_offset_from_cmdline);
58
59static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
60{
61 long rval;
62 unsigned int rem;
63 unsigned char ways;
64 const unsigned int *prop;
65 unsigned int l2cache_size;
66 struct sram_parameters sram_params;
67
68 if (!dev->dev.of_node) {
69 dev_err(&dev->dev, "Device's OF-node is NULL\n");
70 return -EINVAL;
71 }
72
73 prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
74 if (!prop) {
75 dev_err(&dev->dev, "Missing L2 cache-size\n");
76 return -EINVAL;
77 }
78 l2cache_size = *prop;
79
80 if (get_cache_sram_params(&sram_params))
81 return 0; /* fall back to L2 cache only */
82
83 rem = l2cache_size % sram_params.sram_size;
84 ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
85 if (rem || (ways & (ways - 1))) {
86 dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
87 return -EINVAL;
88 }
89
90 l2ctlr = of_iomap(dev->dev.of_node, 0);
91 if (!l2ctlr) {
92 dev_err(&dev->dev, "Can't map L2 controller\n");
93 return -EINVAL;
94 }
95
96 /*
97 * Write bits[0-17] to srbar0
98 */
99 out_be32(&l2ctlr->srbar0,
100 lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
101
102 /*
103 * Write bits[18-21] to srbare0
104 */
105#ifdef CONFIG_PHYS_64BIT
106 out_be32(&l2ctlr->srbarea0,
107 upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
108#endif
109
110 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
111
112 switch (ways) {
113 case LOCK_WAYS_EIGHTH:
114 setbits32(&l2ctlr->ctl,
115 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
116 break;
117
118 case LOCK_WAYS_TWO_EIGHTH:
119 setbits32(&l2ctlr->ctl,
120 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
121 break;
122
123 case LOCK_WAYS_HALF:
124 setbits32(&l2ctlr->ctl,
125 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
126 break;
127
128 case LOCK_WAYS_FULL:
129 default:
130 setbits32(&l2ctlr->ctl,
131 L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
132 break;
133 }
134 eieio();
135
136 rval = instantiate_cache_sram(dev, sram_params);
137 if (rval < 0) {
138 dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
139 iounmap(l2ctlr);
140 return -EINVAL;
141 }
142
143 return 0;
144}
145
146static int mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
147{
148 BUG_ON(!l2ctlr);
149
150 iounmap(l2ctlr);
151 remove_cache_sram(dev);
152 dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
153
154 return 0;
155}
156
157static const struct of_device_id mpc85xx_l2ctlr_of_match[] = {
158 {
159 .compatible = "fsl,p2020-l2-cache-controller",
160 },
161 {
162 .compatible = "fsl,p2010-l2-cache-controller",
163 },
164 {
165 .compatible = "fsl,p1020-l2-cache-controller",
166 },
167 {
168 .compatible = "fsl,p1011-l2-cache-controller",
169 },
170 {
171 .compatible = "fsl,p1013-l2-cache-controller",
172 },
173 {
174 .compatible = "fsl,p1022-l2-cache-controller",
175 },
176 {
177 .compatible = "fsl,mpc8548-l2-cache-controller",
178 },
179 { .compatible = "fsl,mpc8544-l2-cache-controller",},
180 { .compatible = "fsl,mpc8572-l2-cache-controller",},
181 { .compatible = "fsl,mpc8536-l2-cache-controller",},
182 { .compatible = "fsl,p1021-l2-cache-controller",},
183 { .compatible = "fsl,p1012-l2-cache-controller",},
184 { .compatible = "fsl,p1025-l2-cache-controller",},
185 { .compatible = "fsl,p1016-l2-cache-controller",},
186 { .compatible = "fsl,p1024-l2-cache-controller",},
187 { .compatible = "fsl,p1015-l2-cache-controller",},
188 { .compatible = "fsl,p1010-l2-cache-controller",},
189 { .compatible = "fsl,bsc9131-l2-cache-controller",},
190 {},
191};
192
193static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
194 .driver = {
195 .name = "fsl-l2ctlr",
196 .of_match_table = mpc85xx_l2ctlr_of_match,
197 },
198 .probe = mpc85xx_l2ctlr_of_probe,
199 .remove = mpc85xx_l2ctlr_of_remove,
200};
201
202static __init int mpc85xx_l2ctlr_of_init(void)
203{
204 return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
205}
206
207static void __exit mpc85xx_l2ctlr_of_exit(void)
208{
209 platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
210}
211
212subsys_initcall(mpc85xx_l2ctlr_of_init);
213module_exit(mpc85xx_l2ctlr_of_exit);
214
215MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
216MODULE_LICENSE("GPL v2");