1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * NVIDIA Tegra SoC device tree board support
  4 *
  5 * Copyright (C) 2011, 2013, NVIDIA Corporation
  6 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  7 * Copyright (C) 2010 Google, Inc.
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/clk/tegra.h>
 12#include <linux/dma-mapping.h>
 13#include <linux/init.h>
 14#include <linux/io.h>
 15#include <linux/irqchip.h>
 16#include <linux/irqdomain.h>
 17#include <linux/kernel.h>
 18#include <linux/of_address.h>
 19#include <linux/of_fdt.h>
 20#include <linux/of.h>
 21#include <linux/of_platform.h>
 22#include <linux/pda_power.h>
 23#include <linux/platform_device.h>
 24#include <linux/serial_8250.h>
 25#include <linux/slab.h>
 26#include <linux/sys_soc.h>
 27#include <linux/usb/tegra_usb_phy.h>
 28
 29#include <linux/firmware/trusted_foundations.h>
 30
 31#include <soc/tegra/fuse.h>
 32#include <soc/tegra/pmc.h>
 33
 34#include <asm/firmware.h>
 35#include <asm/hardware/cache-l2x0.h>
 36#include <asm/mach/arch.h>
 37#include <asm/mach/time.h>
 38#include <asm/mach-types.h>
 39#include <asm/setup.h>
 40
 41#include "board.h"
 42#include "common.h"
 43#include "cpuidle.h"
 44#include "iomap.h"
 45#include "irq.h"
 46#include "pm.h"
 47#include "reset.h"
 48#include "sleep.h"
 49
 50/*
 51 * Storage for debug-macro.S's state.
 52 *
 53 * This must be in .data not .bss so that it gets initialized each time the
 54 * kernel is loaded. The data is declared here rather than debug-macro.S so
 55 * that multiple inclusions of debug-macro.S point at the same data.
 56 */
 57u32 tegra_uart_config[3] = {
 58	/* Debug UART initialization required */
 59	1,
 60	/* Debug UART physical address */
 61	0,
 62	/* Debug UART virtual address */
 63	0,
 64};
 65
 66static void __init tegra_init_early(void)
 67{
 68	of_register_trusted_foundations();
 69	tegra_cpu_reset_handler_init();
 70	call_firmware_op(l2x0_init);
 71}
 72
 73static void __init tegra_dt_init_irq(void)
 74{
 75	tegra_init_irq();
 76	irqchip_init();
 77}
 78
 79static void __init tegra_dt_init(void)
 80{
 81	struct device *parent = tegra_soc_device_register();
 82
 83	of_platform_default_populate(NULL, NULL, parent);
 84}
 85
 86static void __init tegra_dt_init_late(void)
 87{
 88	tegra_init_suspend();
 89	tegra_cpuidle_init();
 90
 91	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
 92	    of_machine_is_compatible("compal,paz00"))
 93		tegra_paz00_wifikill_init();
 94
 95	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
 96	    of_machine_is_compatible("nvidia,tegra20"))
 97		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
 98}
 99
100static const char * const tegra_dt_board_compat[] = {
101	"nvidia,tegra124",
102	"nvidia,tegra114",
103	"nvidia,tegra30",
104	"nvidia,tegra20",
105	NULL
106};
107
108DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
109	.l2c_aux_val	= 0x3c400001,
110	.l2c_aux_mask	= 0xc20fc3fe,
111	.smp		= smp_ops(tegra_smp_ops),
112	.map_io		= tegra_map_common_io,
113	.init_early	= tegra_init_early,
114	.init_irq	= tegra_dt_init_irq,
115	.init_machine	= tegra_dt_init,
116	.init_late	= tegra_dt_init_late,
117	.dt_compat	= tegra_dt_board_compat,
118MACHINE_END