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1/*
2 * arch/arm/mach-tegra/sleep.S
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
6 *
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
23 */
24
25#include <linux/linkage.h>
26
27#include <asm/assembler.h>
28
29#include <mach/iomap.h>
30
31#include "flowctrl.h"
32
33#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
34 + IO_PPSB_VIRT)
35
36/* returns the offset of the flow controller halt register for a cpu */
37.macro cpu_to_halt_reg rd, rcpu
38 cmp \rcpu, #0
39 subne \rd, \rcpu, #1
40 movne \rd, \rd, lsl #3
41 addne \rd, \rd, #0x14
42 moveq \rd, #0
43.endm
44
45/* returns the offset of the flow controller csr register for a cpu */
46.macro cpu_to_csr_reg rd, rcpu
47 cmp \rcpu, #0
48 subne \rd, \rcpu, #1
49 movne \rd, \rd, lsl #3
50 addne \rd, \rd, #0x18
51 moveq \rd, #8
52.endm
53
54/* returns the ID of the current processor */
55.macro cpu_id, rd
56 mrc p15, 0, \rd, c0, c0, 5
57 and \rd, \rd, #0xF
58.endm
59
60/* loads a 32-bit value into a register without a data access */
61.macro mov32, reg, val
62 movw \reg, #:lower16:\val
63 movt \reg, #:upper16:\val
64.endm
65
66/*
67 * tegra_cpu_wfi
68 *
69 * puts current CPU in clock-gated wfi using the flow controller
70 *
71 * corrupts r0-r3
72 * must be called with MMU on
73 */
74
75ENTRY(tegra_cpu_wfi)
76 cpu_id r0
77 cpu_to_halt_reg r1, r0
78 cpu_to_csr_reg r2, r0
79 mov32 r0, TEGRA_FLOW_CTRL_VIRT
80 mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
81 str r3, [r0, r2] @ clear event & interrupt status
82 mov r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
83 str r3, [r0, r1] @ put flow controller in wait irq mode
84 dsb
85 wfi
86 mov r3, #0
87 str r3, [r0, r1] @ clear flow controller halt status
88 mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
89 str r3, [r0, r2] @ clear event & interrupt status
90 dsb
91 mov pc, lr
92ENDPROC(tegra_cpu_wfi)
93
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * arch/arm/mach-tegra/sleep.S
4 *
5 * Copyright (c) 2010-2011, NVIDIA Corporation.
6 * Copyright (c) 2011, Google, Inc.
7 *
8 * Author: Colin Cross <ccross@android.com>
9 * Gary King <gking@nvidia.com>
10 */
11
12#include <linux/linkage.h>
13
14#include <asm/assembler.h>
15#include <asm/cache.h>
16#include <asm/cp15.h>
17#include <asm/hardware/cache-l2x0.h>
18
19#include "iomap.h"
20#include "sleep.h"
21
22#define CLK_RESET_CCLK_BURST 0x20
23#define CLK_RESET_CCLK_DIVIDER 0x24
24
25#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
26/*
27 * tegra_disable_clean_inv_dcache
28 *
29 * disable, clean & invalidate the D-cache
30 *
31 * Corrupted registers: r1-r3, r6, r8, r9-r11
32 */
33ENTRY(tegra_disable_clean_inv_dcache)
34 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
35 dmb @ ensure ordering
36
37 /* Disable the D-cache */
38 mrc p15, 0, r2, c1, c0, 0
39 tst r2, #CR_C @ see tegra_sleep_cpu()
40 bic r2, r2, #CR_C
41 mcrne p15, 0, r2, c1, c0, 0
42 isb
43
44 /* Flush the D-cache */
45 cmp r0, #TEGRA_FLUSH_CACHE_ALL
46 blne v7_flush_dcache_louis
47 bleq v7_flush_dcache_all
48
49 /* Trun off coherency */
50 exit_smp r4, r5
51
52 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
53ENDPROC(tegra_disable_clean_inv_dcache)
54#endif
55
56#ifdef CONFIG_PM_SLEEP
57/*
58 * tegra_init_l2_for_a15
59 *
60 * set up the correct L2 cache data RAM latency
61 */
62ENTRY(tegra_init_l2_for_a15)
63 mrc p15, 0, r0, c0, c0, 5
64 ubfx r0, r0, #8, #4
65 tst r0, #1 @ only need for cluster 0
66 bne _exit_init_l2_a15
67
68 mrc p15, 0x1, r0, c9, c0, 2
69 and r0, r0, #7
70 cmp r0, #2
71 bicne r0, r0, #7
72 orrne r0, r0, #2
73 mcrne p15, 0x1, r0, c9, c0, 2
74_exit_init_l2_a15:
75
76 ret lr
77ENDPROC(tegra_init_l2_for_a15)
78
79/*
80 * tegra_sleep_cpu_finish(unsigned long v2p)
81 *
82 * enters suspend in LP2 by turning off the mmu and jumping to
83 * tegra?_tear_down_cpu
84 */
85ENTRY(tegra_sleep_cpu_finish)
86 mov r4, r0
87 /* Flush and disable the L1 data cache */
88 mov r0, #TEGRA_FLUSH_CACHE_ALL
89 bl tegra_disable_clean_inv_dcache
90
91 mov r0, r4
92 mov32 r6, tegra_tear_down_cpu
93 ldr r1, [r6]
94 add r1, r1, r0
95
96 mov32 r3, tegra_shut_off_mmu
97 add r3, r3, r0
98 mov r0, r1
99
100 ret r3
101ENDPROC(tegra_sleep_cpu_finish)
102
103/*
104 * tegra_shut_off_mmu
105 *
106 * r0 = physical address to jump to with mmu off
107 *
108 * called with VA=PA mapping
109 * turns off MMU, icache, dcache and branch prediction
110 */
111 .align L1_CACHE_SHIFT
112 .pushsection .idmap.text, "ax"
113ENTRY(tegra_shut_off_mmu)
114 mrc p15, 0, r3, c1, c0, 0
115 movw r2, #CR_I | CR_Z | CR_C | CR_M
116 bic r3, r3, r2
117 dsb
118 mcr p15, 0, r3, c1, c0, 0
119 isb
120#ifdef CONFIG_CACHE_L2X0
121 /* Disable L2 cache */
122 check_cpu_part_num 0xc09, r9, r10
123 retne r0
124
125 mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
126 ldr r3, [r2, #L2X0_CTRL]
127 tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
128 mov r3, #0
129 strne r3, [r2, #L2X0_CTRL]
130#endif
131 ret r0
132ENDPROC(tegra_shut_off_mmu)
133 .popsection
134
135/*
136 * tegra_switch_cpu_to_pllp
137 *
138 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
139 */
140ENTRY(tegra_switch_cpu_to_pllp)
141 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
142 mov32 r5, TEGRA_CLK_RESET_BASE
143 mov r0, #(2 << 28) @ burst policy = run mode
144 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
145 str r0, [r5, #CLK_RESET_CCLK_BURST]
146 mov r0, #0
147 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
148 ret lr
149ENDPROC(tegra_switch_cpu_to_pllp)
150#endif